©
1999
DATA SHEET
µ
PD3778
MOS INTEGRATED CIRCUIT
The
µ
PD3778 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The
µ
PD3778 has 3 rows of 10600 pixels, and each row has a double-sided readout type of charge transfer register.
And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi/A4 color
image scanners and so on.
FEATURES
• Valid photocell : 10600 pixels × 3
• Photocell's pitch : 4
µ
m
• Photocell size : 4 × 4
µ
m2
• Line spacing : 48
µ
m (12 lines) Red line-Green line, Green line-Blue line
• Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
• Resolution : 48 dot/mm A4 (210 × 297 mm) size (shorter side)
1200 dpi US letter (8.5” × 11”) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate : 5 MHz MAX.
• Power supply : +12 V
• On-chip circuits : Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number Package
µ
PD3778CY CCD linear image sensor 32-pin plastic DIP (400 mil)
Document No. S14374EJ1V0DSJ1 (1st edition)
Date published October 2000 N CP(K)
Printed in Japan
10600 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
µ
PD3778
2Data Sheet S14374EJ1V0DS00
BLOCK DIAGRAM
CCD analog shift register
Transfer gate
CCD analog shift register
Transfer gate
D14
D64
S1
S2
S10599
S10600
D65
D66
D67
Photocell
(Blue)
........
V
OD
GND GND
11629
30
31
32
V
OUT
1
(
Blue)
V
OUT
2
(
Green)
V
OUT
3
(
Red)
φ
1
19
φ
1
11
18
φ
TG1
(Blue)
2
φ
RB
3
φ
CLB
φ
2
14
φ
2
22
17
φ
TG2
(Green)
15
φ
TG3
(Red)
CCD analog shift register
Transfer gate
CCD analog shift register
Transfer gate
D14
D64
S1
S2
S10599
S10600
D65
D66
D67
Photocell
(Green)
........
CCD analog shift register
Transfer gate
CCD analog shift register
Transfer gate
D14
D64
S1
S2
S10599
S10600
D65
D66
D67
Photocell
(Red)
........
µ
PD3778
3
Data Sheet S14374EJ1V0DS00
PIN CONFIGURATION (Top View)
CCD linear image sensor 32-pin plastic DIP (400 mil)
•
µ
PD3778CY
1
2
3
4
5
6
7
8
9
10
11
NC
NC
V
OUT
2
V
OUT
1
IC
1
φ
TG1
φ
No connection
No connection
NC No connection
NC No connection
Output signal 2 (Green)
Output signal 1 (Blue)
Output drain voltage
Internal connection
Shift register clock 1
Transfer gate clock 2
(for Green)
V
OUT
3GND
1
φ
TG3
φ
Output signal 3 (Red)Ground
Reset gate clock
Shift register clock 2
ICInternal connection
ICInternal connection
ICInternal connection
ICInternal connection
Shift register clock 1
10600
10600
10600
Red
Green
Blue
1
1
1
Internal connection
Transfer gate clock 1
(for Blue)
Transfer gate clock 3
(for Red)
V
OD
IC
2
φ
2
φ
Shift register clock 2
GND
Ground
RB
φ
Reset feed-through level
clamp clock CLB
φ
No connection NC
No connection NC
No connection NC
No connection NC
No connection NC
TG2
φ
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
IC Internal connection
IC Internal connection
Caution Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
µ
PD3778
4Data Sheet S14374EJ1V0DS00
PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
µ
4 m
µ
2 m
µ
m
2
Channel stopper
Aluminum
shield
Blue photocell array
4 m
µ
Green photocell array
4 m
µ
Red photocell array
4 m
µ
12 lines
(48 m)
µ
12 lines
(48 m)
µ
µ
PD3778
5
Data Sheet S14374EJ1V0DS00
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)
Parameter Symbol Ratings Unit
Output drain voltage VOD –0.3 to +15 V
Shift register clock voltage V
φ
1, V
φ
2–0.3 to +8 V
Reset gate clock voltage V
φ
RB –0.3 to +8 V
Reset feed-through level clamp clock voltage V
φ
CLB –0.3 to +8 V
Transfer gate clock voltage V
φ
TG1 to V
φ
TG3 –0.3 to +8 V
Operating ambient temperature TA–25 to +60 °C
Storage temperature Tstg –40 to +70 °C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)
Parameter Symbol MIN. TYP. MAX. Unit
Output drain voltage VOD 11.4 12.0 12.6 V
Shift register clock high level V
φ
1H, V
φ
2H 4.5 5.0 5.5 V
Shift register clock low level V
φ
1L, V
φ
2L –0.3 0 +0.5 V
Reset gate clock high level V
φ
RBH 4.5 5.0 5.5 V
Reset gate clock low level V
φ
RBL –0.3 0 +0.5 V
Reset feed-through level clamp clock high level V
φ
CLBH 4.5 5.0 5.5 V
Reset feed-through level clamp clock low level V
φ
CLBL –0.3 0 +0.5 V
Transfer gate clock high level V
φ
TG1H to V
φ
TG3H 4.5 V
φ
1HNote V
φ
1HNote V
Transfer gate clock low level V
φ
TG1L to V
φ
TG3L –0.3 0 +0.5 V
Data rate f
φ
RB – 1.0 5.0 MHz
Note When Transfer gate clock high level (V
φ
TG1H to V
φ
TG3H) is higher than Shift register clock high level (V
φ
1H),
Image lag can increase.
µ
PD3778
6Data Sheet S14374EJ1V0DS00
ELECTRICAL CHARACTERISTICS
TA = +25 °C, VOD = 12 V, data rate (f
φ
RB) = 2 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p,
light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Saturation voltage Vsat 2.0 2.5 – V
Saturation exposure Red SER 0.694 lx•s
Green SEG 0.757 lx•s
Blue SEB 1.250 lx•s
Photo response non-uniformity PRNU VOUT = 1.0 V 6 20 %
Average dark signal ADS Light shielding 0.2 4.0 mV
Dark signal non-uniformity DSNU Light shielding 1.5 4.0 mV
Power consumption PW400 600 mW
Output impedance ZO0.5 1 kΩ
Response Red RR2.52 3.60 4.68 V/lx•s
Green RG2.31 3.30 4.29 V/lx•s
Blue RB1.40 2.00 2.60 V/lx•s
Image lag IL VOUT = 1.0 V 2.0 10.0 %
Offset level Note1 VOS 4.0 6.0 7.0 V
Output fall delay time Note2 tdVOUT = 1.0 V 50 ns
Total transfer efficiency TTE VOUT = 1.0 V, 92 98 %
data rate = 5 MHz
Register imbalance RI VOUT = 1.0 V 0 1.0 4.0 %
Response peak Red 630 nm
Green 540 nm
Blue 460 nm
Dynamic range DR1 Vsat /DSNU 1666 times
DR2 Vsat /σ CDS 2500 times
Reset feed-through noise Note1 RFTN Light shielding –1000 –300 +500 mV
Random noise (CDS) σ CDS Light shielding – 1.0 – mV
Notes 1. Refer to TIMING CHART 2.
2. When each fall time of
φ
1 and
φ
2 (t2, t1) is the TYP. value (refer to TIMING CHART 2).
µ
PD3778
7
Data Sheet S14374EJ1V0DS00
INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V)
Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit
Shift register clock pin capacitance 1 C
φ
1
φ
1 11 400 pF
19 400 pF
Shift register clock pin capacitance 2 C
φ
2
φ
2 14 400 pF
22 400 pF
Reset gate clock pin capacitance C
φ
RB
φ
RB 2 15 pF
Reset feed-through level clamp clock pin capacitance
C
φ
CLB
φ
CLB 3 15 pF
Transfer gate clock pin capacitance C
φ
TG
φ
TG1 18 120 pF
φ
TG2 17 120 pF
φ
TG3 15 120 pF
Remark Pins 11 and 19 (
φ
1), 14 and 22 (
φ
2) are each connected inside of the device.
µ
PD3778
8Data Sheet S14374EJ1V0DS00
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
61
62
63
64
65
66
10663
10664
10665
10666
10667
10668
10669
V
OUT
1 to
V
OUT
3
CLB
φ
RB
φ
2
φ
1
φ
TG1 to
φ
TG3
φ
NoteNote
Invalid photocell
(3 pixels)
Invalid photocell
(2 pixels)
Valid photocell
(10600 pixels)
Optical black
(49 pixels)
1
2
3
4
5
6
7
8
TIMING CHART 1 (for each color)
Note Input the
φ
RB and
φ
CLB pulses continuously during this period, too.
µ
PD3778
9
Data Sheet S14374EJ1V0DS00
TIMING CHART 2 (for each color)
φ
VOUT
CLB
φ
RB
φ
2
φ
190 %
10 %
90 %
10 %
90 %
10 %
90 %
10 %
+
_RFTN
RFTN
VOS
t2t1
t4
t6
t3
t5
t10 t8 t7 t9 t11
td
10 %
td
10 %
µ
PD3778
10 Data Sheet S14374EJ1V0DS00
φ
TG1 to
φ
TG3,
φ
1,
φ
2 TIMING CHART
1
φ
2
φ
t15
90 %
10 %
90 %
TG1 to TG3
φ
t13 t12 t14
t16
φ
Symbol MIN. TYP. MAX. Unit
t1, t2 0 25 – ns
t3 20 50 – ns
t4 70 250 – ns
t5, t6 0 25 – ns
t7 30 50 – ns
t8, t9 0 25 – ns
t10 30 50 – ns
t11 5 15 – ns
t12 5000 10000 – ns
t13, t14 0 50 – ns
t15, t16 900 1000 – ns
φ
1,
φ
2 cross points
1
φ
2
φ
2.0 V or more 2.0 V or more
Remark Adjust cross points of
φ
1 and
φ
2 with input resistance of each pin.
µ
PD3778
11
Data Sheet S14374EJ1V0DS00
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage: Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure: SE
Product of intensity of illumination (IX) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity: PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.
4. Average dark signal: ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
5. Dark signal non-uniformity: DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid
pixels at light shielding. This is calculated by the following formula.
x
Register Dark
DC level
V
OUT
∆x
ADS
DSNU
Register Dark
DC level
V
OUT
PRNU (%) =
x =
xj : Output voltage of valid pixel number j
∆x
∆x : maximum of xj − x
x
10600
Σ
j=1
10600
xj
× 100
ADS (mV) =
d
j
: Dark signal of valid pixel number j
10600
Σ
j=1
10600
d
j
d
j
: Dark signal of valid pixel number j
DSNU (mV) : maximum of d
j
− ADS
j = 1 to 10600
µ
PD3778
12 Data Sheet S14374EJ1V0DS00
6. Output impedance: ZO
Impedance of the output pins viewed from outside.
7. Response: R
Output voltage divided by exposure (Ix•s).
Note that the response varies with a light source (spectral characteristic).
8. Image Lag: IL
The rate between the last output voltage and the next one after read out the data of a line.
9. Register imbalance: RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average
output voltage of all the valid pixels.
n : Number of valid pixels
Vj: Output voltage of each pixel
V
OUT
φ
TG
Light
V
OUT
ON OFF
V
1
V1
IL (%) = ×100
VOUT
RI (%) =
2
n j = 1
n
2
(V2j – 1 – V2j)
1
n
j = 1
n
Vj
×100
∑
∑
µ
PD3778
13
Data Sheet S14374EJ1V0DS00
10. Random noise (CDS): σCDS
Random noise (CDS) σCDS is defined as the standard deviation of a valid pixel output signal with 100 times (=
100 lines) data sampling at dark (light shielding). This is measured by the following procedure.
1. One valid photocell in one reading is fixed as measurement point.
2. The output level is measured during the Reset feed-through period which is averaged over 100 ns to get “VDi”.
3. The output level is measured during the Video output time averaged over 100 ns to get “VOi”.
4. The correlated double sampling output is defined by “VCDSi = VDi – VOi”.
5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines).
6. Calculate the standard deviation σCDS using the following formula.
V
OUT
Reset feed-through
Video output
σCDS (mV) = , V =
Σ
i=1
100
(VCDSi – V)2
Σ
i=1
100
VCDSi
100 100
1
µ
PD3778
14 Data Sheet S14374EJ1V0DS00
STANDARD CHARACTERISTIC CURVES (Nominal)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (TA = +25 °C)
Operatin
g
Ambient Temperature TA(°C) Stora
g
e Time (ms)
8
4
2
1
0.5
0.25
0.1 100 20304050
Relative Output Voltage
Relative Output Voltage
2
1
0.2
0.11510
400 500 600 700 800
100
80
60
40
20
0B
B
G
R
G
Response Ratio (%)
Wavelength (nm)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter) (T
A
= +25 °C)
µ
PD3778
15
Data Sheet S14374EJ1V0DS00
APPLICATION CIRCUIT EXAMPLE
PD3778
µ
4.7 Ω
4.7 Ω
4.7 Ω
B3
+12 V
10 Ω
µ
0.1 F
µ
47 F/25 V
µ
0.1 F
µ
10 F/16 V
+
B2
+5 V
+5 V
µ
0.1 F
µ
10 F/16 V
+
+
4.7 Ω
B1
47 Ω
47 Ω
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
4.7 Ω
4.7 Ω
4.7 Ω
NC
NC
V
OUT
2
V
OUT
1
IC
1
φ
TG1
φ
NC
NC
V
OUT
3GND
1
φ
1
φ
TG3
φ
IC
IC
IC
IC
V
OD
IC
2
φ
2
φ
GND
RB
φ
CLB
φ
TG
φ
2
φ
RB
φ
CLB
φ
NC
NC
NC
NC
NC
TG2
φ
IC
IC
Caution Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
Remark The inverters shown in the above application circuit example are the 74HC04 or 74AC04.
µ
PD3778
16 Data Sheet S14374EJ1V0DS00
47 F/25 V
B1 to B3 EQUIVALENT CIRCUIT
+
µ
12 V
100 Ω
100 Ω
CCD
VOUT 2SC945
2 kΩ
µ
PD3778
17
Data Sheet S14374EJ1V0DS00
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (400 mil)
2.58±0.3
0.25±0.05
10.16
(1.80)
2
1
3
0~10°
32C-1CCD-PKG3
Refractive indexDimensionsName
1.552.2×6.4×0.7Plastic cap
(5.42)
6.15±0.3
9.05±0.3
9.25±0.3
12.6±0.5
54.8±0.5
55.2±0.5
1.02±0.15
0.46±0.06 4.21±0.5
4.55±0.5
1 The 1st valid pixel The center of the pin1
4.1±0.5
38.1
2.54
116
32
1st valid pixel
(Unit : mm)
17
4
2 The surface of the chip The top of the cap
3 The bottom of the package The surface of the chip
4 Thickness of plastic cap over CCD chip
µ
PD3778
18 Data Sheet S14374EJ1V0DS00
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
For more details, refer to our document "Semiconductor Device Mounting Technology Manual"(C10535E).
Type of Through-hole Device
µ
PD3778CY : CCD linear image sensor 32-pin plastic DIP (400 mil)
Caution During assembly care should be taken to prevent solder or flux from contacting the plastic cap.
The optical characteristics could be degraded by such contact.
Conditions
Pin temperature: 300 °C or below,
Heat time: 3 seconds or less (per pin)
Process
Partial heating method
µ
PD3778
19
Data Sheet S14374EJ1V0DS00
NOTES ON CLEANING THE PLASTIC CAP
1 CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches.
The optical characteristics of the CCD will be degraded if the cap is scratched during
cleaning.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended
solvents below. Excessive pressure should not be applied to the cap during cleaning. If the
cap requires multiple cleanings it is recommended that a clean surface or cloth be used.
2 RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap. Use of
solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
Solvents Symbol
Ethyl Alcohol EtOH
Methyl Alcohol MeOH
Isopropyl Alcohol IPA
N-methyl Pyrrolidone NMP
µ
PD3778
20 Data Sheet S14374EJ1V0DS00
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
µ
PD3778
21
Data Sheet S14374EJ1V0DS00
[MEMO]
µ
PD3778
22 Data Sheet S14374EJ1V0DS00
[MEMO]
µ
PD3778
23
Data Sheet S14374EJ1V0DS00
[MEMO]
µ
PD3778
M8E 00. 4
The information in this document is current as of July, 1999. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
•
•
•
•
•
•
