TMS320F2808, TMS320F2806
TMS320F2801, UCD9501Digital Signal Processors
Data Manual
Literature Number: SPRS230EOctober 2003 – Revised April 2005
ADVANCE INFORMATION concerns new products in the samplingor preproduction phase of development. Characteristic data andother specifications are subject to change without notice.
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Contents
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Revision History ........................................................................................................................... 81 Features ............................................................................................................................ 112 Introduction ....................................................................................................................... 122.1 Pin Assignments ............................................................................................................ 132.2 Signal Descriptions ......................................................................................................... 163 Functional Overview ........................................................................................................... 223.1 Memory Map ................................................................................................................ 233.2 Brief Descriptions ........................................................................................................... 273.2.1 C28x CPU ....................................................................................................... 273.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 283.2.3 Peripheral Bus .................................................................................................. 283.2.4 Real-Time JTAG and Analysis ................................................................................ 283.2.5 Flash .............................................................................................................. 283.2.6 M0, M1 SARAMs ............................................................................................... 293.2.7 L0, L1, H0 SARAMs ............................................................................................ 293.2.8 Boot ROM ........................................................................................................ 293.2.9 Security .......................................................................................................... 303.2.10 Peripheral Interrupt Expansion (PIE) Block .................................................................. 303.2.11 External Interrupts (XINT1, XINT2, XNMI) ................................................................... 313.2.12 Oscillator and PLL .............................................................................................. 313.2.13 Watchdog ........................................................................................................ 313.2.14 Peripheral Clocking ............................................................................................. 313.2.15 Low-Power Modes .............................................................................................. 313.2.16 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 313.2.17 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 323.2.18 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 323.2.19 Control Peripherals ............................................................................................. 323.2.20 Serial Port Peripherals ......................................................................................... 323.3 Register Map ................................................................................................................ 333.4 Device Emulation Registers ............................................................................................... 353.5 Interrupts .................................................................................................................... 363.5.1 External Interrupts .............................................................................................. 383.6 System Control ............................................................................................................. 393.6.1 OSC and PLL Block ............................................................................................ 403.6.2 External Reference Oscillator Clock Option ................................................................. 423.6.3 Watchdog Block ................................................................................................. 423.7 Low-Power Modes Block .................................................................................................. 444 Peripherals ........................................................................................................................ 454.1 32-Bit CPU-Timers 0/1/2 .................................................................................................. 454.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6) .......................................................................... 474.3 Hi-Resolution PWM (HRPWM) ........................................................................................... 494.4 Enhanced CAP Modules (eCAP1/2/3/4) ................................................................................ 504.5 Enhanced QEP Modules (eQEP1/2) ..................................................................................... 524.6 Enhanced Analog-to-Digital Converter (ADC) Module ................................................................ 544.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) ..................................... 584.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B) .................................................... 634.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D) ........................................... 664.10 Inter-Integrated Circuit (I
2
C) ............................................................................................... 704.11 GPIO MUX .................................................................................................................. 725 Device Support .................................................................................................................. 76
2Contents
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TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
5.1 Device and Development Support Tool Nomenclature ................................................................ 765.2 Documentation Support ................................................................................................... 776 Electrical Specifications ...................................................................................................... 806.1 Absolute Maximum Ratings ............................................................................................... 806.2 Recommended Operating Conditions ................................................................................... 806.3 Electrical Characteristics ................................................................................................. 816.3.1 TMS320F2808 Current Consumption by Power-Supply Pins ........................................................ 826.3.2 TMS320F2806 Current Consumption by Power-supply Pins ........................................................ 836.3.3 TMS320F2801/UCD9501 Current Consumption by Power-supply Pins ............................................ 846.4 Reducing Current Consumption ......................................................................................... 846.5 Current Consumption Graphs ............................................................................................ 856.6 Signal Transition Levels ................................................................................................... 866.7 Timing Parameter Symbology ............................................................................................ 876.8 General Notes on Timing Parameters ................................................................................... 876.9 Test Load Circuit .......................................................................................................... 886.10 Device Clock Table ........................................................................................................ 886.11 Clock Requirements and Characteristics ............................................................................... 896.12 Reset Timing ............................................................................................................... 906.13 Power Sequencing ......................................................................................................... 906.14 High Resolution PWM Characteristics (at SYSCLKOUT = 100 MHz) ............................................... 926.15 On-Chip Analog-to-Digital Converter .................................................................................... 936.15.1 ADC Absolute Maximum Ratings ...................................................................................... 936.15.2 ADC Electrical Characteristics ......................................................................................... 936.15.3 ADC Power-Up Control Bit Timing ..................................................................................... 956.15.4 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ........................................................ 966.15.5 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) ...................................................... 976.15.6 Definitions .................................................................................................................. 986.16 Detailed Descriptions ..................................................................................................... 987 Mechanical Data ............................................................................................................... 100
Contents 3
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TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
List of Figures
2-1 TMS320F2808 100-Pin PZ LQFP (Top View) ................................................................................. 13
2-2 TMS320F2806 100-Pin PZ LQFP (Top View) ................................................................................. 14
2-3 TMS320F2801/UCD9501 100-Pin PZ LQFP (Top View) .................................................................... 15
2-4 TMS320F280x 100-Ball GGM and ZGM MicroStar™ BGA (Bottom View) ............................................... 16
3-1 Functional Block Diagram ........................................................................................................ 22
3-2 F2808 Memory Map .............................................................................................................. 23
3-3 F2806 Memory Map .............................................................................................................. 24
3-4 F2801/9501 Memory Map ........................................................................................................ 25
3-5 External and PIE Interrupt Sources ............................................................................................. 36
3-6 Multiplexing of Interrupts Using the PIE Block ................................................................................ 37
3-7 Clock and Reset Domains ....................................................................................................... 39
3-8 OSC and PLL Block Diagram ................................................................................................... 40
3-9 Recommended Crystal/Clock Connection ..................................................................................... 42
3-10 Watchdog Module ................................................................................................................. 43
4-1 CPU-Timers ........................................................................................................................ 45
4-2 CPU-Timer Interrupt Signals and Output Signal .............................................................................. 46
4-3 Multiple PWM Modules in a 280x System ..................................................................................... 47
4-4 ePWM Sub-modules Showing Critical Internal Signal Interconects ........................................................ 49
4-5 eCAP Functional Block Diagram ................................................................................................ 50
4-6 eQEP Functional Block Diagram ................................................................................................ 52
4-7 Block Diagram of the ADC Module ............................................................................................. 55
4-8 ADC Pin Connections With Internal Reference ............................................................................... 56
4-9 ADC Pin Connections With External Reference .............................................................................. 57
4-10 eCAN Block Diagram and Interface Circuit .................................................................................... 59
4-11 eCAN-A Memory Map ............................................................................................................ 60
4-12 eCAN-B Memory Map ............................................................................................................ 61
4-13 Serial Communications Interface (SCI) Module Block Diagram ............................................................ 65
4-14 SPI Module Block Diagram (Slave Mode) ..................................................................................... 69
4-15 I
2
C Peripheral Module Interfaces ............................................................................................... 71
4-16 GPIO MUX Block Diagram ....................................................................................................... 72
4-17 Qualification Using Sampling Window .......................................................................................... 74
4-18 Sampling Mode .................................................................................................................... 74
5-1 Example of TMS320x280x Device Nomenclature ............................................................................ 77
6-1 Typical Operational Current Versus Frequency (F2808) .................................................................... 85
6-2 Typical Operational Power Versus Frequency (F2808) ...................................................................... 86
6-3 Output Levels ...................................................................................................................... 86
6-4 Input Levels ........................................................................................................................ 86
6-5 3.3-V Test Load Circuit ........................................................................................................... 88
6-6 Clock Timing ....................................................................................................................... 90
4List of Figures
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TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
6-7 Power-on Reset ................................................................................................................... 91
6-8 Warm Reset ........................................................................................................................ 92
6-9 Effect of Writing Into PLLCR Register .......................................................................................... 92
6-10 ADC Analog Input Impedance Model ........................................................................................... 94
6-11 ADC Power-Up Control Bit Timing .............................................................................................. 95
6-12 Sequential Sampling Mode (Single-Channel) Timing ........................................................................ 96
6-13 Simultaneous Sampling Mode Timing .......................................................................................... 97
List of Figures 5
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TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
List of Tables
2-1 Hardware Features ............................................................................................................... 12
2-2 Signal Descriptions ............................................................................................................... 17
3-1 Addresses of Flash Sectors in F2808 .......................................................................................... 26
3-2 Addresses of Flash Sectors in F2806 .......................................................................................... 26
3-3 Addresses of Flash Sectors in F2801/9501 ................................................................................... 26
3-4 Wait States ......................................................................................................................... 27
3-5 Boot Mode Selection .............................................................................................................. 29
3-6 Peripheral Frame 0 Registers ................................................................................................... 33
3-7 Peripheral Frame 1 Registers ................................................................................................... 34
3-8 Peripheral Frame 2 Registers ................................................................................................... 34
3-9 Device Emulation Registers ..................................................................................................... 35
3-10 PIE Peripheral Interrupts ......................................................................................................... 37
3-11 PIE Configuration and Control Registers ...................................................................................... 38
3-12 External Interrupt Registers ...................................................................................................... 38
3-13 PLL, Clocking, Watchdog, and Low-Power Mode Registers ................................................................ 40
3-14 PLLCR Register Bit Definitions .................................................................................................. 41
3-15 Possible PLL Configuration Modes ............................................................................................. 42
3-16 Low-Power Modes ................................................................................................................ 44
4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers ................................................................... 46
4-2 ePWM Control and Status Registers ........................................................................................... 48
4-3 eCAP Control and Status Registers ............................................................................................ 51
4-4 eQEP Control and Status Registers ............................................................................................ 53
4-5 ADC Registers ..................................................................................................................... 57
4-6 3.3-V eCAN Transceivers ....................................................................................................... 59
4-7 CAN Register Map ................................................................................................................ 62
4-8 SCI-A Registers ................................................................................................................... 64
4-9 SCI-B Registers ................................................................................................................... 64
4-10 SPI-A Registers ................................................................................................................... 67
4-11 SPI-B Registers ................................................................................................................... 67
4-12 SPI-C REGISTERS ............................................................................................................... 68
4-13 SPI-D Registers ................................................................................................................... 68
4-14 I
2
C-A Registers .................................................................................................................... 71
4-15 GPIO Registers ................................................................................................................... 73
6-1 Typical Current Consumption by Various Peripherals (at 100 MHz) ....................................................... 85
6-2 TMS320x280x Clock Table and Nomenclature ............................................................................... 88
6-3 Input Clock Frequency ........................................................................................................... 89
6-4 XCLKIN Timing Requirements - PLL Bypassed or Enabled ................................................................ 89
6-5 XCLKIN Timing Requirements - PLL Disabled ................................................................................ 89
6-6 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ......................................................... 89
6List of Tables
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TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
6-7 Reset ( XRS) Timing Requirements ............................................................................................. 90
6-8 ADC Power-Up Delays ........................................................................................................... 95
6-9 Sequential Sampling Mode Timing ............................................................................................. 96
6-10 Simultaneous Sampling Mode Timing .......................................................................................... 97
List of Tables 7
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Revision History
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
This data manual was revised from SPRS230D to SPRS230E. The technical changes made in bothrevisions D and E are listed below.
Scope: This document has been reviewed for technical accuracy; the technical content is up to date as ofthe specified release date with the following changes:
Revision C to D
Location Additions, Deletions, Changes
Global Added the UCD9501 device and High Resolution PWM (HRPWM) channels where appropriateFeatures Added HRPWM channels to Features pageTable 2-1 Added HRPWM channels to Hardware Features tableTable 2-2 Added notes on pullups to the GPIO pin sectionSection 3.2.11 Changed text in External Interrupts in Section 3.5.1 and Section 3.2.11Figure 3-8 Changed Figure 3-8 (OSC and PLL Block Diagram)Table 3-4 Changed comments on Peripheral Frame 1 in Table 3-4Table 3-9 Changed PARTID description in Table 3-9Table 3-15 Changed Table 3-15Section 5.2 Updated list of documents availableSection 4.3 Added section on High Resolution PWM as Section 4.3Table 4-2 Added HRPWM registers to Table 4-2 (ePWM Control and Status Registers)Figure 4-4 Added HRPWM to ePWM sub-module figureTable 6-7 Added a value to the last row of the reset timing tableFigure 6-11 Added figure for ADC Power-up Control Bit TimingSection 6.15.4 Changed section on Sequential Sampling Mode and added section on Simultaneous Sampling ModeSection 6.15.2 Merged ac electrical characteristics and dc into one table and changed values in the resulting table,Section 6.15.2
Revision D to E
Location Additions, Deletions, Modifications
Figure 2-3 Changed pin number 91 in TMS320F2801/UCD9501 PZ pinoutTable 2-2 Changed several signal descriptions, corrected some notes and formatting of GPIO pinsFigure 3-1 Changed functional block diagram to include UCD9501 deviceFigure 3-2 Changed memory map for 2808 deviceFigure 3-3 Changed memory map for 2806 deviceFigure 3-4 Changed memory map for 2801 device and added 9501 deviceTable 3-5 Changed Boot ROM description and tableFigure 3-7 Changed Clock and Reset Domains figureFigure 3-8 Changed OSC and PLL Block Diagram to delete PLL bypass and replace PLLCR with OSCCLK orVCOCLKTable 3-16 Changed Low Power ModesSection 3.2.11 Changed header External Interrupts (External Interrupts (XINT1, 2, 13, XNMI) to (XINT1, XINT2,XNMI)Section 3.6.1.1 Changed text descriptionSection 3.6.2 Corrected 30 MHz to 20 MHzTable 3-10 Changed note to show 43 instead of 45 interruptsTable 3-11 Replaced note on PIE Configuration and Control Registers tableFigure 4-2 Changed position of TINT1 in CPU -Timer Interrupt Signals and Output Signal figure and added anote
8Revision History
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TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Revision D to E (continued)
Section 4.5 Changed eQEP1/1 to eQEP1/2 in header and F2808 to 280x in descriptionSection 4.8 Changed equation for Max Bit Rate in SCI feature listSection 4.9 Changed Baud rate equation in SPI feature listTable 4-4 Corrected typographical error in QPOSCINT registerTable 4-2 Corrected typographical errors for TBPHSHR, TBPRD, and AQCSFRC register addressesTable 4-5 Changed register address for ADCRESULT8Section 4.6 Added note to equation for digital value in ADC features listFigure 4-4 Corrected errors in HRPWM figureSection 6.3.1 Corrected typos in current consumption by power-supply pins tables Section 6.3.1 to Section 6.3.3Table 6-2 Corrected typos in 280x Clock and Nomenclature tableTable 6-1 Corrected typo in note on Typical Current Consumption by Various Peripherals (at 100 MHz) tableFigure 6-10 Corrected value for c
h
in ADC Analog Input Impedance Model figureTable 6-9 Added a value for t
d(schx_n+1)
in Sequential Sampling tableSection 6.15.2 Corrected two typos in ADC electrical characteristicsFigure 6-13 Changed channel Bv to Bx in Simultaneous Sampling timing diagramSection 6.15.6 Changed definition of Reference VoltageSection 6.16 Changed description of Total Harmonic Distribution
Revision History 9
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TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
10 Revision History
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ADVANCE INFORMATION
1 Features
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
•Three 32-Bit CPU Timers•High-Performance Static CMOS Technology– 100 MHz (10-ns Cycle Time)
•Serial Port Peripherals– Low-Power (1.8-V Core, 3.3-V I/O) Design
– Up to 4 Serial Peripheral Interface (SPI)Modules– 3.3-V Flash Voltage
– Up to 2 Serial Communications Interface•JTAG Boundary Scan Support
(SCI), Standard UART Modules•High-Performance 32-Bit CPU (TMS320C28x)
– Up to 2 Enhanced Controller Area Network– 16 x 16 and 32 x 32 MAC Operations
(eCAN) Modules– 16 x 16 Dual MAC
– One Inter-Integrated-Circuit (I
2
C) Bus– Harvard Bus Architecture
•12-Bit ADC, 16 Channels– Atomic Operations
– 2 x 8 Channel Input Multiplexer– Fast Interrupt Response and Processing
– Two Sample-and-Hold– Unified Memory Programming Model
– Single/Simultaneous Conversions– Code-Efficient (in C/C++ and Assembly)
– Fast Conversion Rate: 160 ns/6.25 MSPS•On-Chip Memory
– Internal or External Reference– F2808: 64K X 16 Flash, 18K X 16 SARAM
•Up to 35 Individually Programmable,F2806: 32K X 16 Flash, 10K X 16 SARAM
Multiplexed General-Purpose Input/OutputF2801: 16K X 16 Flash, 6K X 16 SARAM
(GPIO) Pins With Input Filtering9501: 16K X 16 Flash, 6K X 16 SARAM
•Advanced Emulation Features– 1K x 16 OTP ROM
– Analysis and Breakpoint Functions•Boot ROM (4K x 16)
– Real-Time Debug via Hardware– With Software Boot Modes (via SCI, SPI,CAN, I
2
C, and Parallel I/O)
•Development Tools Include– Standard Math Tables
– ANSI C/C++ Compiler/Assembler/Linker
– Supports TMS320C24x™/240x Instructions•Clock and System Control
– Code Composer Studio™ IDE– Dynamic PLL Ratio Changes Supported
– DSP/BIOS™– On-Chip Oscillator
– JTAG Scan Controllers
(1)– Clock-Fail-Detect Mode
[Texas Instruments (TI) or Third-Party]– Watchdog Timer Module
– Evaluation Modules•Any GPIO A Pin Can Be Connected to One of
– Broad Third-Party Digital Motor Controlthe Three External Core Interrupts
Support•Peripheral Interrupt Expansion (PIE) Block
•Low-Power Modes and Power SavingsThat Supports All 43 Peripheral Interrupts
– IDLE, STANDBY, HALT Modes Supported•128-Bit Security Key/Lock
– Disable Individual Peripheral Clocks– Protects Flash/OTP/L0/L1 Blocks
•Package Options– Prevents Firmware Reverse Engineering
– Thin Quad Flatpack (PZ)•Enhanced Control Peripherals
– MicroStar BGA™ (GGM, ZGM)– Up to 16 PWM Outputs
•Temperature Options:– Up to 4 HRPWM Outputs With 150 ps MEP
– A: -40°C to 85°CResolution
– S: -40°C to 125°C– Up to Four Capture Inputs
– Q: -40°C to 125°C– Up to Two Quadrature Encoder Interfaces– Up to Six 32-bit Timers– Up to Six 16-bit Timers
(1) IEEE Standard 1149.1-1990 Standard Test Access Port andBoundary Scan Architecture
TMS320C24x, Code Composer Studio, DSP/BIOS, MicroStar BGA, TMS320C28x, MicroStar, C28x, TMS320C2000, TMS320 aretrademarks of Texas Instruments.eZdsp is a trademark of Spectrum Digital.XDS510 is a trademark of Texas Instruments.
ADVANCE INFORMATION concerns new products in the sampling
Copyright © 2003–2005, Texas Instruments Incorporatedor preproduction phase of development. Characteristic data andother specifications are subject to change without notice.
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ADVANCE INFORMATION
2 Introduction
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
The TMS320F2808, TMS320F2806, and TMS320F2801/UCD9501 devices, members of theTMS320C28x™ DSP generation, are highly integrated, high-performance solutions for demanding controlapplications. UCD9501 is a 32-bit Digital Signal Controller for power management.
Throughout this document, TMS320F2808, TMS320F2806, and TMS320F2801/UCD9501 are abbreviatedas F2808, F2806, and F2801/9501, respectively. TMS320x280x device reference guides are applicable tothe UCD9501 device as well.
Figure 2-1 provides a summary of each device's features.
Table 2-1. Hardware Features
FEATURE F2808 F2806 F2801/9501
Instruction cycle (at 100 MHz) 10 ns 10 ns 10 ns18K 10K 6KSingle-access RAM (SARAM) (16-bit word)
(L0, L1, M0, M1, H0) (L0, L1, M0, M1) (L0, M0, M1)3.3-V on-chip flash (16-bit word) 64K 32K 16KCode security for on-chip flash/SARAM/OTP blocks Yes Yes YesBoot ROM (4K X16) Yes Yes YesOne-time programmable (OTP) ROM Yes Yes YesExternal memory interface No No NoePWM1, ePWM2 ePWM1, ePWM2 ePWM1,Enhanced PWM outputs (six 16-bit timer-based modules
ePWM3, ePWM4, ePWM3, ePWM4, ePWM2,with 2 PWM outputs/module)
ePWM5, ePWM6 ePWM5, ePWM6 ePWM3ePWM1A, ePWM2A ePWM1A, ePWM2A ePWM1A, ePWM2AHRPWM channels (up to 4)
ePWM3A, ePWM4A ePWM3A, ePWM4A ePWM3AeCAP1, eCAP2 eCAP1, eCAP2Enhanced 32-bit CAPTURE inputs or auxiliary PWM outputs eCAP1, eCAP2eCAP3, eCAP4 eCAP3, eCAP4Enhanced 32-bit QEP channels (four inputs/channel) eQEP1, eQEP2 eQEP1, eQEP2 eQEP1Watchdog timer Yes Yes Yes12-Bit ADC channels 16 16 1632-Bit CPU timers 3 3 3SPI-A, SPI-B, SPI-A, SPI-B,Serial Peripheral Interface (SPI) SPI-A, SPI-BSPI-C, SPI-D SPI-C, SPI-DSerial Communications Interface (SCI) SCI-A, SCI-B SCI-A, SCI-B SCI-AEnhanced Controller Area Network (eCAN) eCAN-A, eCAN-B eCAN-A eCAN-AInter-Integrated Circuit (I
2
C) I2C-A I2C-A I2C-ADigital I/O pins (shared) 35 35 35External interrupts 3 3 3Supply voltage 1.8-V Core, 3.3-V I/O 1.8-V Core, 3.3-V I/O 1.8-V Core, 3.3-V I/O100-Pin PZ 100-Pin PZ 100-Pin PZPackaging
100-Ball GGM, ZGM 100-Ball GGM, ZGM 100-Ball GGM, ZGMA: -40°C to 85°C Yes Yes YesTemperature options S: -40°C to 125°C Yes Yes YesQ: -40°C to 125°C
(1)
Yes Yes YesProduct status
(2)
TMX TMX TMX
(1) The Q temperature version will be available once the S version is qualified for the Q100 automotive fault grading.(2) See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages.TMX is an experimental device that is not necessarily representative of the final device's electrical specifications.
12 Introduction
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ADVANCE INFORMATION
2.1 Pin Assignments
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TDO
GPIO27/ECAP4/EQEP2S/SPISTEB
EMU0
EMU1
GPIO24/ECAP1/EQEP2A/SPISIMOB
X2
X1
XCLKIN
GPIO25/ECAP2/EQEP2B/SPISOMIB
TEST1
TEST2
GPIO26/ECAP3/EQEP2I/SPICLKB
GPIO3/EPWM2B/SPISOMID
GPIO0/EPWM1A
GPIO2/EPWM2A
GPIO1/EPWM1B/SPISIMOD
GPIO34
ADCRESEXT
ADCREFP
ADCREFM
ADCREFIN
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
TCK
TMS
TDI
GPIO23/EQEP1I/SPISTEC/SCIRXB
GPIO22/EQEP1S/SPICLKC/SCITXB
GPIO11/EPWM6B/SCIRXB/ECAP4
GPIO21/EQEP1B/SPISOMIC/CANRXB
XCLKOUT
GPIO20/EQEP1A/SPISIMOC/CANTXB
GPIO9/EPWM5B/SCITXB/ECAP3
GPIO7/EPWM4B/SPISTED/ECAP2
GPIO19/SPISTEA/SCIRXB
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
GPIO18/SPICLKA/SCITXB
GPIO5/EPWM3B/SPICLKD/ECAP1
GPIO4/EPWM3A
GPIO30/CANRXA
GPIO31/CANTXA
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
XRS
TRST
VSS
VDD
VDDIO
GPIO10/EPWM6A/CANRXB/ADCSOCBO
VSS
GPIO8/EPWM5A/CANTXB/ADCSOCAO
VDD
VSS
GPIO17/SPISOMIA/CANRXB/TZ6
VSS
VSS
VDD
VDDIO
GPIO16/SPISIMOA/CANTXB/TZ5
VDD2A18
VSS2AGND
VDDAIO
GPIO12/TZ1/CANTXB/SPISIMOB
vSS
VDDIO
GPIO29/SCITXDA/TZ6
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO14/TZ3/SCITXB/SPICLKB
vSS
VDD
VDD1A18
vSS1AGND
vSSA2
vDDA2
GPIO15/TZ4/SCIRXB/SPISTEB
VSSAIO
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO13/TZ2/CANRXB/SPISOMIB
VDD3VFL
VSS
VDD
GPIO28/SCIRXDA/TZ5
VSS
VSS
VDD
VSS
VDDIO
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
The TMS320F2808, TMS320F2806, and TMS320F2801/UCD9501 100-pin PZ low-profile quad flatpack(LQFP) pin assignments are shown in Figure 2-1 ,Figure 2-2 and Figure 2-3 .Table 2-2 describes thefunction(s) of each pin.
Figure 2-1. TMS320F2808 100-Pin PZ LQFP (Top View)
Introduction 13
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ADVANCE INFORMATION
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TDO
GPIO27/ECAP4/EQEP2S/SPISTEB
EMU0
EMU1
GPIO24/ECAP1/EQEP2A/SPISIMOB
X2
X1
XCLKIN
GPIO25/ECAP2/EQEP2B/SPISOMIB
TEST1
TEST2
GPIO26/ECAP3/EQEP2I/SPICLKB
GPIO3/EPWM2B/SPISOMID
GPIO0/EPWM1A
GPIO2/EPWM2A
GPIO1/EPWM1B/SPISIMOD
GPIO34
ADCRESEXT
ADCREFP
ADCREFM
ADCREFIN
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
TCK
TMS
TDI
GPIO23/EQEP1i/SPISTEC/SCIRXB
GPIO22/EQEP1S/SPICLKC/SCITXB
XCLKOUT
GPIO20/EQEP1A/SPISIMOC
GPIO9/EPWM5B/SCITXB//ECAP3
GPIO7/EPWM4B/SPISTED/ECAP2
GPIO19/SPISTEA/SCIRXB
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
GPIO18/SPICLKA/SCITXB
GPIO5/EPWM3B/SPICLKD/ECAP1
GPIO4/EPWM3A
GPIO30/CANRXA
GPIO31/CANTXA
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
XRS
TRST
GPIO11/EPWM6B/SCIRXB/ECAP4
GPIO21/EQEP1B/SPISOMIC
VSS
VSS
VDD
VDDIO
GPIO16/SPISIMOA/TZ5
VDD2A18
VSS2AGND
VDDAIO
VSS
VDD
VDDIO
GPIO10/EPWM6A/ADCSOCBO
VSS
GPIO8/EPWM5A/ADCSOCAO
VDD
VSS
GPIO17/SPISOMIA/TZ6
VDD3VFL
VSS
VDD
GPIO28/SCIRXDA/TZ5
VSS
VSS
VDD
VSS
VDDIO
GPIO13/TZ2/SPISOMIB
GPIO12/TZ1/SPISIMOB
GPIO29/SCITXDA/TZ6
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO14/TZ3/SCITXB/SPICLKB
vSS
VDD
VDD1A18
vSS1AGND
vSSA2
vDDA2
GPIO15/TZ3/SCIRXB/SPISTEB
VSSAIO
vSS
VDDIO
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Figure 2-2. TMS320F2806 100-Pin PZ LQFP (Top View)
14 Introduction
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ADVANCE INFORMATION
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TDO
EMU0
EMU1
X2
X1
XCLKIN
TEST1
TEST2
GPIO26/SPICLKB
GPIO0/EPWM1A
GPIO2/EPWM2A
GPIO1/EPWM1B
GPIO34
ADCRESEXT
ADCREFP
ADCREFM
ADCREFIN
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
TCK
TMS
TDI
XCLKOUT
GPIO30/CANRXA
GPIO31/CANTXA
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
XRS
TRST
GPIO12/TZ1/SPISIMOB
vSS
VDDIO
GPIO29/SCITXDA/TZ6
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO14/TZ3/SPICLKB
vSS
VDD
VDD1A18
vSS1AGND
vSSA2
vDDA2
GPIO32/SDAA/EPWMSYNCI/ADSOCAO
GPIO13/TZ2/SPISOMIB
VDD3VFL
VSS
VDD
GPIO28/SCIRXDA/TZ5
VSS
VSS
VDD
GPIO21/EQEP1B
VSS
VDD
GPIO23/EQEP1I
GPIO22/EQEP1S
VDDIO
GPIO10/ADCSOCBO
GPIO20/EQEP1A
VSS
GPIO9
GPIO8/ADCSOCAO
VDD
GPIO7/ECAP2
GPIO19/SPISTEA
GPIO6/EPWMSYNCI/EPWMSYSNCO
GPIO11
VSS
GPIO18/SPICLKA
GPIO5/EPWM3B/ECAP1
GPIO17/SPISOMIA/TZ6
GPIO4/EPWM3A
VSS
VSS
VDD
VDDIO
GPIO16/SPISIMOA/TZ5
GPIO3/EPWM2B
VDD2A18
VSS2AGND
VDDAIO
GPIO15/TZ4/SPISTEB
VSS
GPIO27/SPISTEB
VDDIO
GPIO24/ECAP1/SPISIMOB
VSSAIO
GPIO25/ECAP2/SPISIMOB
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Figure 2-3. TMS320F2801/UCD9501 100-Pin PZ LQFP (Top View)
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4
C
B
A
D
E
21 3
K
F
G
H
J
5 76 98 10
Bottom View
TRST TCK
TDI
TDO TMS
EMU0
EMU1
TEST1
TEST2
X1
X2
XRS
GPIO0GPIO1
GPIO2 GPIO3 GPIO4
GPIO5
GPIO6GPIO7
GPIO9 GPIO8
GPIO10
GPIO11
GPIO12 GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23GPIO24GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30GPIO31
GPIO32
GPIO33
GPIO34
VDDA2
VDD1A18 DVDD
VDDIO
VSSAIO
VDDAIO
VSSA2 ADCINA7
D
VDD2A18
VDD
VDD
VDD
VDD
VDD
VDDIO
VDDIO
VDDIO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSVSS
ADCINB2
ADCINA6
ADCINA5ADCINA4 ADCINA3 ADCINA2
ADCINA1 ADCINA0
ADCINB7
ADCINB1
ADCINB0
ADCLO
ADCINB3 ADCINB5
ADCINB4
ADCINB6
2.2 Signal Descriptions
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Figure 2-4. TMS320F280x 100-Ball GGM and ZGM MicroStar™ BGA (Bottom View)
Table 2-2 describes the signals on the 280x devices. All digital inputs are TTL-compatible. All outputs are3.3 V with CMOS levels. Inputs are not 5-V tolerant.
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TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Table 2-2. Signal Descriptions
PIN NO.NAME DESCRIPTION
(1)PZ PIN GGM# BALL #
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control ofthe operations of the device. If this signal is not connected or driven low, the device operates in itsfunctional mode, and the test reset signals are ignored.NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an activehigh test pin and must be maintained low at all times during normal device operation. In a low-noiseTRST 84 A6
environment, TRST may be left floating. In other instances, an external pulldown resistor is highlyrecommended. The value of this resistor should be based on drive strength of the debugger podsapplicable to the design. A 2.2-k Ωresistor generally offers adequate protection. Since this isapplication-specific, it is recommended that each target board is validated for proper operation ofthe debugger and the application. (I, ↓)TCK 75 A10 JTAG test clock with internal pullup (I, ↑)JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAPTMS 74 B10
controller on the rising edge of TCK. (I, ↑)JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instructionTDI 73 C9
or data) on a rising edge of TCK. (I, ↑)JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)TDO 76 B9
are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulatorEMU0 80 A8
system and is defined as input/output through the JTAG scan. (I/O/Z, 8 mA drive ↑)Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulatorEMU1 81 B7
system and is defined as input/output through the JTAG scan. (I/O/Z, 8 mA drive, ↑)
FLASH
VDD3VFL 96 C4 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.TEST1 97 A3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)TEST2 98 B3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
CLOCK
Output clock derived from SYSCLKOUT to be used as a general-purpose clock source. XCLKOUTis either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT.This is controlled by the bits 1,0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =XCLKOUT 66 E8 SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The statusof the XCLKOUT pin may then be read through the XCLKOUTDAT bit in the XCLKOUT register.Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during a reset.(I/O/Z, 8 mA drive).External Oscillator Input. This pin is to feed clock from an external 3.3-V oscillator. If an externalXCLKIN 90 B5
oscillator is not used, this pin must be tied to GND. (I)Internal Oscillator Input. A quartz crystal or a ceramic resonator may be connected across X1 andX2. If an external oscillator is used, X1 must be tied to GND. The X1 pin is referenced to the 1.8-VX1 88 E6
core digital power supply. If a 3.3-V oscillator is to be used, connect it to XCLKIN and tie X1 toGND. (I)Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 andX2 86 C6
X2. If X2 is not used it must be left unconnected. (O)
RESET
Device Reset (in) and Watchdog Reset (out).Device reset. XRS causes the device to terminate execution. The PC will point to the addresscontained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at thelocation pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs.XRS 78 B8
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 XCLKINcycles. (I/OD, ↑)The output buffer of this pin is an open-drain with an internal pullup (100 µA, typical). It isrecommended that this pin be driven by an open-drain device.
ADC SIGNALS
ADCINA7 16 F3 ADC Group A, Channel 7 input (I)ADCINA6 17 F4 ADC Group A, Channel 6 input (I)
(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑= Pullup, ↓= Pulldown
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TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Table 2-2. Signal Descriptions (continued)
PIN NO.NAME DESCRIPTION
(1)PZ PIN GGM# BALL #
ADCINA5 18 G4 ADC Group A, Channel 5 input (I)ADCINA4 19 G1 ADC Group A, Channel 4 input (I)ADCINA3 20 G2 ADC Group A, Channel 3 input (I)ADCINA2 21 G3 ADC Group A, Channel 2 input (I)ADCINA1 22 H1 ADC Group A, Channel 1 input (I)ADCINA0 23 H2 ADC Group A, Channel 0 input (I)ADCINB7 34 K5 ADC Group B, Channel 7 input (I)ADCINB6 33 H4 ADC Group B, Channel 6 input (I)ADCINB5 32 K4 ADC Group B, Channel 5 input (I)ADCINB4 31 J4 ADC Group B, Channel 4 input (I)ADCINB3 30 K3 ADC Group B, Channel 3 input (I)ADCINB2 29 H3 ADC Group B, Channel 2 input (I)ADCINB1 28 J3 ADC Group B, Channel 1 input (I)ADCINB0 27 K2 ADC Group B, Channel 0 input (I)ADCLO 24 J1 Low Reference (connect to analog ground) (I)ADCRESEXT 38 F5 ADC External Current Bias Resistor. Connect a 22 k Ωresistor to analog ground.ADCREFIN 35 J5 External reference input (I)ADCREFP 37 G5 Internal Reference Positive Output (O)ADCREFM 36 H5 Internal Reference Medium Output (O)
CPU AND I/O POWER PINS
V
DDA2
15 F2 ADC Analog Power Pin (3.3 V)V
SSA2
14 F1 ADC Analog Ground PinV
DDAIO
26 J2 ADC Analog I/O Power Pin (3.3 V)V
SSAIO
25 K1 ADC Analog I/O Ground PinV
DD1A18
12 E4 ADC Analog Power Pin (1.8 V)V
SS1AGND
13 E5 ADC Analog Ground PinV
DD2A18
40 J6 ADC Analog Power Pin (1.8 V)V
SS2AGND
39 K6 ADC Analog Ground PinV
DD
10 E2V
DD
42 G6V
DD
59 F10
CPU and Logic Digital Power Pins (1.8 V)V
DD
68 D7V
DD
85 B6V
DD
93 D4V
DDIO
3 C2V
DDIO
46 H7
Digital I/O Power Pin (3.3 V)V
DDIO
65 E9V
DDIO
82 A7
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TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Table 2-2. Signal Descriptions (continued)
PIN NO.NAME DESCRIPTION
(1)PZ PIN GGM# BALL #
V
SS
2 B1V
SS
11 E3V
SS
41 H6V
SS
49 K9V
SS
55 H10V
SS
62 F7 Digital Ground PinsV
SS
69 D10V
SS
77 A9V
SS
87 D6V
SS
89 A5V
SS
94 A4
GPIOA AND PERIPHERAL SIGNALS
(2)
GPIO0 General purpose input/output 0 (I/O/Z)
(3)
EPWM1A Enhanced PWM1 Output A and HRPWM channel (O)47 K8- -- -GPIO1 General purpose input/output 1 (I/O/Z)
(3)
EPWM1B Enhanced PWM1 Output B (O)44 K7SPISIMOD SPI-D slave in, master out (I/O) (not available on F2801/9501)- -GPIO2 General purpose input/output 2 (I/O/Z)
(3)
EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)45 J7- -- -GPIO3 General purpose input/output 3 (I/O/Z)
(3)
EPWM2B Enhanced PWM2 Output B (O)48 J8SPISOMID SPI-D slave out, master in (I/O) (not available on F2801/9501)- -GPIO4 General purpose input/output 4 (I/O/Z)
(3)
EPWM3A Enhanced PWM3 output A and HRPWM channel (O)51 J9- -- -GPIO5 General purpose input/output 5 (I/O/Z)
(3)
EPWM3B Enhanced PWM3 output B (O)53 H9SPICLKD SPI-D clock (I/O) (not available on F2801/9501)ECAP1 eCAP input/output 1 (I/O)GPIO6 General purpose input/output 6 (I/O/Z)
(3)
EPWM4A Enhanced PWM4 output A and HRPWM channel (not available on F2801/9501) (O)56 G9EPWMSYNCI External ePWM sync pulse input (I)EPWMSYNCO External ePWM sync pulse output (O)GPIO7 General purpose input/output 7 (I/O/Z)
(3)
EPWM4B Enhanced PWM4 output B (not available on F2801/9501) (O)58 G8SPISTED SPI-D slave transmit enable (not available on F2801/9501 (I/O)ECAP2 eCAP input/output 2 (I/O)GPIO8 General purpose input/output 8 (I/O/Z)
(3)
EPWM5A Enhanced PWM5 output A (not available on F2801/9501) (O)60 F9CANTXB Enhanced CAN-B transmit (not available on F2806/F2801/9501) (O)ADCSOCAO ADC start-of-conversion A (O)GPIO9 General purpose input/output 9 (I/O/Z)
(3)
EPWM5B Enhanced PWM5 output B (not available on F2801/9501) (O)61 F8SCITXB SCI-B transmit data (not available on F2801/9501) (O)ECAP3 Enhanced capture input/output 3 (not available on F2801/9501) (I/O)
(2) All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectivelyenabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default atreset. The peripheral signals that are listed under them are alternate functions.(3) The pullups on GPIO0-GPIO11 pins are not enabled at reset.
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TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Table 2-2. Signal Descriptions (continued)
PIN NO.NAME DESCRIPTION
(1)PZ PIN GGM# BALL #
GPIO10 General purpose input/output 10 (I/O/Z)
(3)
EPWM6A Enhanced PWM6 output A (not available on F2801/9501) (O)64 E10CANRXB Enhanced CAN-B receive (not available on F2806/F2801/9501) (I)ADCSOCBO ADC start-of-conversion B (O)GPIO11 General purpose input/output 11 (I/O/Z)
(3)
EPWM6B Enhanced PWM6 output B (not available on F2801/9501) (O)70 D9SCIRXB SCI-B receive data (not available on F2801/9501) (I)ECAP4 Enhanced CAP Input/Output 4 (not available on F2801/9501) (I/O)GPIO12 General purpose input/output 12 (I/O/Z)
(4)
TZ1 Trip Zone input 1 (I)1 B2CANTXB CAN-B transmit (not available on F2806/F2801/9501) (O)SPISIMOB SPI-B Slave in, Master out (I/O)GPIO13 General purpose input/output 13 (I/O/Z)
(4)
TZ2 Trip zone input 2 (I)95 B4CANRXB CAN-B receive (not available on F2806/F2801/9501) (I)SPISOMIB SPI-B slave out, master in (I/O)GPIO14 General purpose input/output 14 (I/O/Z)
(4)
TZ3 Trip zone input 3 (I)8 D3SCITXB SCI-B transmit (not available on F2801/9501) (O)SPICLKB SPI-B clock input/output (I/O)GPIO15 General purpose input/output 15 (I/O/Z)
(4)
TZ4 Trip zone input (I)9 E1SCIRXB SCI-B receive (not available on F2801/9501) (I)SPISTEB SPI-B slave transmit enable (I/O)GPIO16 General purpose input/output 16 (I/O/Z)
(4)
SPISIMOA SPI-A slave in, master out (I/O)50 K10CANTXB CAN-B transmit (not available on F2806/F2801/9501) (O)TZ5 Trip zone input 5 (I)GPIO17 General purpose input/output 17 (I/O/Z)
(4)
SPISOMIA SPI-A slave out, master in (I/O)52 J10CANRXB CAN-B receive (not available on F2806/F2801/9501) (I)TZ6 Trip zone input 6(I)GPIO18 General purpose input/output 18 (I/O/Z)
(4)
SPICLKA SPI-A clock input/output (I/O)SCITXB 54 H8 SCI-B transmit (not available on F2801/9501) (O)- -- -GPIO19 General purpose input/output 19 (I/O/Z)
(4)
SPISTEA SPI-A slave transmit enable input/output (I/O)SCIRXB 57 G10 SCI-B receive (not available on F2801/9501) (I)- -- -GPIO20 General purpose input/output 20 (I/O/Z)
(4)
EQEP1A Enhanced QEP1 input A (I)63 F6SPISIMOC SPI-C slave in, master out (not available on F2801/9501) (I/O)CANTXB CAN-B transmit (not available on F2806/F2801/9501) (O)GPIO21 General purpose input/output 21 (I/O/Z)
(4)
EQEP1B Enhanced QEP1 input A (I)67 E7SPISOMIC SPI-C master in, slave out (not available on F2801/9501) (I/O)CANRXB CAN-B receive (not available on F2806/ F2801/9501) (I)GPIO22 General purpose input/output 22 (I/O/Z)
(4)
EQEP1S Enhanced QEP1 strobe (I/O)71 D8SPICLKC SPI-C clock (not available on F2801/9501) (I/O)SCITXB SCI-B transmit (not available on F2801/9501) (O)GPIO23 General purpose input/output 23 (I/O/Z)
(4)
EQEP1I Enhanced QEP1 index (I/O)72 C10SPISTEC SPI-C slave transmit enable (not available on F2801/9501) (I/O)SCIRXB SCI-B receive (I) (not available on F2801/9501)
(4) The pullups on GPIO12-GPIO34 are enabled upon reset.
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TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Table 2-2. Signal Descriptions (continued)
PIN NO.NAME DESCRIPTION
(1)PZ PIN GGM# BALL #
GPIO24 General purpose input/output 24 (I/O/Z)
(4)
ECAP1 Enhanced capture 1 (I/O)83 C7EQEP2A Enhanced QEP2 input A (I) (not available on F2801/9501)SPISIMOB SPI-B slave in, master out (I/O)GPIO25 General purpose input/output 25 (I/O/Z)
(4)
ECAP2 Enhanced capture 2 (I/O)91 C5EQEP2B Enhanced QEP2 input B (I) (not available on F2801/9501)SPISOMIB SPI-B master in, slave out (I/O)GPIO26 General purpose input/output 26 (I/O/Z)
(4)
ECAP3 Enhanced capture 3 (I/O)99 A2EQEP2I Enhanced QEP2 index (I/O) (not available on F2801/9501)SPICLKB SPI-B clock (I/O)GPIO27 General purpose input/output 27 (I/O/Z)
(4)
ECAP4 Enhanced capture 4 (I/O) (not available on F2801/9501)79 C8EQEP2S Enhanced QEP2 strobe (I/O) (not available on F2801)SPISTEB SPI-B slave transmit enable (I/O)GPIO28 General purpose input/output 28. This pin has an 8-mA (typical) output buffer. (I/O/Z)
(4)
SCIRXDA SCI receive data (I)92 D5- -TZ5 Trip zone 5 (I)GPIO29 General purpose input/output 29. This pin has an 8-mA (typical) output buffer. (I/O/Z)
(4)
SCITXDA SCI transmit data (O)4 C3- -TZ6 Trip zone 6 (I)GPIO30 General purpose input/output 30. This pin has an 8-mA (typical) output buffer. (I/O/Z)
(4)
CANRXA CAN-A receive data (I)6 D2- -- -GPIO31 General purpose input/output 31. This pin has an 8-mA (typical) output buffer. (I/O/Z)
(4)
CANTXA CAN-A transmit data (O)7 D1- -- -GPIO32 General purpose input/output 32 (I/O/Z)
(4)
SDAA I2C data open-drain bidirectional port (I/OD)100 A1EPWMSYNCI Enhanced PWM external sync pulse input (I)ADCSOCAO ADC start-of-conversion (O)GPIO33 General-Purpose Input/Output 33 (I/O/Z)
(4)
SCLA I2C clock open-drain bidirectional port (I/OD)5 C1EPWMSYNCO Enhanced PWM external synch pulse output (O)ADCSOCBO ADC start-of-conversion (O)GPIO34 General-Purpose Input/Output 34 (I/O/Z)
(4)
- -43 G7- -- -
Introduction 21
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3 Functional Overview
INT[12:1]
Real-Time JTAG
(TDI, TDO, TRST, TCK,
TMS, EMU0, EMU1)
C28x CPU
(100 MHz)
NMI, INT13
Memory Bus
Boot ROM
4 K 16
(1-wait state)
Memory Bus
FLASH
64 K x 16 F2808)
32K x 16 (F2806)
16K x 16 (F2801)
16K x 16 (9501)
H0 SARAM§C)
8 K 16
(0-wait)
L1 SARAM(B)
4 K 16
(0-wait)
L0 SARAM
4 K 16
(0-wait)
M0 SARAM
1 K 16
M1 SARAM
1 K 16
INT14
32-bit CPU TIMER 0
32-bit CPU TIMER 1
32-bit CPU TIMER 2
SYSCLKOUT
SYSRS
RS
CLKIN
12-Bit ADC
ADCSOCA/B
SOCA/B
16 Channels
12
6
32
XCLKOUT
XRS
XCLKIN
X1
X2
32
System Control
(Oscillator, PLL,
Peripheral Clocking,
Low Power Modes,
WatchDog)
EPWM1/2/3/4/5/6
(12 PWM outputs,
6 trip zones,
6 timers 16-bit)
ECAP1/2/3/4
(4 timers 32-bit)
eQEP1/2
eCAN-A/B (32 mbox)
External Interrupt
Control
PIE
(96 Interrupts)(A)
FIFO
FIFO
FIFO
SCI-A/B
SPI-A/B/C/D
I2C-A
4
8
4
2
16
4
GPIO MUX
GPIOs
(35)
TINT0
TINT1
TINT2
7
OTP
1K 16
Peripheral Bus
Protected by the code-security module.
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A. 43 of the possible 96 interrupts are used on the devices.B. Not available in F2801/9501C. Not available in F2806 or F2801/9501
Figure 3-1. Functional Block Diagram
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3.1 Memory Map
0x00 0000
Block Start
Address Data Space Prog Space
M0 SARAM (1 K 16)
M1 SARAM (1 K 16)
0x00 0400
Peripheral Frame 0
0x00 0800
0x00 0D00
Peripheral Frame 1
(protected)
0x00 6000
Peripheral Frame 2
(protected)
0x00 7000
L0 SARAM (0-wait)
(4 k 16, Secure Zone, Dual Mapped)
0x00 8000
L1 SARAM (0-wait)
(4 k 16, Secure Zone, Dual Mapped)
0x00 9000
H0 SARAM (0-wait)
(8 k 16, Dual Mapped)
0x00 A000
0x00 C000
OTP
(1 k 16, Secure Zone)
0x3D 7800
0x3D 7C00
FLASH
(64 k 16, Secure Zone)
0x3E 8000
0x3F 7FF8 128-bit Password
L0 SARAM (0-wait)
(4 k 16, Secure Zone, Dual Mapped)
0x3F 8000
L1 SARAM (0-wait)
(4 k 16, Secure Zone, Dual Mapped)
0x3F 9000
H0 SARAM (0-wait)
(8 k 16, Dual Mapped)
0x3F A000
0x3F F000
Boot ROM (4 k 16)
Vectors (32 32)
(enabled if VMAP = 1, ENPIE = 0)
0x3F FFC0
Low 64K [0000 − FFFF]
(24x/240x equivalent data space)
High 64K [3F0000 − 3FFFFF]
(24x/240x equivalent program space)
Reserved
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
0x00 0E00
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A. Memory blocks are not to scale.B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.User program cannot access these memory maps in program space.C. “ Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.D. Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 3-2. F2808 Memory Map
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0x00 0000
Block Start
Address Data Space
M0 SARAM (1K 16)
0x00 0400
0x00 0800
0x00 0D00
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
0x3D 7800
0x3D 7C00
0x3F 7FF8
0x3F 8000
0x3F 9000
0x3F A000
0x3F C000
0x3F FFC0
OTP
(1 K 16, Secure Zone)
FLASH
(32 K 16, Secure Zone)
Boot ROM (4 K 16)
Low 64K [0000−FFFF]
(24x/240x equivalent data space)
High 64K [3F0000 −3FFFF]
(24x/240x equivalent program space)
Reserved
M1 SARAM (1K 16)
L0 SARAM (0-wait)
(4k 16, Secure Zone, Dual Mapped)
L1 SARAM (0-wait)
(4k 16, Secure Zone, Dual Mapped)
L0 SARAM (0-wait) (4k 16,
Secure Zone, Dual Mapped)
L1 SARAM (0-wait) (4k 16,
Secure Zone, Dual Mapped)
128-bit Password
0x3F 0000
Prog Space
Peripheral Frame 0
Peripheral Frame 1
(protected)
Peripheral Frame 2
(protected)
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
Vectors (32 32)
(enabled if VMAP = 1, ENPIE = 0)
0x00 0E00
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A. Memory blocks are not to scale.B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.User program cannot access these memory maps in program space.C. “ Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.D. Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 3-3. F2806 Memory Map
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0x00 0000
Block Start
Address
0x00 0400
0x00 0800
0x00 0D00
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x3D 7800
0x3F 4000
0x3F 7FF8
0x3F 8000
0x3F 9000
0x3F C000
0x3F−FFC0
OTP
(1K 16, Secure Zone)
FLASH
(16 K 16, Secure Zone)
L0 (0-wait)
(4 K 16, Secure Zone, Dual Mapped)
Boot ROM (4 K 16)
Reserved
128-bit Password
Data Space Prog Space
0x3D 7C00
Vectors (32 32)
(enabled if VMAP = 1, ENPIE = 0)
Low 64K [0000−FFFF]
(24x/240x equivalent data space)
High 64K [3F0000 −3FFFF]
(24x/240x equivalent program space)
M0 SARAM (1 K 16)
M1 SARAM (1 K 16)
Peripheral Frame 0
Peripheral Frame 1
( protected)
Peripheral Frame 2
(protected)
L0 SARAM (0-wait)
(4 k 16, Secure Zone, Dual Mapped)
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
0x00 0E00
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
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A. Memory blocks are not to scale.B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.User program cannot access these memory maps in program space.C. “ Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.D. Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 3-4. F2801/9501 Memory Map
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Table 3-1. Addresses of Flash Sectors in F2808
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3E 8000
Sector D (16K x 16)0x3E BFFF0x3E C000
Sector C (16K x 16)0x3E FFFF0x3F 0000
Sector B (16K x 16)0x3F 3FFF0x3F 4000
Sector A (16K x 16)0x3F 7F7F0x3F 7F80 Program to 0x0000 when using the0x3F 7FF5 Code Security Module0x3F 7FF6 Boot-to-Flash Entry Point0x3F 7FF7 (program branch instruction here)0x3F 7FF8 Security Password (128-Bit)0x3F 7FFF (Do not program to all zeros)
Table 3-2. Addresses of Flash Sectors in F2806
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3F 0000
Sector D (8K x 16)0x3F 1FFF0x3F 2000
Sector C (8K x 16)0x3F 3FFF0x3F 4000
Sector B (8K x 16)0x3F 5FFF0x3F 6000
Sector A (8K x 16)0x3F 7F7F0x3F 7F80 Program to 0x0000 when using the0x3F 7FF5 Code Security Module0x3F 7FF6 Boot-to-Flash Entry Point0x3F 7FF7 (program branch instruction here)0x3F 7FF8 Security Password (128-Bit)0x3F 7FFF (Do not program to all zeros)
Table 3-3. Addresses of Flash Sectors in F2801/9501
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3F 4000 Sector D (4K x 16)0x3F 4FFF0x3F 5000 Sector C (4K x 16)0x3F 5FFF0x3F 6000 Sector B (4K x 16)0x3F 6FFF0x3F 7000 Sector A (4K x 16)0x3F 7F7F0x3F 7F80 Program to 0x0000 when using the0x3F 7FF5 Code Security Module0x3F 7FF6 Boot-to-Flash Entry Point0x3F 7FF7 (program branch instruction here)0x3F 7FF8 Security Password (128-Bit)0x3F 7FFF (Do not program to all zeros)
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3.2 Brief Descriptions
3.2.1 C28x CPU
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Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to bewrite/read peripheral block protected. The protected mode ensures that all accesses to these blockshappen as written. Because of the C28x pipeline, a write immediately followed by a read, to differentmemory locations, will appear in reverse order on the memory bus of the CPU. This can cause problemsin certain peripheral applications where the user expected the write to occur first (as written). The C28xCPU supports a block protection mode where a region of memory can be protected so as to make surethat operations occur as written (the penalty is extra cycles are added to align the operations). This modeis programmable and by default, it will protect the selected zones.
The wait states for the various spaces in the memory map area are listed in Table 3-4 .
Table 3-4. Wait States
AREA WAIT-STATES COMMENTS
M0 and M1 SARAMs 0-wait FixedPeripheral Frame 0 0-wait Fixed0-wait (writes)Peripheral Frame 1 Fixed. The eCAN peripheral can extend a cycle as needed.2-wait (reads)0-wait (writes)Peripheral Frame 2 Fixed2-wait (reads)L0 & L1 SARAMs 0-wait
Programmed via the Flash registers. 1-wait-state operationProgrammable,OTP is possible at a reduced CPU frequency. See Section1-wait minimum
Section 3.2.5 for more information.Programmed via the Flash registers. 0-wait-state operationProgrammable, is possible at reduced CPU frequency. The CSM passwordFlash
0-wait minimum locations are hardwired for 16 wait-states. See SectionSection 3.2.5 for more information.H0 SARAM 0-wait FixedBoot-ROM 1-wait Fixed
The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is avery efficient C/C++ engine, hence enabling users to develop not only their system control software in ahigh-level language, but also enables math algorithms to be developed using C/C++. The C28x is asefficient in DSP math tasks as it is in system control tasks that typically are handled by microcontrollerdevices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MACcapabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle highernumerical resolution problems that would otherwise demand a more expensive floating-point processorsolution. Add to this the fast interrupt response with automatic context save of critical registers, resulting ina device that is capable of servicing many asynchronous events with minimal latency. The C28x has an8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x toexecute at high speeds without resorting to expensive high-speed memories. Special branch-look-aheadhardware minimizes the latency for conditional discontinuities. Special store conditional operations furtherimprove performance.
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3.2.2 Memory Bus (Harvard Bus Architecture)
3.2.3 Peripheral Bus
3.2.4 Real-Time JTAG and Analysis
3.2.5 Flash
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As with many DSP type devices, multiple busses are used to move data between the memories andperipherals and the CPU. The C28x memory bus architecture contains a program read bus, data read busand data write bus. The program read bus consists of 22 address lines and 32 data lines. The data readand write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enablesingle cycle 32-bit operations. The multiple bus architecture, commonly termed "Harvard Bus", enables theC28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals andmemories attached to the memory bus will prioritize memory accesses. Generally, the priority of memorybus accesses can be summarized as follows:
Highest: Data Writes (Simultaneous data and program writes cannot occur on the memory bus.)Program Writes (Simultaneous data and program writes cannot occur on the memory bus.)Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur on the memorybus.)Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the memorybus.)
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the280x devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridgemultiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16address lines and 16 or 32 data lines and associated control signals. Two versions of the peripheral busare supported on the 280x. One version only supports 16-bit accesses (called peripheral frame 2). Theother version supports both 16- and 32-bit accesses (called peripheral frame 1).
The 280x implements the standard IEEE 1149.1 JTAG interface. Additionally, the 280x supports real-timemode of operation whereby the contents of memory, peripheral and register locations can be modifiedwhile the processor is running and executing code and servicing interrupts. The user can also single stepthrough non-time critical code while enabling time-critical interrupts to be serviced without interference.The 280x implements the real-time mode in hardware within the CPU. This is a unique feature to the280x, no software monitor is required. Additionally, special analysis hardware is provided which allows theuser to set hardware breakpoint or data/address watch-points and generate various user-selectable breakevents when a match occurs.
The F2808 contains 64K x 16 of embedded flash memory, segregated into four 16K X 16 sectors. TheF2806 has 32K X 16 of embedded flash, segregated into four 8K X 16 sectors. The F2801 contains 16K X16 of embedded Flash (four 4K X 16 sectors). All three devices also contain a single 1K x 16 of OTPmemory at address range 0x3D 7800 - 0x3D 7BFF. The user can individually erase, program, and validatea flash sector while leaving other sectors untouched. However, it is not possible to use one sector of theflash or the OTP to execute flash algorithms that erase/program other sectors. Special memory pipeliningis provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to bothprogram and data space; therefore, it can be used to execute code or store data information.
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3.2.6 M0, M1 SARAMs
3.2.7 L0, L1, H0 SARAMs
3.2.8 Boot ROM
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NOTEThe F2808/F2806/F2801 Flash and OTP wait states can be configured by the application.This allows applications running at slower frequencies to configure the flash to use fewerwait states.
Flash effective performance can be improved by enabling the flash pipeline mode in theFlash options register. With this mode enabled, effective performance of linear codeexecution will be much faster than the raw performance indicated by the wait stateconfiguration alone. The exact performance gain when using the Flash pipeline mode isapplication-dependent. The pipeline mode is not available for the OTP block.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers,see the TMS320x280x System Control and Interrupts Reference Guide (literature numberSPRU712).
All 280x devices contain these two blocks of single access memory, each 1K x 16 in size. The stackpointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blockson C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 toexecute code or for data variables. The partitioning is performed within the linker. The C28x devicepresents a unified memory map to the programmer. This makes for easier programming in high-levellanguages.
The F2808 contains an additional 16K x 16 of single-access RAM, divided into 3 blocks (L0-4K, L1-4K,H0-8K). The F2806 contains an additional 8K x 16 of single-access RAM, divided into 2 blocks (L0-4K,L1-4K). The F2801 contains an additional 4K x 16 of single-access RAM (L0-4K). Each block can beindependently accessed to minimize CPU pipeline stalls. Each block is mapped to both program and dataspace.
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tellthe bootloader software what boot mode to use on power up. The user can select to boot normally or todownload new software from an external connection or to select boot software that is programmed in theinternal Flash. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use inmath related algorithms.
Table 3-5. Boot Mode Selection
GPIO18 GPIO29 GPIO34MODE DESCRIPTION SPICLKA SCITXASCITXB
Boot to Flash Jump to Flash address 0x3F 7FF6 1 1 1You must have programmed a branch instruction here priorto reset to redirect code execution as desired.SCI-A Boot Load a data stream from SCI-A 1 1 0SPI-A Boot Load from an external serial SPI EEPROM on SPI-A 1 0 1I2C Boot Load data from an external EEPROM at address 0x50 on 1 0 0the I2C buseCAN-A Boot Call CAN_Boot to load from eCAN-A mailbox 1. 0 1 1Boot to M0 SARAM Jump to M0 SARAM address 0x00 0000. 0 1 0Boot to OTP Jump to OTP address 0x3D 7800 0 0 1Parallel I/O Boot Load data from GPIO0 - GPIO15 0 0 0
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3.2.9 Security
3.2.10 Peripheral Interrupt Expansion (PIE) Block
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The 280x devices support high levels of security to protect the user firmware from being reverseengineered. The security features a 128-bit password (hardcoded for 16 wait states), which the userprograms into the flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1SARAM blocks. The security feature prevents unauthorized users from examining the memory contentsvia the JTAG port, executing code from external memory or trying to boot-load some undesirable softwarethat would export the secure memory contents. To enable access to the secure blocks, the user mustwrite the correct 128-bit "KEY" value, which matches the value stored in the password locations within theFlash.
NOTEFor code security operation, all addresses between 0x3F7F80 and 0x3F7FF5 cannot beused as program code or data, but must be programmed to 0x0000 when the CodeSecurity Passwords are programmed. If security is not a concern, then these addressesmay be used for code or data.
The 128-bit password (at 0x3F 7FF8 - 0x3F 7FFF) must not be programmed to zeros.Doing so would permanently lock the device.
NOTECode Security Module Disclaimer
The Code Security Module ("CSM") included on this device was designed to passwordprotect the data stored in the associated memory (either ROM or Flash) and is warrantedby Texas Instruments (TI), in accordance with its standard terms and conditions, toconform to TI's published specifications for the warranty period applicable for this device.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BECOMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATEDMEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EX-CEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONSCONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANYIMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULARPURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, IN-DIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING INANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOTTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDEDDAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OFGOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECON-OMIC LOSS.
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. ThePIE block can support up to 96 peripheral interrupts. On the 280x, 43 of the possible 96 interrupts areused by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in adedicated RAM block that can be overwritten by the user. The vector is, automatically fetched by the CPUon servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled inhardware and software. Each individual interrupt can be enabled/disabled within the PIE block.
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3.2.11 External Interrupts (XINT1, XINT2, XNMI)
3.2.12 Oscillator and PLL
3.2.13 Watchdog
3.2.14 Peripheral Clocking
3.2.15 Low-Power Modes
3.2.16 Peripheral Frames 0, 1, 2 (PFn)
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The 280x supports three masked external interrupts (XINT1, XINT2, XNMI). XNMI can be connected tothe INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, orboth negative and positive edge triggering and can also be enabled/disabled (including the XNMI). Themasked interrupts also contain a 16-bit free running up counter, which is reset to zero when a validinterrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the281x devices, there are no dedicated pins for the external interrupts. Rather, any Port A GPIO pin can beconfigured to trigger any external interrupt.
The 280x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit.A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-flyin software, enabling the user to scale back on operating frequency if lower power operation is desired.Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.
The 280x devices contain a watchdog timer. The user software must regularly reset the watchdog counterwithin a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdogcan be disabled if necessary.
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumptionwhen a peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and theADC blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to bedecoupled from increasing CPU clock speeds.
The 280x devices are full static CMOS devices. Three low-power modes are provided:
IDLE: Place CPU into low-power mode. Peripheral clocks may be turned off selectively and onlythose peripherals that need to function during IDLE are left operating. An enabled interruptfrom an active peripheral or the watchdog timer will wake the processor from IDLE mode.STANDBY: Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.An external interrupt event will wake the processor and the peripherals. Execution beginson the next valid cycle after detection of the interrupt eventHALT: Turn off oscillator. This mode basically shuts down the device and places it in the lowestpossible power consumption mode. A reset or external signal can wake the device fromthis mode.
The 280x segregate peripherals into three sections. The mapping of peripherals is as follows:
PF0: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector TableFlash: Flash Control, Programming, Erase, Verify RegistersTimers: CPU-Timers 0, 1, 2 RegistersCSM: Code Security Module KEY RegistersADC: 12-Bit ADC RegistersPF1: eCAN: eCAN Mailbox and Control RegistersGPIO: GPIO MUX Configuration and Control Registers
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3.2.17 General-Purpose Input/Output (GPIO) Multiplexer
3.2.18 32-Bit CPU-Timers (0, 1, 2)
3.2.19 Control Peripherals
3.2.20 Serial Port Peripherals
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ePWM: Enhanced Pulse Width Modulator Module and RegisterseCAP: Enhanced Capture Module and RegisterseQEP: Enhanced Quadrature Encoder Pulse Module and RegistersPF2: SYS: System Control RegistersSCI: Serial Communications Interface (SCI) Control and RX/TX RegistersSPI: Serial Port Interface (SPI) Control and RX/TX RegistersADC: ADC Status, Control, and Result RegisterI
2
C: Inter-Integrated Circuit Module and Registers
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. Thisenables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pinsare configured as inputs. The user can individually program each pin for GPIO mode or peripheral signalmode. For specific inputs, the user can also select the number of input qualification cycles. This is to filterunwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-powermodes.
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clockprescaling. The timers have a 32-bit count down register, which generates an interrupt when the counterreaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 isreserved for Real-Time OS (RTOS)/BIOS applications. CPU-Timer 1 is also reserved for TI systemfunctions. CPU-Timer 2 is connected to INT14 of the CPU. CPU-Timer 1 can be connected to INT13 ofthe CPU. CPU-Timer 0 is for general use and is connected to the PIE block.
The 280x devices support the following peripherals which are used for embedded control andcommunication:
ePWM: The enhanced PWM peripheral supports independent/complementary PWM generation,adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle tripmechanism. Some of the PWM pins support HRPWM features.eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to fourprogrammable events in continuous/one-shot capture modes.This peripheral can also be configured to generate an auxiliary PWM signal.eQEP: The enhanced QEP peripheral uses a 32-bit position counter, supports low-speedmeasurement using capture unit and high-speed measurement using a 32-bit unit timer.This peripheral has a watchdog timer to detect motor stall and input error detection logicto identify simultaneous edge transition in QEP signals.ADC: The ADC block is a 12-bit converter, single ended, 16-channels. It contains twosample-and-hold units for simultaneous sampling.
The 280x devices support the following serial communication peripherals:
eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, timestamping of messages, and is CAN 2.0B-compliant.
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3.3 Register Map
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SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream ofprogrammed length (one to sixteen bits) to be shifted into and out of the device at aprogrammable bit-transfer rate. Normally, the SPI is used for communications between theDSP controller and external peripherals or another processor. Typical applications includeexternal I/O or peripheral expansion through devices such as shift registers, displaydrivers, and ADCs. Multi-device communications are supported by the master/slaveoperation of the SPI. On the 280x, the SPI contains a 16-level receive and transmit FIFOfor reducing interrupt servicing overhead.SCI: The serial communications interface is a two-wire asynchronous serial port, commonlyknown as UART. On the 280x, the SCI contains a 16-level receive and transmit FIFO forreducing interrupt servicing overhead.I
2
C: The inter-integrated circuit (I
2
C) module provides an interface between a DSP and otherdevices compliant with Philips Semiconductors Inter-IC bus (I
2
C-bus) specification version2.1 and connected by way of an I
2
C-bus. External components attached to this 2-wireserial bus can transmit/receive up to 8-bit data to/from the DSP through the I
2
C module.On the 280x, the I
2
C contains a 16-level receive and transmit FIFO for reducing interruptservicing overhead.
The 280x devices contain three peripheral register spaces. The spaces are categorized as follows:
Peripheral These are peripherals that are mapped directly to the CPU memory bus.Frame 0: See Table 3-6Peripheral These are peripherals that are mapped to the 32-bit peripheral bus.Frame 1 See Table 3-7Peripheral These are peripherals that are mapped to the 16-bit peripheral bus.Frame 2: See Table 3-8
Table 3-6. Peripheral Frame 0 Registers
(1) (2)
NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE
(3)
0x0880Device Emulation Registers 384 EALLOW protected0x09FF
0x0A80 EALLOW protectedFLASH Registers
(4)
960x0ADF CSM Protected0x0AE0Code Security Module Registers 16 EALLOW protected0x0AEF
0x0C00CPU-TIMER0/1/2 Registers 64 Not EALLOW protected0x0C3F
0x0CE0PIE Registers 32 Not EALLOW protected0x0CFF
0x0D00PIE Vector Table 256 EALLOW protected0x0DFF
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.(2) Missing segments of memory space are reserved and should not be used in applications.(3) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instructiondisables writes to prevent stray code or pointers from corrupting register contents.(4) The Flash Registers are also protected by the Code Security Module (CSM).
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Table 3-7. Peripheral Frame 1 Registers
(1) (2)
NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE
0x6000 256 Some eCAN control registers (and selected bits in other eCANeCANA Registers
0x60FF (128 x 32) control registers) are EALLOW-protected.0x6100 256eCANA Mailbox RAM Not EALLOW-protected0x61FF (128 x 32)0x6200 256 Some eCAN control registers (and selected bits in other eCANeCANB Registers
0x62FF (128 x 32) control registers) are EALLOW-protected.0x6300 256eCANB Mailbox RAM Not EALLOW-protected0x63FF (128 x 32)0x6800 64 Some ePWM registers are EALLOW protected.ePWM1 Registers
0x683F (32 x 32) See Table 4-20x6840 64 Some ePWM registers are EALLOW protected.ePWM2 Registers
0x687F (32 x 32) See Table 4-2.0x6880 64 Some ePWM registers are EALLOW protected.ePWM3 Registers
0x68BF (32 x 32) See Table 4-2.0x68C0 64 Some ePWM registers are EALLOW protected.ePWM4 Registers
0x68FF (32 x 32) See Table 4-2.0x6900 64 Some ePWM registers are EALLOW protected.ePWM5 Registers
0x693F (32 x 32) See Table 4-2.0x6940 64 Some ePWM registers are EALLOW protected.ePWM6 Registers
0x697F (32 x 32) See Table 4-2.0x6A00 32eCAP1 Registers Not EALLOW protected0x6A1F (16 x 32)0x6A20 32eCAP2 Registers Not EALLOW protected0x6A3F (16 x 32)0x6A40 32eCAP3 Registers Not EALLOW protected0x6A5F (16 x 32)0x6A60 32eCAP4 Registers Not EALLOW protected0x6A7F (16 x 32)0x6B00 64eQEP1 Registers Not EALLOW protected0x6B3F (32 x 32)0x6B40 64eQEP2 Registers Not EALLOW protected0x6B7F (32 x 32)0x6F80 128GPIO Control Registers EALLOW protected0x6FBF (64 x 32)0x6FC0 32GPIO Data Registers Not EALLOW protected0x6FDF (16 x 32)GPIO Interrupt and LPM 0x6FE0 32
EALLOW protectedSelect Registers 0x6FFF (16 x 32)
(1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.(2) Missing segments of memory space are reserved and should not be used in applications.
Table 3-8. Peripheral Frame 2 Registers
(1) (2)
NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE
0x7010System Control Registers 32 EALLOW Protected0x702F
0x7040SPI-A Registers 16 Not EALLOW Protected0x704F
0x7050SCI-A Registers 16 Not EALLOW Protected0x705F
(1) Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).(2) Missing segments of memory space are reserved and should not be used in applications.
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3.4 Device Emulation Registers
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Table 3-8. Peripheral Frame 2 Registers (continued)
NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE
0x7070External Interrupt Registers 16 Not EALLOW Protected0x707F
0x7100ADC Registers 32 Not EALLOW Protected0x711F
0x7740SPI-B Registers 16 Not EALLOW Protected0x774F
0x7750SCI-B Registers 16 Not EALLOW Protected0x775F
0x7760SPI-C Registers 16 Not EALLOW Protected0x776F
0x7780SPI-D Registers 16 Not EALLOW Protected0x778F
0x7900I
2
C Registers 48 Not EALLOW Protected0x792F
These registers are used to control the protection mode of the C28x CPU and to monitor some criticaldevice signals. The registers are defined in Table 3-9 .
Table 3-9. Device Emulation Registers
ADDRESSNAME SIZE (x16) DESCRIPTIONRANGE
0x0880DEVICECNF 2 Device Configuration Register0x0881PARTID 0x0882 1 Part ID Register 0x00, 0x01 - F281x0x03 - C281x/R281x
0x2C - F2801/9501
0x34 - F28060x3C - F2808REVID 0x0883 1 Revision ID Register (0x0000 - Silicon Rev. 0)(0x0001 - Silicon Rev. A)PROTSTART 0x0884 1 Block Protection Start Address RegisterPROTRANGE 0x0885 1 Block Protection Range Address Register
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3.5 Interrupts
XINT2
C28
CPU
CPU TIMER 2 (for TI/RTOS)
CPU TIMER 0
Watchdog
Peripherals
(SPI, SCI, I2C, eCAN, ePWM, eCAP, eQEP, ADC)
TINT0
Interrupt Control
XNMICR(15:0)
XINT1
Interrupt Control
XINT1
XINT1CR(15:0)
Interrupt Control
XINT2
XINT2CR(15:0)
GPIO
MUX
WDINT
INT1 to
INT12
INT13
INT14
NMI
XINT1CTR(15:0)
XINT2CTR(15:0)
XNMICTR(15:0)
CPU TIMER 1 (for TI)
TINT2
Low Power Modes
LPMINT
WAKEINT
TINT1
int13_select
XNMI_XINT13
GPIO0.int
GPIO31.int
ADC XINT2SOC
GPIOXINT1SEL(4:0)
GPIOXINT2SEL(4:0)
GPIOXNMISEL(4:0)
nmi_select
1
MUX
MUX
PIE
96 InterruptsMUXMUX
MUX
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Figure 3-5 shows how the various interrupt sources are multiplexed within the 280x devices.
Figure 3-5. External and PIE Interrupt Sources
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8interrupts per group equals 96 possible interrupts. On the 280x, 43 of these are used by peripherals asshown in Table 3-10 .
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INT12
MUX
INT11
INT2
INT1
CPU
(Enable)(Flag)
INTx
INTx.8
PIEIERx(8:1) PIEIFRx(8:1)
MUX
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
From
Peripherals or
External
Interrupts
(Enable) (Flag)
IER(12:1)IFR(12:1)
Global
Enable
INTM
1
0
PIEACKx
(Enable/Flag)
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Figure 3-6. Multiplexing of Interrupts Using the PIE Block
Table 3-10. PIE Peripheral Interrupts
(1)
PIE INTERRUPTSCPU INTER-
RUPTS
INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
WAKEINT TINT0 ADCINT SEQ2INT SEQ1INTINT1 XINT2 XINT1 reserved(LPM/WD) (TIMER 0) (ADC) (ADC) (ADC)
EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINTINT2 reserved reserved
(ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)
EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INTINT3 reserved reserved
(ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)
ECAP4_INT ECAP3_INT ECAP2_INT ECAP1_INTINT4 reserved reserved reserved reserved
(eCAP4) (eCAP3) (eCAP2) (eCAP1)
EQEP2_INT EQEP1_INTINT5 reserved reserved reserved reserved reserved reserved
(eQEP2) (eQEP1)
SPITXINTD SPIRXINTD SPITXINTC SPIRXINTC SPITXINTB SPIRXINTB SPITXINTA SPIRXINTAINT6
(SPI-D) (SPI-D) (SPI-C) (SPI-C) (SPI-B) (SPI-B) (SPI-A) (SPI-A)
INT7 reserved reserved reserved reserved reserved reserved reserved reserved
I2CINT2A I2CINT1AINT8 reserved reserved reserved reserved reserved reserved
(I2C-A) (I2C-A)
ECAN1_INTB ECAN0_INTB ECAN1_INTA ECAN0_INTA SCITXINTB SCIRXINTB SCITXINTA SCIRXINTAINT9
(CAN-B) (CAN-B) (CAN-A) (CAN-A) (SCI-B) (SCI-B) (SCI-A) (SCI-A)
INT10 reserved reserved reserved reserved reserved reserved reserved reserved
INT11 reserved reserved reserved reserved reserved reserved reserved reserved
INT12 reserved reserved reserved reserved reserved reserved reserved reserved
(1) Out of the 96 possible interrupts, 43 interrupts are currently used. The remaining interrupts are reserved for future devices. Theseinterrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group isbeing used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag whilemodifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:1) No peripheral within the group is asserting interrupts.2) No peripheral interrupts are assigned to the group (example PIE group 12).
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3.5.1 External Interrupts
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Table 3-11. PIE Configuration and Control Registers
NAME ADDRESS SIZE (X16) DESCRIPTION
(1)
PIECTRL 0x0CE0 1 PIE, Control RegisterPIEACK 0x0CE1 1 PIE, Acknowledge RegisterPIEIER1 0x0CE2 1 PIE, INT1 Group Enable RegisterPIEIFR1 0x0CE3 1 PIE, INT1 Group Flag RegisterPIEIER2 0x0CE4 1 PIE, INT2 Group Enable RegisterPIEIFR2 0x0CE5 1 PIE, INT2 Group Flag RegisterPIEIER3 0x0CE6 1 PIE, INT3 Group Enable RegisterPIEIFR3 0x0CE7 1 PIE, INT3 Group Flag RegisterPIEIER4 0x0CE8 1 PIE, INT4 Group Enable RegisterPIEIFR4 0x0CE9 1 PIE, INT4 Group Flag RegisterPIEIER5 0x0CEA 1 PIE, INT5 Group Enable RegisterPIEIFR5 0x0CEB 1 PIE, INT5 Group Flag RegisterPIEIER6 0x0CEC 1 PIE, INT6 Group Enable RegisterPIEIFR6 0x0CED 1 PIE, INT6 Group Flag RegisterPIEIER7 0x0CEE 1 PIE, INT7 Group Enable RegisterPIEIFR7 0x0CEF 1 PIE, INT7 Group Flag RegisterPIEIER8 0x0CF0 1 PIE, INT8 Group Enable RegisterPIEIFR8 0x0CF1 1 PIE, INT8 Group Flag RegisterPIEIER9 0x0CF2 1 PIE, INT9 Group Enable RegisterPIEIFR9 0x0CF3 1 PIE, INT9 Group Flag RegisterPIEIER10 0x0CF4 1 PIE, INT10 Group Enable RegisterPIEIFR10 0x0CF5 1 PIE, INT10 Group Flag RegisterPIEIER11 0x0CF6 1 PIE, INT11 Group Enable RegisterPIEIFR11 0x0CF7 1 PIE, INT11 Group Flag RegisterPIEIER12 0x0CF8 1 PIE, INT12 Group Enable RegisterPIEIFR12 0x0CF9 1 PIE, INT12 Group Flag RegisterReserved 0x0CFA 6 Reserved0x0CFF
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vectortable is protected.
Table 3-12. External Interrupt Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
XINT1CR 0x7070 1 XINT1 control registerXINT2CR 0x7071 1 XINT2 control register0x7072reserved 50x7076XNMICR 0x7077 1 XNMI control registerXINT1CTR 0x7078 1 XINT1 counter registerXINT2CTR 0x7079 1 XINT2 counter register0x707Areserved 50x707EXNMICTR 0x707F 1 XNMI counter register
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3.6 System Control
PLL
X1
X2
Power
Modes
Control
Watchdog
Block
28x
CPU
Peripheral Bus
Low-Speed Peripherals
SCI-A/B, SPI-A/B/C/D
Peripheral
Registers
High-Speed Prescaler
Low-Speed Prescaler
Clock Enables
GPIO
MUX
System
Control
Registers
XCLKIN
ADC
Registers 12-Bit ADC 16 ADC inputs
LSPCLK
I/O
Peripheral Reset
SYSCLKOUT(A) XRS
Reset
GPIOs
Peripheral
Registers I/O
OSC
CLKIN(A)
HSPCLK
eCAN-A/B
I2C-A
Peripheral
Registers I/O
ePWM 1/2/3/4/5/6
eCAP 1/2/3/4 eQEP 1/2
Peripheral
Registers CPU
Timers
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Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive andnegative edge. For more information, see the TMS320x280x System Control and Interrupts ReferenceGuide (literature number SPRU712).
This section describes the 280x oscillator, PLL and clocking mechanisms, the watchdog function and thelow power modes. Figure 3-7 shows the various clock and reset domains in the 280x devices that will bediscussed.
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequencyas SYSCLKOUT).
Figure 3-7. Clock and Reset Domains
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3.6.1 OSC and PLL Block
X1
XCLKIN
(3.3-V clock input)
On chip
oscillator
X2
xor
PLLSTS[OSCOFF]
OSCCLK
PLL VCOCLK
4-bit PLL Select (PLLCR)
OSCCLK or
VCOCLK /2 CLKIN
OSCCLK 0
PLLSTS[PLLOFF]
nn ≠ 0
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The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-13 .
Table 3-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers
(1)
NAME ADDRESS SIZE (x16) DESCRIPTION
XCLK 0x7010 1 XCLKOUT Pin Control and X1 and XCLKIN Status RegisterPLLSTS 0x7011 1 PLL Status Register0x7012reserved 80x7019HISPCP 0x701A 1 High-Speed Peripheral Clock Prescaler RegisterLOSPCP 0x701B 1 Low-Speed Peripheral Clock Prescaler RegisterPCLKCR0 0x701C 1 Peripheral Clock Control Register 0PCLKCR1 0x701D 1 Peripheral Clock Control Register 1LPMCR0 0x701E 1 Low Power Mode Control Register 00x701Freserved 10x7020PLLCR 0x7021 1 PLL Control RegisterSCSR 0x7022 1 System Control and Status RegisterWDCNTR 0x7023 1 Watchdog Counter Registerreserved 0x7024 1WDKEY 0x7025 1 Watchdog Reset Key Register0x7026reserved 30x7028WDCR 0x7029 1 Watchdog Control Register0x702Areserved 60x702F
(1) All of the registers in this table are EALLOW protected.
Figure 3-8 shows the OSC and PLL block on the 280x.
Figure 3-8. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal to be attached to the 280x devices using the X1 and X2pins. If a crystal is not used, an external oscillator can be directly connected to the XCLKIN pin, the X2 pinis left unconnected, and X1 is tied low. The logic-high level in this case should not exceed V
DDIO
. ThePLLCR bits [3:0] set the clocking ratio.
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Table 3-14. PLLCR Register Bit Definitions
VALUE DESCRIPTION
0000 (PLL bypass) CLKIN = OSCCLK/20001 CLKIN = (OSCCLK*1)/20010 CLKIN = (OSCCLK*2)/20011 CLKIN = (OSCCLK*3)/20100 CLKIN = (OSCCLK*4)/20101 CLKIN = (OSCCLK*5)/20110 CLKIN = (OSCCLK*6)/20111 CLKIN = (OSCCLK*7)/21000 CLKIN = (OSCCLK*8)/21001 CLKIN = (OSCCLK*9)/21010 CLKIN = (OSCCLK*10)/21011-1111 reserved
3.6.1.1 Loss of Input Clock
In PLL-enabled and PLL-bypass mode, if the input clock XCLKIN or the oscillator clock is removed orabsent, the PLL will still issue a "limp-mode" clock. The limp-mode clock continues to clock the CPU andperipherals at a typical frequency of 1-4 MHz. Limp mode is not specified to work from power-up, onlyafter input clocks have been present initially. In PLL bypass mode, the limp mode clock from the PLL isautomatically routed to the CPU if the input clock is removed or absent.
Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdogreset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stopsdecrementing (i.e., the watchdog counter does not change with the limp-mode clock). In addition to this,the device will be reset and the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions couldbe used by the application firmware to detect the input clock failure and initiate necessary shut-downprocedure for the system.
3.6.1.2 PLL-Based Clock Module
The 280x devices have an on-chip, PLL-based clock module. This module provides all the necessaryclocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratiocontrol to select different CPU clock rates. The watchdog module should be disabled before writing to thePLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 131072XCLKIN cycles.
The PLL-based clock module provides two modes of operation:•Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time baseto the device.•External clock source operation - This mode allows the internal oscillator to be bypassed. The deviceclocks are generated from an external clock source input on the XCLKIN pin.
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External Clock Signal
(Toggling 0−VDD)
CL1(A)
X2X1 XCLKIN X2
Crystal CL2(A)
(a) (b)
NC
X1
XCLKIN
3.6.2 External Reference Oscillator Clock Option
3.6.3 Watchdog Block
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A. TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with theDSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can alsoadvise the customer regarding the proper tank component values that will produce proper start up and stability overthe entire operating range.
Figure 3-9. Recommended Crystal/Clock Connection
Table 3-15. Possible PLL Configuration Modes
PLL MODE REMARKS SYSCLKOUT
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLLblock is disabled in this mode. This can be useful to reduce system noise andPLL Off for low power operation. The PLLCR register must first be set to 0x0000 (PLL OSCCLK/2Bypass) before entering this mode. The CPU clock (CLKIN) is derived directlyfrom the input clock on either X1/X2 or XCLKIN divided by 2.PLL Bypass is the default PLL configuration upon power-up or after anexternal reset ( XRS). This mode is selected when the PLLCR register is set toPLL Bypass 0x0000 or while the PLL locks to a new frequency after the PLLCR register OSCCLK/2has been modified. In this mode, the PLL itself is bypassed but the PLL is notturned off.Achieved by writing a non-zero value n into the PLLCR register. Upon writingPLL Enable OSCCLK*n/2to the PLLCR the device will switch to PLL Bypass mode until the PLL locks.
The typical specifications for the external quartz crystal for a frequency of 20 MHz are listed below:•Fundamental mode, parallel resonant•C
L
(load capacitance) = 12 pF•C
L1
= C
L2
= 24 pF•C
shunt
= 6 pF•ESR range = 30 to 60 Ω
The watchdog block on the 280x is similar to the one used on the 240x and 281x devices. The watchdogmodule generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog upcounter has reached its maximum value. To prevent this, the user disables the counter or the softwaremust periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset thewatchdog counter. Figure 3-10 shows the various functional blocks within the watchdog module.
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/512
OSCCLK
WDCR (WDPS(2:0))
WDCLK
WDCNTR(7:0)
WDKEY(7:0) Bad Key
Good Key
101
WDCR (WDCHK(2:0))
Bad
WDCHK
Key
WDCR (WDDIS)
Clear Counter
SCSR (WDENINT)
Watchdog
Prescaler
Generate
Output Pulse
(512 OSCCLKs)
8-Bit
Watchdog
Counter
CLR
WDRST
WDINT
Watchdog
55 + AA
Key Detector
XRS
Core-reset
WDRST(A)
Internal
Pullup
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A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3-10. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remainsfunctional is the watchdog. The WATCHDOG module will run off the PLL clock or the oscillator clock. TheWDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). SeeSection Section 3.7 , Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out ofIDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence sois the WATCHDOG.
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3.7 Low-Power Modes Block
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The low-power modes on the 280x are similar to the 240x devices. Table 3-16 summarizes the variousmodes.
Table 3-16. Low-Power Modes
MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT EXIT
(1)
XRS,
Watchdog Interrupt,IDLE 00 On On On
(2)
Any Enabled Interrupt,XNMI
XRS,On Watchdog Interrupt,STANDBY 01 Off Off(watchdog still running) GPIO Port A signal,Debugger
(3)
, XNMIOff
XRS,HALT 1X (oscillator and PLL turned off, Off Off
XNMI ,Debugger
(3)watchdog not functional)
(1) The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, willexit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise theIDLE mode will not be exited and the device will go back into the indicated low power mode.(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) isstill functional while on the 24x/240x the clock is turned off.(3) On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode: This mode is exited by any enabled interrupt or an XNMI that is recognized bythe processor. The LPM block performs no tasks during this mode as long as theLPMCR0(LPM) bits are set to 0,0.STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBYmode. The user must select which signal(s) will wake the device in theGPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLKbefore waking the device. The number of OSCCLKs is specified in the LPMCR0register.HALT Mode: Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the devicefrom HALT mode. The user selects the signal in the GPIOLPMSEL register.
NOTEThe low-power modes do not affect the state of the output pins (PWM pins included).They will be in whatever state the code left them in when the IDLE instruction wasexecuted. See the TMS320x280x System Control and Interrupts Reference Guide(literature number SPRU712) for more details.
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4 Peripherals
4.1 32-Bit CPU-Timers 0/1/2
Borrow
Reset
Timer Reload
SYSCLKOUT
TCR.4
(Timer Start Status)
TINT
16-Bit Timer Divide-Down
TDDRH:TDDR 32-Bit Timer Period
PRDH:PRD
32-Bit Counter
TIMH:TIM
16-Bit Prescale Counter
PSCH:PSC
Borrow
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The integrated peripherals of the 280x are described in the following subsections:•Three 32-bit CPU-Timers•Up to six enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6)•Up to four enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4)•Up to two enhanced QEP modules (eQEP1, eQEP2)•Enhanced analog-to-digital converter (ADC) module•Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)•Up to two serial communications interface modules (SCI-A, SCI-B)•Up to four serial peripheral interface (SPI) modules (SPI-A, SPI-B, SPI-C, SPI-D)•Inter-integrated circuit module (I
2
C)•Digital I/O and shared pin functions
There are three 32-bit CPU-timers on the 280x devices (CPU-TIMER0/1/2).
CPU-Timer 1 is reserved for TI system functions and Timer 2 is reserved for DSP/BIOS™. CPU-Timer 0can be used in user applications. These timers are different from the timers that are present in the ePWMmodules.
NOTENOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in theapplication.
Figure 4-1. CPU-Timers
In the 280x devices, the timer interrupt signals ( TINT0, TINT1, TINT2) are connected as shown inFigure 4-2 .
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INT1
to
INT12
INT14
C28x
TINT2
TINT0
PIE CPU-TIMER 0
CPU-TIMER 2
(Reserved for
DSP/BIOS)
INT13 TINT1 CPU-TIMER 1
(Reserved for TI
system functions)
XINT13
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
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A. The timer registers are connected to the memory bus of the C28x processor.B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.C. While TIMER1 is reserved, INT13 is not reserved and the user can use XINT13 connected to INT13.
Figure 4-2. CPU-Timer Interrupt Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with thevalue in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of theC28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. Theregisters listed in Table 4-1 are used to configure the timers. For more information, see the TMS320x280xSystem Control and Interrupts Reference Guide (literature number SPRU712).
Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
TIMER0TIM 0x0C00 1 CPU-Timer 0, Counter RegisterTIMER0TIMH 0x0C01 1 CPU-Timer 0, Counter Register HighTIMER0PRD 0x0C02 1 CPU-Timer 0, Period RegisterTIMER0PRDH 0x0C03 1 CPU-Timer 0, Period Register HighTIMER0TCR 0x0C04 1 CPU-Timer 0, Control Registerreserved 0x0C05 1TIMER0TPR 0x0C06 1 CPU-Timer 0, Prescale RegisterTIMER0TPRH 0x0C07 1 CPU-Timer 0, Prescale Register HighTIMER1TIM 0x0C08 1 CPU-Timer 1, Counter RegisterTIMER1TIMH 0x0C09 1 CPU-Timer 1, Counter Register HighTIMER1PRD 0x0C0A 1 CPU-Timer 1, Period RegisterTIMER1PRDH 0x0C0B 1 CPU-Timer 1, Period Register HighTIMER1TCR 0x0C0C 1 CPU-Timer 1, Control Registerreserved 0x0C0D 1TIMER1TPR 0x0C0E 1 CPU-Timer 1, Prescale RegisterTIMER1TPRH 0x0C0F 1 CPU-Timer 1, Prescale Register HighTIMER2TIM 0x0C10 1 CPU-Timer 2, Counter RegisterTIMER2TIMH 0x0C11 1 CPU-Timer 2, Counter Register HighTIMER2PRD 0x0C12 1 CPU-Timer 2, Period RegisterTIMER2PRDH 0x0C13 1 CPU-Timer 2, Period Register HighTIMER2TCR 0x0C14 1 CPU-Timer 2, Control Register
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4.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6)
PIE
TZ1 to TZ6
Peripheral Bus
ePWM1 module
ePWM2 module
ePWMx module
SYNCO
SYNCI
SYNCI
SYNCO
SYNCI
SYNCO
ADC
GPIO
MUX
xSYNCI
xSYNCO
to eCAP1 module (sync in)
xSOC
EPWMxA
EPWMxB
EPWM2A
EPWM2B
EPWM1A
EPWM1B
EPWM1INT
EPWM1SOC
EPWM2INT
EPWM2SOC
EPWMxINT
EPWMxSOC
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
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Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers (continued)
NAME ADDRESS SIZE (x16) DESCRIPTION
reserved 0x0C15 1TIMER2TPR 0x0C16 1 CPU-Timer 2, Prescale RegisterTIMER2TPRH 0x0C17 1 CPU-Timer 2, Prescale Register High0x0C18reserved 400x0C3F
The 280x device contains up to six enhanced PWM Modules (ePWM). Figure 4-3 shows a block diagramof multiple PWM modules. Figure 4-4 shows the signal interconnections with the ePWM. See theTMS320x280x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (literature numberSPRU791) for more details.
Figure 4-3. Multiple PWM Modules in a 280x System
Table 4-2 shows the complete ePWM register set per module.
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TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Table 4-2. ePWM Control and Status Registers
NAME EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 SIZE (x16) / DESCRIPTION#SHADOW
TBCTL 0x6800 0x6840 0x6880 0x68C0 0x6900 0x6940 1 / 0 Time Base Control RegisterTBSTS 0x6801 0x6841 0x6881 0x68C1 0x6901 0x6941 1 / 0 Time Base Status RegisterTBPHSHR 0x6802 0x6842 0x6882 0x68C2 N/A N/A 1 / 0 Time Base Phase HiRes RegisterTBPHS 0x6803 0x6843 0x6883 0x68C3 0x6903 0x6943 1 / 0 Time Base Phase RegisterTBCNT 0x6804 0x6844 0x6884 0x68C4 0x6904 0x6944 1 / 0 Time Base Counter RegisterTBPRD 0x6805 0x6845 0x6885 0x68C5 0x6905 0x6945 1 / 1 Time Base Period Register SetCMPCTL 0x6807 0x6847 0x6887 0x68C7 0x6907 0x6947 1 / 0 Counter Compare Control RegisterCMPAHR 0x6808 0x6848 0x6888 0x68C8 N/A N/A 1 / 1 Time Base Compare A HiRes RegisterCMPA 0x6809 0x6849 0x6889 0x68C9 0x6909 0x6949 1 / 1 Counter Compare A Register SetCMPB 0x680A 0x684A 0x688A 0x68CA 0x690A 0x694A 1 / 1 Counter Compare B Register SetAQCTLA 0x680B 0x684B 0x688B 0x68CB 0x690B 0x694B 1 / 0 Action Qualifier Control Register For Output AAQCTLB 0x680C 0x684C 0x688C 0x68CC 0x690C 0x694C 1 / 0 Action Qualifier Control Register For Output BAQSFRC 0x680D 0x684D 0x688D 0x68CD 0x690D 0x694D 1 / 0 Action Qualifier Software Force RegisterAQCSFRC 0x680E 0x684E 0x688E 0x68CE 0x690E 0x694E 1 / 1 Action Qualifier Continuous S/W Force Register SetDBCTL 0x680F 0x684F 0x688F 0x68CF 0x690F 0x694F 1 / 1 Dead-Band Generator Control RegisterDBRED 0x6810 0x6850 0x6890 0x68D0 0x6910 0x6950 1 / 0 Dead-Band Generator Rising Edge Delay Count RegisterDBFED 0x6811 0x6851 0x6891 0x68D1 0x6911 0x6951 1 / 0 Dead-Band Generator Falling Edge Delay Count RegisterTZSEL 0x6812 0x6852 0x6892 0x68D2 0x6912 0x6952 1 / 0 Trip Zone Select Register
(1)
TZCTL 0x6814 0x6854 0x6894 0x68D4 0x6914 0x6954 1 / 0 Trip Zone Control Register
(1)
TZEINT 0x6815 0x6855 0x6895 0x68D5 0x6915 0x6955 1 / 0 Trip Zone Enable Interrupt Register
(1)
TZFLG 0x6816 0x6856 0x6896 0x68D6 0x6916 0x6956 1 / 0 Trip Zone Flag RegisterTZCLR 0x6817 0x6857 0x6897 0x68D7 0x6917 0x6957 1 / 0 Trip Zone Clear Register
(1)
TZFRC 0x6818 0x6858 0x6898 0x68D8 0x6918 0x6958 1 / 0 Trip Zone Force Register
(1)
ETSEL 0x6819 0x6859 0x6899 0x68D9 0x6919 0x6959 1 / 0 Event Trigger Selection RegisterETPS 0x681A 0x685A 0x689A 0x68DA 0x691A 0x695A 1 / 0 Event Trigger Prescale RegisterETFLG 0x681B 0x685B 0x689B 0x68DB 0x691B 0x695B 1 / 0 Event Trigger Flag RegisterETCLR 0x681C 0x685C 0x689C 0x68DC 0x691C 0x695C 1 / 0 Event Trigger Clear RegisterETFRC 0x681D 0x685D 0x689D 0x68DD 0x691D 0x695D 1 / 0 Event Trigger Force RegisterPCCTL 0x681E 0x685E 0x689E 0x68DE 0x691E 0x695E 1 / 0 PWM Chopper Control RegisterHRCNFG 0x6820 0x6860 0x68A0 0x68E0 N/A N/A 1 / 0 HiRes Configuration Register
(1) Registers that are EALLOW protected.
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CTR=PRD
TBPRD shadow (16)
TBPRD active (16)
Counter
up/down
(16 bit)
TBCNT
active (16)
TBCTL[CNTLDE]
TBCTL[SWFSYNC]
(software forced sync)
EPWMxSYNCI
CTR=ZERO
CTR_Dir
CTR=CMPB
Disabled
Sync
in/out
select
Mux
TBCTL[SYNCOSEL]
EPWMxSYNCO
TBPHS active (24)
16 8TBPHSHR (8)
Phase
control
Time−base (TB)
CTR=CMPA
CMPA active (24)
16
CMPA shadow (24)
Action
qualifier
(AQ)
8
16
Counter compare (CC)
CMPB active (16)
CTR=CMPB
CMPB shadow (16)
CMPAHR (8)
EPWMA
EPWMB
Dead
band
(DB) (PC)
chopper
PWM zone
(TZ)
Trip
CTR = ZERO
EPWMxAO
EPWMxBO
EPWMxTZINT
TZ1 to TZ6
HiRes PWM (HRPWM)
CTR = PRD
CTR = ZERO
CTR = CMPB
CTR = CMPA
CTR_Dir
Event
trigger
and
interrupt
(ET)
EPWMxINT
EPWMxSOCA
EPWMxSOCB
CTR=ZERO
4.3 Hi-Resolution PWM (HRPWM)
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
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Figure 4-4. ePWM Sub-modules Showing Critical Internal Signal Interconects
The HRPWM module offers PWM resolution (time granularity) which is significantly better than what canbe achieved using conventionally derived digital PWM methods. The key points for the HRPWM moduleare:
•Significantly extends the time resolution capabilities of conventionally derived digital PWM•Typically used when effective PWM resolution falls below ~ 9-10 bits. This occurs at PWM frequenciesgreater than ~200 KHz when using a CPU/System clock of 100 MHz.•This capability can be utilized in both duty cycle and phase-shift control methods.•Finer time granularity control or edge positioning is controlled via extensions to the Compare A andPhase registers of the ePWM module.•HRPWM capabilities are offered only on the A signal path of an ePWM module (i.e., on the EPWMxAoutput). EPWMxB output has conventional PWM capabilities.
Only PWM channels ePWM 1A, 2A, 3A, 4A support HRPWM features. The remaining ePWMchannels do not support the HRPWM features.
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4.4 Enhanced CAP Modules (eCAP1/2/3/4)
TSCTR
(counter−32 bit) RST
CAP1
(APRD active) LD
CAP2
(ACMP active) LD
CAP3
(APRD shadow) LD
CAP4
(ACMP shadow) LD
Continuous /
Oneshot
Capture Control
LD1
LD2
LD3
LD4
32
32
PRD [0−31]
CMP [0−31]
CTR [0−31]
eCAPx
Interrupt
Trigger
and
Flag
control
to PIE
CTR=CMP
32
32
32
32
32
ACMP
shadow Event
Pre-scale
CTRPHS
(phase register−32 bit)
SYNCOut
SYNCIn
Event
qualifier
Polarity
select
Polarity
select
Polarity
select
Polarity
select
CTR=PRD
CTR_OVF
4
PWM
compare
logic
CTR [0−31]
PRD [0−31]
CMP [0−31]
CTR=CMP
CTR=PRD
CTR_OVF
OVF
APWM mode
Delta−mode
SYNC
4
Capture events
CEVT[1:4]
APRD
shadow
32
32
MODE SELECT
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
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The 280x device contains up to four enhanced capture (eCAP) modules. Figure 4-5 shows a functionalblock diagram of a module. See the TMS320x280x Enhanced Capture (eCAP) Module Reference Guide(literature number SPRU807) for more details.
The eCAP modules are clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1/2/3/4ENCLK) in the PCLKCR1 register are used to turn off the eCAPmodules individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK,ECAP3ENCLK, and ECAP4ENCLK are set to low, indicating that the peripheral clock is off.
Figure 4-5. eCAP Functional Block Diagram
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Table 4-3. eCAP Control and Status Registers
NAME ECAP1 ECAP2 ECAP3 ECAP4 SIZE DESCRIPTION
(x16)
TSCTR 0x6A00 0x6A20 0x6A40 0x6A60 2 Time-Stamp CounterCTRPHS 0x6A02 0x6A22 0x6A42 0x6A62 2 Counter Phase Offset Value RegisterCAP1 0x6A04 0x6A24 0x6A44 0x6A64 2 Capture 1 RegisterCAP2 0x6A06 0x6A26 0x6A46 0x6A66 2 Capture 2 RegisterCAP3 0x6A08 0x6A28 0x6A48 0x6A68 2 Capture 3 RegisterCAP4 0x6A0A 0x6A2A 0x6A4A 0x6A6A 2 Capture 4 RegisterReserved 0x6A0C- 0x6A2C- 0x6A4C- 0x6A6C- 80x6A12 0x6A32 0x6A52 0x6A72ECCTL1 0x6A14 0x6A34 0x6A54 0x6A74 1 Capture Control Register 1ECCTL2 0x6A15 0x6A35 0x6A55 0x6A75 1 Capture Control Register 2ECEINT 0x6A16 0x6A36 0x6A56 0x6A76 1 Capture Interrupt Enable RegisterECFLG 0x6A17 0x6A37 0x6A57 0x6A77 1 Capture Interrupt Flag RegisterECCLR 0x6A18 0x6A38 0x6A58 0x6A78 1 Capture Interrupt Clear RegisterECFRC 0x6A19 0x6A39 0x6A59 0x6A79 1 Capture Interrupt Force RegisterReserved 0x6A1A- 0x6A3A- 0x6A5A- 0x6A7A- 60x6A1F 0x6A3F 0x6A5F 0x6A7F
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4.5 Enhanced QEP Modules (eQEP1/2)
QWDTMR
QWDPRD
16
QWDOGUTIME
QUPRD
QUTMR
32
UTOUT
WDTOUT
Quadrature
capture unit
(QCAP)
QCPRDLAT
QCTMRLAT
16
QFLG
QEPSTS
QEPCTL
Registers
used by
multiple units
QCLK
QDIR
QI
QS
PHE
PCSOUT
Quadrature
decoder
(QDU)
QDECCTL
16
Position counter/
control unit
(PCCU)
QPOSLAT
QPOSSLAT
16
QPOSILAT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
GPIO
MUX
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxS
EQEPxI
QPOSCMP QEINT
QFRC
32
QCLR
QPOSCTL
1632
QPOSCNT
QPOSMAX
QPOSINIT
PIE EQEPxINT
Enhanced QEP (eQEP) peripheral
System
control registers
QCTMR
QCPRD
1616
QCAPCTL
EQEPxENCLK
SYSCLKOUT
Data bus
To CPU
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
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The 280x device contains up to two enhanced quadrature encoder (eQEP) modules. See theTMS320x280x Enhanced Quadrature Encoder (eQEP) Module Reference Guide (literature numberSPRU790) for more details.
Figure 4-6. eQEP Functional Block Diagram
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Table 4-4. eQEP Control and Status Registers
NAME EQEP1 AD- EQEP2 AD- EQEP1 REGISTER DESCRIPTIONDRESS DRESS SIZE(x16)/
#SHADOW
QPOSCNT 0x6B00 0x6B40 2/0 eQEP Position CounterQPOSINIT 0x6B02 0x6B42 2/0 eQEP Initialization Position CountQPOSMAX 0x6B04 0x6B44 2/0 eQEP Maximum Position CountQPOSCMP 0x6B06 0x6B46 2/1 eQEP Position-compareQPOSILAT 0x6B08 0x6B48 2/0 eQEP Index Position LatchQPOSSLAT 0x6B0A 0x6B4A 2/0 eQEP Strobe Position LatchQPOSLAT 0x6B0C 0x6B4C 2/0 eQEP Position LatchQUTMR 0x6B0E 0x6B4E 2/0 eQEP Unit TimerQUPRD 0x6B10 0x6B50 2/0 eQEP Unit Period RegisterQWDTMR 0x6B12 0x6B52 1/0 eQEP Watchdog TimerQWDPRD 0x6B13 0x6B53 1/0 eQEP Watchdog Period RegisterQDECCTL 0x6B14 0x6B54 1/0 eQEP Decoder Control RegisterQEPCTL 0x6B15 0x6B55 1/0 eQEP Control RegisterQCAPCTL 0x6B16 0x6B56 1/0 eQEP Capture Control RegisterQPOSCTL 0x6B17 0x6B57 1/0 eQEP Position-compare Control RegisterQEINT 0x6B18 0x6B58 1/0 eQEP Interrupt Enable RegisterQFLG 0x6B19 0x6B59 1/0 eQEP Interrupt Flag RegisterQCLR 0x6B1A 0x6B5A 1/0 eQEP Interrupt Clear RegisterQFRC 0x6B1B 0x6B5B 1/0 eQEP Interrupt Force RegisterQEPSTS 0x6B1C 0x6B5C 1/0 eQEP Status RegisterQCTMR 0x6B1D 0x6B5D 1/0 eQEP Capture TimerQCPRD 0x6B1E 0x6B5E 1/0 eQEP Capture Period RegisterQCTMRLAT 0x6B1F 0x6B5F 1/0 eQEP Capture Timer LatchQCPRDLAT 0x6B20 0x6B60 1/0 eQEP Capture Period LatchReserved 0x6B21- 0x6B61- 31/00x6B3F 0x6B7F
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4.6 Enhanced Analog-to-Digital Converter (ADC) Module
Digital Value 0,
Digital Value 4096 Input Analog Voltage ADCLO
3
when input ≤ 0 V
when 0 V < input < 3 V
when input ≥ 3 VDigital Value 4095,
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
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A simplified functional block diagram of the ADC module is shown in Figure 4-7 . The ADC moduleconsists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC moduleinclude:
•12-bit ADC core with built-in S/H•Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)•Fast conversion rate: 160 ns at 12.5-MHz ADC clock, 6.25 MSPS•16-channel, MUXed inputs•Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversioncan be programmed to select any 1 of 16 input channels•Sequencer can be operated as two independent 8-state sequencers or as one large 16-statesequencer (i.e., two cascaded 8-state sequencers)•Sixteen result registers (individually addressable) to store conversion values– The digital value of the input analog voltage is derived by:
A. All fractional values are truncated.•Multiple triggers as sources for the start-of-conversion (SOC) sequence– S/W - software immediate start– ePWM start of conversion– XINT2 ADC start of conversion•Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS.•Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" tosynchronize conversions.•SOCA and SOCB triggers can operate independently in dual-sequencer mode.•Sample-and-hold (S/H) acquisition time window has separate prescale control.
The ADC module in the 280x has been enhanced to provide flexible interface to ePWM peripherals. TheADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 160 ns at 12.5-MHzADC clock. The ADC module has 16 channels, configurable as two independent 8-channel modules. Thetwo independent 8-channel modules can be cascaded to form a 16-channel module. Although there aremultiple input channels and two sequencers, there is only one converter in the ADC module. Figure 4-7shows the block diagram of the ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each modulehas the choice of selecting any one of the respective eight channels available through an analog MUX. Inthe cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer,once the conversion is complete, the selected channel value is stored in its respective RESULT register.Autosequencing allows the system to convert the same channel multiple times, allowing the user toperform oversampling algorithms. This gives increased resolution over traditional single-sampled conver-sion results.
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Result Registers
EPWMSOCB
S/W
GPIO/XINT2
_ADCSOC
EPWMSOCA
S/W
Sequencer 2
Sequencer 1 SOCSOC
ADC Control Registers
70B7h
70B0h
70AFh
70A8h
Result Reg 15
Result Reg 8
Result Reg 7
Result Reg 1
Result Reg 0
Module
ADC
12-Bit
Analog
MUX
ADCINA0
ADCINA7
ADCINB0
ADCINB7
System
Control Block High-Speed
Prescaler
HSPCLK
ADCENCLK
DSP
SYSCLKOUT
S/H
S/H
HALT
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Figure 4-7. Block Diagram of the ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extentpossible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths.This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs.Furthermore, proper isolation techniques must be used to isolate the ADC module power pins ( V
DD1A18
,V
DD2A18
, V
DDA2
, V
DDAIO
) from the digital supply. Figure 4-8 shows the ADC pin connections for the 280xdevices.
NOTE1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of theADC module is controlled by the high-speed peripheral clock (HSPCLK).2. The behavior of the ADC module based on the state of the ADCENCLK and HALTsignals is as follows:–ADCENCLK: On reset, this signal will be low. While reset is active-low ( XRS) theclock to the register will still function. This is necessary to make sure all registersand modes go into their default reset state. The analog module, however, will bein a low-power inactive state. As soon as reset goes high, then the clock to theregisters will be disabled. When the user sets the ADCENCLK signal high, thenthe clocks to the registers will be enabled and the analog module will be enabled.There will be a certain time delay (ms range) before the ADC is stable and can beused.
–HALT: This mode only affects the analog module. It does not affect the registers.In this mode, the ADC module goes into low-power mode. This mode also will stopthe clock to the CPU, which will stop the HSPCLK; therefore, the ADC registerlogic will be turned off indirectly.
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ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCREFIN
ADC External Current Bias Resistor ADCRESEXT
ADCREFP
VDD1A18
VDD2A18
VSS1AGND
VSS2AGND
VDDAIO
VSSAIO
VDDA2
VSSA2
ADC Reference Positive Output
ADCREFMADC Reference Medium Output
ADC Power
ADC Analog and Reference I/O Power
Analog input 0−3 V with respect to ADCLO
Connect to analog ground
22 k
2.2 F (A)
2.2 F (A)
ADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin
ADC Analog Power Pin (3.3 V)
ADCREFP and ADCREFM should not
be loaded by external circuitry
ADC Analog Ground Pin
ADC 16-Channel Analog Inputs
2.048 V, float or ground if internal reference is used
ADC Analog Ground Pin
ADC Analog Ground Pin
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
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Figure 4-8 shows the ADC pin-biasing for internal reference and Figure 4-9 shows the ADC pin-biasing forexternal reference.
A. TAIYO YUDEN LMK212BJ225MG-T or equivalentB. External decoupling capacitors are recommended on all power pins.C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 4-8. ADC Pin Connections With Internal Reference
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ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCREFIN
ADC External Current Bias Resistor ADCRESEXT
ADCREFP
VDD1A18
VDD2A18
VSS1AGND
VSS2AGND
VDDAIO
VSSAIO
VDDA2
VSSA2
ADC Reference Positive Output
ADCREFMADC Reference Medium Output
ADC Analog Power
ADC Analog and Reference I/O Power
Analog input 0−3 V with respect to ADCLO
Connect to Analog Ground
22 k
2.2 F (A)
2.2 F (A) ADCREFP and ADCREFM should not
be loaded by external circuitry
ADC 16-Channel Analog Inputs
Connect to 2.048-V precision source (D)
ADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)
ADC Analog I/O Ground Pin
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
ADC Analog Ground Pin
ADC Analog Ground Pin
ADC Analog Power Pin (3.3 V)
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
A. TAIYO YUDEN LMK212BJ225MG-T or equivalentB. External decoupling capacitors are recommended on all power pins.C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.D. External voltage on ADCREFIN is enabled by changing bits 15:14 in the ADC Reference Select register depending onthe voltage used on this pin. TI recommends TI part REF3020 or equivalent for 2.048-V generation. Overall gainaccuracy will be determined by accuracy of this voltage source.
Figure 4-9. ADC Pin Connections With External Reference
NOTEThe temperature rating of any recommended component must match the rating of the endproduct.
The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-5 .
Table 4-5. ADC Registers
(1)
NAME ADDRESS
(1)
ADDRESS
(2)
SIZE (x16) DESCRIPTION
ADCTRL1 0x7100 1 ADC Control Register 1ADCTRL2 0x7101 1 ADC Control Register 2ADCMAXCONV 0x7102 1 ADC Maximum Conversion Channels RegisterADCCHSELSEQ1 0x7103 1 ADC Channel Select Sequencing Control Register 1ADCCHSELSEQ2 0x7104 1 ADC Channel Select Sequencing Control Register 2ADCCHSELSEQ3 0x7105 1 ADC Channel Select Sequencing Control Register 3ADCCHSELSEQ4 0x7106 1 ADC Channel Select Sequencing Control Register 4ADCASEQSR 0x7107 1 ADC Auto-Sequence Status RegisterADCRESULT0 0x7108 0x0B00 1 ADC Conversion Result Buffer Register 0ADCRESULT1 0x7109 0x0B01 1 ADC Conversion Result Buffer Register 1ADCRESULT2 0x710A 0x0B02 1 ADC Conversion Result Buffer Register 2ADCRESULT3 0x710B 0x0B03 1 ADC Conversion Result Buffer Register 3
(1) The registers in this column are Peripheral Frame 2 Registers.(2) The ADC result registers are dual mapped in the 280x DSP. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait states and leftjustified. Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 0 wait sates and right justified. During high speed/continuousconversion use of the ADC, use the 0 wait state locations for fast transfer of ADC results to user memory.
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4.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Table 4-5. ADC Registers (continued)
NAME ADDRESS
(1)
ADDRESS
(2)
SIZE (x16) DESCRIPTION
ADCRESULT4 0x710C 0x0B04 1 ADC Conversion Result Buffer Register 4ADCRESULT5 0x710D 0x0B05 1 ADC Conversion Result Buffer Register 5ADCRESULT6 0x710E 0x0B06 1 ADC Conversion Result Buffer Register 6ADCRESULT7 0x710F 0x0B07 1 ADC Conversion Result Buffer Register 7ADCRESULT8 0x7110 0x0B08 1 ADC Conversion Result Buffer Register 8ADCRESULT9 0x7111 0x0B09 1 ADC Conversion Result Buffer Register 9ADCRESULT10 0x7112 0x0B0A 1 ADC Conversion Result Buffer Register 10ADCRESULT11 0x7113 0x0B0B 1 ADC Conversion Result Buffer Register 11ADCRESULT12 0x7114 0x0B0C 1 ADC Conversion Result Buffer Register 12ADCRESULT13 0x7115 0x0B0D 1 ADC Conversion Result Buffer Register 13ADCRESULT14 0x7116 0x0B0E 1 ADC Conversion Result Buffer Register 14ADCRESULT15 0x7117 0x0B0F 1 ADC Conversion Result Buffer Register 15ADCTRL3 0x7118 1 ADC Control Register 3ADCST 0x7119 1 ADC Status Register0x711AReserved 20x711BADCREFSEL 0x711C 1 ADC Reference Select RegisterADCOFFTRIM 0x711D 1 ADC Offset Trim Register0x711EReserved 2 ADC Status Register0x711F
The CAN module has the following features:•Fully compliant with CAN protocol, version 2.0B•Supports data rates up to 1 Mbps•Thirty-two mailboxes, each with the following properties:– Configurable as receive or transmit– Configurable with standard or extended identifier– Has a programmable receive mask– Supports data and remote frame– Composed of 0 to 8 bytes of data– Uses a 32-bit time stamp on receive and transmit message– Protects against reception of new message– Holds the dynamically programmable priority of transmit message– Employs a programmable interrupt scheme with two interrupt levels– Employs a programmable alarm on transmission or reception time-out•Low-power mode•Programmable wake-up on bus activity•Automatic reply to a remote request message•Automatic retransmission of a frame in case of loss of arbitration or error•32-bit local network time counter synchronized by a specific message (communication in conjunctionwith mailbox 16)•Self-test mode– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided,thereby eliminating the need for another node to provide the acknowledge bit.
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Mailbox RAM
(512 Bytes)
32-Message Mailbox
of 4 × 32-Bit Words
Memory Management
Unit
CPU Interface,
Receive Control Unit,
Timer Management Unit
eCAN Memory
(512 Bytes)
Registers and Message
Objects Control
32 32
Message Controller
32 3232 3232 32
eCAN Protocol Kernel Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
Enhanced CAN Controller 32
Controls Address Data
eCAN1INTeCAN0INT
32
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
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NOTEFor a SYSCLKOUT of 100 MHz, the smallest bit rate possible is 15.6 kbps.
Figure 4-10. eCAN Block Diagram and Interface Circuit
Table 4-6. 3.3-V eCAN Transceivers
PART NUMBER SUPPLY LOW-POWER MODE SLOPE CON- VREF OTHER T
AVOLTAGE TROL
SN65HVD230 3.3 V Standby Adjustable Yes – -40 °C to 85 °CSN65HVD230Q 3.3 V Standby Adjustable Yes – -40 °C to 125 °CSN65HVD231 3.3 V Sleep Adjustable Yes – -40 °C to 85 °CSN65HVD231Q 3.3 V Sleep Adjustable Yes – -40 °C to 125 °CSN65HVD232 3.3 V None None None – -40 °C to 85 °CSN65HVD232Q 3.3 V None None None – -40 °C to 125 °CSN65HVD233 3.3 V Standby Adjustable None Diagnostic -40 °C to 125 °CLoopbackSN65HVD234 3.3 V Standby & Sleep Adjustable None – -40 °C to 125 °CSN65HVD235 3.3 V Standby Adjustable None Autobaud -40 °C to 125 °CLoopback
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Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
Abort Acknowledge − CANAA
Received Message Pending − CANRMP
Received Message Lost − CANRML
Remote Frame Pending − CANRFP
Global Acceptance Mask − CANGAM
Master Control − CANMC
Bit-Timing Configuration − CANBTC
Error and Status − CANES
Transmit Error Counter − CANTEC
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Global Interrupt Flag 1 − CANGIF1
Time-Out Control − CANTOC
Time-Out Status − CANTOS
Reserved
eCAN-A Control and Status Registers
Message Identifier − MSGID
61E8h−61E9h
Message Control − MSGCTRL
Message Data Low − MDL
Message Data High − MDH
Message Mailbox (16 Bytes)
Control and Status Registers
6000h
603Fh
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
6040h
607Fh
6080h
60BFh
60C0h
60FFh
eCAN-A Memory (512 Bytes)
Message Object Time Stamps (MOTS)
(32 × 32-Bit RAM)
Message Object Time-Out (MOTO)
(32 × 32-Bit RAM)
Mailbox 0
6100h−6107h
Mailbox 1
6108h−610Fh
Mailbox 2
6110h−6117h
Mailbox 3
6118h−611Fh
eCAN-A Memory RAM (512 Bytes)
Mailbox 4
6120h−6127h
Mailbox 28
61E0h−61E7h
Mailbox 29
61E8h−61EFh
Mailbox 30
61F0h−61F7h
Mailbox 31
61F8h−61FFh
61EAh−61EBh
61ECh−61EDh
61EEh−61EFh
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
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Figure 4-11. eCAN-A Memory Map
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Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
Abort Acknowledge − CANAA
Received Message Pending − CANRMP
Received Message Lost − CANRML
Remote Frame Pending − CANRFP
Global Acceptance Mask − CANGAM
Master Control − CANMC
Bit-Timing Configuration − CANBTC
Error and Status − CANES
Transmit Error Counter − CANTEC
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Global Interrupt Flag 1 − CANGIF1
Time-Out Control − CANTOC
Time-Out Status − CANTOS
Reserved
eCAN-B Control and Status Registers
Message Identifier − MSGID
63E8h−63E9h
Message Control − MSGCTRL
Message Data Low − MDL
Message Data High − MDH
Message Mailbox (16 Bytes)
Control and Status Registers
6200h
623Fh
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
6240h
627Fh
6280h
62BFh
62C0h
62FFh
eCAN-B Memory (512 Bytes)
Message Object Time Stamps (MOTS)
(32 × 32-Bit RAM)
Message Object Time-Out (MOTO)
(32 × 32-Bit RAM)
Mailbox 0
6300h−6307h
Mailbox 1
6308h−630Fh
Mailbox 2
6310h−6317h
Mailbox 3
6318h−631Fh
eCAN-B Memory RAM (512 Bytes)
Mailbox 4
6320h−6327h
Mailbox 28
63E0h−63E7h
Mailbox 29
63E8h−63EFh
Mailbox 30
63F0h−63F7h
Mailbox 31
63F8h−63FFh
63EAh−63EBh
63ECh−63EDh
63EEh−63EFh
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Figure 4-12. eCAN-B Memory Map
The CAN registers listed in Table 4-7 are used by the CPU to configure and control the CAN controllerand the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAMcan be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
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Table 4-7. CAN Register Map
(1)
ECAN-A ECAN-B SIZEREGISTER NAME DESCRIPTIONADDRESS ADDRESS (x32)
CANME 0x6000 0x6200 1 Mailbox enableCANMD 0x6002 0x6202 1 Mailbox directionCANTRS 0x6004 0x6204 1 Transmit request setCANTRR 0x6006 0x6206 1 Transmit request resetCANTA 0x6008 0x6208 1 Transmission acknowledgeCANAA 0x600A 0x620A 1 Abort acknowledgeCANRMP 0x600C 0x620C 1 Receive message pendingCANRML 0x600E 0x620E 1 Receive message lostCANRFP 0x6010 0x6210 1 Remote frame pendingCANGAM 0x6012 0x6212 1 Global acceptance maskCANMC 0x6014 0x6214 1 Master controlCANBTC 0x6016 0x6216 1 Bit-timing configurationCANES 0x6018 0x6218 1 Error and statusCANTEC 0x601A 0x621A 1 Transmit error counterCANREC 0x601C 0x621C 1 Receive error counterCANGIF0 0x601E 0x621E 1 Global interrupt flag 0CANGIM 0x6020 0x6220 1 Global interrupt maskCANGIF1 0x6022 0x6222 1 Global interrupt flag 1CANMIM 0x6024 0x6224 1 Mailbox interrupt maskCANMIL 0x6026 0x6226 1 Mailbox interrupt levelCANOPC 0x6028 0x6228 1 Overwrite protection controlCANTIOC 0x602A 0x622A 1 TX I/O controlCANRIOC 0x602C 0x622C 1 RX I/O controlCANTSC 0x602E 0x622E 1 Time stamp counter (Reserved in SCC mode)CANTOC 0x6030 0x6230 1 Time-out control (Reserved in SCC mode)CANTOS 0x6032 0x6232 1 Time-out status (Reserved in SCC mode)
(1) These registers are mapped to Peripheral Frame 1.
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4.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B)
Baud rate =
LSPCLK
16
LSPCLK
(BRR 1) * 8 when BRR ≠ 0
Baud rate = when BRR = 0
•
Max bit rate 100 MHz
16 6.25 106bs
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
The 280x devices include two serial communications interface (SCI) modules. The SCI modules supportdigital communications between the CPU and other asynchronous peripherals that use the standardnon-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has itsown separate enable and interrupt bits. Both can be operated independently or simultaneously in thefull-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity,overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bitbaud-select register.
Features of each SCI module include:•Two external pins:– SCITXD: SCI transmit-output pin– SCIRXD: SCI receive-input pinNOTE: Both pins can be used as GPIO if not used for SCI.– Baud rate programmable to 64K different rates:
•Data-word format– One start bit– Data-word length programmable from one to eight bits– Optional even/odd/no parity bit– One or two stop bits•Four error-detection flags: parity, overrun, framing, and break detection•Two wake-up multiprocessor modes: idle-line and address bit•Half- or full-duplex operation•Double-buffered receive and transmit functions•Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithmswith status flags.– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TXEMPTY flag (transmitter-shift register is empty)– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)•Separate enable bits for transmitter and receiver interrupts (except BRKDT)
•NRZ (non-return-to-zero) format•Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTEAll registers in this module are 8-bit registers that are connected to Peripheral Frame 2.When a register is accessed, the register data is in the lower byte (7-0), and the upperbyte (15-8) is read as zeros. Writing to the upper byte has no effect.
Enhanced features:•Auto baud-detect hardware logic•16-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 4-8 and Table 4-9 .
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TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Table 4-8. SCI-A Registers
(1)
NAME ADDRESS SIZE (x16) DESCRIPTION
SCICCRA 0x7050 1 SCI-A Communications Control RegisterSCICTL1A 0x7051 1 SCI-A Control Register 1SCIHBAUDA 0x7052 1 SCI-A Baud Register, High BitsSCILBAUDA 0x7053 1 SCI-A Baud Register, Low BitsSCICTL2A 0x7054 1 SCI-A Control Register 2SCIRXSTA 0x7055 1 SCI-A Receive Status RegisterSCIRXEMUA 0x7056 1 SCI-A Receive Emulation Data Buffer RegisterSCIRXBUFA 0x7057 1 SCI-A Receive Data Buffer RegisterSCITXBUFA 0x7059 1 SCI-A Transmit Data Buffer RegisterSCIFFTXA
(2)
0x705A 1 SCI-A FIFO Transmit RegisterSCIFFRXA
(2)
0x705B 1 SCI-A FIFO Receive RegisterSCIFFCTA
(2)
0x705C 1 SCI-A FIFO Control RegisterSCIPRIA 0x705F 1 SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produceundefined results.(2) These registers are new registers for the FIFO mode.
Table 4-9. SCI-B Registers
(1) (2)
NAME ADDRESS SIZE (x16) DESCRIPTION
SCICCRB 0x7750 1 SCI-B Communications Control RegisterSCICTL1B 0x7751 1 SCI-B Control Register 1SCIHBAUDB 0x7752 1 SCI-B Baud Register, High BitsSCILBAUDB 0x7753 1 SCI-B Baud Register, Low BitsSCICTL2B 0x7754 1 SCI-B Control Register 2SCIRXSTB 0x7755 1 SCI-B Receive Status RegisterSCIRXEMUB 0x7756 1 SCI-B Receive Emulation Data Buffer RegisterSCIRXBUFB 0x7757 1 SCI-B Receive Data Buffer RegisterSCITXBUFB 0x7759 1 SCI-B Transmit Data Buffer RegisterSCIFFTXB
(2)
0x775A 1 SCI-B FIFO Transmit RegisterSCIFFRXB
(2)
0x775B 1 SCI-B FIFO Receive RegisterSCIFFCTB
(2)
0x775C 1 SCI-B FIFO Control RegisterSCIPRIB 0x775F 1 SCI-B Priority Control Register
(1) Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produceundefined results.(2) These registers are new registers for the FIFO mode.
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TX FIFO _0
LSPCLK
WUT
Frame Format and Mode
Even/Odd Enable
Parity
SCI RX Interrupt select logic
BRKDT
RXRDY
SCIRXST.6
SCICTL1.3
8SCICTL2.1
RX/BK INT ENA
SCIRXD
SCIRXST.1
TXENA
SCI TX Interrupt select logic
TX EMPTY
TXRDY
SCICTL2.0
TX INT ENA
SCITXD
RXENA
SCIRXD
RXWAKE
SCICTL1.6
RX ERR INT ENA
TXWAKE
SCITXD
SCICCR.6 SCICCR.5
SCITXBUF.7-0
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
SCILBAUD. 7 - 0
Transmitter-Data
Buffer Register
8SCICTL2.6
SCICTL2.7
Baud Rate
LSbyte
Register
RXSHF
Register
TXSHF
Register
SCIRXST.5
1TX FIFO _1
-----
TX FIFO _15
8
TX FIFO registers
TX FIFO
TX Interrupt
Logic
TXINT
SCIFFTX.14
RX FIFO _15
SCIRXBUF.7-0
Receive Data
Buffer register
SCIRXBUF.7-0
-----
RX FIFO_1
RX FIFO _0
8
RX FIFO registers
SCICTL1.0
RX Interrupt
Logic
RXINT
RX FIFO
SCIFFRX.15
RXFFOVF
RX Error
SCIRXST.7
PEFE OE
RX Error
SCIRXST.4 - 2
To CPU
To CPU
AutoBaud Detect logic
SCICTL1.1
SCIFFENA
Interrupts
Interrupts
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
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Figure 4-13 shows the SCI module block diagram.
Figure 4-13. Serial Communications Interface (SCI) Module Block Diagram
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4.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)
Baud rate =
LSPCLK
4
LSPCLK
(SPIBRR 1) when SPIBRR = 3 to 127
Baud rate = when SPIBRR = 0,1, 2
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
The 280x devices include the four-pin serial peripheral interface (SPI) module. Up to four SPI modules(SPI-A, SPI-B, SPI-C, and SPI-D) are available. The SPI is a high-speed, synchronous serial I/O port thatallows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of thedevice at a programmable bit-transfer rate. Normally, the SPI is used for communications between theDSP controller and external peripherals or another processor. Typical applications include external I/O orperipheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevicecommunications are supported by the master/slave operation of the SPI.
The SPI module features include:•Four external pins:– SPISOMI: SPI slave-output/master-input pin– SPISIMO: SPI slave-input/master-output pin– SPISTE: SPI slave transmit-enable pin– SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.•Two operational modes: master and slaveBaud rate: 125 different programmable rates.
SPI performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted suchthat the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.•Data word length: one to sixteen data bits•Four clocking schemes (controlled by clock polarity and clock phase bits) include:– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of theSPICLK signal and receives data on the rising edge of the SPICLK signal.– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of thefalling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of theSPICLK signal and receives data on the falling edge of the SPICLK signal.– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of thefalling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.•Simultaneous receive and transmit operation (transmit function can be disabled in software)•Transmitter and receiver operations are accomplished through either interrupt-driven or polledalgorithms.
•Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTEAll registers in this module are 16-bit registers that are connected to Peripheral Frame 2.When a register is accessed, the register data is in the lower byte (7-0), and the upperbyte (15-8) is read as zeros. Writing to the upper byte has no effect.
Enhanced feature:•16-level transmit/receive FIFO•Delayed transmit control
The SPI port operation is configured and controlled by the registers listed in Table 4-10 .
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SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Table 4-10. SPI-A Registers
NAME ADDRESS SIZE (X16) DESCRIPTION
(1)
SPICCR 0x7040 1 SPI-A Configuration Control RegisterSPICTL 0x7041 1 SPI-A Operation Control RegisterSPISTS 0x7042 1 SPI-A Status RegisterSPIBRR 0x7044 1 SPI-A Baud Rate RegisterSPIRXEMU 0x7046 1 SPI-A Receive Emulation Buffer RegisterSPIRXBUF 0x7047 1 SPI-A Serial Input Buffer RegisterSPITXBUF 0x7048 1 SPI-A Serial Output Buffer RegisterSPIDAT 0x7049 1 SPI-A Serial Data RegisterSPIFFTX 0x704A 1 SPI-A FIFO Transmit RegisterSPIFFRX 0x704B 1 SPI-A FIFO Receive RegisterSPIFFCT 0x704C 1 SPI-A FIFO Control RegisterSPIPRI 0x704F 1 SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefinedresults.
Table 4-11. SPI-B Registers
NAME ADDRESS SIZE (X16) DESCRIPTION
(1)
SPICCR 0x7740 1 SPI-B Configuration Control RegisterSPICTL 0x7741 1 SPI-B Operation Control RegisterSPISTS 0x7742 1 SPI-B Status RegisterSPIBRR 0x7744 1 SPI-B Baud Rate RegisterSPIRXEMU 0x7746 1 SPI-B Receive Emulation Buffer RegisterSPIRXBUF 0x7747 1 SPI-B Serial Input Buffer RegisterSPITXBUF 0x7748 1 SPI-B Serial Output Buffer RegisterSPIDAT 0x7749 1 SPI-B Serial Data RegisterSPIFFTX 0x774A 1 SPI-B FIFO Transmit RegisterSPIFFRX 0x774B 1 SPI-B FIFO Receive RegisterSPIFFCT 0x774C 1 SPI-B FIFO Control RegisterSPIPRI 0x774F 1 SPI-B Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefinedresults.
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Table 4-12. SPI-C REGISTERS
NAME ADDRESS SIZE (X16) DESCRIPTION
(1)
SPICCR 0x7760 1 SPI-C Configuration Control RegisterSPICTL 0x7761 1 SPI-C Operation Control RegisterSPISTS 0x7762 1 SPI-C Status RegisterSPIBRR 0x7764 1 SPI-C Baud Rate RegisterSPIRXEMU 0x7766 1 SPI-C Receive Emulation Buffer RegisterSPIRXBUF 0x7767 1 SPI-C Serial Input Buffer RegisterSPITXBUF 0x7768 1 SPI-C Serial Output Buffer RegisterSPIDAT 0x7769 1 SPI-C Serial Data RegisterSPIFFTX 0x776A 1 SPI-C FIFO Transmit RegisterSPIFFRX 0x776B 1 SPI-C FIFO Receive RegisterSPIFFCT 0x776C 1 SPI-C FIFO Control RegisterSPIPRI 0x776F 1 SPI-C Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefinedresults.
Table 4-13. SPI-D Registers
NAME ADDRESS SIZE (X16) DESCRIPTION
(1)
SPICCR 0x7780 1 SPI-D Configuration Control RegisterSPICTL 0x7781 1 SPI-D Operation Control RegisterSPISTS 0x7782 1 SPI-D Status RegisterSPIBRR 0x7784 1 SPI-D Baud Rate RegisterSPIRXEMU 0x7786 1 SPI-D Receive Emulation Buffer RegisterSPIRXBUF 0x7787 1 SPI-D Serial Input Buffer RegisterSPITXBUF 0x7788 1 SPI-D Serial Output Buffer RegisterSPIDAT 0x7789 1 SPI-D Serial Data RegisterSPIFFTX 0x778A 1 SPI-D FIFO Transmit RegisterSPIFFRX 0x778B 1 SPI-D FIFO Receive RegisterSPIFFCT 0x778C 1 SPI-D FIFO Control RegisterSPIPRI 0x778F 1 SPI-D Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefinedresults.
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S
SPICTL.0
SPI INT FLAG SPI INT
ENA
SPISTS.6
S
Clock
Polarity
Talk
LSPCLK
456 123 0
0123
SPI Bit Rate
State Control
SPIRXBUF
Buffer Register
Clock
Phase
Receiver
Overrun Flag
SPICTL.4
Overrun
INT ENA
SPICCR.3 − 0
SPIBRR.6 − 0 SPICCR.6 SPICTL.3
SPIDAT.15 − 0
SPICTL.1
M
S
M
Master/Slave
SPISTS.7
SPIDAT
Data Register
M
S
SPICTL.2
SPI Char
SPISIMO
SPISOMI
SPICLK
SW2
S
M
M
S
SW3
To CPU
M
SW1
SPITXBUF
Buffer Register
RX FIFO _0
RX FIFO _1
−−−−−
RX FIFO _15
TX FIFO registers
TX FIFO _0
TX FIFO _1
−−−−−
TX FIFO _15
RX FIFO registers
16
16
16
TX Interrupt
Logic
RX Interrupt
Logic
SPIINT/SPIRXINT
SPITXINT
SPIFFOVF FLAG
SPIFFRX.15
16
TX FIFO Interrupt
RX FIFO Interrupt
SPIRXBUF
SPITXBUF
SPIFFTX.14
SPIFFENA
SPISTE(A)
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Figure 4-14 is a block diagram of the SPI in slave mode.
A. SPISTE is driven low by the master for a slave device.
Figure 4-14. SPI Module Block Diagram (Slave Mode)
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4.10 Inter-Integrated Circuit (I
2
C)
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
The 280x device contains one I
2
C Serial Port. Figure 4-15 shows how the I
2
C peripheral module interfaceswithin the 280x device.
The I
2
C module has the following features:•Compliance with the Philips Semiconductors I
2
C-bus specification (version 2.1):– Support for 1-bit to 8-bit format transfers– 7-bit and 10-bit addressing modes– General call– START byte mode– Support for multiple master-transmitters and slave-receivers– Support for multiple slave-transmitters and master-receivers– Combined master transmit/receive and receive/transmit mode– Data transfer rate of from 10 kbps up to 400 kbps (Philips Fast-mode ra•One 16-bit receive FIFO and one 16-bit transmit FIFO•One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of thefollowing conditions:
– Transmit-data ready– Receive-data ready– Register-access ready– No-acknowledgment received– Arbitration lost– Stop condition detected– Addressed as slave•An additional interrupt that can be used by the CPU when in FIFO mode•Module enable/disable capability•Free data format mode
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SYSRS
Data[16]
SYSCLKOUT
Data[16]
Addr[16]
Control
I2CINT1A
I2CINT2A
C28X CPU
GPIO
MUX I2C−A
System Control
Block
I2CAENCLK
PIE
Block
SDAA
SCLA
Peripheral Bus
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
A. The I
2
C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I
2
C port arealso at the SYSCLKOUT rate.B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I
2
C port for low poweroperation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 4-15. I
2
C Peripheral Module Interfaces
The registers in Table 4-14 configure and control the I
2
C port operation.
Table 4-14. I
2
C-A Registers
NAME ADDRESS DESCRIPTION
I2COAR 0x7900 I
2
C own address registerI2CIER 0x7901 I
2
C interrupt enable registerI2CSTR 0x7902 I
2
C status registerI2CCLKL 0x7903 I
2
C clock low-time divider registerI2CCLKH 0x7904 I
2
C clock high-time divider registerI2CCNT 0x7905 I
2
C data count registerI2CDRR 0x7906 I
2
C data receive registerI2CSAR 0x7907 I
2
C slave address registerI2CDXR 0x7908 I
2
C data transmit registerI2CMDR 0x7909 I
2
C mode registerI2CISRC 0x790A I
2
C interrupt source registerI2CPSC 0x790C I
2
C prescaler registerI2CFFTX 0x7920 I
2
C FIFO transmit registerI2CFFRX 0x7921 I
2
C FIFO receive registerI2CRSR - I
2
C receive shift register (not accessible to the CPU)I2CXSR - I
2
C transmit shift register (not accessible to the CPU)
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4.11 GPIO MUX
GPxDAT (read)
Input
Qualification
GPxMUX1/2
High Impedance
Output Control
GPIOx pin
XRS
0 = Input, 1 = Output
Low Power
Modes Block
GPxDIR (latch)
Peripheral 2 Input
Peripheral 3 Input
Peripheral 1 Output
Peripheral 2 Output
Peripheral 3 Output
Peripheral 1 Output Enable
Peripheral 2 Output Enable
Peripheral 3 Output Enable
00
01
10
11
00
01
10
11
00
01
10
11
GPxCTRL
Peripheral 1 Input
N/C
GPxPUD
LPMCR0
Internal
Pullup
GPIOLMPSEL
GPxQSEL1/2
GPxSET
GPxDAT (latch)
GPxCLEAR
GPxTOGGLE
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXNMISEL
= Default at Reset
PIE
External Interrupt
MUX
Asynchronous
path
Asynchronous path
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
On the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIOpin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pinis shown in Figure 4-16 . Because of the open drain capabilities of the I
2
C pins, the GPIO MUX blockdiagram for these pins differ. See the TMS320x280x System Control and Interrupts Reference Guide(literature number SPRU712) for details.
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR registerdepending on the particular GPIO pin selected.B. GPxDAT latch/read are accessed at the same memory location.
Figure 4-16. GPIO MUX Block Diagram
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SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
The 280x supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-15 shows the GPIOregister mapping.
Table 4-15. GPIO Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31)GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15)GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31)GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15)GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31)GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31)GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0 to 31)0x6F8Ereserved 20x6F8FGPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 35)GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 35)GPBQSEL2 0x6F94 2 reservedGPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 35)GPBMUX2 0x6F98 2 reservedGPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 35)GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32 to 35)0x6F9Ereserved 2 reserved0x6F9F
0x6FA0reserved 320x6FBF
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT 0x6FC0 2 GPIO Data Register (GPIO0 to 31)GPASET 0x6FC2 2 GPIO Data Set Register (GPIO0 to 31)GPACLEAR 0x6FC4 2 GPIO Data Clear Register (GPIO0 to 31)GPATOGGLE 0x6FC6 2 GPIO Data Toggle Register (GPIO0 to 31)GPBDAT 0x6FC8 2 GPIO Data Register (GPIO32 to 35)GPBSET 0x6FCA 2 GPIO Data Set Register (GPIO32 to 35)GPBCLEAR 0x6FCC 2 GPIO Data Clear Register (GPIO32 to 35)GPBTOGGLE 0x6FCE 2 GPIO Data Toggle Register (GPIO32 to 35)0x6FD0reserved 160x6FDF
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31)GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31)GPIOXNMISEL 0x6FE2 1 XNMI GPIO Input Select Register (GPIO0 to 31)0x6FE3reserved 50x6FE7GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31)0x6FEAreserved 220x6FFF
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GPyCTRL Reg
SYNC
SYSCLKOUT
Qualification Input Signal
Qualified By 3
or 6 Samples
GPIOx
Time between samples
GPxQSEL
Number of Samples
Sampling Window GPxCTRL[QUALPRD]
A
GPxQSEL = 1, 1 (6 samples)
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers fromfour choices:
•Synchronization To SYSCLKOUT Only (GPxQSEL1/2=0,0): This is the default mode of all GPIO pinsat reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).•Qualification Using Sampling Window (GPxQSEL1/2=0,1 and 1,0): In this mode the input signal, aftersynchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles beforethe input is allowed to change.
Figure 4-17. Qualification Using Sampling Window
•The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable ingroups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. Thesampling window is either 3-samples or 6-samples wide and the output is only changed when ALLsamples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).
A. The qualification block generates both the 3 and 6 sample signals. A MUX is then used to select which sample modeis used.B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
Figure 4-18. Sampling Mode
•No Synchronization (GPxQSEL1/2=1,1): This mode is used for peripherals where synchronization isnot required (synchronization is performed within the peripheral).
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Due to the multi-level multiplexing that is required on the 280x device, there may be cases where aperipheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is notselected, the input signal will default to either a 0 or 1 state, depending on the peripheral.
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5 Device Support
5.1 Device and Development Support Tool Nomenclature
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSPs,including tools to evaluate the performance of the processors, generate code, develop algorithmimplementations, and fully integrate and debug software and hardware modules.
The following products support development of 280x-based applications:
Software Development Tools•Code Composer Studio™ Integrated Development Environment (IDE)– C/C++ Compiler– Code generation tools– Assembler/Linker
– Cycle Accurate Simulator•Application algorithms•Sample applications code
Hardware Development Tools•2808 eZdsp™•JTAG-based emulators - SPI515, XDS510PP, XDS510PP Plus, XDS510™ USB•Universal 5-V dc power supply•Documentation and cables
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of allTMS320™ DSP devices and support tools. Each TMS320™ DSP commercial family member has one ofthree prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefixdesignators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages ofproduct development from engineering prototypes (TMX/TMDX) through fully qualified productiondevices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electricalspecifications
TMP Final silicon die that conforms to the device's electrical specifications but has not completedquality and reliability verificationTMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualificationtestingTMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the followingdisclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality andreliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standardproduction devices. Texas Instruments recommends that these devices not be used in any productionsystem because their expected end-use failure rate still is undefined. Only qualified production devices areto be used.
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TMS 320 F 2808 PZ
DEVICE FAMILY
A
5.2 Documentation Support
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
TI device nomenclature also includes a suffix with the device family name. This suffix indicates thepackage type (for example, PBK) and temperature range (for example, A). Figure 5-1 provides a legendfor reading the complete device name for any family member.
Figure 5-1. Example of TMS320x280x Device Nomenclature
Extensive documentation supports all of the TMS320™ DSP family generations of devices from productannouncement through applications development. The types of documentation available include: datasheets and data manuals, with design specifications; and hardware and software applications.TMS320x280x device reference guides are applicable to the UCD9501 device as well. Useful referencedocumentation includes:
SPRU051: TMS320x281x, 280x Serial Communication Interface (SCI) Reference GuideDescribes the SCI, which is a two-wire asynchronous serial port, commonly known as aUART. The SCI modules support digital communications between the CPU and otherasynchronous peripherals that use the standard non-return-to-zero (NRZ) format.
SPRU059: TMS320x281x, 280x Serial Peripheral Interface (SPI) Reference GuideDescribes the SPI - a high-speed synchronous serial input/output (I/O) port that allows aserial bit stream of programmed length (one to sixteen bits) to be shifted into and out of thedevice at a programmed bit-transfer rate. The SPI is used for communications between theDSP controller and external peripherals or another controller.
SPRU074: TMS320x281x, 280x Enhanced Controller Area Network (eCAN) Reference GuideDescribes the eCAN that uses established protocol to communicate serially with othercontrollers in electrically noisy environments. With 32 fully configurable mailboxes andtime-stamping feature, the eCAN module provides a versatile and robust serial communi-cation interface. The eCAN module implemented in the 281x DSP is compatible with theCAN 2.0B standard (active).
SPRU430: TMS320C28x DSP CPU and Instruction Set Reference GuideDescribes the central processing unit (CPU) and the assembly language instructions of theTMS320C28x fixed-point digital signal processors (DSPs). It also describes emulationfeatures available on these DSPs.
SPRU513: TMS320C28x Assembly Language Tools User's GuideDescribes the assembly language tools (assembler and other tools used to developassembly language code), assembler directives, macros, common object file format, andsymbolic debugging directives for the TMS320C28x device.
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SPRU514: TMS320C28x Optimizing C Compiler User's Guidedescribes the TMS320C28x C/C++ compiler. This compiler accepts ANSI standard C/C++source code and produces TMS320 DSP assembly language source code for theTMS320C28x device.
SPRU566: TMS320x281x, 280x Peripheral Reference GuideDescribes the peripheral reference guides of the 28x digital signal processors (DSPs).
SPRU608: The TMS320C28x Instruction Set Simulator Technical OverviewDescribes the simulator, available within the Code Composer Studio for TMS320C2000 IDE,that simulates the instruction set of the C28x core.
SPRU625: TMS320C28x DSP/BIOS Application Programming Interface (API) Reference GuideDescribes development using DSP/BIOS.
SPRU712: TMS320x280x System Control and Interrupts Reference GuideDescribes the various interrupts and system control features of the 280x digital signalprocessors (DSPs).
SPRU716: TMS320x280x Analog-to-Digital Converter (ADC) Reference GuideDescribes the ADC module. The module is a 12-bit pipelined ADC. The analog circuits ofthis converter, referred to as the core in this document, include the front-end analogmultiplexers (MUXs), sample-and-hold (S/H) circuits, the conversion core, voltage regulators,and other analog supporting circuits. Digital circuits, referred to as the wrapper in thisdocument, include programmable conversion sequencer, result registers, interface to analogcircuits, interface to device peripheral bus, and interface to other on-chip modules.
SPRU722: TMS320x280x Boot ROM Reference GuideDescribes the purpose and features of the bootloader (factory-programmed boot-loadingsoftware). It also describes other contents of the device on-chip boot ROM and identifieswhere all of the information is located within that memory.
SPRU790: TMS320x280x Enhanced Quadrature Encoder Pulse (eQEP) Reference GuideDescribes the eQEP module, which is used for interfacing with a linear or rotary incrementalencoder to get position, direction, and speed information from a rotating machine in highperformance motion and position control systems. It includes the module description andregisters.
SPRU791: TMS320x280x Enhanced Pulse Width Modulator (ePWM) Module Reference GuideThe PWM peripheral is an essential part of controlling many of the power related systemsfound in both commercial and industrial equipments. This guide describes the main areasthat include digital motor control, switch mode power supply control, UPS (uninterruptiblepower supplies), and other forms of power conversion. The PWM peripheral can beconsidered as performing a DAC function, where the duty cycle is equivalent to a DACanalog value, it is sometimes referred to as a Power DAC.
SPRU807: TMS320x280x Enhanced Capture (eCAP) Module Reference GuideDescribes the enhanced capture module. It includes the module description and registers.
SPRU924: High-Resolution Pulse Width Modulator (HRPWM)This document describes the operation of the High-Resolution extension to the Pulse WidthModulator (HRPWM).
SPRA550: 3.3 V DSP for Digital Motor ControlThe application report first describes a scenario of a 3.3-V-only motor controller indicatingthat for most applications, no significant issue of interfacing between 3.3 V and 5 V exists.Cost-effective 3.3-V/5-V interfacing techniques are then discussed for the situations where
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such interfacing is needed. On-chip 3.3-V analog-to-digital converter (ADC) versus 5-V ADCis also discussed. Guidelines for component layout and printed circuit board (PCB) designthat can reduce system noise and EMI effects are summarized in the last section.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signalprocessing research and education. The TMS320 DSP newsletter, Details on Signal Processing, ispublished quarterly and distributed to update TMS320 DSP customers on product information.
Updated information on the TMS320 DSP controllers can be found on the worldwide web at:http://www.ti.com.
To send comments regarding this data manual (literature number SPRS230), use the com-ments@books.sc.ti.com email address, which is a repository for feedback. For questions and support,contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.
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6 Electrical Specifications
6.1 Absolute Maximum Ratings
(1)
6.2 Recommended Operating Conditions
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
This section provides the absolute maximum ratings and the recommended operating conditions for theTMS320F280x DSPs.
Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges.Supply voltage range, V
DDIO
, V
DDA2
, V
DDAIO
- 0.3 V to 4.6 VSupply voltage range, V
DD
, V
DD1A18
, V
DD2A18
- 0.5 V to 2.5 VV
DD3VFL
range - 0.3 V to 4.6 VInput voltage range, V
IN
- 0.3 V to 4.6 VOutput voltage range, V
O
- 0.3 V to 4.6 VInput clamp current, I
IK
(V
IN
< 0 or V
IN
> V
DDIO
)
(2)
± 20 mAOutput clamp current, I
OK
(V
O
< 0 or V
O
> V
DDIO
) ± 20 mAOperating ambient temperature ranges, T
A
: A version (GGM, PZ)
(3)
- 40°C to 85°CT
A
: S version (GGM, PZ)
(3)
- 40°C to 125°CT
A
: Q version (GGM, PZ)
(3)
- 40°C to 125°CStorage temperature range, T
stg
(3)
- 65°C to 150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect toV
SS
.(2) Continuous clamp current per pin is ± 2 mA(3) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall devicelife. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data forTMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963).
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V
DDIO
Device supply voltage, I/O 3.14 3.3 3.47 VV
DD
Device supply voltage CPU 1.71 1.8 1.89 VV
SS
Supply ground 0 VV
DDA2
, V
DDAIO
ADC supply voltage (3.3 V) 3.14 3.3 3.47 VV
DD1A18
, ADC supply voltage (1.8 V) 1.71 1.8 1.89 VV
DD2A18
V
DD3VFL
Flash programming supply volt- 3.14 3.3 3.47 Vagef
SYSCLKOUT
Device clock frequency (system 2 100 MHzclock)V
IH
High-level input voltage 2 V
DDIO
VV
IL
Low-level input voltage 0.8I
OH
High-level output source current, All I/Os except Group 2 -4 mAV
OH
= 2.4 V
Group 2
(1)
-8I
OL
Low-level output sink current, V
OL
All I/Os except Group 2 4 mA= V
OL
MAX
Group 2
(1)
8T
A
Ambient temperature A version -40 85S version -40 125 °CQ version -40 125
(1) Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, and EMU1.
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6.3 Electrical Characteristics
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
over recommended operating conditions (unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
OH
= I
OH
MAX 2.4V
OH
High-level output voltage VI
OH
= 50 µA V
DDIO
- 0.2V
OL
Low-level output voltage I
OL
= I
OL
MAX 0.4 VV
DDIO
= 3.3 V,Input cur-
With pullup All I/Os(including XRS) -100V
IN
= 0 VI
IL
rent µA(low level)
With pulldown V
DDIO
= 3.3 V, V
IN
= 0 V ±2Input cur- With pullup V
DDIO
= 3.3 V, V
IN
= V
DD
±2I
IH
rent µAWith pulldown V
DDIO
= 3.3 V, V
IN
= V
DD
50(high level)Output current,I
OZ
high-impedance state V
O
= V
DDIO
or 0 V ±2 µA(off-state)C
I
Input capacitance 2 pFC
o
Output capacitance 3 pF
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6.3.1 TMS320F2808 Current Consumption by Power-Supply Pins
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SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
over recommended operating conditions during low-power modes at 100-MHz SYSCLKOUT
I
DD
I
DDIO
(1)
I
DD3VFL
I
DDA18
(2)MODE TEST CONDITIONS
TYP MAX
(3)
TYP MAX
(3)
TYP MAX
(3)
TYP MAX
(3)
•The following peripheralclocks are enabled:– ePWMn
– eCAPn
– eQEPn
– eCAN-A
– SCI-A
– SPI-A
– ADCOperational
190 mA 15 mA 35 mA 20 mA– I
2
C(Flash)
•All PWM pins aretoggled at 100 kHz.•Data is continuously
transmitted out of theSCI-A, SC-IB, andeCAN-A ports. Thehardware multiplier isexercised.
•Code is running out offlash with 3 wait-states.
•Flash is powered down•XCLKOUT is turned off•The following peripheralclocks are enabled:IDLE 75 mA 60 µA 0 5 µA– eCAN-A
– SCI-A
– SPI-A
– I
2
C
•Flash is powered downSTANDBY 5 mA 60 µA 0 5 µA•Peripheral clocks areturned off
•Flash is powered down•Peripheral clocks areHALT 25 µA 60 µA 0 5 µAturned off•Input clock is disabled
(1) I
DDIO
includes a small amount of current (around 1 mA) flowing into V
DDA2
, and V
DDAIO
pins in the operational mode.(2) I
DDA18
includes current into VDD1A18 and VDD2A18 pins.(3) MAX numbers are at 125°C, and MAX voltage (V
DD
= 2.0 V; V
DDIO
, V
DD3VFL
, V
DDA
= 3.6 V).
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6.3.2 TMS320F2806 Current Consumption by Power-supply Pins
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
over recommended operating conditions during low-power modes at 100 MHz SYSCLKOUT
I
DD
I
DDIO
(1)
I
DD3VFL
I
DDA18
(2)
MODE TEST CONDITIONS
MAX
(3TYP TYP MAX
(3)
TYP MAX
(3)
TYP MAX
(3))
•The following peripheral clocks are en-abled:
– ePWMn
– eCAPn
– eQEPn
– eCAN-A
– SCI-AOperational
– SPI-A
190 mA 15 mA 35 mA 20 mA(Flash)
– ADC
– I
2
C•All PWM pins are toggled at 100 kHz.•Data is continuously transmitted out ofthe SCI-A, SC-IB, and eCAN-A ports.The hardware multiplier is exercised.•Code is running out of flash with 3wait-states.
•Flash is powered down.•XCLKOUT is turned off•The following peripheral clocks are en-abled:IDLE 75 mA 60 µA 0 5 µA– eCAN-A
– SCI-A
– SPI-A
– I
2
C
•Flash is powered down.STANDBY 5 mA 60 µA 0 5 µA•Peripheral clocks are turned off.
•Flash is powered down.HALT 25 µA 60 µA 0 5 µA•Peripheral clocks are turned off.•Input clock is disabled.
(1) I
DDIO
includes a small amount of current (around 1 mA) flowing into V
DDA2
and V
DDAIO
, pins in the operational mode.(2) I
DDA18
includes current into V
DD1A18
and V
DD2A18
pins.(3) MAX numbers are at 125 °C, and MAX voltage (V
DD
= 2.0 V; V
DDIO
, V
DD3VFL
, V
DDA
= 3.6 V).
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6.3.3 TMS320F2801/UCD9501 Current Consumption by Power-supply Pins
6.4 Reducing Current Consumption
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
over recommended operating conditions during low-power modes at 100-MHz SYSCLKOUT
I
DD
I
DDIO
(1)
I
DD3VFL
I
DDA18
(2)
MODE TEST CONDITIONS
MAX
(3TYP TYP MAX
(3)
TYP MAX
(3)
TYP MAX
(3))
•The following peripheral clocks are en-abled:
– ePWMn
– eCAPn
– eQEPn
– eCAN-A
– SCI-AOperational
– SPI-A
175 mA 12 mA 35 mA 20 mA(Flash)
– ADC
– I
2
C•All PWM pins are toggled at 100 kHz.•Data is continuously transmitted out ofthe SCI-A, SC-IB, and eCAN-A ports.The hardware multiplier is exercised.•Code is running out of flash with 3wait-states.
•Flash is powered down.•XCLKOUT is turned off.•The following peripheral clocks are en-abled:IDLE 75 mA 60 µA 0 5 µA– eCAN-A
– SCI-A
– SPI-A
– I
2
C
•Flash is powered down.STANDBY 5 mA 60 µA 0 5 µA•Peripheral clocks are turned off.
•Flash is powered down.HALT 25 µA 60 µA 0 5 µA•Peripheral clocks are turned off.•Input clock is disabled
(1) I
DDIO
includes a small amount of current (around 1 mA) flowing into V
DDA2
and V
DDAIO
, pins in the operational mode.(2) I
DDA18
includes current into V
DDA1A18
and V
DD2A18
pins.(3) MAX numbers are at 125 °C, and MAX voltage (V
DD
= 2.0 V; V
DDIO
, V
DD3VFL
, V
DDA
= 3.6 V).
280x devices have a richer peripheral mix compared to the 281x family. While the McBSP has beenremoved, the following new peripherals have been added on the 280x:•3 SPI modules•1 CAN module•1 I
2
C module
The two event manager modules of the 281x have been enhanced and replaced with separate ePWM (6),eCAP (4) and eQEP (2) modules, providing tremendous flexibility in applications. Like 281x, 280x DSPsincorporate a unique method to reduce the device current consumption. Since each peripheral unit has anindividual clock-enable bit, significant reduction in current consumption can be achieved by turning off theclock to any peripheral module that is not used in a given application. Furthermore, any one of the threelow-power modes could be taken advantage of to reduce the current consumption even further. Table 6-1indicates the typical reduction in current consumption achieved by turning off the clocks.
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6.5 Current Consumption Graphs
0
50
100
150
200
250
0 20 40 60 80 100
SYSCLKOUT (MHz)
mA
IDD IDDA18 Total 1.8 IDDIO IDD3VFL Total 3.3
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Table 6-1. Typical Current Consumption by VariousPeripherals (at 100 MHz)
(1)
PERIPHERAL I
DD
CURRENTMODULE REDUCTION (mA)
ADC 8
(2)
I2C 5eQEP 5ePWM 5eCAP 3SCI 4SPI 5eCAN 11
(1) All peripheral clocks are disabled upon reset. Writing to/readingfrom peripheral registers is possible only after the peripheral clocksare turned on.(2) This number represents the current drawn by the digital portion ofthe ADC module. Turning off the clock to the ADC module results inthe elimination of the current drawn by the analog portion of theADC (I
DDA18
) as well.
NOTEThe baseline I
DD
current (current when the core is executing a dummy loop with noperipherals enabled) is 110 mA, typical. To arrive at the I
DD
current for a given application,the current-drawn by the peripherals (enabled by that application) must be added to thebaseline I
DD
current.
Figure 6-1. Typical Operational Current Versus Frequency (F2808)
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0
100
200
300
400
500
600
0 20 40 60 80 100
SYSCLKOUT (MHz)
Power
Power
6.6 Signal Transition Levels
0.4 V (VOL)
20%
2.4 V (VOH)
80%
0.8 V (VIL)
10%
2.0 V (VIH)
90%
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Figure 6-2. Typical Operational Power Versus Frequency (F2808)
Some of the signals use different reference voltages, see the recommended operating conditions table.Output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.4 V.
Figure 6-3 shows output levels.
Figure 6-3. Output Levels
Output transition times are specified as follows:•For a high-to-lowtransition, the level at which the output is said to be no longer high is below 80% ofthe total voltage range and lower and the level at which the output is said to be low is 20% of the totalvoltage range and lower.•For a low-to-high transition, the level at which the output is said to be no longer low is 20% of the totalvoltage range and higher and the level at which the output is said to be high is 80% of the total voltagerange and higher.
Figure 6-4 shows the input levels.
Figure 6-4. Input Levels
Input transition times are specified as follows:•For a high-to-low transition on an input signal, the level at which the input is said to be no longer highis 90% of the total voltage range and lower and the level at which the input is said to be low is 10% ofthe total voltage range and lower.
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6.7 Timing Parameter Symbology
6.8 General Notes on Timing Parameters
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
•For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is10% of the total voltage range and higher and the level at which the input is said to be high is 90% ofthe total voltage range and higher.
NOTESee the individual timing diagrams for levels used for testing timing parameters.
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten thesymbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their mean- Letters and symbols and their mean-ings: ings:a access time H Highc cycle time (period) L Lowd delay time V Valid
Unknown, changing, or don'tf fall time X
care levelh hold time Z High impedancer rise timesu setup timet transition timev valid timew pulse duration (width)
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such thatall output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actualcycles. For actual cycle examples, see the appropriate cycle description section of this document.
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6.9 Test Load Circuit
Transmission Line
4.0 pF 1.85 pF
Z0 = 50 Ω
(see note)
Tester Pin Electronics Data Sheet Timing Reference Point
Output
Under
Test
42 Ω3.5 nH
Device Pin
(see note)
6.10 Device Clock Table
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
This test load circuit is used to measure all switching characteristics provided in this document.
A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and itstransmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used toproduce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary toadd or subtract the transmission line delay (2 ns or longer) from the data sheet timing.B. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at thedevice pin.
Figure 6-5. 3.3-V Test Load Circuit
This section provides the timing requirements and switching characteristics for the various clock optionsavailable on the 280x DSPs. Table 6-2 lists the cycle times of various clocks.
Table 6-2. TMS320x280x Clock Table and Nomenclature
MIN NOM MAX UNIT
t
c(OSC)
, Cycle time 28.6 50 nsOn-chip oscillatorclock
Frequency 20 35 MHzt
c(CI)
, Cycle time 10 250 nsXCLKIN
Frequency 4 100 MHzt
c(SCO)
, Cycle time 10 500 nsSYSCLKOUT
Frequency 2 100 MHzt
c(XCO)
, Cycle time 10 2000 nsXCLKOUT
Frequency 0.5 100 MHzt
c(HCO)
, Cycle time 10 20
(1)
nsHSPCLK
Frequency 50
(1)
100 MHzt
c(LCO)
, Cycle time 20 40
(1)
nsLSPCLK
Frequency 25
(1)
50 MHzt
c(ADCCLK)
, Cycle time 80 nsADC clock
Frequency 12.5 MHzt
c(SPC)
, Cycle time 80 nsSPI clock
Frequency 12.5 MHz
(1) This is the default reset value if SYSCLKOUT = 100 MHz.
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6.11 Clock Requirements and Characteristics
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
The clock provided at the XCLKIN pin generates the internal CPU clock cycle.
Table 6-3. Input Clock Frequency
PARAMETER MIN TYP MAX UNIT
Resonator 20 35f
x
Input clock frequency Crystal 20 35 MHzXCLKIN 4 100f
l
Limp mode clock frequency 2 MHz
Table 6-4. XCLKIN Timing Requirements - PLL Bypassed or Enabled
NO. MIN MAX UNIT
C8 t
c(CI)
Cycle time, XCLKIN 10 250 nsC9 t
f(CI)
Fall time, XCLKIN Up to 30 MHz 6 ns30 MHz to 100 MHz 2 nsC10 t
r(CI)
Rise time, XCLKIN Up to 30 MHz 6 ns30 MHz to 100 MHz 2 nsC11 t
w(CIL)
Pulse duration, X1/XCLKIN low as a percentage of t
c(CI)
40 60 %C12 t
w(CIH)
Pulse duration, X1 XCLKIN high as a percentage of t
c(CI)
40 60 %
Table 6-5. XCLKIN Timing Requirements - PLL Disabled
NO. MIN MAX UNIT
C8 t
c(CI)
Cycle time, XCLKIN 10 250 nsC9 t
f(CI)
Fall time, XCLKIN Up to 30 MHz 6 ns30 MHz to 100 MHz 2 nsC10 t
r(CI)
Rise time, XCLKIN Up to 30 MHz 6 ns30 MHz to 100 MHz 2 nsC11 t
w(CIL)
Pulse duration, X1/XCLKIN low as a percentage of t
c(CI)
40 60 %C12 t
w(CIH)
Pulse duration, X1 XCLKIN high as a percentage of t
c(CI)
40 60 %
The possible configuration modes are shown in Table 3-15 .
Table 6-6. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
(1) (2)
NO. PARAMETER MIN TYP MAX UNIT
C1 t
c(XCO)
Cycle time, XCLKOUT 10 nsC3 t
f(XCO)
Fall time, XCLKOUT 2 nsC4 t
r(XCO)
Rise time, XCLKOUT 2 nsC5 t
w(XCOL)
Pulse duration, XCLKOUT low H-2 H+2 nsC6 t
w(XCOH)
Pulse duration, XCLKOUT high H-2 H+2 nsC7 t
p
PLL lock time 131072t
c(CI)
ns
(1) A load of 40 pF is assumed for these parameters.(2) H = 0.5t
c(XCO)
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C4
C3
XCLKOUT(B)
XCLKIN
C5
C9
C10
C1
C8
C6
(A)
6.12 Reset Timing
6.13 Power Sequencing
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown isintended to illustrate the timing parameters only and may differ based on configuration.B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 6-6. Clock Timing
Table 6-7. Reset ( XRS) Timing Requirements
(1)
MIN NOM MAX UNIT
t
w(RSL1)
Pulse duration, stable XCLKIN to XRS high 8t
c(CI)
cyclesWarm reset 8t
c(CI)t
w(RSL2)
Pulse duration, XRS low cyclesWD-initiated reset 512t
c(CI)
Pulse duration, reset pulse generated by watch-t
w(WDRS)
512t
c(CI)
cyclesdogt
d(EX)
Delay time, address/data valid after XRS high 32t
c(CI)
cyclest
OSCST
(2)
Oscillator start-up time 1 10 mst
h(boot-mode)
Hold time for boot-mode pins 2520t
c(CI)
cycles
(1) If external oscillator/clock sources are used, reset time has to be low at least for 1 ms after V
DD
reaches 1.5 V.(2) Dependent on crystal/resonator and board design.
The restrictions placed on power sequencing for the 281x devices have been relaxed for the 280xdevices. For the 281x devices, the power sequencing requirements dictate that the 3.3-V rail must beginits ramp prior to the 1.8-V (or 1.9-V) rail. For 280x devices, the 3.3-V and 1.8-V rail can instead ramptogether. For customers migrating their design from the 281x, the sequencing scheme used for the 281xdevices can still be applied to a 280x device.
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tw(RSL1)
th(boot-mode)(B)
VDDIO, VDD3VFL
VDDA2, VDDAIO
(3.3 V)
XCLKIN
X1
XRS
Boot-Mode
Pins
VDD, VDD1A18,
VDD2A18
(1.8 V)
XCLKOUT
I/O Pins
User-Code Dependent
User-Code Dependent
Boot-ROM Execution Starts Peripheral/GPIO Function
Based on Boot Code
GPIO Pins as Input
XCLKIN/8(A)
GPIO Pins as Input (State Depends on Internal PU/PD)
tOSCST
User-Code Dependent
Address/Data/
Control
(Internal)
Address/Data Valid. Internal Boot-ROM Code Execution Phase
User-Code Execution Phase
td(EX)
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
A. Upon power up, SYSCLKOUT is XCLKIN/2. Since the XCLKOUTDIV bits in the XCLK register come up with a resetstate of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT =XCLKIN/8 during this phase.B. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot codebranches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (indebugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. TheSYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6-7. Power-on Reset
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XCLKIN/8
(XCLKIN * 5)
th(boot-mode)(A)
tw(RSL2)
XCLKIN
X1
XRS
Boot-Mode
Pins
XCLKOUT
I/O Pins
Address/Data/
Control
(Internal)
Boot-ROM Execution Starts
User-Code Execution Starts
User-Code Dependent
User-Code Execution Phase
(Don’t Care)
User-Code Dependent
User-Code Execution
Peripheral/GPIO Function
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
GPIO Pins as Input Peripheral/GPIO Function
td(EX)
X1/XCLKIN
SYSCLKOUT
Write to PLLCR
XCLKIN*2
(Current CPU
Frequency)
XCLKIN/2
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, tp) is
131072 XCLKIN Cycles Long.)
XCLKIN*4
(Changed CPU Frequency)
6.14 High Resolution PWM Characteristics (at SYSCLKOUT = 100 MHz)
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot codebranches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (indebugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. TheSYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6-8. Warm Reset
Figure 6-9. Effect of Writing Into PLLCR Register
MIN TYP MAX UNIT
Micro Edge Positioning (MEP) step size 150 ps
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6.15 On-Chip Analog-to-Digital Converter
6.15.1 ADC Absolute Maximum Ratings
(1)
6.15.2 ADC Electrical Characteristics
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Supply voltage range, V
SSAIO
/V
SSA2
to V
DDAIO
/V
DDA2
-0.3 V to 4.6 VV
SS1AGND
/V
SS2AGND
to V
DD1A18
/V
DD2A18
-0.3 V to 2.5 VAnalog Input (ADCIN) Clamp Current, total (max) ± 20 mA
(2)
(1) Unless otherwise noted, the list of absolute maximum ratings are specified over operating conditions. Stresses beyond those listedunder Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Exposure toabsolute-maximum-rated conditions for extended periods may affect device reliability.(2) The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above V
DDA2
or below V
SSA2
. Thecontinuous clamp current per pin is ± 2 mA.
over recommended operating conditions
PARAMETER MIN TYP MAX UNIT
DC SPECIFICATIONS
(1)
Resolution 12 Bits1 kHzADC clock
12.5 MHz
ACCURACY
1-12.5 MHz ADC clockINL (Integral nonlinearity) ±1.5 LSB(6.25 MSPS)
1-12.5 MHz ADC clockDNL (Differential nonlinearity) ±1 LSB(6.25 MSPS)Offset error
(2)
±60 LSBOffset error with hardware trimming ±4 LSBOverall gain error with internal reference
(3)
±60 LSBOverall gain error with external reference ±60 LSBChannel-to-channel offset variation ±4 LSBChannel-to-channel gain variation ±4 LSB
ANALOG INPUT
Analog input voltage (ADCINx to ADCLO)
(4)
0 3 VADCLO -5 0 5 mVInput capacitance 10 pFInput leakage current 3 ±5 µA
INTERNAL VOLTAGE REFERENCE
(3)
V
ADCREFP
- ADCREFP output voltage at the pin based on internal reference 1.275 VV
ADCREFM
- ADCREFM output voltage at the pin based on internal reference 0.525 VVoltage difference, ADCREFP - ADCREFM 0.75 VTemperature coefficient 50 PPM/°CReference noise 100 µV
EXTERNAL VOLTAGE REFERENCE
(3) (5)
V
ADCREFIN
- External reference voltage input on ADCREFIN pin 2.048 V
(1) Tested at 12.5-MHz ADCCLK(2) 1 LSB has the weighted value of 3.0/4096 = 0.732 mV.(3) A single internal/external band gap reference sources both ADCREFP and ADCREFM signals, and hence, these voltages tracktogether. The ADC converter uses the difference between these two as its reference. The total gain error will be the combination of thegain error shown here and the voltage reference accuracy (ADCREFP - ADCREFM).(4) Voltages above V
DDA
+ 0.3 V or below V
SS
- 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin.To avoid this, the analog inputs should be kept within these limits.(5) TI recommends using high precision external reference TI part REF3020/3120 or equivalent.
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ac
RsADCIN0
Cp
10 pF
Ron
1 kΩ
1.64 pF
Ch
Switch
Typical Values of the Input Circuit Components:
Switch Resistance (Ron): 1 kΩ
Sampling Capacitor (Ch): 1.64 pF
Parasitic Capacitance (Cp): 10 pF
Source Resistance (Rs): 50 Ω
28x DSP
Source
Signal
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
ADC Electrical Characteristics (continued)
over recommended operating conditions
PARAMETER MIN TYP MAX UNIT
AC SPECIFICATIONS
SINAD (100 kHz) Signal-to-noise ratio + distortion 66 dBSNR (100 kHz) Signal-to-noise ratio 67 dBTHD (100 kHz) Total harmonic distortion -74 dBENOB (100 kHz) Effective number of bits 10.6 BitsSFDR (100 kHz) Spurious free dynamic range 76 dB
Figure 6-10. ADC Analog Input Impedance Model
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6.15.3 ADC Power-Up Control Bit Timing
ADC Power Up Delay ADC Ready for Conversions
PWDNBG
PWDNREF
PWDNADC
Request for
ADC
Conversion
td(BGR)
td(PWD)
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Figure 6-11. ADC Power-Up Control Bit Timing
Table 6-8. ADC Power-Up Delays
PARAMETER
(1)
MIN TYP MAX UNIT
t
d(BGR)
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3 5 msregister (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit isenabled.t
d(PWD)
Delay time for power-down control to be stable. Bit delay time for band-gap 20 50 µsreference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0)
1 msmust be set to 1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3register (PWDNADC)must be set to 1 before any ADC conversions are initiated.
(1) Timings maintain compatibility to the 281x ADC module. The 280x ADC also supports driving all 3 bits at the same time and waitingt
d(BGR)
ms before first conversion.
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6.15.4 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
Analog Input on
Channel Ax or Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
tdschx_n
tdschx_n+1
Sample n
Sample n+1Sample n+2
tSH
ADC Event Trigger from
ePWM or Other Sources
td(SH)
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Axto Bx). The ADC can start conversions on event triggers from the ePWM, software trigger, or from anexternal ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel onevery Sample/Hold pulse. The conversion time and latency of the Result register update are explainedbelow. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. Theselected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulsewidth can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
Figure 6-12. Sequential Sampling Mode (Single-Channel) Timing
Table 6-9. Sequential Sampling Mode Timing
SAMPLE n SAMPLE n + 1 AT 12.5 MHz REMARKSADC CLOCK,
t
c(ADCCLK)
= 80 nS
t
d(SH)
Delay time from event trigger to 2.5t
c(ADCCLK)samplingt
SH
Sample/Hold width/Acquisition (1 + Acqps) * 80 ns with Acqps = 0 Acqps value = 0-15Width t
c(ADCCLK)
ADCTRL1[8:11]t
d(schx_n)
Delay time for first result to appear 4t
c(ADCCLK)
320 nsin Result registert
d(schx_n+1)
Delay time for successive results to (2 + Acqps) * 160 nsappear in Result register t
c(ADCCLK)
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6.15.5 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
Analog Input on
Channel Ax
Analog Input on
Channel Bx
ADC Clock
Sample and Hold
SH Pulse
tSH
tdschA0_n
tdschB0_n
tdschB0_n+1
Sample n Sample n+1 Sample n+2
tdschA0_n+1
td(SH)
ADC Event Trigger from
ePWM or Other Sources
SMODE Bit
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, orfrom an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selectedchannels on every Sample/Hold pulse. The conversion time and latency of the result register update areexplained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result registerupdate. The selected channels will be sampled simultaneously at the falling edge of the Sample/Holdpulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADCclocks wide (maximum).
NOTEIn Simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,and not in other combinations (such as A1/B3, etc.).
Figure 6-13. Simultaneous Sampling Mode Timing
Table 6-10. Simultaneous Sampling Mode Timing
SAMPLE n SAMPLE n + 1 AT 12.5 MHz REMARKSADC CLOCK,
t
c(ADCCLK)
= 80 nS
t
d(SH)
Delay time from event trigger to sam- 2.5t
c(ADCCLK)plingt
SH
Sample/Hold width/Acquisition Width (1 + Acqps) * 80 ns with Acqps = 0 Acqps value = 0-15t
c(ADCCLK)
ADCTRL1[8:11]t
d(schA0_n)
Delay time for first result to appear in 4t
c(ADCCLK)
320 nsResult registert
d(schB0_n)
Delay time for first result to appear in 5t
c(ADCCLK)
400 nsResult registert
d(schA0_n+1)
Delay time for successive results to (3 + Acqps) * 240 nsappear in Result register t
c(ADCCLK)
t
d(schB0_n+1)
Delay time for successive results to (3 + Acqps) * 240 nsappear in Result register t
c(ADCCLK)
Electrical Specifications 97
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ADVANCE INFORMATION
6.15.6 Definitions
6.16 Detailed Descriptions
formula,
N(SINAD 1.76)
6.02
it is possible to get a measure of performance expressed as N, the effective
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC.
Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels ata time. These inputs are software-selectable.
Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate withlow power consumption.
Conversion Modes
The conversion can be performed in two different conversion modes:•Sequential sampling mode (SMODE = 0)•Simultaneous sampling mode (SMODE = 1)
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through fullscale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point isdefined as level 1/2 LSB beyond the last code transition. The deviation is measured from the center ofeach particular code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this idealvalue. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as thedeviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The lasttransition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is thedeviation of the actual difference between first and last code transitions and the ideal difference betweenfirst and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectralcomponents below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD isexpressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following
number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequencycan be calculated directly from its measured SINAD.
98 Electrical Specifications
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ADVANCE INFORMATION
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measuredinput signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
Electrical Specifications 99
www.ti.com
ADVANCE INFORMATION
7 Mechanical Data
TMS320F2808, TMS320F2806TMS320F2801, UCD9501Digital Signal Processors
SPRS230E – OCTOBER 2003 – REVISED APRIL 2005
The following mechanical package diagram(s) reflect the most current released mechanical data availablefor the designated device(s).
100 Mechanical Data
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TMS320F2801GGMA PREVIEW BGA GGM 100 184 TBD Call TI Call TI
TMS320F2801GGMQ PREVIEW BGA GGM 100 184 TBD Call TI Call TI
TMS320F2801PZA PREVIEW LQFP PZ 100 90 TBD Call TI Call TI
TMS320F2801PZQ PREVIEW LQFP PZ 100 90 TBD Call TI Call TI
TMS320F2801ZGMA PREVIEW BGA MI
CROSTA
R
ZGM 100 184 TBD Call TI Call TI
TMS320F2801ZGMQ PREVIEW BGA MI
CROSTA
R
ZGM 100 184 TBD Call TI Call TI
TMS320F2806GGMA PREVIEW BGA GGM 100 184 TBD Call TI Call TI
TMS320F2806GGMQ PREVIEW BGA GGM 100 184 TBD Call TI Call TI
TMS320F2806PZA PREVIEW LQFP PZ 100 90 TBD Call TI Call TI
TMS320F2806PZQ PREVIEW LQFP PZ 100 90 TBD Call TI Call TI
TMS320F2806ZGMA PREVIEW BGA MI
CROSTA
R
ZGM 100 184 TBD Call TI Call TI
TMS320F2806ZGMQ PREVIEW BGA MI
CROSTA
R
ZGM 100 184 TBD Call TI Call TI
TMS320F2808GGMA PREVIEW BGA GGM 100 184 TBD Call TI Call TI
TMS320F2808GGMQ PREVIEW BGA GGM 100 184 TBD Call TI Call TI
TMS320F2808PZA PREVIEW LQFP PZ 100 90 TBD Call TI Call TI
TMS320F2808PZQ PREVIEW LQFP PZ 100 1 TBD Call TI Call TI
TMS320F2808ZGMA PREVIEW BGA MI
CROSTA
R
ZGM 100 184 TBD Call TI Call TI
TMS320F2808ZGMQ PREVIEW BGA MI
CROSTA
R
ZGM 100 184 TBD Call TI Call TI
TMX320F2801GGMA ACTIVE BGA GGM 100 1 TBD Call TI Call TI
TMX320F2801PZA ACTIVE LQFP PZ 100 1 TBD Call TI Call TI
TMX320F2806GGMA ACTIVE BGA GGM 100 1 TBD Call TI Call TI
TMX320F2806PZA ACTIVE LQFP PZ 100 1 TBD Call TI Call TI
TMX320F2808GGMA ACTIVE BGA GGM 100 1 TBD Call TI Call TI
TMX320F2808PZA ACTIVE LQFP PZ 100 1 TBD Call TI Call TI
UCD9501PZA PREVIEW LQFP PZA 100 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2005
Addendum-Page 1
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2005
Addendum-Page 2
MECHANICAL DATA
MPBG028B FEBRUAR Y 1997 – REVISED MAY 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GGM (S–PBGA–N100) PLASTIC BALL GRID ARRAY
0,08 0,10
1,40 MAX
0,85
0,55
0,45 0,45
0,35
0,95
4
C
B
A
D
E
213
K
F
G
H
J
576 9810
Seating Plane
SQ
9,90
10,10 7,20 TYP
0,40
0,40
A1 Corner
Bottom View
4145257–3/C 12/01
0,80
0,80
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice
C. MicroStar BGA configuration.
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK
4040149/B 11/96
50
26 0,13 NOM
Gage Plane
0,25
0,45
0,75
0,05 MIN
0,27
51
25
75
1
12,00 TYP
0,17
76
100
SQ
SQ
15,80
16,20
13,80
1,35
1,45
1,60 MAX
14,20
0°–7°
Seating Plane
0,08
0,50 M
0,08
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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