W25Q256FV
Publication Release Date: February 26, 2016
Preliminary Revision I
3V 256M-BIT
SERIAL FLASH MEMORY WITH
DUAL/QUAD SPI & QPI
W25Q256FV
- 1 -
Table of Contents
1. GENERAL DESCRIPTIONS ............................................................................................................. 5
2. FEATURES ....................................................................................................................................... 5
3. PACKAGE TYPES AND PIN CONFIGURATIONS ........................................................................... 6
3.1 Pad Configuration WSON 8x6-mm ...................................................................................... 6
3.2 Pad Description WSON 8x6-mm .......................................................................................... 6
3.3 Pin Configuration SOIC 300-mil ........................................................................................... 7
3.4 Pin Description SOIC 300-mil ............................................................................................... 7
3.5 Pin Configuration PDIP 300-mil ............................................................................................ 8
3.6 Pin Description SOIC 150/208-mil, WSON 6x5-mm / USON 4x3-mm / PDIP 300-mil ........ 8
3.7 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 9
3.8 Ball Description TFBGA 8x6-mm ......................................................................................... 9
4. PIN DESCRIPTIONS ...................................................................................................................... 10
4.1 Chip Select (/CS) ................................................................................................................ 10
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ................................... 10
4.3 Write Protect (/WP) ............................................................................................................ 10
4.4 HOLD (/HOLD) ................................................................................................................... 10
4.5 Serial Clock (CLK) .............................................................................................................. 10
4.6 Reset (/RESET) .................................................................................................................. 10
5. BLOCK DIAGRAM .......................................................................................................................... 11
6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 12
6.1 SPI / QPI Operations .......................................................................................................... 12
6.1.1 Standard SPI Instructions ..................................................................................................... 12
6.1.2 Dual SPI Instructions ............................................................................................................ 12
6.1.3 Quad SPI Instructions ........................................................................................................... 13
6.1.4 QPI Instructions .................................................................................................................... 13
6.1.5 3-Byte / 4-Byte Address Modes ............................................................................................ 13
6.1.6 Hold Function ....................................................................................................................... 14
6.1.7 Software Reset & Hardware /RESET pin .............................................................................. 14
6.2 Write Protection .................................................................................................................. 15
7. STATUS AND CONFIGURATION REGISTERS ............................................................................ 16
7.1 Status Registers ................................................................................................................. 16
7.1.1 Erase/Write In Progress (BUSY) Status Only ................................................................ 16
7.1.2 Write Enable Latch (WEL) Status Only .......................................................................... 16
7.1.3 Block Protect Bits (BP3, BP2, BP1, BP0) Volatile/Non-Volatile Writable ....................... 17
7.1.4 Top/Bottom Block Protect (TB) Volatile/Non-Volatile Writable ....................................... 17
7.1.5 Complement Protect (CMP) Volatile/Non-Volatile Writable ............................................ 17
W25Q256FV
Publication Release Date: February 26, 2016
- 2 - Preliminary Revision I
7.1.6 Status Register Protect (SRP1, SRP0) Volatile/Non-Volatile Writable ........................... 17
7.1.7 Erase/Program Suspend Status (SUS) Status Only....................................................... 18
7.1.8 Security Register Lock Bits (LB3, LB2, LB1) Volatile/Non-Volatile OTP Writable .......... 18
7.1.9 Quad Enable (QE) Volatile/Non-Volatile Writable .......................................................... 18
7.1.10 Current Address Mode (ADS) Status Only ................................................................... 19
7.1.11 Power-Up Address Mode (ADP) Non-Volatile Writable ................................................ 19
7.1.12 Write Protect Selection (WPS) Volatile/Non-Volatile Writable ..................................... 19
7.1.13 Output Driver Strength (DRV1, DRV0) Volatile/Non-Volatile Writable ......................... 20
7.1.14 /HOLD or /RESET Pin Function (HOLD/RST) Volatile/Non-Volatile Writable .............. 20
7.1.15 Reserved Bits Non Functional ...................................................................................... 20
7.1.16 W25Q256FV Status Register Memory Protection (WPS = 0, CMP = 0) ............................ 21
7.1.17 W25Q256FV Status Register Memory Protection (WPS = 0, CMP = 1) ............................ 22
7.1.18 W25Q256FV Individual Block Memory Protection (WPS=1) .............................................. 23
7.2 Extended Address Register Volatile Writable Only ...................................................... 24
8. INSTRUCTIONS ............................................................................................................................. 25
8.1 Device ID and Instruction Set Tables ................................................................................. 25
8.1.1 Manufacturer and Device Identification ................................................................................ 25
8.1.2 Instruction Set Table 1 (Standard/Dual/Quad SPI, 3-Byte & 4-Byte Address Mode)(1) ......... 26
8.1.3 Instruction Set Table 2 (Standard/Dual/Quad SPI Instructions, 3-Byte Address Mode)(1) .... 27
8.1.4 Instruction Set Table 3 (Standard/Dual/Quad SPI Instructions, 4-Byte Address Mode)(1) .... 28
8.1.5 Instruction Set Table 4 (QPI Instructions, 3-Byte & 4-Byte Address Mode)(14) ..................... 29
8.1.6 Instruction Set Table 5 (QPI Instructions, 3-Byte Address Mode)(14) .................................... 30
8.1.7 Instruction Set Table 6 (QPI Instructions, 4-Byte Address Mode)(14) .................................... 30
8.2 Instruction Descriptions ...................................................................................................... 32
8.2.1 Write Enable (06h) ............................................................................................................... 32
8.2.2 Write Enable for Volatile Status Register (50h) .................................................................... 32
8.2.3 Write Disable (04h) ............................................................................................................... 33
8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) .............. 33
8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) .............. 34
8.2.6 Read Extended Address Register (C8h) .............................................................................. 37
8.2.7 Write Extended Address Register (C5h) .............................................................................. 38
8.2.8 Enter 4-Byte Address Mode (B7h) ........................................................................................ 39
8.2.9 Exit 4-Byte Address Mode (E9h) .......................................................................................... 39
8.2.10 Read Data (03h) ................................................................................................................. 40
8.2.11 Read Data with 4-Byte Address (13h) ................................................................................ 41
8.2.12 Fast Read (0Bh) ................................................................................................................. 42
8.2.13 Fast Read with 4-Byte Address (0Ch) ................................................................................ 44
8.2.14 Fast Read Dual Output (3Bh) ............................................................................................. 45
8.2.15 Fast Read Dual Output with 4-Byte Address (3Ch) ............................................................ 46
8.2.16 Fast Read Quad Output (6Bh) ............................................................................................ 47
8.2.17 Fast Read Quad Output with 4-Byte Address (6Ch) ........................................................... 48
W25Q256FV
- 3 -
8.2.18 Fast Read Dual I/O (BBh) ................................................................................................... 49
8.2.19 Fast Read Dual I/O with 4-Byte Address (BCh) .................................................................. 51
8.2.20 Fast Read Quad I/O (EBh) ................................................................................................. 53
8.2.21 Fast Read Quad I/O with 4-Byte Address (ECh) ................................................................ 56
8.2.22 Word Read Quad I/O (E7h) ................................................................................................ 58
8.2.23 Octal Word Read Quad I/O (E3h) ....................................................................................... 60
8.2.24 Set Burst with Wrap (77h) .................................................................................................. 62
8.2.25 Page Program (02h) ........................................................................................................... 63
8.2.26 Quad Input Page Program (32h) ........................................................................................ 65
8.2.27 Sector Erase (20h) ............................................................................................................. 66
8.2.28 32KB Block Erase (52h) ..................................................................................................... 67
8.2.29 64KB Block Erase (D8h) ..................................................................................................... 68
8.2.30 Chip Erase (C7h / 60h) ....................................................................................................... 69
8.2.31 Erase / Program Suspend (75h) ......................................................................................... 70
8.2.32 Erase / Program Resume (7Ah) ......................................................................................... 72
8.2.33 Power-down (B9h) .............................................................................................................. 73
8.2.34 Release Power-down / Device ID (ABh) ............................................................................. 74
8.2.35 Read Manufacturer / Device ID (90h) ................................................................................. 76
8.2.36 Read Manufacturer / Device ID Dual I/O (92h) ................................................................... 77
8.2.37 Read Manufacturer / Device ID Quad I/O (94h) ................................................................. 78
8.2.38 Read Unique ID Number (4Bh)........................................................................................... 79
8.2.39 Read JEDEC ID (9Fh) ........................................................................................................ 80
8.2.40 Read SFDP Register (5Ah) ................................................................................................ 81
8.2.41 Erase Security Registers (44h) ........................................................................................... 82
8.2.42 Program Security Registers (42h) ...................................................................................... 83
8.2.43 Read Security Registers (48h) ........................................................................................... 84
8.2.44 Set Read Parameters (C0h) ............................................................................................... 85
8.2.45 Burst Read with Wrap (0Ch) ............................................................................................... 86
8.2.46 Enter QPI Mode (38h) ......................................................................................................... 87
8.2.47 Exit QPI Mode (FFh) ........................................................................................................... 88
8.2.48 Individual Block/Sector Lock (36h) ..................................................................................... 89
8.2.49 Individual Block/Sector Unlock (39h) .................................................................................. 90
8.2.50 Read Block/Sector Lock (3Dh) ........................................................................................... 91
8.2.51 Global Block/Sector Lock (7Eh) .......................................................................................... 92
8.2.52 Global Block/Sector Unlock (98h) ....................................................................................... 92
8.2.53 Enable Reset (66h) and Reset Device (99h) ...................................................................... 93
9. ELECTRICAL CHARACTERISTICS ............................................................................................... 94
9.1 Absolute Maximum Ratings (1)(2) ...................................................................................... 94
9.2 Operating Ranges............................................................................................................... 94
9.3 Power-up Timing and Write Inhibit Threshold(1) ................................................................ 95
9.4 DC Electrical Characteristics .............................................................................................. 96
9.5 AC Measurement Conditions(1) ......................................................................................... 97
W25Q256FV
Publication Release Date: February 26, 2016
- 4 - Preliminary Revision I
9.6 AC Electrical Characteristics(6) ........................................................................................... 98
9.7 Serial Output Timing ......................................................................................................... 100
9.8 Serial Input Timing ............................................................................................................ 100
9.9 /HOLD Timing ................................................................................................................... 100
9.10 /WP Timing ....................................................................................................................... 100
10. PACKAGE SPECIFICATIONS ...................................................................................................... 101
10.1 8-Pad WSON 8x6-mm (Package Code E) ....................................................................... 101
10.2 8-Pin PDIP 300-mil (Package Code A) ............................................................................. 102
10.3 16-Pin SOIC 300-mil (Package Code F) .......................................................................... 103
10.4 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 Ball Array) ......................................... 104
10.5 24-Ball TFBGA 8x6-mm (Package Code C, 6x4 Ball Array) ............................................ 105
11. ORDERING INFORMATION ........................................................................................................ 106
11.1 Valid Part Numbers and Top Side Marking ...................................................................... 107
12. REVISION IISTORY .................................................................................................................... 108
W25Q256FV
- 5 -
1. GENERAL DESCRIPTIONS
The W25Q256FV (256M-bit) Serial Flash memory provides a storage solution for systems with limited
space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash
devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP)
and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current
consumption as low as 4mA active and A for power-down. All devices are offered in space-saving
packages.
The W25Q256FV array is organized into 131,072 programmable pages of 256-bytes each. Up to 256
bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of
128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The
W25Q256FV has 8,192 erasable sectors and 512 erasable blocks respectively. The small 4KB sectors
allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.)
The W25Q256FV support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2-
clocks instruction cycle Quad Peripheral Interface (QPI): Serial Clock, Chip Select, Serial Data I/O0 (DI),
I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing
equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when
using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard
Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient
memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP
(execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide
further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID
and SFDP Register, a 64-bit Unique Serial Number and three 256-bytes Security Registers.
2. FEATURES
New Family of SpiFlash Memories
W25Q256FV: 256M-bit / 32M-byte
Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
3 or 4-Byte Addressing Mode
Software & Hardware Reset
Highest Performance Serial Flash
104MHz Standard/Dual/Quad SPI clocks
208/416MHz equivalent Dual/Quad SPI
50MB/S continuous data transfer rate
More than 100,000 erase/program cycles
More than 20-year data retention
Efficient “Continuous Read”
Continuous Read with 8/16/32/64-Byte Wrap
As few as 8 clocks to address memory
Quad Peripheral Interface (QPI) reduces
instruction overhead
Allows true XIP (execute in place) operation
Outperforms X16 Parallel Flash
Low Power, Wide Temperature Range
Single 2.7 to 3.6V supply
4mA active current, <1µA Power-down (typ.)
-40°C to +85°C operating range
Flexible Architecture with 4KB sectors
Uniform Sector/Block Erase (4K/32K/64K-Byte)
Program 1 to 256 byte per programmable page
Erase/Program Suspend & Resume
Advanced Security Features
Software and Hardware Write-Protect
Power Supply Lock-Down and OTP protection
Top/Bottom, Complement array protection
Individual Block/Sector array protection
64-Bit Unique ID for each device
Discoverable Parameters (SFDP) Register
3X256-Bytes Security Registers with OTP locks
Volatile & Non-volatile Status Register Bits
Space Efficient Packaging
8-pad WSON 8x6-mm
8-pin PDIP 300-mil
16-pin SOIC 300-mil (additional /RESET pin)
24-ball TFBGA 8x6-mm
Contact Winbond for KGD and other options
W25Q256FV
Publication Release Date: February 26, 2016
- 6 - Preliminary Revision I
3. PACKAGE TYPES AND PIN CONFIGURATIONS
W25Q256FV is offered in an 8-pad WSON 8x6-mm (package code E), a 16-pin SOIC 300-mil (package
code F) and two 24-ball 8x6-mm TFBGA (package code B & C) packages as shown in Figure 1a-c
respectively. Package diagrams and dimensions are illustrated at the end of this datasheet.
3.1 Pad Configuration WSON 8x6-mm
1
2
3
4
/CS
DO (IO1)
/WP (IO2)
GND
VCC
/HOLD or /RESET
(IO3)
DI (IO0)
CLK
Top View
8
7
6
5
Figure 1a. W25Q256FV Pad Assignments, 8-pad WSON 8x6-mm (Package Code E)
3.2 Pad Description WSON 8x6-mm
PAD NO.
PAD NAME
I/O
1
/CS
I
2
DO (IO1)
I/O
3
/WP (IO2)
I/O
4
GND
5
DI (IO0)
I/O
6
CLK
I
7
/HOLD or /RESET
(IO3)
I/O
8
VCC
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.
W25Q256FV
- 7 -
3.3 Pin Configuration SOIC 300-mil
1
2
3
4
/CS
DO (IO1) /WP (IO2)
GND
VCC
/HOLD (IO3)
DI (IO0)
CLK
Top View
NC
/RESET
NC
NC
NC
NC
NC
NC5
6
7
8
10
9
11
12
13
14
15
16
Figure 1b. W25Q256FV Pin Assignments, 16-pin SOIC 300-mil (Package Code F)
3.4 Pin Description SOIC 300-mil
PIN NO.
PIN NAME
I/O
FUNCTION
1
/HOLD (IO3)
I/O
Hold Input (Data Input Output 3)(2)
2
VCC
Power Supply
3
/RESET
I
Reset Input(3)
4
N/C
No Connect
5
N/C
No Connect
6
N/C
No Connect
7
/CS
I
Chip Select Input
8
DO (IO1)
I/O
Data Output (Data Input Output 1)(1)
9
/WP (IO2)
I/O
Write Protect Input (Data Input Output 2)(2)
10
GND
Ground
11
N/C
No Connect
12
N/C
No Connect
13
N/C
No Connect
14
N/C
No Connect
15
DI (IO0)
I/O
Data Input (Data Input Output 0)(1)
16
CLK
I
Serial Clock Input
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.
3. The /RESET pin on SOIC-16 package is independent of the HOLD/RST bit and QE bit settings in the Status Register. This pin
can be treated as ‘No Connect’ in the system if RESET function is not needed
W25Q256FV
Publication Release Date: February 26, 2016
- 8 - Preliminary Revision I
3.5 Pin Configuration PDIP 300-mil
1
2
3
4
8
7
6
5
/CS
DO (IO1)
/WP (IO2)
GND
VCC
/HOLD (IO3)
DI (IO0)
CLK
Top View
Figure 1c. W25Q16DV Pin Assignments, 8-pin PDIP (Package Code DA)
3.6 Pin Description SOIC 150/208-mil, WSON 6x5-mm / USON 4x3-mm / PDIP 300-mil
PIN NO.
PIN NAME
I/O
FUNCTION
1
/CS
I
Chip Select Input
2
DO (IO1)
I/O
Data Output (Data Input Output 1)*1
3
/WP (IO2)
I/O
Write Protect Input ( Data Input Output 2)*2
4
GND
Ground
5
DI (IO0)
I/O
Data Input (Data Input Output 0)*1
6
CLK
I
Serial Clock Input
7
/HOLD (IO3)
I/O
Hold Input (Data Input Output 3)*2
8
VCC
Power Supply
*1 IO0 and IO1 are used for Standard and Dual SPI instructions
*2 IO0 IO3 are used for Quad SPI instructions
W25Q256FV
- 9 -
3.7 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)
D1 /HOLD(IO3)
/RESET
DI(IO0)DO(IO1)
/WP (IO2)
D2 D3 D4
NC
E1
NCNCNC
E2 E3 E4
NC
F1
NCNCNC
F2 F3 F4
NC
A1
NCNCNC
A2 A3 A4
NC
B1
VCCGNDCLK
B2 B3 B4
NC
C1
NC/CS
C2 C3 C4
NC
Top View
Package Code C
D1 /HOLD(IO3)
/RESET
DI(IO0)DO(IO1)
/WP (IO2)
D2 D3 D4
NC
E1
NCNCNC
E2 E3 E4
NC
B5
NCNCNC
A2 A3 A4
NC
B1
VCCGNDCLK
B2 B3 B4
NC
C1
NC/CS
C2 C3 C4
NC
Top View
Package Code B
C5
NC
D5
NC
E5
NC
A5
NC
Figure 1c. W25Q256FV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code B & C)
3.8 Ball Description TFBGA 8x6-mm
BALL NO.
PIN NAME
I/O
FUNCTION
B2
CLK
I
Serial Clock Input
B3
GND
Ground
B4
VCC
Power Supply
C2
/CS
I
Chip Select Input
C4
/WP (IO2)
I/O
Write Protect Input (Data Input Output 2)(2)
D2
DO (IO1)
I/O
Data Output (Data Input Output 1)(1)
D3
DI (IO0)
I/O
Data Input (Data Input Output 0)(1)
D4
/HOLD or /RESET
(IO3)
I/O
Hold or Reset Input (Data Input Output 3)(2)
Multiple
NC
No Connect
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.
W25Q256FV
Publication Release Date: February 26, 2016
- 10 - Preliminary Revision I
4. PIN DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
input must track the VCC supply level at power-up (see “Write Protection” and Figure 58). If needed a pull-
up resister on the /CS pin can be used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25Q256FV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge of
CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.
4.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (CMP, TB, BP3, BP2, BP1 and BP0) bits and Status
Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be
hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O,
the /WP pin function is not available since this pin is used for IO2. See Figure 1a-c for the pin
configuration of Quad I/O operation.
4.4 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,
while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored
(don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be
useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the
QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is
used for IO3. See Figure 1a-c for the pin configuration of Quad I/O operation.
4.5 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Operations")
4.6 Reset (/RESET)
The /RESET pin allows the device to be reset by the controller. For 8-pin packages, when QE=0, the IO3
pin can be configured either as a /HOLD pin or as a /RESET pin depending on Status Register setting.
When QE=1, the /HOLD or /RESET function is not available for 8-pin configuration.
W25Q256FV
- 11 -
5. BLOCK DIAGRAM
Figure 2. W25Q256FV Serial Flash Memory Block Diagram
003000h 0030FFh
002000h 0020FFh
001000h 0010FFh
Column Decode
And 256-Byte Page Buffer
Beginning
Page Address Ending
Page Address
W25Q256FV
SPI
Command &
Control Logic
Byte Address
Latch / Counter
Status
Register
Write Control
Logic
Page Address
Latch / Counter
DO (IO1)
DI (IO0)
/CS
CLK
/HOLD (IO3)
or RESET
/WP (IO2)
High Voltage
Generators
xx0F00h xx0FFFh
Sector 0 (4KB)
xx0000h xx00FFh
xx1F00h xx1FFFh
Sector 1 (4KB)
xx1000h xx10FFh
xx2F00h xx2FFFh
Sector 2 (4KB)
xx2000h xx20FFh
xxDF00h xxDFFFh
Sector 13 (4KB)
xxD000h xxD0FFh
xxEF00h xxEFFFh
Sector 14 (4KB)
xxE000h xxE0FFh
xxFF00h xxFFFFh
Sector 15 (4KB)
xxF000h xxF0FFh
Block Segmentation
Data
Security Register 1 - 3
Write Protect Logic and Row Decode
000000h 0000FFh
SFDP Register
0000FF00h 0000FFFFh
Block 0 (64KB)
00000000h 000000FFh
007FFF00h 007FFFFFh
Block 127 (64KB)
007F0000h 007F00FFh
0080FF00h 0080FFFFh
Block 128 (64KB)
00800000h 008000FFh
00FFFF00h 00FFFFFFh
Block 255 (64KB)
00FF0000h 00FF00FFh
0100FF00h 0100FFFFh
Block 256 (64KB)
01000000h 010000FFh
01FFFF00h 01FFFFFFh
Block 511 (64KB)
01FF0000h 01FF00FFh
W25Q256FV
Publication Release Date: February 26, 2016
- 12 - Preliminary Revision I
6. FUNCTIONAL DESCRIPTIONS
6.1 SPI / QPI Operations
Power Up
ADP bit value
3-Byte Address
Standard SPI
Dual SPI
Quad SPI
Enable 4-Byte (B7h)
4-Byte Address
QPI
4-Byte Address
Standard SPI
Dual SPI
Quad SPI
3-Byte Address
QPI
Disable 4-Byte (E9h)
Enable 4-Byte (B7h)
Disable 4-Byte (E9h)
Enable QPI (38h) Enable QPI (38h)Disable QPI (FFh) Disable QPI (FFh)
SPI Reset
(66h + 99h)
QPI Reset
(66h + 99h)
ADP = 0 ADP = 1
Device Initialization
& Status Register Refresh
(Non-Volatile Cells)
Hardware
Reset
Hardware
Reset
Figure 3. W25Q256FV Serial Flash Memory Operation Diagram
6.1.1 Standard SPI Instructions
The W25Q256FV is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions
use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of
CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is
not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and
rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
6.1.2 Dual SPI Instructions
The W25Q256FV supports Dual SPI operation when using instructions such as Fast Read Dual Output
(3Bh)” and “Fast Read Dual I/O (BBh). These instructions allow data to be transferred to or from the
device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are
ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-
W25Q256FV
- 13 -
critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins
become bidirectional I/O pins: IO0 and IO1.
6.1.3 Quad SPI Instructions
The W25Q256FV supports Quad SPI operation when using instructions such as Fast Read Quad Output
(6Bh)”, Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h) and “Octal Word Read Quad I/O
(E3h). These instructions allow data to be transferred to or from the device four to six times the rate of
ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and
random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus
(XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the
/WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile
Quad Enable bit (QE) in Status Register-2 to be set.
6.1.4 QPI Instructions
The W25Q256FV supports Quad Peripheral Interface (QPI) operations only when the device is switched
from Standard/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction. The typical SPI
protocol requires that the byte-long instruction code being shifted into the device only via DI pin in eight
serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial
clocks are required. This can significantly reduce the SPI instruction overhead and improve system
performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only
one mode can be active at any given time. “Enter QPI (38h)” and “Exit QPI (FFh)” instructions are used to
switch between these two modes. Upon power-up or after a software reset using “Reset (99h)” instruction,
the default state of the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile
Quad Enable bit (QE) in Status Register-2 is required to be set. When using QPI instructions, the DI and
DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3
respectively. See Figure 3 for the device operation modes.
6.1.5 3-Byte / 4-Byte Address Modes
The W25Q256FV provides two Address Modes that can be used to specify any byte of data in the
memory array. The 3-Byte Address Mode is backward compatible to older generations of serial flash
memory that only support up to 128M-bit data. To address the 256M-bit or more data in 3-Byte Address
Mode, Extended Address Register must be used in addition to the 3-Byte addresses.
4-Byte Address Mode is designed to support Serial Flash Memory devices from 256M-bit to 32G-bit. The
extended Address Register is not necessary when the 4-Byte Address Mode is enabled.
Upon power up, the W25Q256FV can operate in either 3-Byte Address Mode or 4-Byte Address Mode,
depending on the Non-Volatile Status Register Bit ADP (S17) setting. If ADP=0, the device will operate in
3-Byte Address Mode; if ADP=1, the device will operate in 4-Byte Address Mode. The factory default value
for ADP is 0.
To switch between the 3-Byte or 4-Byte Address Modes, “Enter 4-Byte Mode (B7h)” or Exit 4-Byte Mode
(E9h)” instructions must be used. The current address mode is indicated by the Status Register Bit ADS
(S16).
W25Q256FV
Publication Release Date: February 26, 2016
- 14 - Preliminary Revision I
6.1.6 Hold Function
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q256FV operation to be
paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where
the SPI data and clock signals are shared with other devices. For example, consider if the page buffer
was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD
function can save the state of the instruction and the data in the buffer so programming can resume where
it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual
SPI operation, not during Quad SPI. The Quad Enable Bit QE in Status Register-2 is used to determine if
the pin is used as /HOLD pin or data I/O pin. When QE=0 (factory default), the pin is /HOLD, when QE=1,
the pin will become an I/O pin, /HOLD function is no longer available.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on
the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the
/HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the
rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD
condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data
Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip
Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid
resetting the internal logic state of the device.
6.1.7 Software Reset & Hardware /RESET pin
The W25Q256FV can be reset to the initial power-on state by a software Reset sequence, either in SPI
mode or QPI mode. This sequence must include two consecutive commands: Enable Reset (66h) &
Reset (99h). If the command sequence is successfully accepted, the device will take approximately 30uS
(tRST) to reset. No command will be accepted during the reset period.
For the WSON-8 and TFBGA package types, W25Q256FV can also be configured to utilize a hardware
/RESET pin. The HOLD/RST bit in the Status Register-3 is the configuration bit for /HOLD pin function or
RESET pin function. When HOLD/RST=0 (factory default), the pin acts as a /HOLD pin as described
above; when HOLD/RST=1, the pin acts as a /RESET pin. Drive the /RESET pin low for a minimum period
of ~1us (tRESET*) will reset the device to its initial power-on state. Any on-going Program/Erase operation
will be interrupted and data corruption may happen. While /RESET is low, the device will not accept any
command input.
If QE bit is set to 1, the /HOLD or /RESET function will be disabled, the pin will become one of the four
data I/O pins.
Hardware /RESET pin has the highest priority among all the input signals. Drive /RESET low for a
minimum period of ~1us (tRESET*) will interrupt any on-going external/internal operations, regardless the
status of other SPI signals (/CS, CLK, IOs, /WP and/or /HOLD).
Note: While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset the device, a
1us minimum is recommended to ensure reliable operation.
W25Q256FV
- 15 -
6.2 Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the W25Q256FV
provides several means to protect the data from inadvertent writes.
Device resets when VCC is below threshold
Time delay write disable after Power-up
Write enable/disable instructions and automatic write disable after erase or program
Software and Hardware (/WP pin) write protection using Status Registers
Additional Individual Block/Sector Locks for array protection
Write Protection using Power-down instruction
Lock Down write protection for Status Register until the next power-up
One Time Program (OTP) write protection for array and Security Registers using Status Register*
* Note: This feature is available upon special order. Please contact Winbond for details.
Upon power-up or at power-down, the W25Q256FV will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status
Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until
the VCC-min level and tVSL time delay is reached.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-
disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Protect (SRP0, SRP1) and Block Protect (CMP, TB, BP[3:0]) bits. These settings allow a
portion or the entire memory array to be configured as read only. Used in conjunction with the Write
Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See
Status Register section for further information. Additionally, the Power-down instruction offers an extra
level of write protection as all instructions are ignored except for the Release Power-down instruction.
The W25Q256FV also provides another Write Protect method using the Individual Block Locks. Each
64KB block (except the top and bottom blocks, total of 510 blocks) and each 4KB sector within the
top/bottom blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is
0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or
Program commands issued to the corresponding sector or block will be ignored. When the device is
powered on, all Individual Block Lock bits will be 1, so the entire memory array is protected from
Erase/Program. An “Individual Block Unlock (39h)” instruction must be issued to unlock any specific sector
or block.
The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When
WPS=0 (factory default), the device will only utilize CMP, TB, BP[3:0] bits to protect specific areas of the
array; when WPS=1, the device will utilize the Individual Block Locks for write protection.
W25Q256FV
Publication Release Date: February 26, 2016
- 16 - Preliminary Revision I
7. STATUS AND CONFIGURATION REGISTERS
Three Status and Configuration Registers are provided for W25Q256FV. The Read Status Register-1/2/3
instructions can be used to provide status on the availability of the flash memory array, whether the device
is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status,
Erase/Program Suspend status, output driver strength, power-up and current Address Mode. The Write
Status Register instruction can be used to configure the device write protection features, Quad SPI setting,
Security Register OTP locks, Hold/Reset functions, output driver strength and power-up Address Mode.
Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits
(SRP0, SRP1), the Write Enable instruction, and during Standard/Dual SPI operations, the /WP pin.
7.1 Status Registers
S7 S6 S5 S4 S3 S2 S1 S0
SRP0 TB BP3BP2BP1BP0WEL BUSY
Status Register Protect 0
(Volatile/Non-Volatile Writable)
Top/Bottom Protect Bit
(Volatile/Non-Volatile Writable)
Block Protect Bits
(Volatile/Non-Volatile Writable)
Write Enable Latch
(Status-Only)
Erase/Write In Progress
(Status-Only)
Figure 4a. Status Register-1
7.1.1 Erase/Write In Progress (BUSY) Status Only
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or
Erase/Program Security Register instruction. During this time the device will ignore further instructions
except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and
tCE in AC Characteristics). When the program, erase or write status/security register instruction has
completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.
7.1.2 Write Enable Latch (WEL) Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase
Security Register and Program Security Register.
W25Q256FV
- 17 -
7.1.3 Block Protect Bits (BP3, BP2, BP1, BP0) Volatile/Non-Volatile Writable
The Block Protect Bits (BP3, BP2, BP1, BP0) are non-volatile read/write bits in the status register (S5, S4,
S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write
Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can
be protected from Program and Erase instructions (see Status Register Memory Protection table). The
factory default setting for the Block Protection Bits is 0, none of the array protected.
7.1.4 Top/Bottom Block Protect (TB) Volatile/Non-Volatile Writable
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP3, BP2, BP1, BP0) protect from
the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection
table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction
depending on the state of the SRP0, SRP1 and WEL bits.
7.1.5 Complement Protect (CMP) Volatile/Non-Volatile Writable
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in
conjunction with TB, BP3, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once
CMP is set to 1, previous array protection set by TB, BP3, BP2, BP1 and BP0 will be reversed. For
instance, when CMP=0, a top 64KB block can be protected while the rest of the array is not; when
CMP=1, the top 64KB block will become unprotected while the rest of the array become read-only. Please
refer to the Status Register Memory Protection table for details. The default setting is CMP=0.
7.1.6 Status Register Protect (SRP1, SRP0) Volatile/Non-Volatile Writable
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register
(S8 and S7). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable (OTP) protection.
SRP1
SRP0
/WP
Status
Register
Description
0
0
X
Software
Protection
/WP pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
0
1
0
Hardware
Protected
When /WP pin is low the Status Register locked and cannot
be written to.
0
1
1
Hardware
Unprotected
When /WP pin is high the Status register is unlocked and can
be written to after a Write Enable instruction, WEL=1.
1
0
X
Power Supply
Lock-Down
Status Register is protected and cannot be written to again
until the next power-down, power-up cycle.(1)
1
1
X
One Time
Program(2)
Status Register is permanently protected and cannot be
written to.
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available upon special order. Please contact Winbond for details.
W25Q256FV
Publication Release Date: February 26, 2016
- 18 - Preliminary Revision I
S15 S14 S13 S12 S11 S10 S9 S8
SUS CMP LB3LB2LB1 (R) QE SRP1
Status Register Protect 1
(Volatile/Non-Volatile Writable)
Complement Protect
(Volatile/Non-Volatile Writable)
Security Register Lock Bits
(Volatile/Non-Volatile OTP Writable)
Reserved
Quad Enable
(Volatile/Non-Volatile Writable)
Suspend Status
(Status-Only)
Figure 4b. Status Register-2
7.1.7 Erase/Program Suspend Status (SUS) Status Only
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a
Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume
(7Ah) instruction as well as a power-down, power-up cycle.
7.1.8 Security Register Lock Bits (LB3, LB2, LB1) Volatile/Non-Volatile OTP Writable
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The
default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the
Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-Byte Security Register will become read-only permanently.
7.1.9 Quad Enable (QE) Volatile/Non-Volatile Writable
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that enables Quad SPI
operation. When the QE bit is set to a 0 state (factory default for part number with ordering options IG
and IF), the /WP pin and /HOLD are enabled, the device operates in Standard/Dual SPI modes. When
the QE bit is set to a 1(factory default for Quad Enabled part numbers with ordering option IQ), the Quad
IO2 and IO3 pins are enabled, and /WP and /HOLD functions are disabled, the device operates in
Standard/Dual/Quad SPI modes.
QE bit is required to be set to a 1 before issuing an “Enter QPI (38h)” to switch the device from
Standard/Dual/Quad SPI to QPI, otherwise the command will be ignored. When the device is in QPI mode,
QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot change QE bit from a
“1” to a “0”.
WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during
standard SPI or Dual SPI operation, the QE bit should never be set to a 1.
W25Q256FV
- 19 -
S23 S22 S21 S20 S19 S18 S17 S16
HOLD
/RST DRV1DRV0 (R) (R) WPS ADP ADS
Power Up Address Mode
(Non-Volatile Writable)
Output Driver Strength
(Volatile/Non-Volatile Writable)
Reserved
Write Protect Selection
(Volatile/Non-Volatile Writable)
Current Address Mode
(Status-Only)
/HOLD or /RESET Function
(Volatile/Non-Volatile Writable)
Figure 4c. Status Register-3
7.1.10 Current Address Mode (ADS) Status Only
The Current Address Mode bit is a read only bit in the Status Register-3 that indicates which address
mode the device is currently operating in. When ADS=0, the device is in the 3-Byte Address Mode, when
ADS=1, the device is in the 4-Byte Address Mode.
7.1.11 Power-Up Address Mode (ADP) Non-Volatile Writable
The ADP bit is a non-volatile bit that determines the initial address mode when the device is powered on
or reset. This bit is only used during the power on or device reset initialization period, and it is only writable
by the non-volatile Write Status sequence (06h + 11h). When ADP=0 (factory default), the device will
power up into 3-Byte Address Mode, the Extended Address Register must be used to access memory
regions beyond 128Mb. When ADP=1, the device will power up into 4-Byte Address Mode directly.
7.1.12 Write Protect Selection (WPS) Volatile/Non-Volatile Writable
The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the device will
use the combination of CMP, TB, BP[3:0] bits to protect a specific area of the memory array. When
WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The
default value for all Individual Block Lock bits is 1 upon device power on or after reset.
W25Q256FV
Publication Release Date: February 26, 2016
- 20 - Preliminary Revision I
7.1.13 Output Driver Strength (DRV1, DRV0) Volatile/Non-Volatile Writable
The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1, DRV0
Driver Strength
0, 0
100%
0, 1
75%
1, 0
50%
1, 1
25%(default)
7.1.14 /HOLD or /RESET Pin Function (HOLD/RST) Volatile/Non-Volatile Writable
The HOLD/RST bit is used to determine whether /HOLD or /RESET function should be implemented on
the hardware pin. When HOLD/RST=0 (factory default), the pin acts as /HOLD; when HOLD/RST=1, the
pin acts as /RESET. However, /HOLD or /RESET functions are only available when QE=0. If QE is set to
1, the /HOLD and /RESET functions are disabled, the pin acts as a dedicated data I/O pin.
7.1.15 Reserved Bits Non Functional
There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to
ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be
written as “0”, but there will not be any effects.
W25Q256FV
- 21 -
7.1.16 W25Q256FV Status Register Memory Protection (WPS = 0, CMP = 0)
STATUS REGISTER(1)
W25Q256FV (256M-BIT / 32M-BYTE) MEMORY PROTECTION(2)
TB
BP3
BP2
BP1
BP0
PROTECTED
BLOCK(S)
PROTECTED
ADDRESSES
PROTECTED
DENSITY
PROTECTED
PORTION
X
0
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
511
01FF0000h - 01FFFFFFh
64KB
Upper 1/512
0
0
0
1
0
510 thru 511
01FE0000h - 01FFFFFFh
128KB
Upper 1/256
0
0
0
1
1
508 thru 511
01FC0000h - 01FFFFFFh
256KB
Upper 1/128
0
0
1
0
0
504 thru 511
01F80000h - 01FFFFFFh
512KB
Upper 1/64
0
0
1
0
1
496 thru 511
01F00000h - 01FFFFFFh
1MB
Upper 1/32
0
0
1
1
0
480 thru 511
01E00000h - 01FFFFFFh
2MB
Upper 1/16
0
0
1
1
1
448 thru 511
01C00000h - 01FFFFFFh
4MB
Upper 1/8
0
1
0
0
0
384 thru 511
01800000h - 01FFFFFFh
8MB
Upper 1/4
0
1
0
0
1
256 thru 511
01000000h - 01FFFFFFh
16MB
Upper 1/2
1
0
0
0
1
0
00000000h - 0000FFFFh
64KB
Lower 1/512
1
0
0
1
0
0 thru 1
00000000h - 0001FFFFh
128KB
Lower 1/256
1
0
0
1
1
0 thru 3
00000000h - 0003FFFFh
256KB
Lower 1/128
1
0
1
0
0
0 thru 7
00000000h - 0007FFFFh
512KB
Lower 1/64
1
0
1
0
1
0 thru 15
00000000h - 000FFFFFh
1MB
Lower 1/32
1
0
1
1
0
0 thru 31
00000000h - 001FFFFFh
2MB
Lower 1/16
1
0
1
1
1
0 thru 63
00000000h - 003FFFFFh
4MB
Lower 1/8
1
1
0
0
0
0 thru 127
00000000h - 007FFFFFh
8MB
Lower 1/4
1
1
0
0
1
0 thru 255
00000000h - 00FFFFFFh
16MB
Lower 1/2
X
1
1
0
X
0 thru 511
00000000h - 01FFFFFFh
32MB
ALL
X
1
X
1
X
0 thru 511
00000000h - 01FFFFFFh
32MB
ALL
Notes:
1. X = don’t care
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be
ignored.