Integrated Silicon Solution, Inc. 1
Rev. A
11/09/2010
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS42SM32160C
IS42RM32160C
NOVEMBER 2010
FEATURES:
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access and pre-
charge
• Programmable CAS latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8, and Full
Page
• Programmable Burst Sequence:
• Sequential and Interleave
• Auto Refresh (CBR)
• TCSR (Temperature Compensated Self Refresh)
• PASR (Partial Arrays Self Refresh): 1/16, 1/8,
1/4, 1/2, and Full
• Deep Power Down Mode (DPD)
• Driver Strength Control (DS): 1/4, 1/2, and Full
OPTIONS:
• Configuration: 16Mx32
• Power Supply:
IS42SMxxx - Vdd/Vddq = 3.3V
IS42RMxxx - Vdd/Vddq = 2.5V
• Package: 90 Ball BGA (8x13mm)
• Temperature Range:
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
• Die revision: C
16Mx32
512Mb Mobile Synchronous DRAM
DESCRIPTION:
ISSI's IS42SM/RM32160C is a 512Mb Mobile Syn-
chronous DRAM configured as a quad 4M x32 DRAM.
It achieves high-speed data transfer using a pipeline
architecture with a synchronous interface. All inputs and
outputs signals are registered on the rising edge of the
clock input, CLK. The 512Mb SDRAM is internally con-
figured by stacking two 256Mb, 16Mx16 devices. Each
of the 4M x32 banks is organized as 8192 rows by 512
columns by 32 bits.
KEY TIMING PARAMETERS
Parameter -7 -75 Unit
CLK Cycle Time
CAS Latency = 3
7 7.5 ns
CAS Latency = 2
9.6 9.6 ns
CLK Frequency
CAS Latency = 3
143 133 Mhz
CAS Latency = 2
104 104 Mhz
Access Time from CLK
CAS Latency = 3
5.4 5.4 ns
CAS Latency = 2
7 7 ns
ADDRESS TABLE
Parameter 16Mx32
Configuration 4M x 32 x 4 banks
Bank Address Pins BA0, BA1
Autoprecharge Pins A10/AP
Row Addresses A0 – A12
Column Addresses A0 – A8
Refresh Count 8K / 64ms
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IS42RM32160C
FUNCTIONAL BLOCK DIAGRAM (16Mx16)
CLK
CKE
CS
RAS
CAS
WE
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
A10
A12
COMMAND
DECODER
&
CLOCK
GENERATOR MODE
REGISTER
REFRESH
CONTROLLER
REFRESH
COUNTER
SELF
REFRESH
CONTROLLER
ROW
ADDRESS
LATCH
MULTIPLEXER
COLUMN
ADDRESS LATCH
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
DATA IN
BUFFER
DATA OUT
BUFFER
DQML
DQMH
DQ 0-15
V
DD
/V
DDQ
V
ss
/V
ss
Q
13
13
9
13
13
9
16
16 16
16
512
(x 16)
8192
8192
8192
ROW DECODER
8192
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
BANK CONTROL LOGIC
ROW
ADDRESS
BUFFER
A11
2
FUNCTIONAL BLOCK DIAGRAM (16Mx32)
Die 01 Die 02
DQ0 –D
Q31
CS
CLK
CKE
Command
Addresses
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IS42RM32160C
Symbol Type Description
CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of
CLK. CLK also increments the internal burst counter and controls the output registers.
CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE goes low synchronously
with clock (set-up and hold time same as other inputs), the internal clock is suspended from the next clock
cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks
are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes.
CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE
becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during
Power Down and Self Refresh modes, providing low standby power.
BA0, BA1 Input Bank Select: BA0 and BA1 defines to which bank the BankActivate, Read, Write, or BankPrecharge
command is being applied.
A0-A12 Input Address Inputs:A0-A12 are sampled during the BankActivate command (row address A0-A12) and Read/
Write command (column address A0-A8 with A10 defining Auto Precharge) to select one location in the
respective bank. During a Precharge command,A10 is sampled to determine if all banks are to be precharged
(A10 =HIGH).
The address inputs also provide the op-code during a Mode Register Set .
CS Input Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the command decoder.All commands
are masked when CS is sampled HIGH. CS provides for external bank selection on systems with multiple
banks. It is considered part of the command code.
RAS Input Row Address Strobe: The RAS signal defines the operation commands in conjunction with the CAS and
WE signals and is latched at the positive edges of CLK. When RAS and CS are asserted “LOW” and CAS
is asserted “HIGH,” either the BankActivate command or the Precharge command is selected by the WE
signal. When the WE is asserted “HIGH,” the BankActivate command is selected and the bank designated
by BA is turned on to the active state. When the WE is asserted “LOW,” the Precharge command is selected
and the bank designated by BA is switched to the idle state after the precharge operation.
CAS Input Column Address Strobe: The CAS signal defines the operation commands in conjunction with the RAS
and WE signals and is latched at the positive edges of CLK. When RAS is held “HIGH” and CS is asserted
“LOW,” the column access is started by asserting CAS ”LOW.” Then, the Read or Write command is selected
by asserting WE “LOW” or “HIGH.”
WE Input Write Enable: The WE signal defines the operation commands in conjunction with the RAS and CAS signals
and is latched at the positive edges of CLK. The WE input is used to select the BankActivate or Precharge
command and Read or Write command.
DQM0-3 Input Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer controls. The I/O buffers
are placed in a high-z state when DQM is sampled HIGH. Input data is masked when DQM is sampled
HIGH during a write cycle. Output data is masked (two-clock latency) when DQM is sampled HIGH during
a read cycle. DQM3 masks DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0
masks DQ7-DQ0
DQ0-31 Input/
Output
Data I/O: The DQ0-31 input and output data are synchronized with the positive edge of CLK. The I/Os are
byte-maskable during Reads and Writes.
PIN DESCRIPTIONS
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IS42RM32160C
PIN CONFIGURATION
PACKAGE CODE: B 90 BALL FBGA (Top View) (8.00 mm x 13.00 mm Body, 0.8 m Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ26
DQ28
VSSQ
VSSQ
VDDQ
VSS
A4
A7
CLK
DQM1
VDDQ
VSSQ
VSSQ
DQ11
DQ13
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
VDDQ
DQ15
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
A12
A9
NC
VSS
DQ9
DQ14
VSSQ
VSS
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
CAS
VDD
DQ6
DQ1
VDDQ
VDD
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
CS
WE
DQ7
DQ5
DQ3
VSSQ
DQ0
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
A11
RAS
DQM0
VSSQ
VDDQ
VDDQ
DQ4
DQ2
A0-A12 Row Address Input
A0-A8 Column Address Input
BA0, BA1 Bank Select Address
DQ0 to DQ31 Data I/O
CLK System Clock Input
CKE Clock Enable
CS Chip Select
RAS Row Address Strobe Command
CAS Column Address Strobe Command
PIN DESCRIPTIONS
WE Write Enable
DQM0-DQM3 x32 Input/Output Mask
Vdd Power
Vss Ground
Vddq Power Supply for I/O Pin
Vssq Ground for I/O Pin
NC No Connect
Integrated Silicon Solution, Inc. 5
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IS42RM32160C
Mobile SDRAM Functionality
ISSI’s 512Mb Mobile SDRAMs are pin compatible and have similar functionality with ISSI’s standard SDRAMs, but
offer lower operating voltages and power saving features. For detailed descriptions of pin functions, command truth
tables, functional truth tables, device operation as well as timing diagrams please refer to ISSI document “Mobile
Synchronous DRAM Device Operations & Timing Diagrams” listed at www.issi.com
REGISTER DEFINITION
Mode Register (MR) & Extended Mode Register (EMR)
There are two mode registers in the Mobile SDRAM; Mode Register (MR) and Extended Mode Register (EMR). The
Mode Register is discussed below, followed by the Extended Mode Register. The Mode Register is used to define
the specific mode of operation of the SDRAM. This definition includes the selection of burst length, a burst type, CAS
Latency, operating mode, and a write burst mode. The mode register is programmed via the LOAD MODE REGISTER
command and will retain the stored information until it is programmed again or the device loses power.
The EMR controls the functions beyond those controlled by the MR. These additional functions are special features
of the Mobile SDRAM. They include temperature-compensated self refresh (TCSR) control, partial-array self refresh
(PASR), and output drive strength. The EMR is programmed via the MODE REGISTER SET command with BA1
= 1 and BA0 = 0 and retains the stored information until it is programmed again or the device loses power. Not
programming the extended mode register upon initialization will result in default settings for the low-power features.
The extended mode will default with the temperature sensor enabled, full drive strength, and full array (all 4 banks)
refresh.
Mode Register Definition
The MR is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a
burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure MODE
REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed again or the device loses power.
Mode register bits M0 - M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4 -
M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE burst mode, and M10,
M11, and M12 are reserved for future use.
The mode register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.
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Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in
MODE REGISTER DEFINITION. The burst length determines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst
is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states
should not be used, as unknown operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-A8 (x32) when the burst length is set to two; by A2-A8 (x32) when the
burst length is set to four; and by A3-A8 (x32) when the burst length is set to eight. The remaining (least significant)
address bit(s) are used to select the starting location within the block. Full-page bursts wrap within the page if the
boundary is reached.
MODE REGISTER DEFINITION
Latency Mode
M6 M5 M4 CAS Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
To ensure compatibility with future devices,
should program A12, A11, A10 = "0"
Write Burst Mode
M9 Mode
0 Programmed Burst Length
1 Single Location Access
Operating Mode
M8 M7 M6-M0 Mode
0 0 Defined Standard Operation
— — — All Other States Reserved
Burst Type
M3 Type
0 Sequential
1 Interleaved
Burst Length
M2 M1 M0 M3=0 M3=1
0 0 0 1 1
0 0 1 2 2
0 1 0 4 4
0 1 1 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved
Reserved
Address Bus (Ax)
Mode Register (Mx)
(1)
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BA1 BA0 Mode Register Definition
0 0 Program Mode Register
0 1 Reserved
1 0 Program Extended Mode Register
1 1 Reserved
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Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in BURST DEFINITION table.
BURST DEFINITION
Burst Starting Column Order of Accesses Within a Burst
Length Address Type = Sequential Type = Interleaved
A 0
2 0 0-1 0-1
1 1-0 1-0
A 1 A 0
0 0 0-1-2-3 0-1-2-3
4 0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
A 2 A 1 A 0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full n = A0-A9 (x8) Cn, Cn + 1, Cn + 2 Not Supported
Page (location 0-y) Cn + 3, Cn + 4...
(y) …Cn - 1,
Cn…
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency
is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS
Latency diagrams.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8
are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.
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Test modes and reserved states should not be used because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
DON'T CARE
UNDEFINED
CLK
COMMAND
DQ
READ NOP NOP NOP
CAS Latency - 3
t
AC
t
OH
D
OUT
T0 T1 T2 T3 T4
tLZ
CLK
COMMAND
DQ
READ NOP NOP
CAS Latency - 2
t
AC
t
OH
D
OUT
T0 T1 T2 T3
tLZ
CAS LATENCY
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EXTENDED MODE REGISTER DEFINITION
The extended mode register is programmed via the MODE REGISTER SET command (BA1 = 1, BA0 = 0) and
retains the stored information until it is programmed again or the device loses power. The extended mode register
must be programmed with E7 through E12 set to “0.” The extended mode register must be loaded when all banks are
idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent
operation. Violating either of these requirements results in unspecified operation. The extended mode register must be
programmed to ensure proper operation.
Temperature-Compensated Self Refresh (TCSR)
TCSR allows the controller to program the refresh interval during self refresh mode, according to the case temperature
of the mobile device. This allows great power savings during self refresh during most operating temperature ranges.
Only during extreme temperatures would the controller have to select a higher TCSR level that will guarantee data
during self refresh.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
PASR
E2 E1 E0 PartialArraySelfRefresh
Coverage
0 0 0 Fully array (4 banks) - (Default)
0 0 1 Half array (banks 0, 1)
0 1 0 Quarter array (bank 0)
0 1 1 Reserved
1 0 0 Reserved
1 0 1 One-eighth array (1/2 bank 0)
1 1 0 One-sixteenth array (1/4 bank 0)
1 1 1 Reserved
TCSR
E4 E3 Max.CaseTemp.
0 0 70oC
0 1 45oC
1 0 15oC
1 1 85oC (Default)
DS
E6 E5 DriverStrength
0 0 Full strength driver (Default)
0 1 Half strength driver
1 0 Quarter strength driver
1 1 Reserved
setto"0"
E12 E11 E10 E9 E8 E7 E6-E0
0 0 0 0 0 0 Valid Normal operation
– – – – – – – All other states reserved
BA1 BA0 ModeRegisterDenition
0 0 Program Mode Register
0 1 Reserved
1 0 Program Extended mode Register
1 1 Reserved
Address Bus (Ax)
Ext. Mode Reg. (Ex)
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Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is
dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures,
requiring the cells to be refreshed more often. Historically, during self refresh, the refresh rate has been set to
accommodate the worst case, or highest temperature range, expected. Thus, during ambient temperatures, the
power consumed during refresh was unnecessarily high because the refresh rate was set to accommodate the higher
temperatures. Setting E4 and E3 allows the DRAM to accommodate more specific temperature regions during self
refresh. The default for ISSI 512Mb Mobile SDRAM is TCSR = 85°C to guarantee refresh operation. This mode of
operation has a higher current consumption because the self refresh oscillator is set to refresh the SDRAM cells
more often than needed. By using an external temperature sensor to determine the operating temperature the Mobile
SDRAM can be programmed for lower temperature and refresh rates, effectively reducing current consumption by
a significant amount. There are four temperature settings, which will vary the self refresh current according to the
selected temperature. This selectable refresh rate will save power when the Mobile DRAM is operating at normal
temperatures.
Partial-Array Self Refresh (PASR)
For further power savings during self refresh, the PASR feature allows the controller to select the amount of memory
that will be refreshed during self refresh. The refresh options are all banks (banks 0, 1, 2, and 3); two banks (banks
0 and 1); and one bank (bank 0). In addition partial amounts of bank 0 (half or quarter of the bank) may be selected.
WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks in
PASR will be refreshed during self refresh. It’s important to note that data in banks 2 and 3 will be lost when the two-
bank option is used. Data will be lost in banks 1, 2, and 3 when the one-bank option is used.
Driver Strength (DS)
Bits E5 and E6 of the EMR can be used to select the driver strength of the DQ outputs. This value should be set
according to the application’s requirements. The default is Full Driver Strength.
Deep Power Down (DPD)
Deep power down mode is for maximum power savings and is achieved by shutting down power to the entire memory
array of the mobile device. Data will be lost once deep power down mode is executed.
DPD mode is entered by having all banks idle, CS and WE held low, with RAS and CAS HIGH at the rising edge of
the clock, while CKE is LOW. CKE must be held LOW during DPD mode. To exit DPD mode, CKE must be asserted
HIGH. Upon exit from DPD mode, at least 200ms of valid clocks with either NOP or COMMAND INHIBIT commands
are applied to the command bus, followed by a full Mobile SDRAM initialization sequence, is required.
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ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters Rating Unit
Vdd Supply Voltage (with respect to Vss) -0.5 to +4.6 V
Vddq Supply Voltage for Output (with respect to Vssq) -0.5 to +4.6 V
Vin Input Voltage (with respect to Vss) -0.5 to Vdd+0.5 V
Vout Output Voltage (with respect to Vssq) -1.0 to Vdd+0.5 V
Ics Short circuit output current 50 mA
Pd Power Dissipation (Ta = 25oC) 1 W
Topt Operating Temperature Com. 0 to +70 °C
Ind. -40 to +85 °C
Tstg Storage Temperature –65 to +150 °C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All voltages are reference to Vss.
CAPACITANCE
Symbol Parameter Min. Max. Unit
Cin Input Capacitance, address and control pin 5.0 7.0 pF
Cclk Input Capacitance, CLK pin 5.0 7.6 pF
Cio Data Input/Output Capacitance 4 6.5 pF
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DC RECOMMENDED OPERATING CONDITIONS
IS42SMxxx - 3.3V Operation
Symbol Parameters Min. Typ. Max. Unit
Vdd Supply Voltage 3.0 3.3 3.6 V
Vddq I/O Supply Voltage 3.0 3.3 3.6 V
Vih(1) Input High Voltage 2.0 – Vddq+0.3 V
Vil(2) Input Low Voltage -0.3 – 0.8 V
Iil Input Leakage Current (0V ≤ Vin ≤ Vdd) -5 – +5 µA
Iol Output Leakage Current (Output disabled, 0V ≤ Vout ≤ Vdd) -5 – +5 µA
Voh Output High Voltage Current (Ioh = -2mA) 2.4 – – V
Vol Output Low Voltage Current (Iol = 2mA) – – 0.4 V
Notes:
1. Vih (overshoot): Vih (max) = Vddq +1.2V (pulse width < 3ns).
2. Vil (undershoot): Vih (min) = -1.2V (pulse width < 3ns).
3. All voltages are referenced to Vss.
Contact Product Marketing for 3.0V + 10% support.
IS42RMxxx - 2.5V Operation
Symbol Parameters Min. Typ. Max. Unit
Vdd Supply Voltage 2.3 2.5 2.7 V
Vddq I/O Supply Voltage 2.3 2.5 2.7 V
Vih(1) Input High Voltage 2.0 - Vdd+0.3 V
Vil(2) Input Low Voltage -0.3 - 0.55 V
Iil Input Leakage Current (0V ≤ Vin ≤ Vdd) -5 – +5 µA
Iol Output Leakage Current (Output disabled, 0V ≤ Vout ≤ Vdd) -5 – +5 µA
Voh Output High Voltage Current (Ioh = -2mA) Vdd-0.2 – - V
Vol Output Low Voltage Current (Iol = 2mA) - – 0.2 V
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Symbol Parameter Test Condition -7 –75 Unit
Idd1(1) Operating Current One Bank Active, CL = 3, BL = 1,
tclk = tCLK(min), tRC = tRC(min)
140 130 mA
Idd2p (4) Precharge Standby Current
(In Power-Down Mode)
CKE ≤ Vil (max), tCK = 15ns
CS ≥ Vdd - 0.2V
2 2 mA
Idd2ps (4) Precharge Standby Current
With Clock Stop
(In Power-Down Mode)
CKE ≤ Vil (max), CLK ≤ Vil (max)
CS ≥ Vdd - 0.2V
2 2 mA
Idd2n(2) Precharge Standby Current
(In Non Power-Down Mode)
CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
tCK = 15 ns
50 50 mA
Idd2ns Precharge Standby Current
With Clock Stop
(In Non-Power Down Mode)
CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
All Inputs Stable
30 30 mA
Idd3p(2) Active Standby Current
(In Power-Down Mode)
CKE ≤ Vil (max), CS ≥ Vdd - 0.2V
tCK = 15 ns
5 5 mA
Idd3ps Active Standby Current
With Clock Stop
(In Power-Down Mode)
CKE ≤ Vil (max), CLK ≤ Vil (max)
CS ≥ Vdd - 0.2V
5 5 mA
Idd3n(2) Active Standby Current
(In Non Power-Down Mode)
CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
tCK = 15 ns
65 65 mA
Idd3ns Active Standby Current
With Clock Stop
(In Non Power-Down Mode)
CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
All Inputs Stable
35 35 mA
Idd4Operating Current All Banks Active, BL =Full, CL = 3
tCK = tCK(min)
180 170 mA
Idd5Auto-Refresh Current tRC = tRC(min), tCLK = tCLK(min) 260 250 mA
Idd6Self-Refresh Current CKE ≤ 0.2V 2.4 2.4 mA
Idd7Self-Refresh: CKE = LOW; tck = tck (MIN);
Address, Control, and Data bus inputs are
stable
Full Array, 85oC
Full Array, 45oC
Half Array, 85oC
Half Array, 45oC
1/4th Array, 85oC
1/4th Array, 45oC
1/8th Array, 85oC
1/8th Array, 45oC
1/16th Array, 85oC
1/16th Array, 45oC
2.4
1.6
2.0
1.3
1.6
1.1
1.4
0.9
1.2
0.8
mA
Izz(3,4) Deep Power Down Current CKE ≤ 0.2V 40 40 mA
DC ELECTRICAL CHARACTERISTICS VDD = 3.3V / 2.5V x32
Notes:
1. Idd (max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
3. Izz values shown are nominal at 25oC. Izz is not testsed.
4. Tested after 500ms delay.
14 Integrated Silicon Solution, Inc.
Rev. A
11/09/2010
IS42SM32160C
IS42RM32160C
AC ELECTRICAL CHARACTERISTICS (1, 2, 3)
-7 -75
Symbol Parameter Min. Max. Min. Max. Unit
tCK3
tCK2
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7
9.6
–
–
7.5
9.6
–
–
ns
ns
tAC3
tAC2
Access Time From CLK
CAS Latency = 3
CAS Latency = 2
–
–
5.4
7.0
–
–
5.4
7.0
ns
ns
tCHI CLK HIGH Level Width 2.5 – 2.5 – ns
tCL CLK LOW Level Width 2.5 – 2.5 – ns
tOH3
tOH2
Output Data Hold Time
CAS Latency = 3
CAS Latency = 2
2.7
2.7
–
–
2.7
2.7
–
–
ns
ns
tLZ Output LOW Impedance Time 0 – 0 – ns
tHZ Output HIGH Impedance Time
CAS Latency = 3
CAS Latency = 2
2.7
2.7
5.4
7.0
2.7
2.7
5.4
7.0
ns
tDS Input Data Setup Time (2) 1.5 – 1.5 – ns
tDH Input Data Hold Time (2) 1.0 – 1.0 – ns
tAS Address Setup Time (2) 1.5 – 1.5 – ns
tAH Address Hold Time (2) 1.0 – 1.0 – ns
tCKS CKE Setup Time (2) 1.5 – 1.5 – ns
tCKH CKE Hold Time (2) 1.0 – 1.0 – ns
tCS Command Setup Time (CS, RAS,
CAS, WE, DQM)(2)
1.5 – 1.5 – ns
tCH Command Hold Time (CS, RAS,
CAS, WE, DQM)(2)
1.0 – 1.0 – ns
tRC Command Period (REF to REF /
ACT to ACT)
67.5 – 67.5 – ns
tRAS Command Period (ACT to PRE) 45 100K 45 100K ns
tRP Command Period (PRE to ACT) 19 – 19 – ns
tRCD Active Command to Read/Write
Command Delay Time
19 – 19 – ns
tRRD Command Period (ACT [0] to
ACT [1])
14 – 15 – ns
tDPL Input Data to Precharge 14 – 15 – ns
Command Delay Time
tDAL Input Data to Active/Refresh
Command Delay Time (During
Auto-Precharge)
35 – 37.5 – ns
tMRD Mode Register Program Time 14 – 15 – ns
tDDE Power Down Exit Setup Time 7 – 7.5 – ns
tSRX Exit Self-Refresh to Active Time 80 – 80 – ns
tT Transition Time 0.3 1.2 0.3 1.2 ns
tREF Refresh Cycle Time
8K times
– 64 – 64 ms
Notes:
1. The power-on sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns. If clock rising time is longer than 1ns, (tR /2 - 0.5) ns should be added to the parameter.
3. The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between
Vih(min.) and Vil (max).
Integrated Silicon Solution, Inc. 15
Rev. A
11/09/2010
IS42SM32160C
IS42RM32160C
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER -7 -75 UNITS
— Clock Cycle Time 7 7.5 ns
— Operating Frequency 143 133 MHz
tcac CAS Latency 3 3 cycle
trcd Active Command To Read/Write Com-
mand Delay Time
3 3 cycle
trac RAS Latency (trcd + tcac)CAS Latency = 3 6 6 cycle
trc Command Period (REF to REF / ACT to
ACT)
10 9 cycle
tras Command Period (ACT to PRE) 7 6 cycle
trp Command Period (PRE to ACT) 3 3 cycle
trrd Command Period (ACT[0] to ACT [1]) 2 2 cycle
tccd Column Command Delay Time
(READ, READA, WRIT, WRITA)
1 1 cycle
tdpl Input Data To Precharge Command Delay
Time
2 2 cycle
tdal Input Data To Active/Refresh Command
Delay Time
(During Auto-Precharge)
5 5 cycle
trbd Burst Stop Command To Output in HIGH-Z
Delay Time
(Write)
CAS Latency = 3 3 3 cycle
twbd Burst Stop Command To Input in Invalid
Delay Time
(Write)
0 0 cycle
trql Precharge Command To Output in HIGH-Z
Delay Time
(Read)
CAS Latency = 3 3 3 cycle
twdl Precharge Command To Input in Invalid
Delay Time
(Write)
0 0 cycle
tpql
Last Output To Auto-Precharge Start
Time (Read)
CAS Latency = 3 -2 -2 cycle
tqmd DQM To Output Delay Time (Read) 2 2 cycle
tdmd DQM To Input Delay Time (Write) 0 0 cycle
tmrd Mode Register Set To Command Delay
Time
2 2 cycle
16 Integrated Silicon Solution, Inc.
Rev. A
11/09/2010
IS42SM32160C
IS42RM32160C
Ordering Information – Vdd = 3.3V
Commercial Range: (0°C to +70°C)
Frequency Speed (ns) Order Part No. Package
143 MHz 7.0 IS42SM32160C-7BL 8x13mm BGA, Lead-free
133 MHz 7.5 IS42SM32160C-75BL 8x13mm BGA, Lead-free
Industrial Range: (-40°C to +85°C)
Frequency Speed (ns) Order Part No. Package
143 MHz 7.0 IS42SM32160C-7BLI 8x13mm BGA, Lead-free
133 MHz 7.5 IS42SM32160C-75BLI 8x13mm BGA, Lead-free
Ordering Information – Vdd = 2.5V
Commercial Range: (0°C to +70°C)
Frequency Speed (ns) Order Part No. Package
133 MHz 7.5 IS42RM32160C-75BL 8x13mm BGA, Lead-free
Industrial Range: (-40°C to +85°C)
Frequency Speed (ns) Order Part No. Package
133 MHz 7.5 IS42RM32160C-75BLI 8x13mm BGA, Lead-free
*Contact ISSI for leaded parts support.
Integrated Silicon Solution, Inc. 17
Rev. A
11/09/2010
IS42SM32160C
IS42RM32160C
2. Reference document : JEDEC MS-207
1. CONTROLLING DIMENSION : MM .
NOTE :
08/28/2008
Package Outline
