MTC -20278 ILTQ
MTC-20279 ILTT
Key Features
▼ Quad ISDN LT ‘U’ interface
functions in a single monolithic
integrated circuit
▼ Pin compatible 2B1Q and
4B3T line code versions
* MTC-20278 ILTQ for 2B1Q
* MTC-20279 ILTT for 4B3T
▼ Full compliance with the
applicable ETSI, ITU and FTZ
requirements
▼ DECT support (2B1Q)
▼ Digital interface bus using
industry-standard GCI
▼ Minimal external components
▼3.3V operating voltage for
low power operation
▼ Advanced 0.5µ CMOS mixed
analog/digital process technol-
ogy
▼ 80 pin Plastic Quad Flat Pack
package
General Description
The MTC-20278/9 chip contains all
the functions necessary to make 4 ‘U’
interfaces in an ISDN Line Termination
card. It comprises 4, fully integrated
echo-canceling ‘U’ interfaces, confor-
mant to the ‘Uk0’ interface point, plus
the necessary support and test func-
tions. The general block diagram is
shown in Figure 1. Two versions of the
device are available - the MTC-20278
offering the 2B1Q line code, and the
MTC-20279 which has 4B3T line cod-
ing. Both devices are pin compatible,
and are fully compliant with the rele-
vant parts of ETSI, FTZ and ITU
requirements for ISDN connection.
The MTC-20278/9 devices offer a
user transport rate of 144kbit/s full
duplex (2B + D) per channel, as well
as fully automatic control of
activate/deactivate protocols and line
supply, and full support of the mainte-
nance channel.
The MTC-20278 offers facilities
required for the synchronisation of
DECT base stations (“heart beat” and
loop length estimation)
The digital interface on the ‘exchange’
side uses the industry-standard GCI
interface in 2 Mbit burst mode. This
mode allows for 8 channels to be multi-
plexed onto the same interface. The
MTC-20278/9 can be set to respond to
either the first 4 or the last 4 timeslots in
the GCI frame. This allows two devices,
totalling 8 ISDN lines, to be multiplexed
onto the same GCI interface.
The MTC-20278/9 takes all timing
information from the GCI clocks, and
so does not require a separate clock
oscillator.
Figure 2 shows the typical circuit con-
figuration of the MTC-20278/9.
Quad Integrated LT (ILT)
ISDN Standard Products
Product Brief
Ordering Information
Part number Package Code Temp.
MTC-20278PQ-C 80PQFP 2B1Q 0 to +70°C
MTC-20278PQ-I 80PQFP 2B1Q -40 to +85°C
MTC-20279PQ-C 80PQFP 4B3T 0 to +70°C
MTC-20279PQ-I 80PQFP 4B3T -40 to +85°C
2
MTC-20278 ILTQ
MTC-20279 ILTT
Channel
Support
Channel
‘U’
interface
Channel
Power
Feed
control
AVDD
AVSS
AREF
LOUT2
LOUT1
LIN2
LIN1
RD2
RD1
FD2
FD1
Channel
Support
Channel
‘U’
interface
Channel
Power
Feed
control
AVDD
AVSS
AREF
LOUT2
LOUT1
LIN2
LIN1
RD2
RD1
FD2
FD1
Channel
Support
Channel
‘U’
interface
Channel
Power
Feed
control
AVDD
AVSS
AREF
LOUT2
LOUT1
LIN2
LIN1
RD2
RD1
FD2
FD1
Channel
Support
Channel
‘U’
interface
Channel
Power
Feed
control
AVDD
AVSS
AREF
LOUT2
LOUT1
LIN2
LIN1
RD2
RD1
FD2
FD1
JTAG Test
Interface
TRST
TCK
TMS
TDI
TDO
GCI port
DOUT
DIN
DCLK
DFR
POS
TSP NRESETVDD VSS
RD3 RD3
RD3RD3
Fig. 1: MTC-20278/9 ILT General block diagram
3
MTC-20278 ILTQ
MTC-20279 ILTT
Fig. 2: MTC-20278/9 ILT - typical component configuration
4
MTC-20278 ILTQ
MTC-20279 ILTT
Fig. 3: GCI bus multiplexing timing diagram
GCI bus ILT channel allocation
Pin Description
Function Name Dir. Description
LOUTn1 O U interface analog outputs. The connections LOUTn1 and LOUTn2
interface the U driver outputs, via termination resistors and the line
coupling transformer, to the UK0 reference point.
LOUTn2 O See LOUTn1
U
LINn1 I LINn1 and LINn2 are the U interface analog inputs to the INT from the
analog ‘hybrid’
Int. LINn2 I See LINn1
AREFn O Analog ground (1.65V). Used as reference voltage for analog functions
5
MTC-20278 ILTQ
MTC-20279 ILTT
AVDDn P VDD for analog U interface functions
AVSSn P VSS (0V ground) for U interface analog functions
RDn1 O Relay driver control
Pow. RDn2 O Relay driver control
Feed
RDn3 I/O Relay Driver/Monnitor input
Cntrl.
FDn1 I Power Feed control input
FDn2 O Power Feed control output
DOUT O GCI interface Data Out
GCI DIN I GCI interface Data In
DCLK O GCI interface Data Clock
Int. DFR O GCI interface Frame Clock
POS I Select GCI burst group: 0 = first 4, 1 = last 4
TRST I TAP controller reset, active low
JTAG TCK I TAP controller clock, maximum 10 MHz
TMS I TAP controller mode selection
INT. TDI I TAP controller input
TDO O TAP controller output
NRESET I Hardware reset, active low. Schmitt trigger input for connection to
external RC or logic device.
TSP I Test Single Pulses. ILT transmits alternate positive and negative
pulses to act as test and search-tone on the line.
VDD P
VDD P Positive supply for digital functions
VDD P
VDD P
VSS P
VSS P 0V ground for digital functions
VSS P
VSS P
6
MTC-20278 ILTQ
MTC-20279 ILTT
Device Packaging
Fig. 4. Device Pinout, 80PQFP
‘U’ interface characteristics - MTC-20278 (2B1Q)
BER / loop range <10-7 Exceeds ETSI requirements.
TSP pulses 666 Hz
‘U’ interface characteristics - MTC-20279 (4B3T)
BER / loop range <10-7 Exceeds FTZ and ETSI requirements.
TSP pulses 1000 Hz
GCI interface characteristics
Nominal bit-rate, DIN and DOUT 2048 kbit/s
Nominal frequency of clock (DCLK) 4096 kHz
Peak-peak input jitter of clock (DCLK) ≤166 ns
Nominal frequency of frame clock (DFR) 8 kHz
Duty-cycle of DFR 40 to 60 %
DC characteristics, logic interfaces (all pins, except where noted)
VIH (input high-level voltage) VDD * 0.7 V min
VIL (input low level voltage) VDD * 0.3 V max
VOH1 (high level output voltage) VDD * 0.9 V min at IOH1 = 0.4mA, except pin DOUT
VOL1 (low level output voltage) VDD * 0.1 V max at IOL1 = 0.4mA, except pin DOUT
CIN (input capacitance) 10 pF max
COUT (capacitive load on outputs) 25 pF max
Iin (input leakage current) 1 µA
MTC-20278 ILTQ
MTC-20279 ILTT
Key circuit characteristics (typical values)
Absolute Maximum Ratings
Operation at these limits is not guaranteed, and device reliability will be adversely effected.
Logic supply voltage (VDD, AVDD) 4 V
Voltage on any pin (except GCI) VDD+0.3 V
VSS-0.3 V
Voltage on GCI interface pins 4 V
Continuous power dissipation 1 W at 25 °C ambient
Storage temperature -55 to +150 °C for < 100 hours
-55 to +100 °C for > 100 hours
Operating Ranges
VDD, AVDD 3.15 to 3.45 V (= 3.3V ± 5%)
Supply noise (p-p): ≤100mV on VDD
≤10mV on AVDD
≤0.1mV on AREF
AREFn output voltage 1.65V ± 3%
Max current on AREFn + or - 0.25 mA
Power consumption ≤250 mW per line in power-up state,
nominal loads on U interfaces, random signals:
U: 150Ωline equivalent
≤10mW per line in power-down state
Temperature range -40 to +85 °C
7
Reliability Information
Early failure rate ≤0.3% at 3000 hours
Long term failure rate ≤300 FIT for 45°C average ambient and 45% average humidity
Lifetime ≥15 years
MTC-20278 ILTQ
MTC-20279 ILTT
10/98 PB0243e
Alcatel Microelectronics acknowledges the trademarks of all companies referred to in this document.
This document contains information on a new product.
Alcatel Microelectronics
reserves the right to make
changes in specifications at any time and without notice.
The information furnished by
Alcatel Microelectronics
in this
document is believed to be accurate and reliable.
However, no responsibility is assumed by
Alcatel Micro-
electronics
for its use, nor for any infringements of patents or
other rights of third parties resulting from its use.
No licence is granted under any patents or patent rights
of
Alcatel Microelectronics
.
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