Rev 1.1a 03/18/2005 Microsemi. Inc.
Copyright 1994 11861 Western Avenue ∞ ∞
∞ ∞
∞ Garden Grove, CA 92841
1(714) 898-8121 ∞∞
∞∞
∞ FAX: (714) 893-2570
REGULATING PULSE WIDTH MODULATOR
FEATURES
••
••
•8V to 40V operation
••
••
•5V reference
••
••
•Reference line and load regulation of 0.4%
••
••
•Reference temperature coefficient < ± 1%
••
••
•100Hz to 300KHz oscillator range
••
••
•Excellent external sync capability
••
••
•Dual 50mA output transistors
••
••
•Current limit circuitry
••
••
•Complete PWM power control circuitry
••
••
•Single ended or push-pull outputs
••
••
•Total supply current less than 10mA
HIGH RELIABILITY FEATURES - SG1524
♦♦
♦♦
♦Available to MIL-STD-883B and DESC SMD
♦♦
♦♦
♦MIL-M-38510/12601BEA - JAN1524J
♦♦
♦♦
♦Radiation data available
♦♦
♦♦
♦LMI level "S" processing available
BLOCK DIAGRAM
DESCRIPTION
This monolithic integrated circuit contains all the control circuitry for a
regulating power supply inverter or switching regulator. Included in a 16-
pin dual-in-line package is the voltage reference, error amplifier, oscillator,
pulse width modulator, pulse steering flip-flop, dual alternating output
switches and current limiting and shut-down circuitry. This device can be
used for switching regulators of either polarity, transformer coupled DC to
DC converters, transformerless voltage doublers and polarity converters,
as well as other power applications. The SG1524 is specified for operation
over the full military ambient temperature range of -55°C to +125°C, the
SG2524 for -25°C to +85°C, and the SG3524 is designed for commercial
applications of 0°C to +70°C.
SG1524/SG2524/SG3524
Rev 1.1a
Copyright 1994 11861 Western Avenue ∞ ∞
∞ ∞
∞ Garden Grove, CA 92841
2(714) 898-8121 ∞∞
∞∞
∞ FAX: (714) 893-2570
Oscillator Charging Current ................................................5mA
Operating Junction Temperature
Hermetic (J, L Packages) ............................................. 150°C
Plastic (N, D Packages) ............................................... 150°C
Storage Temperature Range .............................-65°C to 150°C
Pb-free / RoHS Peak Package Solder Reflow Temp (40 sec. max. exposure)...260°C (+0, -5)
Input Voltage (+VIN)............................................................. 42V
Collector Voltage ................................................................ 40V
Logic Inputs...........................................................-0.3V to 5.5V
Current Limit Sense Inputs ...................................-0.3V to 0.3V
Output Current (each transistor) .................................... 100mA
Reference Load Current .................................................. 50mA
ABSOLUTE MAXIMUM RATINGS (Note 1)
Note 1. Values beyond which damage may occur.
Input Voltage (+VIN) ...................................................
Collector Voltage .......................................................
Error Amp Common Mode Range ..........................
Current Limit Sense Common Mode Range ........
Output Current (each transistor) ...............................
Reference Load Current ...........................................
Oscillator Charging Current ..................................
8V to 40V
0V to 40V
1.8V to 3.4V
-0.3V to 0.3V
0 to 50mA
0 to 20mA
30µA to 2mA
Oscillator Frequency Range .........................
Oscillator Timing Resistor (RT) ........................
Oscillator Timing Capacitor (CT) ............................
Operating Ambient Temperature Range
SG1524 .........................................................
SG2524 ...........................................................
SG3524 ...............................................................
100Hz to 300KHz
1.8KΩ to 100KΩ
1nF to 1.0µF
-55°C to 125°C
-25°C to 85°C
0°C to 70°C
Note 2: Range over which the device is functional and parameter limits are guaranteed.
RECOMMENDED OPERATING CONDITIONS (Note 2)
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1524 with -55 °C ≤ TA ≤ 125°C, SG2524 with
-25°C ≤ TA ≤ 85°C, SG3524 with 0°C ≤ TA ≤ 70°C, and +V IN = 20V. Low duty cycle pulse testing techniques are used which maintains junction and
case temperatures equal to the ambient temperature.)
Note 3. IL = 0mA
5.00
50
Reference Section (Note 3) TJ = 25°C
VIN = 8V to 40V
IL = 0 to 20mA
Over Operating Temperature Range
Over Line, Load and Temperature
VREF = 0V
Output Voltage
Line Regulation
Load Regulation
Temperature Stability (Note 7)
Total Output Voltage Range (Note 7)
Short Circuit Current
Min. Typ. Max. Min. Typ. Max.
SG3524SG1524/2524 UnitsTest ConditionsParameter
4.80
4.80
25
5.20
20
50
50
5.20
150
4.60
4.60
25
5.00
50
5.40
30
50
50
5.40
150
V
mV
mV
mV
V
mA
THERMAL DATA
J Package:
Thermal Resistance-Junction to Case, θJC.................. 30°C/W
Thermal Resistance-Junction to Ambient, θJA .............. 80°C/W
N Package:
Thermal Resistance-Junction to Case, θJC.................. 40°C/W
Thermal Resistance-Junction to Ambient, θJA ............. 65°C/W
D Package:
Thermal Resistance-Junction to Case, θJC................... 50°C/W
Thermal Resistance-Junction to Ambient, θJA ............ 120°C/W
L Package:
Thermal Resistance-Junction to Case, θJC.................. 35°C/W
Thermal Resistance-Junction to Ambient, θJA ........... 120°C/W
Note A. Junction Temperature Calculation: TJ = TA + (PD x θJA).
Note B. The above numbers for θJC are maximums for the limiting
thermal resistance of the package in a standard mount-
ing configuration. The θJA numbers are meant to be
guidelines for the thermal performance of the device/pc-
board system. All of the above assume no ambient
airflow.
Lead Temperature (Soldering, 10 seconds).................................300°C
Rev 1.1a
Copyright 1994 11861 Western Avenue ∞ ∞
∞ ∞
∞ Garden Grove, CA 92841
3(714) 898-8121 ∞∞
∞∞
∞ FAX: (714) 893-2570
VIN = 40VStandby Current
0.80.5
0.2
Threshold Voltage TJ = 25°C
MIN ≤ TJ ≤ MAX
200190
Current Limit Amplifier Section (Note 6)
Sense Voltage
Input Bias Current
49 045 4945
P.W.M. Comparator (Note 4) VCOMP = 0.5V
VCOMP = 3.6V
Minimum Duty Cycle
Maximum Duty Cycle 0%
%
Error Amplifier Section (Note 5) RS ≤ 2KΩ
RL ≥10MΩ, TJ = 25°C
VPIN 1 - VPIN 2 ≥ 150mV
VPIN 2 - VPIN 1 ≥150mV
VCM = 1.8V to 3.4V
VIN = 8V to 40V
TJ = 25°C
Input Offset Voltage
Input Bias Current
Input Offset Current
DC Open Loop Gain
Output Low Level
Output High Level
Common Mode Rejection
Supply Voltage Rejection
Gain-Bandwidth Product (Note 7)
ELECTRICAL CHARACTERISTICS (continued)
36
34
200
3
0.6
3.2
0.3
Oscillator Section (Note 4)
Initial Accuracy
Voltage Stability
Maximum Frequency
Sawtooth Peak Voltage
Sawtooth Valley Voltage
Clock Amplitude
Clock Pulse Width
Min. Typ. Max. Min. Typ. Max.
SG1524/2524 SG3524 UnitsTest ConditionsParameter
TJ = 25°C
MIN ≤ TJ ≤ MAX
VIN = 8V to 40V
RT = 2KΩ, CT = 1nF
VIN = 40V
VIN = 8V
KHz
KHz
%
KHz
V
V
V
µs
44
46
1
3.8
1.2
1.5
40
0.1
400
1
36
34
200
3
0.6
3.2
0.3
44
46
1
3.8
1.2
1.5
40
0.1
400
1
mV
µA
µA
dB
V
V
dB
dB
MHz
10
10
2
0.5
2
1
0.2
4.2
2
60
3.8
1
5
10
1
0.5
0.5
1
0.2
4.2
2
72
3.8
70
55
1
210
200 180 200 220
200 mV
µA
TJ = 25°C
Shutdown Section 1.2
1.8 0.5
0.2 0.8 1.2
1.8 V
V
µA
V
V
µs
µs
50
2
0.4
0.2
50
2
0.4
0.2
1717
Output Section (each transistor)
Collector Leakage Current
Collector Saturation Voltage
Emitter Output Voltage
Collector Voltage Rise Time
Collector Voltage Fall Time
VCE = 40V
IC = 50mA
IE = 50mA
RC = 2KΩ
RC = 2KΩ
Power Consumption
Note 4. FOSC = 40KHz (RT = 2.9KΩ, CT = .01µF)
Note 5. VCM = 2.5V
Note 6. VCM = 0V
Note 7. These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
107107mA
Rev 1.1a
Copyright 1994 11861 Western Avenue ∞ ∞
∞ ∞
∞ Garden Grove, CA 92841
4(714) 898-8121 ∞∞
∞∞
∞ FAX: (714) 893-2570
FIGURE 1 - OUTPUT STAGE DEADTIME VS. CTFIGURE 2 - OSCILLATOR FREQUENCY VS. RT AND CT
APPLICATION NOTES
OSCILLATOR
The oscillator in the SG1524 uses an external resistor RT to
establish a constant charging current into an external capacitor
CT. While this uses more current than a series-connected RC, it
provides a linear ramp voltage at CT which is used as a time-
dependent reference for the PWM comparator. The charging
current is equal to 3.6V/RT, and should be restricted to between
30µA and 2mA. The equivalent range for RT is 1.8K to 100K.
The range of values for CT also has limits, as the discharge time
of CT determines the pulse width of the oscillator output pulse.
The pulse is used (among other things) as a blanking pulse to
both outputs to insure that there is no possibility of having both
outputs on simultaneously during transitions. This output
deadtime relationship is shown in Figure 1. A pulse width below
0.35 microseconds may cause failure of the internal flip-flop to
toggle. This restricts the minimum value of CT to 1000pF. (Note:
Although the oscillator output is a convenient oscilloscope sync
input, the probe capacitance will increase the pulse width and
decrease the oscillator frequency slightly.) Obviously, the upper
limit to the pulse width is determined by the modulation range
required in the power supply at the chosen switching frequency.
Practical values of CT fall between 1000pF and 0.1µF, although
successful 120 Hz oscillators have been implemented with val-
ues up to 5µF and a series surge limit resistor of 100 ohms.
The oscillator frequency is approximately 1/RT•CT; where R is in
ohms, C is in microfarads, and the frequency is in Megahertz. For
greater accuracy, the chart in Figure 2 may be used for a wide
range of operating frequencies.
Note that for buck regulator topologies, the two outputs can be
wire-ORed for an effective 0-90% duty cycle range. With this
connection, the output frequency is the same as the oscillator
frequency. For push-pull applications, the outputs are used
separately; the flip-flop limits the duty cycle range at each output
to 0-45%, and the effective switching frequency at the trans-
former is 1/2 the oscillator frequency.
If it is desired to synchronize the SG1524 to an external clock, a
positive pulse may be applied to the clock pin. The oscillator
should be programmed with RT and CT values that cause it to free-
run at 90% of the external sync frequency. A sync pulse with a
maximum logic 0 of +0.3 volts and a minimum logic 1 of +2.4 volts
applied to Pin 3 will lock the oscillator to the external source. The
minimum sync pulsewidth should be 200 nanoseconds, and the
maximum is determined by the required deadtime. The clock pin
should never be driven more negative than -0.3 volts, nor more
positive than +5.0 volts. The nominal resistance to ground is
3.2K at the clock pin, ±25% over temperature.
If two or more SG1524s must be synchronized together, program
one master unit with RT and CT for the desired frequency. Leave
the RT pins on the slaves open, connect the CT pins to the CT of
the master, and connect the clock pins to the clock pin of the
master. Since CT is a high-impedance node, this sync technique
works best when all devices are close together.
Rev 1.1a
Copyright 1994 11861 Western Avenue ∞ ∞
∞ ∞
∞ Garden Grove, CA 92841
5(714) 898-8121 ∞∞
∞∞
∞ FAX: (714) 893-2570
APPLICATION NOTES (continued)
CURRENT LIMITING
The current limiting circuitry of the SG1524 is shown in Figure 3.
By matching the base-emitter voltages of Q1 and Q2, and
assuming a negligible voltage drop across R1:
C.L. Threshold = VBE(Q1) + I1• R2 - VBE(Q2) = I1• R2
~ 200 mV
Although this circuit provides a relatively small threshold with a
negligible temperature coefficient, there are some limitations to
its use because of its simplicity.
The most important of these is the limited common-mode voltage
range: ±0.3 volts around ground. This requires sensing in the
ground or return line of the power supply. Also precautions
should be taken to not turn on the parasitic substrate diode of the
integrated circuit, even under transient conditions. A Schottky
clamp diode at Pin 5 may be required in some configurations to
achieve this.
A second factor to consider is that the response time is relatively
slow. The current limit amplifier is internally compensated by R1
, C1 , and Q1, resulting in a roll-off pole at approximately 300 Hz.
A third factor to consider is the bias current of the C.L. Sense
pins. A constant current of approximately 150µA flows out of Pin
4, and a variable current with a range of 0-150µA flows out of Pin
5. As a result, the equivalent source impedance seen by the
current sense pins should be less than 50 ohms to keep the
threshold error less than 5%.
Since the gain of this circuit is relatively low (42 dB), there is a
transition region as the current limit amplifier takes over pulse
width control from the error amplifier. For testing purposes,
threshold is defined as the input voltage required to get 25% duty
cycle (+2 volts at the error amplifier output) with the error amplifier
signaling maximum duty cycle.
APPLICATION NOTE: If the current limit function is not used on
the SG1524, the common-mode voltage range restriction re-
quires both current sense pins to be grounded.
FIGURE 3 - CURRENT LIMITING CIRCUITRY OF THE SG1524
In this conventional single-ended regulator circuit, the two out-
puts of the SG1524 are connected in parallel for effective 0 - 90%
duty-cycle modulation. The use of an output inductor requires
and R-C phase compensation network for loop stability.
Push-pull outputs are used in this transformer-coupled DC-DC
regulating converter. Note that the oscillator must be set at twice
the desired output frequency as the SG1524's internal flip-flop
divides the frequency by 2 as it switches the P.W.M. signal from
one output to the other. Current limiting is done here in the
primary so that the pulse width will be reduced should transformer
saturation occur.
Rev 1.1a
Copyright 1994 11861 Western Avenue ∞ ∞
∞ ∞
∞ Garden Grove, CA 92841
6(714) 898-8121 ∞∞
∞∞
∞ FAX: (714) 893-2570
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
16-PIN CERAMIC DIP
J - PACKAGE VREF
+VIN
EB
CB
CA
EA
SHUTDOWN
COMPENSATIONGROUND
OSC. OUTPUT
N.I. INPUT
Ambient
Temperature Range
SG1524J/883B -55°C to 125°C
JAN1524J -55°C to 125°C
SG1524J/DESC -55°C to 125°C
SG1524J -55°C to 125°C
SG2524J -25°C to 85°C
SG3524J 0°C to 70°C
Part No.Package Connection Diagram
INV. INPUT
CT
RT
+C.L. SENSE
-C.L. SENSE
2
3
4
5
6
7
8
1
15
16
14
13
10
9
12
11
2
3
4
5
6
7
8
GROUND
OSC. OUTPUT
N.I. INPUT
INV. INPUT
CT
RT
+C.L. SENSE
-C.L. SENSE
1
15
16
14
13
10
12
11
9
VREF
+VIN
EB
CB
CA
EA
SHUTDOWN
COMPENSATION
SG2524N -25°C to 85°C
SG3524N 0°C to 70°C N Package: RoHS / Pb-free Transition DC: 0503*. 100% Matte Tin Lead Finish
16-PIN PLASTIC DIP
N - PACKAGE
16-PIN NARROW BODY
PLASTIC S.O.I.C.
D - PACKAGE
SG2524D -25°C to 85°C
SG3524D 0°C to 70°C
20-PIN CERAMIC
LEADLESS CHIP CARRIER
L- PACKAGE 4
5
6
7
8
321
9 11121310
14
15
16
17
18
20 19
SG1524L/883B -55°C to 125°C
SG1524L -55°C to 125°C11. COMP
12. SHUTDOWN
13. N.C.
14. EA
15. CA
16. N.C.
17. CB
18. EB
19. N.C.
20. +VIN
1. N.C.
2. VREF
3. INV. INPUT
4. N.I. INPUT
5. OSC. OUTPUT
6. + C.L. SENSE
7. - C.L. SENSE
8. RT
9. CT
10. GROUND
RoHS / Pb-free transition DC:0440 Pb-free / RoHS 100% Matte Tin Lead Finish*
*RoHS compliant
