TS68040DESC02ZAA - Atmel Corporation

Features

•26-42 MIPS Integer Performance

•3.5-5.6 MFLOPS Floating-Point-Performance

•IEEE 754-Compatible FPU

•Independent Instruction and Data MMUs

•4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed

Simultaneously

•32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface

•User-Object-Code Compatibility with All Earlier TS68000 Microprocessors

•Multimas ter/Multip rocessor Support via Bus Snooping

•Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize

Throughput

•4G bytes Direct Addressing Range

•Software Support Including Optimizing C Compiler and UNIX® System V Port

•IEEE P 1149-1 Test Mode (JTAG)

•f = 25 MHz, 33 MHz; VCC = 5V ± 5%; PD = 7W

•The Use of the TS88915T Clock Driver is Suggested

Description

The TS68040 is Atmel’s third gen eration of 68000- compatible , high-perfor mance, 32-

bit microprocessors. The TS68040 is a virtual memory m icroprocessor emplo ying

multiple, concurrent execution units and a highly integrated architecture to provide

very high performance in a monolithic HCMOS device. On a single chip, the TS68040

integrates a 68030-compatible integer unit, an IEEE 754-compatible floating-point unit

(FPU), and fully independent instructi on and data demand- paged memory manage-

ment u nits (M MUs), inc luding 4 K bytes i ndependent instru ction an d data c aches. A

high degree of instruction execution parallelism is achieved through the use of multi-

ple independent execution pipelines, multiple internal buses, and a full internal

Harvard ar ch ite ct ure, including sep ar ate p hy sica l c aches for bot h ins truc ti on an d dat a

access es. The TS6 8040 also directly support s cache co herency in multima ster appl i-

cations with dedicated on-chip bus snooping logic.

The TS68 040 is user- objec t-code compa tib le with previo us me mbers of the TS6800 0

Family and is specifically op timized to reduce the execution time of compiler-gener-

ated code. The 68040 HCMOS technology, provides an ideal balance between speed,

power, and physical device size.

Figure 1 is a simplified block diagr am of the TS68040. Instruction execution is pipe-

lined in both the integer unit and FPU. Independent data and instruction MMUs control

the main caches and the address translation caches (ATCs). The ATCs speed up log-

ical-to-physical address translations by storing recently used translations. The bus

snooper circuit ensures cache coherency in multimaster and multiprocessing

applications.

Screening

•MIL-STD-883

• DESC. Drawing 5962-93143

• Atmel Standards

Third-

Generation

32-bit

Microprocessor

TS68040

Rev. 2116A–H I REL –0 9/0 2

2TS68040 2116A–HIREL–09/02

Figure 1. Block Diagram

R suffix

PGA 179

Ceramic Pin Grid Array

Cavity Down

F suffix

CQFP 196

Gullwing Shape Lead

Ceramic Quad Fla Pack

INSTRUCTION

CACHE

DATA

CACHE

DATA MEMORY UNIT

INSTRUCTION MEMORY UNIT

INSTRUCTION

ATC

DATA

ATC

INSTRUCTION

FETCH

DECODE

EFFECTIVE

ADDRESS

CALCULATE

EXECUTE

EFFECTIVE

ADDRESS

FETCH

INSTRUCTION

MMU/CACHE/SNOOP

CONTROLLER

BUS

CONTROL

SIGNALS

DATA

BUS

ADDRESS

BUS

DATA

MMU/CACHE/SNOOP

CONTROLLER

OPERAND DATA BUS

INSTRUCTION DATA BUS

INSTRUCTION

ADDRESS

DATA

ADDRESS

WRITE

BACK

INTEGER

UNIT

CONVERT

EXECUTE

WRITE

BACK

FLOATING-

POINT

UNIT

TS68040

2116A–HIREL–09/02

Introduction The TS68040 is an enhanced, 32-bit, HCMOS microprocessor that combines the inte-

ger unit processing capabilities of the TS68030 microprocessor with independent

4K bytes dat a and instruc tion cach es and an on-chip F PU. The TS680 40 maintains the

32-bit registers available with the entire TS68000 Family as well as the 32-bit address

and data p aths, rich instructi on set, and ve rsatile ad dressing modes. Ins truction ex ecu-

tion proceeds in parallel with accesses to the internal caches, MMU operations, and bus

controller activity. Additionally, the integer unit is optimized for high-level language

environments.

The TS68040 FPU is user-object-code compatible with the TS68882 floating-point

coprocessor and conforms to the ANSI/IEEE Standard 754 for binary floating-point arith-

metic . The FPU ha s been opti mized to ex ecute th e most comm only us ed subse t of the

TS68 882 ins tructio n set, and inclu des addi tional in struc tion fo rmats for singl e and dou-

ble-precision rounding of results. Floating-point instructions in the FPU execute

concurrently with integer instructions in the integer unit.

The MMUs support multiprocessing, virtual memory systems by translating logical

addres ses to phy sical address es u sing tra nslation tables stored in mem ory . The MMUs

store recently used address mappings in two separate ATCs-on-chip. When an ATC

contai ns the phy sical add ress for a b us cycle re queste d by the proc essor, a translat ion

table search is avoided and the physical address is supplied immediately, incurring no

delay for address translation. Each MMU has two transparent translation registers avail-

able that define a one-to-one mapping for address space segments ranging in size from

16M bytes to 4G bytes each.

Each MMU provides read-only and supervisor-only protections on a page basis. Also,

processes can be given isolated address spaces by assigning each a uniqu e table

struct ure an d updat ing the root poin ter up on a tas k sw ap. Iso lated a ddress spaces pro-

tect the integrity of independent processes.

The i nstructio n and d ata cac hes op erate inde pendentl y from th e rest of t he mach ine,

storing information for fast access by the execution units. Each cache resides on its own

internal address bus and internal data bus, allowing simultaneous access to both. The

data cache provides write through or copyback write modes that can be configured on a

page-by-page basis.

The TS68040 bus controller supports a high-speed, non multiplexed, synchronous

external bu s inte rface, which allows the following t ransfer sizes: byte, word ( 2 bytes),

long word (4 bytes), and line (16 bytes). Line accesses are performed using burst trans-

fers for both reads and writes to provide high data transfer rates.

4TS68040 2116A–HIREL–09/02

Pin Assignments

PGA 179

Figure 2. Bottom View

Table 1. Power Supply Affectation to PGA Body

GND VCC

PLL S8

Internal Logic C6, C7, C9, C11,C13, K3 , K16, L3, M16, R4, R11, R13,

S10, T4, S9, R6, R10 C5, C8, C10, C12, C14, H3, H16, J3, J16, L16, M3, R5,

R12, R8

Output Drivers B2, B4, B6, B8, B10, B13 , B15, B17, D2 , D17, F 2, F17,

H2, H17, L2, L17, N2, N17, Q2, Q17, S2, S15, S17 B5, B9, B14, C2, C17, G2, G17, M2, M17, R2, R17,

S16

TS68040

2116A–HIREL–09/02

CQFP 196

Figure 3. Pin Assignments

Table 2. Power Supply Affectation to CQFP Body

GND VCC

PLL 127

Internal Logic 4, 9, 10, 19, 32, 45, 73, 88, 113, 119, 121, 122, 124,

125, 129, 130, 141, 159, 172 3, 18, 31, 40, 46, 60, 72, 87, 114, 126, 137, 158, 173,

186

Output Drive rs 7, 15, 22, 28 , 35, 42, 49 , 50, 51, 57, 63, 69, 76, 77, 83,

84, 91, 97, 98, 99, 105, 106, 146, 147, 148, 149, 155,

162, 163, 169, 176, 182, 183, 189, 195, 196

12, 25, 38, 54, 66, 80, 94, 102, 152, 166, 179, 192

6TS68040 2116A–HIREL–09/02

Signal Description Figure 4 and Table 3 describe the signals on the TS68040 and indicate signal functions.

The t est sig nals, TR ST, TMS, TCK , TDI, and T DO, comp ly w ith sub set P -1149.1 of th e

IEEE testability bus standard.

Figure 4. Functional Signal Groups

TS68040

2116A–HIREL–09/02

Table 3. Signal Index

Signal Name Mnemonic Function

Address Bus A31-A0 32-bit address bus used to address any of 4G bytes

Data Bus D31-D0 32-bit data bus used to transfer up to 32 bits of data per bus transfer

Transfer Typ e TT1, TT0 Indicates the general transfer type: normal, MOVE 16, alternate logical function

code, and acknowledg e

Transfer Modifier TM2, TM0 Indicates supplemental information about the access

Transfer Line Number TLN1, TL N0 Indicates which cache line in a set is being pushed or loaded by the current line

transfer

User Programmable Attributes UPA1,

UPA0 User-defined signals, controlled by the corresponding user attribute bits from the

address translatio n entry

Read Write R/W Identifies the transfer as a read or write

Transfer Size SIZ1, SIZ0 Indicat es th e data tr ans fer siz e. The se sign al s, tog eth er with A0 and A1, de fin e the

active sections of the data bus

Bus Lock LOCK Indicates a bus transfer is part of a read-modify-write operation, and that the

sequence of transfers should not be interrupted

Bus Lock End LOCKE Indicates the current transfer is the last in a locked sequence of transfer

Cach e Inhibit Out CIOUT Indicates the processor will not cache the current bus transfer

Transfer Start TS Indicates the beginning of a bus transfer

Transfer in Progre ss TIP Asserted for the duration of a bus transfer

Transfer Ack nowl edg e TA Asserted to acknowled ge a bus tran sfe r

Transfer Error Acknow le dge TEA Indicates an error condition exists for a bus transfer

Transfer Ca ch e Inhib it TCI Indicates the current bus transfer should not be cached

Transfer Burst Inhibi t TBI Indicates the slave cannot handle a line burst access

Data Latch Enable DLE Alternate clock input used to latch input data when the processor is operating in

DLE mode

Snoop Control SC1, SC0 Indicates the snoo ping operation required during an alternate master access

Memory Inhibit MI Inhibits memory devices from responding to an alternate master access during

snooping operations

Bus Request BR Asserted by the proc essor to request bus mastership

Bus Grant BG Asserted by an arbiter to grant bus mastership to the processor

Bus Busy BB Asserted by the current bus master to indicate it has assumed ownership of the bus

Cache Disab le CDIS Dynamically disables the internal caches to assist emulator support

MMU Disable MDIS Disables the translation mechanism of the MMUs

Reset In RSTI Processor reset

Reset Out RSTO Asserted during execution of the RESET instruction to reset external devices

Interrupt Priority Level IPL2-IPL0 Provides an encoded interrupt level to the processor

Interrupt Pending IPEND Indicates an interrupt is pending

Autovector AVEC Used duri ng an interrupt a ck nowl edg e tra ns fer to request intern al g en erat ion of th e

vector number

Processor Status PST3-PS T0 Indicates in tern al pro c essor status

8TS68040 2116A–HIREL–09/02

Scope This drawing describes the specific requirements for the microprocessor T S68040 -

25 MHz and 3 3 MHz, in compliance with MIL-STD-883 class B or Atmel standard

screening.

Applicable

Documents

MIL-STD-883 1. MIL-STD-883: test methods and procedures for electronics.

2. MIL-I-38535: general specifications for microcircuits.

3. DESC 5962-93143.

Requirements

General The micro circuits are in acc ordance w ith the app licable doc ument and as specifie d

herein.

Design and Construction

Terminal Connections See Figure 2 and Figure 3.

Lead Material and Finish Lead materi al and fin ish sha ll be as spe ci fied in MIL-STD-883 (s ee enclo se d “MI L- STD-

883 C and Internal Standard” on page 46).

Package The macro circuits are packaged in hermetically sealed ceramic packages which con-

form to case outlines of MIL-STD-1835-or as follow:

• CMGA 10-179-PAK pin grid array, but see “179 pins – PGA” on page 43.

• Similar to CQCC1-F196C-U6 ceramic uniform lead chip carrier package with

ceramic nonconductive tie-bar but use Atmel’s internal drawing, see “196 pins – Tie

Bar CQFP Cavity Up (on request)” on page 44.

• Gullwing shape CQFP see “196 pins – Gullwing CQFP cavity up” on page 45.

Bus Clock BCLK Clock input used to derive all bus signal timing

Processor Clock PCLK Clock input used for internal logic timing. The PCLK frequency is exactly 2X the

BCLK frequency

Test Clock TCK Clock signal for the IEEE P1149.1 test access port (TAP)

Test Mode Select TMS Selects the principle operations of the test-support circuitry

Test Data Input TDI Serial data input for the TAP

Test Data Output TDO Serial data output for the TAP

Test Reset TRST Provides an asynchronous reset of the TAP controller

Power Supply VCC Power supply

Ground GND Ground conne cti on

Table 3. Signal Index (Continued)

Signal Name Mnemonic Function

TS68040

2116A–HIREL–09/02

The precise case outlines are described at the end of the specification (See “Pack age

Mechanical Data” on page 43.) and into MIL-STD-1835.

Electrical Characteristics

Absolute Maximum Ratings Stresses above the abso lute maximum rating may cause permanent damage to the

device. Extended operation at the maximum levels may degrade performance and affect

reliability.

Note: 1. This dev ic e is no t tes ted at T C = +12 5°C . Te sti ng is p erfo rmed by setti ng t he j unc tio n te mperature T j = +1 25 °C and all ow ing

the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature.

Note: 1. This de vi ce is n ot tes ted at TC = + 125°C. Test ing is p erformed by s etti ng the ju nc tio n temperature T J = + 125°C and all owin g

the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature.

Table 4. Absolute Maximum Ratings

Symbol Parameter Condition Min Max Unit

VCC Supply Voltage Range -0.3 7.0 V

VIInput Voltage Range -0.3 7.0 V

PDPower Dissipation Large buff ers enabled 7.7 W

Small buffers enabl ed 6.3 W

TCOperating Temperature -55 TJ°C

Tstg Storage Temperature Range -65 +150 °C

TJJunction Temperature(1) +125 °C

Tlead Lead Temper ature Max.10 sec soldering +300 °C

Table 5. Recommended Conditions of Use

Unless otherwise stated, all voltages are referenced to the reference terminal

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage Range +4.75 +5.25 V

VIL Logic Low Level Input Voltage Range GND

- 0.3 0.8 V

VIH Logic High Level Input Voltage Range +2.0 VCC + 0.3 V

VOH High Level Output Voltage 2.4 V

VOL Low Level Output Voltage 0.5 V

fcClock Frequency -25 MHz Version 25 MHz

-33 MHz Version 33 MHz

TCCase Operating Temperature Range(1) -55 TJmax °C

TJMaximum Operating Junction Temperature +125 °C

10 TS68040 2116A–HIREL–09/02

Thermal Considerations

General Thermal

Considerations This section is only given as user information.

As microprocessors are becoming more complex and requiring more power, the need to

efficiently cool the device becomes increasingly more important. In the past, the

TS68000 Family, has been able to provide a 0-70°C ambient temperature part for

speeds le ss than 40 MHz . However, the T S68040 , which has a 50 MHz arithm etic lo gic

unit (ALU) speed, is specified with a maximum power dissipation for a particular mode, a

maximum junction temperature, and a thermal resistance from the die junction to the

case. This pro vides a more accu rate me thod of evaluat ing the en vironme nt, tak ing int o

conside ration bot h the air-fl ow and amb ient temperatu re availabl e. This a lso allo ws a

user the info rm ati on to d es ign a co oli ng m etho d whi ch mee ts bo th the r mal perfor ma nc e

requirements and constraints of the board environment.

This section discusses the device characteristics for thermal management, several

methods of thermal management, and an example of one method of cooling the

TS68040.

Thermal Device

Characteristics The TS68040 presents some inherent characteristics which should be considered when

evaluating a meth od of cooling the device. The following paragraphs discuss these

die/package and power considerations.

Die and Packag e The TS68040 is being placed in a cavity-down alumina-ceramic 179-pin PGA that has a

specified thermal resistance from junction to case of 1°C/W. This package differs from

previous TS68000 Family PGA packages which were cavity up. This cavity-down design

allows the die to be attached to the top surface of the package, which increases the abil-

ity of the part to dis sipate heat through the packag e surface or an attached he at sink.

The maximum perimeter that the TS68040 allows for a heat sink on its surface without

interfe rin g wit h the capa cito r pads is 1.48 " x 1.48 ". T he s pecifi c di mens ions and d esig n

of the particular heat sink will need to be determined by the system designer considering

both thermal performance requirements and size requirements.

Power Considera tions The TS68040 has a maximum power rating, which varies depending on the operating

frequency and the output buffer mode combination being used. The large buffer output

mode dissip ates m ore p ower than t he sm all, a nd the high er freq uencies of o perat ion

dissipate more power than the lower frequencies. The following paragraphs discuss

trade-of fs in using the di fferent outpu t buffer mode s, calculation of specific maximum

power dissipation for differ ent modes, and the relationship of thermal resistances and

temperatures.

TS68040

2116A–HIREL–09/02

Output Buffer Mode The 68040 is capable of resetting to enable for a combination of either large buffers or

small buffers on the outputs of the miscellaneous control signals, data bus, and address

bus/transfer attribute pins. The large buffers offer quicker output times, which allow for

an easi er logic de sign. Howev er, they do so by driving about 11 times as much curr ent

as the small buffers (refer to TS68040 Electrical specifications for current output). The

designer should consider whether the quicker timings present enough advantage to jus-

tify the additional consideration to the individual signal terminations, the die power

consumption, and the required cooling for the device. Since the TS68040 can be pow-

ered-up in one of eight ou tput buffer modes upon reset, the actual maximum power

consump tion fo r TS68 040 rated at a particu lar ma ximum o perating freque ncy is depen-

dent upon the power up mode. Therefore, the TS68040 is rated at a maximum power

dissip ation for eith er the large buffer s or s mall buffers at a p artic ular fr equen cy (r efer to

TS68040 Electrical specifications). This allows the possibility of some of the thermal

management to be controlled upon reset. The following equation provides a rough

method to calculate the maximum power consumption for a chosen output buffer mode:

PD = PDSB + (PDLB - PDSB) · (PINSLB/PINSCLB) (1)

where:

PD = Max. power dissipation for output buffer mode

selected

PDSB = Max. powe r dissipation for small buffer mode

(all outputs)

PDLB = Max. power dissipation for large buffer mode

(all outputs)

PINSLB = Number of pins large buffer mode

PINSCLB = Number of pins capable of the large buffer

mode

Table 6 s hows the simp lified relation ship on the m aximum power di ssipation for ei ght

possib le config ur ati ons of output buffe r modes .

Table 6. Maximum Power Dissipation for Output Buffer Mode Configurations

Output Configuration Maximum Power Dissipation

Data Bus Address Bus and

Transfer Attrib. Misc. Control

Signals PD

Small Buffer Small Buffer Small Buffer PDSB

Small Buffer Small Buffer Large Buffer PDSB + (PDLB - PDSB) · 13%

Small Buffer Large Buffer Small Buffer PDSB + (PDLB - PDSB) · 52%

Small Buffer Large Buffer Large Buffer PDSB + (PDLB - PDSB) · 65%

Large Buffer Sma ll Buffe r Small Buffer PDSB + (PDLB - PDSB) · 35%

Large Buffer Sma ll Buffe r Large Buffer PDSB + (PDLB - PDSB) · 48%

Large Buffer Large Buffer Small Buffer PDSB + (PDLB - PDSB) · 87%

Large Buffer Large Buffer Large Buffer PDSB + (PDLB - PDSB) · 100%

12 TS68040 2116A–HIREL–09/02

To calc ulate the specific power dis sipation of a specif ic design , the term ination method

of each signal must be considered. For example, a signal output that is not connected

would not dissipate any additional power if it were configured in the large buffer rather

than the small buffer mode.

Relationships Between

Thermal Resistances and

Temperatures

Since the maximum operating junction temperature has been specified to be 125°C.

The maximum case temperature, TC, in °C can be obtained from:

TC = TJ - PD · ΦJC (2)

where:

TC= Ma ximum case temperatur e

TJ= Maximum junction temperature

PD= Maximum power dissipation of the device

ΦJC = Thermal resistance between the junction of the die and the case

In general, the ambient temperature, TA, in °C is a function of the following formula:

TA = TJ - PD · ΦJC - PD · ΦCA (3)

Where the thermal resistance from case to ambient, ΦCA, is the only user-dependent

parameter once a buffer output configuration has been determined. As seen from equa-

tion (3), reducing the case to am bient thermal resistance increases the maximum

operati ng a mbien t tem perat ure. The refore , by util izin g su ch m ethod s as hea t si nks and

ambient ai r cooli ng to minimi ze the ΦCA, a hig her ambie nt oper ating tem peratur e and/or

a lower junction temperature can be achieved.

However, an easier approach to thermal evaluation uses the following formulas:

TA = TJ - PD · ΦJA (4)

or alternatively,

TJ = TA - PD · ΦJA (5)

where:

ΦJA = thermal resistance from the junction to the ambient (ΦJC + ΦCA).

This total ther mal r esistan ce of a package , ΦJA, is a co mbi nat ion o f i ts two c om pone nts ,

ΦJC an d ΦCA. T hese componen ts represent the ba rrier to heat flow fr om the semicon-

ductor junction to the package (case) surface (ΦJC) and from the case to the outside

ambient (ΦJC). Although ΦJC is device related and cannot be inf luenced by the user, ΦCA

is user depende nt. Thus, good thermal management by the use r can significantly

reduce ΦCA achieving either a lower semiconductor junction temperature or a higher

ambient operating temperature.

Thermal Management

Techniques To attain a reasonable ma ximum ambient operating temper ature, a user must r educe

the bar rier to heat flo w from the sem iconducto r junction to th e outside amb ient (ΦJA).

The only way to accomplish this is to significantly reduce ΦCA by ap plying such the rmal

management techniques as heat sinks and ambient air cooling.

The following paragraphs discuss some results of a thermal study of the TS68040

device without using any thermal management techniques; using only air-flow cooling,

using only a heat sink, and using heat sink combined with air-flow cooling.

TS68040

2116A–HIREL–09/02

Thermal Characteristics in

Still Air A sam ple size of th ree TS68 040 packages wa s tested in free-air cooling with no heat

sink. M easur em ent s sho w ed tha t th e av erag e ΦJA was 2 2.8° C/W wit h a stand ar d d evi a-

tion of 0.44°C/W. The test was performed with 3W of power being dissipated from within

the package. The test determined that ΦJA will decrease slightly for the increasing power

diss ipation r ange p ossible. There fore, si nce the vari ance in ΦJA within the possible

power dissipati on range is negligible , it can be as sumed for cal culation purpos es that

ΦJA is vali d at all powe r l evel s. Us ing the for mu las in trodu ced pr ev iou sly , Tabl e 7 s hows

the res ults of a maximum power dissipati on of 3 and 5W with no he at sink or air- flow

(refer to Table 6 to calculate other power dissipation values).

As seen by looking at the ambient temperature results, most use rs will want to im ple-

ment some type of thermal management to obtain a more reasonable maximum

ambient temperature.

Thermal Characteristics in

Forced Air A sample size of three TS68040 packages was tested in forced air cooling in a wind tun-

nel with no heat sink. This test was performed with 3W of power being dissipated from

within the package. As previously mentioned, since the variance in ΦJA wit h in t he p ossi -

ble power range is negligible, it can be assumed for calculation purposes that ΦJA is

constant at all power levels. Using the previous formulas, Table 8 shows the results of

the maximum power dissipation at 3 and 5W with air-flow and no heat sink (refer to

Table 6 to calculate other power dissipation values).

Table 7. Thermal Parameters With No Heat Sink or Air-flow

Defined Parameters Measured Calculated

PDTJΦJC ΦJA ΦCA = ΦJA - ΦJC TC = TJ - PD * ΦJC TA = TJ - PD * ΦJA

3 Watts 125°C 1°C/W 21.8°C/W 20.8°C/W 122°C 59.6°C

5 Watts 125°C 1°C/W 21.8°C/W 20.8°C/W 120°C 16°C

Table 8. Thermal Parameters With Forced Air Flow and No Heat Sink

Thermal Mgmt.

Technique Defined Parameters Measured Calculated

Air-flow velocity PDTJΦJC ΦJA ΦCA TCTA

100 LFM 3W 125°C 1°C/W 11.7°C/ W 10.7°C/W 122°C 89.9°C

250 LFM 3W 125°C 1°C/W 10°C/W 9°C /W 122°C 95°C

500 LFM 3W 125°C 1°C/W 8.9°C/W 7.9°C/W 122°C 98.3°C

750 LFM 3W 125°C 1°C/W 8.5°C/W 7.5°C/W 122°C 99.5°C

1000 LFM 3W 125°C 1°C/W 8.3°C/W 7.3°C/W 122°C 100.1°C

100 LFM 5W 125°C 1°C/W 11.7°C/ W 10.7°C/W 120°C 66.5°C

250 LFM 5W 125°C 1°C/W 10°C/W 9°C/W, 120°C 75°C

500 LFM 5W 125°C 1°C/W 8.9°C/W 7.9°C/W 120°C 80.5°C

750 LFM 5W 125°C 1°C/W 8.5°C/W 7.5°C/W 120°C 82.5°C

1000 LFM 5W 125°C 1°C/W 8.3°C/W 7.3°C/W 120°C 83.5°C

14 TS68040 2116A–HIREL–09/02

By reviewing the maximum ambient operat ing temperatures, it can be seen that by

using the all- smal l-buffer confi guration of the TS68040 with a r elativ ely small amount of

air flow (100 LFM), a 0-70°C ambient operating temperature can be achieved. However,

depending on th e o utpu t buffer configur ation and av ai la ble fo rc ed -air c ool in g, addi tiona l

thermal management techniques may be r equired.

Thermal Characteristics with

a Heat Sink In choosing a heat sink the designer must consider many factors: heat sink size and

compo sition , method of att achment , and ch oice of a we t or dry c onnec tion. Th e follow -

ing paragraphs discuss the relationship of these decisions to the thermal performance of

the design noticed during experimentation.

The heat s ink size i s one of the mos t signific ant par amete rs to con sider in the sel ectio n

of a heat sink. Obviously a larger heat sink will provide better cooling. However, it is less

obvious that the most benefit of the larger heat sink of the pin fin type used in the exper-

imentation would be at still air conditions. Under forced-air conditions as low as 100

LFM, the difference between the ΦCA becomes very small (0.4°C/W or less). This differ-

ence conti nues to decr ease as the for ced air flow increases . The parti cular heat sink

used in our testi ng fit t he perimete r pa ckage surfac e ar ea avai labl e within the capaci tor

pads on the T S68040 (1.48" x 1.48") an d showed a nic e compromise between height

and thermal performance needs. The heat sink base perimeter area was 1.24" x 1.30"

and its height was 0.49". It was a pin-fin-type (i.e. bed of nails) design composed of Al

alloy. The heat sink is shown in Figure 5 can be obtained through Thermalloy Inc. by ref-

erencing part number 2338B.

Figure 5. Heat Sink Example

TS68040

2116A–HIREL–09/02

All pin fin heat sink s tested were made from extrusion Al products. The planar face of

the heat sink mating to the package should have a good degree of planarity; if it has any

curvatur e, the curvatu re s hould be co nvex at the c entral region of the heat s ink s urface

to provide inti mate physical contac t to the PGA surfac e. All heat sin ks tested met this

criteria. Nonplanar, concave curvature the central regions of the heat sink will result in

poor thermal contact to the package. A specification needs to be determined for the pla-

narity of the surface as part of any heat sink design.

Although there are several ways to attach a heat sink to the package, it was easiest to

use a demountable heat sink attach called “E-Z attach for PGA packages” developed by

Thermalloy (see Figure 6). The heat sink is clamped to the package with the help of a

steel spring to a plastic frame (or plastic shoes Besides the height of the heat sink and

plastic frame, no additional height added to the package. The interface between the

ceram ic packa ge and the heat sink was e valuat ed for both d ry and wet (i .e., ther mal

grease) interfaces in still air. The thermal grease reduced the ΦCA quite significantly

(about 2.5 °C/ W) in stil l air . T heref or e, it was used in al l oth er testi ng done wi th the he at

sink. According to other testing, attachment with thermal grease provided about the

same thermal performance as if a thermal epoxy were used.

Figure 6. Heat Sink with Attachment

A sample size of one TS68040 package was tested in still air with the heat sink and

attachment method previously described. This test was performed with 3W of power

being dissipated from within the package. Since the variance in ΦJA within the possible

power ran ge is negligib le, it can be assumed for calcula tion purposes that ΦJA is con-

stant at all power levels. Table 9 shows the result assuming a maximum power

dissip ation of the part at 3 and 5W (re fer to Table 6 to ca lculate oth er power dis sipa tion

values).

16 TS68040 2116A–HIREL–09/02

Thermal Characteristics with

a Heat Sink

and Forced Air

A sample size of three TS68040 packages was tested in forced-air cooling in a wind tun-

nel with a hea t sink. Th is test was performed with 3W of p ower being di ssipated from

within the package. As mentioned previously, the variance in ΦJA within the possible

power ran ge is negligible; it can be as su med for c alcul ati on pu rp oses that ΦJA is valid at

all power le ve ls . Table 10 shows the re su lts, assum in g a maximum power diss ip ati on at

3 and 5W with ai r flow and h eat s ink t her ma l man age men t ( refe r to Tabl e 6 t o c al cula te

other power dissipation values).

Thermal Testing Summary T estin g pro ved t hat a h eat si nk in c ombi nation with a relativ ely small amount of air -fl ow

(100 LFM or less) will easily realize a 0-70°C ambient operating temperature for the

TS68 040 with al most any c onfigur ation of the output buffers . A heat si nk alon e may be

capable of providing all necessary cooling, depending on the particular heat sink

height/si ze restr aints, the maximum ambient operating temperature required, and the

output buffer co nfiguration chos en. Also forced air coolin g alone may attain a 0-70°C

ambient operating temperature. However this factor is highly dependent on the output

buffer configuration chosen and the available forced air for cooling. Figure 7 is a sum-

mary of the test results of the relationship between ΦJA and air-flow for the TS68040.

Table 9. Thermal Parameters With Heat Sink and No Air Flow

Thermal Mgmt.

Technique Defined Parameters Measured Calculated

Heat Sink PDTJΦJC ΦJA ΦCA TCTA

2338B 3W 125°C 1°C/W 14°C/W 13°C/W 122°C 83°C

2338B 5W 125°C 1°C/W 14°C/W 13°C/W 120°C 55°C

Table 10. Thermal Parameters with Heat Sink and Air Flow

Thermal Mgmt. Technique Defined Parameters Measured Calculated

Air-flow Heat sink PDTJΦJC ΦJA ΦCA TCTA

100 LFM 2338B 3W 125°C 1°C/W 3.1°C/W 2.1°C/W 122°C 115.7°C

250 LFM 2338B 3W 125°C 1°C/W 2.2°C/W 1.2°C/W 122°C 118.4°C

500 LFM 2338B 3W 125°C 1°C/W 1.7°C/W 0.7°C/W 122°C 119.9°C

750 LFM 2338B 3W 125°C 1°C/W 1.5°C/W 0.5°C/W 122°C 120.5°C

1000 LFM 2338B 3W 125°C 1°C/W 1.4°C/W 0.4°C/W 122°C 120.8°C

100 LFM 2338B 5W 125°C 1°C/W 3.1°C/W 2.1°C/W 120°C 109.5°C

250 LFM 2338B 5W 125°C 1°C/W 2.2°C/W 1.2°C/W 120°C 114°C

500 LFM 2338B 5W 125°C 1°C/W 1.7°C/W 0.7°C/W 120°C 116.5°C

750 LFM 2338B 5W 125°C 1°C/W 1.5°C/W 0.5°C/W 120°C 117.5°C

1000 LFM 2338B 5W 125°C 1°C/W 1.4°C/W 0.4°C/W 120°C 118°C

TS68040

2116A–HIREL–09/02

Figure 7. Relationship of ΦJA Air-Flow for PGA

Mechanical and

Environment The microcircuits shall meet all mechanical environmental requirements of either MIL-

STD-883 for class B devices or for Atmel standard screening.

Marking The document where are defined the marking are identified in the related reference doc-

uments. Each microcircuit are legible and permanently m arked with the following

information as minimum:

• Atmel Logo

• Manufacturer’s Part Number

• Class B Identification

• Date-code Of Inspection Lot

• ESD Identifier If Available

• Country Of Manufacturing

Table 11. Characteristics Guaranteed

Package Symbol Parameter Value Unit

PGA 179 θJ-A Thermal Resistance Junction-to-ambien t See Figure 7 ° C/W

θJ-C Thermal Res istan ce Junction-to- case 1 °C/W

CQFP 196 θJ-A Thermal Resistance Junction -to-ambient TBD °C/W

θJ-C Thermal Res istan ce Junction-to- case 1 °C/W

18 TS68040 2116A–HIREL–09/02
Quality Conformance 
Inspection
DESC/MIL-STD-883 Is in ac cordan ce with M IL-M-38 535 and  method 50 05 of M IL-STD-8 83. Grou p A and B
inspections are performed on each production lot. Groups C and D inspection are per-
formed on a periodical basis.
Electrical 
Characteristics
General Requirements All static and dynamic electrical characteristics specified for inspection purposes and the
relevant measurement conditions are given below:
• Table 12: Static electrical characteristics for the electrical variants.
• Table 13: Dynamic electrical characteristics for TS68040 (25 MHz, 33 MHz).
For static characteristics (Table 12), test methods  refer to IEC 748-2 method number,
where existing.
For dynamic characteristics (Table 13), test methods refer to clause “Static Characteris-
tics” on page 18 of this specification.
Indication of “min.” or “max.” in the column «test temperature» means minimum or max-
imum operating temperature as defined in sub-clause Table 5 here above.
Static Characteristics
Table 12.  Electric al Char ac te rist ic s
-55°C ≤ TC ≤ TJmax; 4.75V ≤ VCC ≤ 5.25V unless otherwise specified(1)(2)(3)(4)
Symbol Characteristic Min Max Unit
VIH Input High  Voltage 2 VCC V
VIL Input Low Volta ge GND 0.8 V
VUUndershoot - 0.8 V
Iin Input Leakage Current
at 0.5/2.4V AVEC, BCLK BG, CDIS,
IPLn, MDIS , PCLK, RSTI, SCn,
TBI, TCI, TCK, TEA -20 20 µA
ITSI Hi-z (Off-state) Leakage Current
at 0.5/2.4V An, BB, CIO UT, Dn, LOCK,
LOCKE, R/W, SIZn, TA, TDO,
TIP, TLNn, TMn, TS, TTn, UPAn -20 20 µA
IIL Signal L ow Input Current
VIL = 0.8V TMS, TDI, TRST -1.1 -0.18 mA
IIH Signal High Input Current
VIH = 2.0V TMS, TDI, TRST -0.94 -0.16 mA
VOH Output High Voltage
Larger Buffers - IOH = 35 mA
Small Buffers - IOH = 5 mA 2.4 V

19
TS68040
2116A–HIREL–09/02
Notes: 1. All testing to be performed using worst-case test conditions unless otherwise specified.
2. Maximum operating junction temperature (TJ) = +125°. Minimum case operating temperature (TC) = -55°. This device is not
tested at  T C = + 125 °. Te sti ng  is  performed by  setting the junction te mp erature TJ = +125°and allowing the case and ambient
temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature.
3. Capacitance is periodically sampled rather than 100% tested.
4. Power diss ipa tio n may  vary in betwe en lim its dependi ng on the app lic at ion .
Dynamic Characteristics
Notes: 1. All testing to be performed using worst-case test conditions unless otherwise specified.
2. Maximum operating junction temperature (TJ) = +125°. Minimum case operating temperature (TC) = -55°. This device is not
tested at  T C = + 125 °. Te sti ng  is  performed by  setting the junction te mp erature TJ = +125°and allowing the case and ambient
temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature.
3. Specification value at maximum frequency of operation.
4. If not tested, shall be guaranteed to the limits specified.
VOL Output Low Voltage
Larger buffers - IOL = 35 mA
Small buffers - IOL = 5 mA 0.5 V
PDPower Dissipation (TJ = 125°C)
Larger Buffers Enabled
Small Buffers Enabled
7.7
6.3 W
Cin Capacitance - Note 4
Vin = 0V, f = 1 MHz 25 pF
Table 12.  Electric al Char acteristic s (Co nti nue d)
-55°C ≤ TC ≤ TJmax; 4.75V ≤ VCC ≤ 5.25V unless otherwise specified(1)(2)(3)(4)
Symbol Characteristic Min Max Unit
Table 13.  Clock AC Timing Speci fications (see Figure 8)
-55°C ≤ TC ≤ TJmax; 4.75V ≤ VCC ≤ 5.25V unless otherwise specified(1)(2)(3)(4)
Num Characteristic
25 MHz 33 MHz
UnitMinMaxMinMax
Frequenc y of Ope rati on 20 25 20 33 MHz
1 PCLK Cycle Time 20 25 15 25 ns
2 PCLK Rise Time(4) 1.7 1.7 ns
3PCLK Fall Time
(4) 1.6 1.6 ns
4 PCLK Duty Cycle Measured at 1.5V(4) 47.5 52.5 46.67 53.33 %
4a PCLK Pulse Width High Measured at 1.5V(3)(4) 9.5 10.5 7 8 ns
4b PCLK Pulse Width Low Measured at 1.5V(3)(4) 9.5 10.5 7 8 ns
5 BCLK Cycle Time 40 50 30 60 ns
6, 7 BCLK Rise and Fall Time 4 3 ns
8 BCLK Duty Cycle Measured at 1.5V(4) 40 60 40 60 %
8a BCLK Pulse Width High Measured at 1.5V(4) 16 24 12 18 ns
8b BCLK Pulse Width Low Measured at 1.5V(4) 16 24 12 18 ns
9 PCLK, BCLK Frequency Stabi li ty(4) 1000 1000 ppm
10 PCLK to BCLK Skew 9 n/a ns

20 TS68040 2116A–HIREL–09/02
Figure 8.  Clock Input Timing
Table 14.  Output AC Timing Specifications(1) (Figure 9 to Figure 15)
These output specifications are only for 25 MHz. They must be scaled for lower operating frequencies. Refer to
TS6804DH/AD for further information. -55°C ≤ TC ≤ TJmax; 4.75V ≤ VCC ≤ 5.25V unless otherwise specified.(2)(3)(4)
Num Characteristic
25 MHz 33 MHz
Unit
Large 
Buffer(1) Small 
Buffer(1) Large 
Buffer(1) Small 
Buffer(1)
MinMaxMinMaxMinMaxMinMax
11 B CLK to addr ess CIOU T, LOCK, LOCKE, 
R/W, SIZn, TLN, TMn, UPAn valid(5) 9219306.50186.5025ns
12 BCLK to output invalid (output hold) 9 9 6.50 6.50 ns
13 BCLK to TS valid 9 21 9 30 6.50 18 6.50 25 ns
14 BCLK to TIP valid 9 21 9 30 6.50 18 6.50 25 ns
18 BCLK to data-out valid(6) 9239326.50206.5027ns
19 BCLK to dat a-out invalid (output hold)(6) 9 9 6.50 6.50 ns
20 BCLK to output low impedance(5)(6) 9 9 6.50 6.50 ns
21 BCLK to data-out high impedance 9 20 9 20 6.50 17 6.50 17 ns
26 BCLK to multiplexed address valid(5) 19 31 19 40 14 26 14 33 ns
27 BCLK to multiplexed address driven(5) 19 19 14 14 ns
28 BCLK to multiplexed address high 
impedance(5)(6) 9189186.50156.5015ns
29 BCLK to multiplexed data driven(6) 19 19 14 20 14 20 ns
30 BCLK to multiplexed data valid(6) 19 33 19 42 14 28 14 35 ns
38 B CLK to  address CIOU T, LOCK, LOCKE, 
R/W, SIZn, TS, TLNn, TMn, TTn, UPAn high 
impedance(5)
9189186.50156.5015ns
39 BCLK to BB, TA, TIP high impedance 19 28 19 28 14 23 14 23 ns
40 BCLK to BR, BB valid 9 21 9 30 6.50 18 6.50 25 ns
43 BCLK to MI valid 9 21 9 30 6.50 18 6.50 25 ns
48 BCLK to TA valid 9 21 9 30 6.50 18 6.50 25 ns
50 BCLK to IPEND, PSTn, RSTO valid 9 21 9 30 6.50 18 6.50 25 ns

TS68040

2116A–HIREL–09/02

Notes: 1. Output timing is specified for a valid signal measured at the pin. Large buffer timing is specified driving a 50Ω tran smis sion

line with a len gth char acterized by a 2. 5 ns one-w a y pro pag ati on de la y, terminated through 50Ω to 2.5V. Large bu ffer o utpu t

imp edanc e is typic ally 3Ω, resulting in incident wave switching for this environment. Small buffer timing is specified driving

an untermina ted 30Ω transmission line with a length characterized by a 2.5 ns one-way propagation delay. Small buffer out-

put impedance is typically 30Ω; the small buffer specifications include approximately 5 ns for the signal to propagate the

length of the transmission line and back.

2. All testing to be performed using worst-case test conditions unless otherwise specified.

3. The following pins are active low: AVEC, BG, BS, BR, CDIS, CIOUT, IPEND, IPLO , IPL1, IPL2, LOCK, LOCKE, MDIS, MI,

RST0, RSTI, TA, TBI, TCI, TEA, TIP, TRST, TS and W of R/W.

4. Maximum operating junction temperature (TJ) = +125°. Minimum case operating temperature (TC) = -55°. This device is not

tested at T C = + 125 °. Te sti ng is performed by setting the junction te mp erature TJ = +125°and allowing the case and ambient

temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature.

5. Timing specifications 11, 20 and 38 for address bus output timing apply when normal bus operation is selected. Specifica-

tions 26, 27 and 28 should be used when the multiplexed bus mode of operation is enabled.

6. Timing specifications 18 and 19 for data bus output timing apply when normal bus operation is selected. Specifications 28

and 29 should be used when the multiplexed bus mode of operation is enabled.

Table 15. Input AC Timing Specifications (Figure 9 to Figure 15)

-55°C ≤ TC ≤ TJmax; 4.75V ≤ VCC ≤ 5.25V unless otherwise specified(1)(2)(3)(4)

Num Characteristic

25 MHz 33 MHz

UnitMin. Max. Min. Max.

15 Data-in Valid to BCLK (Setup ) 5 4 ns

16 BCLK to Data-in Invalid (Hold) 4 4 ns

17 BCLK to Data-in High Impedance (Read Followed By Write) 49 36.5 ns

22a TA Valid to BCLK (Setup) 10 10 ns

22b TEA Valid to BCLK (Setup) 10 10 ns

22c TCI Valid to BCLK (Setup) 10 10 ns

22d TBI Valid to BCLK (Setup) 11 10 ns

23 BCLK to TA, TEA, TCI, TBI Invalid (H old) 2 2 ns

24 AVEC Valid to BCLK (Setup) 5 5 ns

25 BCLK to AVEC Invalid (Hold) 2 2 ns

31 DLE Width High 8 8 ns

32 Data-in Valid to DLE (Setup) 2 2 ns

33 DLE to Data-in Invalid (Hold) 8 8 ns

34 BCLK to DLE Hold 3 3 ns

35 DLE Hi gh to BCLK 16 12 ns

36 Data-in Valid to BCLK (DLE Mode Setup) 5 5 ns

37 BCLK Data-in Inva li d (DLE Mo de Hold ) 4 4 ns

41a BB Valid to BCLK (Setup) 7 7 ns

41b BG Valid to BCLK (Setup) 8 7 ns

41c CDIS, MDIS Valid to BCLK (Setup) 10 8 ns

41d IPLn Valid to BCLK (Setup) 4 3 ns

42 BCLK to BB, BG, CDIS, IPLn, MDIS Inv ali d (Hold) 2 2 ns

44a Address Valid to BCLK (Setup) 8 7 ns

44b SIZn Valid BCLK (Setup) 12 8 ns

22 TS68040 2116A–HIREL–09/02

Notes: 1. All testing to be performed using worst-case test conditions unless otherwise specified.

2. The following pins are active low: AVEC, BG, BS, BR, CDIS, CIOUT, IPEND, IPLO , IPL1, IPL2, LOCK, LOCKE, MDIS, MI,

RST0, RSTI, TA, TBI, TCI, TEA, TIP, TRST, TS and W of R/W.

3. Maximum operating junction temperature (TJ) = +125°. Minimum case operating temperature (TC) = -55°. This device is not

tested at T C = + 125 °. Te sti ng is performed by setting the junction te mp erature TJ = +125°and allowing the case and ambient

temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature.

4. The levels on CDIS, MDIS, and the IPL2-IPL0 signals enable or disable the multiplexed bus mode, data latch enable mode,

and driver impedance selection respectively.

44c TTn Valid to BCLK (Setup) 6 8.5 ns

44d R/W Valid to BCLK (Setup) 6 5 ns

44e SCn Valid to BCLK (Setup) 10 11 ns

45 BCLK to Address SIZn, TTn, R/W, SCn Invalid (Hold) 2 2 ns

46 TS Valid to BCLK (Setup) 5 9 ns

47 BCLK to TS Invalid (Hold) 2 2 ns

49 BCLK to BB High Impedance (68040 Assumes Bus Mastership) 9 9 ns

51 RSTI Valid to BCLK 5 4 ns

52 BCLK to RSTI Invalid 2 2 ns

53 Mode Select Setup to RSTI Negated(4) 20 20 ns

54 RSTI Negated to Mode Selects Invalid(4) 22ns

Table 15. Input AC Timing Specifications (Figure 9 to Figure 15) (Continued)

-55°C ≤ TC ≤ TJmax; 4.75V ≤ VCC ≤ 5.25V unless otherwise specified(1)(2)(3)(4)

Num Characteristic

25 MHz 33 MHz

UnitMin. Max. Min. Max.

TS68040

2116A–HIREL–09/02

Figure 9. Read/Write Timing

Note: Transfer attribute signals UPAN, SIZN, TTN, TMN, TLNN, R/W, LOCK, LOCKE, CIOUT

Table 16. JTAG Timing Application (Figure 16 to Figure 19)

-55°C ≤ TC ≤ TJmax; 4.75V ≤ VCC ≤ 5.25V unless otherwise specified(1)(2)

Num Characteristic Min Max Unit

TCK Frequency 010MHz

1 TCK Cycle Time 100 ns

2 TCK Clock Pulse Width Measured at 1.5V 40 ns

3 TCK Rise and Fall Times 0 10 ns

4TRST

Setup Time to TCK Falling Edge 40 ns

5TRST

Assert Time 100 ns

6 Boundary Scan Input Data Setup Time 50 ns

7 Boundary Scan Input Data Hold Time 50 ns

8 TCK to Output Data Valid 0 50 ns

9 TCK to Output High Impedance 0 50 ns

10 TMS, TDI Data Setup Time 20 ns

11 TMS, TDI Data Hold Time 5 ns

12 TCK to TDO Data Valid 0 20 ns

13 TCK to TDO High Impedance 0 20 ns

24 TS68040 2116A–HIREL–09/02

Notes: 1. All testing to be performed using worst-case test conditions unless otherwise specified.

2. Maximum operating junction temperature (TJ) = +125°. Minimum case operating temperature (TC) = -55°. This device is not

tested at T C = + 125°. Testi ng is p erforme d by s etting the jun ction t empera ture TJ = + 125° and allow ing t he cas e and a mbien t

temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature.

Switching Test Circuit

and Waveforms Figure 10. Address and Data Bus Timing — Multiplexed Bus Mode

Table 17. Boundary Scan Instruction Codes

Bit 2 Bit 1 Bit 0 Instruction Selected Test Data Register Accessed

0 0 0 Extest Bo undary Scan

001 Highz Bypass

0 1 0 Sample/Preload Boundary Scan

0 1 1 DRVCTLT Boundary Scan

1 0 0 Shutdown Bypass

1 0 1 Private Bypass

1 1 0 DRVCTLS Boundary Scan

1 1 1 Bypass Bypass

TS68040

2116A–HIREL–09/02

Figure 11. DLE Timing Burst Access

Figure 12. Bus Arbitration Timing

26 TS68040 2116A–HIREL–09/02

Figure 13. Snoop Hit Timi ng

TS68040

2116A–HIREL–09/02

Figure 14. Snoop Miss Timing

Figure 15. Other Signal Timing

28 TS68040 2116A–HIREL–09/02

Figure 16. Clock Input Timing Diagram

Figure 17. TRST Timing Diagram

Figure 18. Boundary Scan Timing Diagram

TS68040

2116A–HIREL–09/02

Figure 19. Test Access Port Timing Diagram

Functional

Description

Programming Model The TS68040 integrates the functions of the integer unit, MMU, and FPU. As shown in

Figure 20, the re gisters depi cted in the program ming model prov ide access and control

for th e three u nits. Th e registe rs are pa rtition ed into tw o levels of privi lege: use r and

supe rviso r. Us er pr ogram s, ex ecuti ng in the user mode, can only use the resources of

the user model. System software, executing in the supervisor mode, has unrestricted

access to all processor resources.

The integer portion of the user programming model, consisting of 16, general-purpose,

32-bit registers and two control registers, is the same as the user programming model of

the TS680 30. The TS68 040 user prog ramming mo del also inc orporates the TS68882

programming model consisting of eight, floating-point, 80-bit data registers, a floating-

point control register, a floating-point status regi ster, and a floating-point in struction

address register.

The supervisor pr ogramming model is used exclus ively by TS68040 sys tem program-

mers to implement operating system functions, I/O control, and memory management

subsystems. This supervisor/user distinction in the TS68000 architecture was carefully

planned so tha t all application software c an be written to execute in the nonprivileged

user mode and migrate to th e TS68040 from any TS68000 platform witho ut modifica-

tion. Since system software is usually modified by system designers when porting to a

new design, the control features are properly placed in the supervisor program ming

model. For example, the transparent translation r egisters of the TS68040 can only be

read or wr itten by the supervi sor soft ware; the program ming re sources of user app lica-

tion programs are unaffected by the existence of the transparent translation registers

Registers D0-D7 are data registers containing operands for bit and bit field (1- to 32-bit),

byte (8-bi t), word (16-bi t), long-word ( 32-bit), and quad -word (64- bit) operation s. Regis-

ters A0-A6 and the s tack pointer registers (us er, interrupt, and ma ster) are address

regist er s tha t may be used as softw ar e st ac k po inte r s or bas e ad dres s r egi st ers. R egi s-

ter A7 i s the us er stac k poi nter in user mode, and is eithe r the in terrupt or ma ster stack

pointer (A7’ or A7’’) in supervisor mode. In supervisor mode, the active stack pointer

(inte rrupt or master) is sel ected bas ed on a bit i n the stat us regis ter (SR). T he addre ss

30 TS68040 2116A–HIREL–09/02

registers may be used for word and long-word operations, and all of the 16 general-pur-

pose registers (D0-D7, A0-A7 in Figure 20) may be used as index registers.

The eight, 80-bit, floating-point data regis ters (FP0-FP7) are analogous to the integer

data registers (D0-D7) of all TS68000 Family processors. Floating-point data registers

always conta in extended-p recisio n numbers. All external operan ds, regardle ss of the

data forma t, are con verte d to ext ended-pr ecisio n valu es befo re being u sed in any float-

ing-point calculation or stored in a floating-point data register.

The program counter (PC) usually contains the address of the instruction being exe-

cuted by the TS68040. During instruction execution and exception processing, the

processo r au toma tic al ly i nc remen ts the c onte nts o f th e P C o r place s a new va lue in th e

PC, as appr opriate. T he statu s registe r (SR in the supe rvisor program ming mo del) con-

tains the condition codes that reflect the results of a previous operation and can be used

for conditional instruction execution in a program. The lower byte of the SR is accessible

in user mo de as the cond ition code reg ister (CCR). Ac cess to the upper byte of the SR

is restricted to the supervisor mode.

As part of exception processing, the vector number of the exception provides an index

into the exception vector table. The base address of the exception vector table is stored

in the ve ctor ba se regis ter (VBR). The dis placeme nt of an exc eption vector is added to

the value in the VBR when the TS68040 accesses the vector table during exception

processing.

Altern ate func tion c ode regi sters , SFC and DF C (sour ce and de stinati on), contain 3 -bit

function codes. Function codes can be considered extensions of the 32-bit linear

address. Function codes are automatically generated by the processor to select address

spaces for data and program accesses at the user and supervisor modes. The alternate

function code registers are used by certain instructions to explicitly specify the function

codes for vari ous operatio ns. The cache contro l register (CACR ) controls enabl ing of

the on-chip instruction and data caches of the TS68040.

The supervisor root pointer (SRP) and user root pointer (URP) registers point to the root

of the address translation table tree to be used for super visor mode and user mode

accesses. The URP is used if FC2 of the logical address is zero, and the SRP is used if

FC2 is one.

The transl ation control register (TC) ena bles logic al-to-ph ysical addres s translation and

selects ei ther 4K or 8K page sizes. As s hown in Figure 20, there are four transpar ent

translation regis ters - ITT0 and IT T1 for instruction ac cesses and DTT 0 and DTT1 for

data acc esses. T hese regi sters al low portio ns of the log ical ad dress sp ace to be tran s-

parently mapped and accessed without the use of resident descriptors in an ATC. The

MMU status register (MMUSR) contains status inf ormation from the execution o f a

PTEST instruction. The PTEST instruction searches the translation tables for the logical

address as specified by this instruction’s effective address field and the DFC.

The 32-b it floating-po int control re gister (FPCR) contains an exception enab le byte that

enable s disab les traps for each cla ss of floati ng-point excepti ons and a mo de byte tha t

sets the user-sel ectable m odes. The FP CR can b e read or written to by the user and is

cleared by a hardware reset or a restore operation of the null state. When cleared, the

FPCR provides the IEEE 754 standard defaults. The floating-point status register

(FPSR) contains a condition code byte, quotient bits, an exception status byte, and an

accru ed excep tio n byte. A ll b its in t he FPS R can be re ad or wr itten by th e use r. Execu-

tion of most floating-point instructions modifies this register.

TS68040

2116A–HIREL–09/02

For the subset o f the FPU i ns truc tio ns that gen er ate e xception tr ap s, t he 3 2- bit flo ati ng-

point instruction address register (FPIAR) is loaded with the logical address of an

instru ction b efore the instr uctio n is exec uted. T his add ress c an then b e used by a fl oat-

ing-poin t exception h andler to locate a floating-p oint instruct ion that has caused an

exception. The move floating-point data register (FMOVE) instruction (to from the

FPCR, F PSR, or FPIAR) an d the move multi ple data reg isters (FMOVE N) instru ction

cannot gener ate floating-poi nt exceptions; ther efore, these instru ctions do not modify

the FPIAR. Thus, the FMOVE and FMOVEM instructions can be used to read the

FPIAR in the trap handler without changing the previous value.

Figure 20. Programmi ng Mod el

32 TS68040 2116A–HIREL–09/02

Data Types and

Addressing Modes The TS6804 0 suppo rts the basic data types s hown in T able 18. Some data types ap ply

only to the integer unit, some only to the FPU, and some to both the integer unit and the

FPU. In add ition, the ins truction set su pports oper ations on oth er data types such as

memory addresses.

Note: 1. I U = Integer Unit.

The three integer data formats that are commo n to both the integer unit and the FPU

(byte , word, and lo ng word) ar e the sta ndard twos -compl ement dat a format s defined i n

the TS68000 Family architecture. Whenever an integer is used in a floating-point opera-

tion, the integer is automatically converted by the FPU to an extended-precision floating-

point number before being used. The ability to effectively use integers in floating-point

operations saves user memory because an integer representation of a number usually

requires fewer bits than the equivalent floating-point representation.

Single- a nd dou ble -p reci sion fl oati ng-po in t da ta formats a re im pl eme nted i n th e FP U as

defined by the IEEE standard. These data formats are the main floati ng-point formats

and should be used for most calculations involving real numbers.

The ex tended-pr ecision data format is al so in c onfor mance with the IEEE standa rd, b ut

the standard does not specify this format to the bit level as it does for single- and dou-

ble-p recision. Th e memory form at for the F PU consists of 96 bits (thre e long wor ds).

Only 80 bits are actually used; the other 16 bits are reserved for future use and for long-

word alig nment of the floa ting-poin t data structures in memory. T he extended-p recision

format has a 15-bit exponent, a 64-bit mantissa, and a 1-bit mantissa sign. Extended-

precisi on numbers are intended for us e as temporar y variables , intermed iate value s, or

where extra precision is needed.

The TS68040 addressing modes are shown in Table 19. The register indirect address-

ing modes support post-increment, predecrement, offset, and indexing, which are

particularly useful for handling data structures common to sophisticated applications

and high-level languages. The program counter indirect mode also has indexing and off-

set capabilities; this addressing mode is typically required to support position-

indepe ndent s oftwar e. In a ddition to thes e addr essing modes , the TS68040 prov ides

index s izing an d scali ng featu res that enhanc e softw are perf ormance . Data forma ts ar e

suppor ted orthogo nally by all ar ithmeti c operati ons and by all a ppropriat e addressin g

modes.

Table 18. Data Types

Operand Data Type Size Execution Unit (IU(1), FPU) Notes

Bit 1-bit IU

Bit Field 1-32 bits IU Field of consecutive bits

BCD 32 bits IU Packaged: 2 digits byte

Unpacked: 1 digit byt e

Byte Integer 8 bits IU, FPU

Word Integer 16 bits IU, FPU

Long-word Integer 32 bits IU, FPU

Quad-word Integer 64 bits IU Any two data registers

16-byte 128 bits IU Memory-only, aligned 16 -byte boun dary

Single-precision Real 32 bits FPU 1-bit sign, 8-bit exponent, 23-bit mantissa

Double-precision Real 64 bits FPU 1-bit sign, 11-bit exponent, 52-bit mantissa

Extended-precision Real 80 bits FPU 1-bit sign, 15-bit exponent, 64-bit mantissa

TS68040

2116A–HIREL–09/02

Note: DN = Data register, D0-D7

AN = Address register, A0-A7

d8, d16 = A twos-complement or sign-extended displacement; added as part of the effective address calculation;

size is 8 (d8) or 16 (d16) bits; when omitted, assemblers use a value of zero.

Xn = Address or data register used as an index register; form is Xn, SIZE*SCALE, where SIZE is W or L

(indicates index register size) and SCALE is 1, 2, 4 or 8 (index register os multiplied by SCALE); use of

SIZE and or SCALE is optional.

bd = A twos-complement base displacement; when present, size can be 16 or 32 bits.

od = Outer displacement added as part of effective address calculation after any memory indirection; use is

optional with a size of 16 or 32 bits.

PC = Program counter.

(data) = Immediate value of 8, 16 or 32 bits.

( ) = Effective address.

[ ] = Used as indirect address to long-word address.

– Instruction Set Overview

Table 19. Addressing Modes

Addressing Modes Syntax

Date Register Direct

Address R egi ste r Direct Dn

Address R egi ste r Indire ct

Addres s Register Indire ct With Pos tin crement

Address Register Indirect With Predec rem ent

Address R egi ste r Indire ct With Displace me nt

(An)

(d16, An)

Address Register Indirect With Index (8-bit Displacement)

Address Register Indirect With Index (Base Displacement) (d8, An, Xn)

(bd, An, Xn)

Memory Indi rect

Memor y Indirect Postincrement

Memory Indirect Preindexed ([bd, An], Xn, od)

([bd, An, Xn], od)

Program Counter Indirect With Displacement (d16, PC)

Program Counter Indirect With Index

PC Indirect With Index (8-bit Displacement)

PC Indirect With Index (Base Displacement (d8, PC, Xn)

(bd, PC, Xn)

Program Counter Memory Indirect

PC Memory Ind irect Postindexed

PC Memory Indirect Preindexed ([bd, PC], Xn, od)

([bd, PC, Xn], od)

Absolute

Absolute Short

Absolute Long xxx.W

xxx.L

Immediate # (data)

34 TS68040 2116A–HIREL–09/02

The inst ructi on provid ed by the T S68040 are liste d in Ta ble 20. The ins tructi on set has

been tailored to support high-level languages and is optimized for those instructions

most commonly executed (however, all instructions listed are fully supported). Many

instructions operate on bytes, words, and long words, and most instructions can use any

of the addressing modes of Table 19.

Table 20. Instruction Set Summary

Mnemonic Description

ABCD

ADD

ADDA

ADDI

ADDQ

ADDX

AND

ANDI

ASL, ASR

Add Decimal With Extend

Add

Add Address

Add Immediate

Add Quick

Add With Extend

Logical AND

Logical AND Immediate

Arithmetic Shift Left And Right

Bcc

BCHG

BCLR

BFCHG

BFCLR

BFEXTS

BFEXTU

BFFFO

BFINS

BFSET

BFTST

BKPT

BRA

BSET

BSR

BTST

Branch Conditionally

Test Bit And Change

Test Bit And Clear

Test Bit Field And Change

Test Bit Field And Clear

Signed Bit Field Extract

Unsigned Bit Field Extract

Bit Field Find First One

Bit Field Insert

Test Bit Field And Set

Test Bit Field

Breakpoint

Branch

Test Bit And Set

Branch To Subroutine

Test Bit

CAS

CAS2

CHK

CHK2

CINV(1)

CLR

CMP

CMPA

CMPI

CMPM

CMP2

CPUSH(1)

Compare And Swap Operands

Comp are And Swap Dual Op erands

Check Register Against Bounds

Check Register Against Upper And Lower Bounds

Invalida te Cach e Entries

Clear

Compare

Compare Address

Compare Immed iate

Compar e Memor y To Memory

Compare Register Against Upper And Lower Bounds

Push Then Invalidate Cache Entries

DBCC

DIVS, DIVSL

DIVU, DIVUL

Test Condition, Decrement And Branch

Signed Divide

Unsigned Divide

EOR

EORI

EXG

EXT, EXTB

Logical Exclusive OR

Logical Exclus ive OR Immediate

Exchange Registers

Sign Extend

TS68040

2116A–HIREL–09/02

ILLEGAL Take Illegal Instruction Trap

JMP

JSR Jump

Jump To Subroutine

LEA

LINK

LSL, LSR

Load Effectiv e Addre ss

Link And Allocate

Logical Shift Left And Right

MOVE

MOVE16(1)

MOVEA

MOVE CCR

MOVE SR

MOVE USP

MOVEC(1)

MOVEM

MOVEP

MOVEQ

MOVES(1)

MULS

MULU

Move

16-byte Block Move

Move Addre s s

Move Condition Code Register

Move Status Register

Move User S tack Pointer

Move Control Register

Move Peripheral

Move Quick

Move Alternate Address Space

Move Multip ly

Signed Multiply

Unsigned Multiply

NBCD

NEG

NEGX

NOP

NOT

Negate decimal with extend

Negate

Negate with extend

No operation

Logical complement

ORI Logical Inclusive OR

Logical Inclusive OR Immediate

PACK

PEA

PFLUSH(1)

PTEST(1)

Pack BCD

Push Effective Address

Flush Entry(ies) In The ATCs

Test A Logical Addre ss

RESET

ROL, ROR

ROXL, ROXR

RTD

RTE

RTR

RTS

Reset External Devices

Rotate Left And Right

Rotate With Extend Left And Right

Return And Deallocate

Return From Exception

Return And Restore Codes

Return From Subroutine

Table 20. Instruction Set Summary (Continued)

Mnemonic Description

36 TS68040 2116A–HIREL–09/02

Note: 1. TS6840 additions or alterations to the TS68030 and TS68881/TS68882 instructions

sets.

Note: 1. TS6840 additions or alterations to the TS68030 and TS68881/TS68882 instructions

sets.

The TS68040 floating-point instructions, a commonly used subset of the TS68882

instruction set, are implemented in hardware. The remaining unimplemented instruc-

tions are less frequently used and are efficiently emulated in software, maintaining

compatibility with the TS68881/TS68882 floating-point coprocessors.

The TS68 040 instructi on set include s MOVE 16, a new u ser i ns tr uc tio n th at a ll ows hi gh-

speed transfers of 16-byte blocks between external devices such as memory to memory

or coprocessor to memory.

SBCD

Scc

STOP

SUB

SUBA

SUBI

SUBQ

SUBX

SWAP

Substract Decimal With Extend

Set Conditionally

Stop

Subtract

Subtract Address

Subtract Immediate

Subtract Quick

Subtract With Extend

Swap Register Words

TAS

TRAP

TRAPcc

TRAPV

TST

Test Operand And Set

Trap

Trap Conditionally

Trap On Overflow

Trap Operand

UNLK

UNPK Unlink

Unpack BCD

Table 21. Floating-point instructions

Mnemonic Description

FABS(1)

FADD(1)

FBcc

FCMP

FDBcc

FDIV(1)

FMOVE(1)

FMOVEM

FMUL(1)

FNEG(1)

FRESTORE

FSAVE

FScc

FSQRT(1)

FSUB(1)

FTRAPcc

FTST

Floating-point Absolute Value

Floating-point Add

Branch On Floating-point Condition

Floating-point Compare

Floating-point Decrement And Branch

Floating-point Divide

Move Floating-point Register

Move Multiple Floating-point Registers

Floating-point Multiply

Floating-point Negate

Restore Floating-point Internal State

Save Floating-point Internal State

Set According To Floating-point C ondition

Floating-point Square Root

Floating-point Substract

Trap On Floating-point Condition

Floating-point Test

Table 20. Instruction Set Summary (Continued)

Mnemonic Description

TS68040

2116A–HIREL–09/02

Instruction and Data

Caches Studies have shown that typical programs spend much of their execution time in a few

main rou tines o r tight loops. Earlier membe rs of the T S68000 Fa mily took advan tage of

this local ity of reference ph enomenon to vary ing degrees. The TS68040 takes further

advantage of cache technology with its two, independent, on-chip, physical address

space caches, one for instructions and one for data. The caches reduce the processor’s

external bus activity and increase CPU throughput by lowering the effective memory

access time. For a typica l system desi gn, the large ca ches of the TS68 040 yield a very

high hit rate, providing a substantial increase in system performance. Additionally, the

caches are automatically burstfilled from the external bus whenever a cache miss

occurs.

The autonom ous nature of the caches allo ws instruction- stream fetches, dat a-stream

fetches, and a third external access to occur simultaneously with instruction execution.

For example, if the TS68040 requires both an instruction-stream access and an external

peripheral access and if the instruction is resident in the on-chip cache, the peripheral

access pr oceeds unim peded rath er than being queu ed behind the i nstructio n fetch. If a

data operand is also required and if it is resident in the data cache, it can also be

accessed without hindering either the instruction access from its cache or the peripheral

access external to the chip. The parallelism inherent in the TS68040 also allows multiple

instru ctions that do not requir e any external acce sses to e xecu te concur rently while th e

processor is performing an external access for a previous instruction.

Cache Organization The instruction and data c aches are four-way set-associative with 64 sets of four, 16-

byte lines for a total cache storage of 4K bytes each. As shown in Figure 21, each 16-

byte line contains an address tag and state information. State information for each entry

consists of a valid flag for the entire line in both instruction and data caches and write

status for e ac h l ong wo rd i n the data cache . T he wri te sta tus i n the dat a c ac he sig nif ies

whether or no t t he lon g- wor d dat a i s di r ty ( mea nin g t hat the da ta in th e c ac he ha s bee n

modified but has not been written back to external memory) for data in copyback pages.

38 TS68040 2116A–HIREL–09/02

Figure 21. Cache Organization Overview

The caches are accessed by physical addresses from the on-chip MMUs. The transla-

tion of the upper bits of the logical address occurs concurrently with the accesses into

the set array in the cache by the lower address bits. The output of the ATC is compared

with the tag field in the cache to determine if one of the lines in the selected set matches

the translated physical address. If the tag matches and the entry is valid, then the cache

has a hit.

If the cache hits and the access is a read, the appropriate long word from the cache line

is multiplexed onto the appropriate internal bus. If the cache hits and the access is a

write, the data, regardless of size, is written to the appropriate portion of the correspond-

ing longword entry in the cache.

When a da ta cache miss occurs and a previously valid c ache line is nee ded to cache

the new l ine, an y dirt y data in th e old li ne will be intern ally buf fered and copie d back to

memory after the new cache line has been loaded.

Pushing of dirty data can be forced by the CPUSH instruction.

TS68040

2116A–HIREL–09/02

Cachabil it y of data in each mem o ry pa ge is co ntr olled by two bits in the page des crip t or

for each page. Ca chabl e pages may b e either wr ite th rough or copy back, with no w rite-

allocate for misses to write through pages. Non-cachable pages may also be specified

as non- cachable I/O, fo rcing acces ses to these pa ges to occur i n order of instru ction

execution.

Cache Coherency The TS 68040 has th e ability to sn oop the exter nal bus duri ng accesses by other bus

maste rs to mai ntain coherency betwe en the TS68040’ s caches and exte rnal memory

systems. External write cycles are snooped by both the instruction cache and data

cache; whereas, external read cycles are snooped only by the data cache. In addition,

external cycles can be flagged on the bus as snoopable or non snoopable. When an

externa l cyc le is m ar ke d as sn oop abl e, t he bu s s no ope r che ck s the c ac he s f or a coher-

ency conflict based on the state of the corresponding cache line and the type of external

cycle.

Althoug h the inter nal executi on un its a nd th e bus sno oper c ircuit all ha ve acces s to th e

on-chip caches, the snooper has priority over the execution units to allow the snooper to

resolve coherency discrepancies immediately.

Cache Instructions The TS68040 supports the following instructions for cache maintenance. Both instruc-

tions may selectively operate on the data or instruction cache.

CINV: Invalidates a single line, all lines in a physical page, or the entire cache.

CPUSH: Pushes selected dirty data cache lines to memory, then invalidates all selected

lines.

Operand Transfer

Mechanisms The TS68040 external synchronous bus supports multiple masters and overlaps arbitra-

tion with data transfers. The bus is optimized to perform high-speed transfers to and

from an external cache or memory. The data and address buses are each 32 bits wide.

Transfer Types The TS68040 provides two signals (TT1-TT0) that define four types of bus transfers:

normal access, MOVE16 access, alternate access, and interrupt acknowledge access.

Normal accesses identify normal memory references: MOVE16 accesses are memory

accesses by a MOVE16 instruction; and alternate accesses identify accesses to the

undefine d address spac es (functi on code v alues of 0, 3, 4, 7). The interrup t acknowl-

edge access is used to fetch an interrupt vector during interrupt exception processing.

Burst Transfer Operation During burst read write to cache transfers, the values on the address and transfer type

signals do not change; they are the address of the first requested item of the cache line.

When the TS68040 request a burst read transfer of a cache line, the address bus indi-

cates the addr ess of the long word in the line nee ded first, but the memory sys tem is

expected to provide data in the following order (modulo 4): 0, 1, 2, 3 (long-word offsets).

The first address needed may not be from offset 0; nevertheless, all four long words

must be transferred. Burst writes occur in a similar manner.

Bus Snooping Bus snooping ensures that data in main memory is consistent with data in the on-chip

caches. If an alternate bus master is performing a read transfer on the bus and snooping

is enabl ed, and i f the snoop l ogic de termines that the on-chip data cac he has di rty data

(data valid but not consis tent with memory) for this transfer, the memory is prevented

from res pondin g to the read r equest, and the TS68 040 suppl ies the data d irectly to the

master. If t he alternate master is pe r for ming a write tr an sf er on the bus a nd sn oopi ng is

enabled, and if the snooper determines that one of the on-chip caches has a valid line

for this request, then the snooper may either invalidate or update the line as selected by

the snoop control signals.

40 TS68040 2116A–HIREL–09/02

Exception Processing The TS68040 provides the same extensions to the exception stacking p rocess as the

TS6803 0. If the M bi t in th e status r egister is set , the m as ter sta ck poi nte r is u se d for al l

task-re lated ex ceptio ns. When a nontas k-relate d exce ption occ urs (i. e., an i nterrupt),

the M bit is cle ared, and the i nterrupt stac k pointer is used . This feature allows a task’s

stack area to be carried within a single processor control block, and new tasks may be

initiated by simply reloading the master stack pointer and setting the M bit.

The externally generated exceptions are interrupts, bus errors, and reset conditions.

The interrupts are requests from external devices for processor action; whereas, the bus

error and res et signals are used for ac cess control and proces sor initialization. T he

internally generated exceptions come from instructions, address errors, tracing, or

breakpoints. The TRAP, TRAPcc, TRAPVcc, FTRAPcc , CHK, CHK2, and DIV instruc-

tions c an a ll gen er ate ex ce pti ons as p ar t of thei r in str uc ti on e xe cut io n. Tr acing behav es

like a very high-priority, internally generated interrupt whenever it is processed. The

other internally generated exceptions are caused by unimplemented floating-point

instruc tions, i llegal inst ructions , instructi on fetche s from o dd address es, and p rivilege

violations. Finally, the MMU can generate exceptions, for access violations and for when

invalid descriptors are encountered during table searches.

Exception processing for the TS68040 occurs on the following sequence:

1. an internal copy is made of the status register,

2. the vector number of the exception is determined,

3. current processor status is saved,

4. the exception vector offset is determined by multiplying the vector number by

four.

This offset is then added to the contents of the VBR to determine the memory address

of the exception vector. The instruction at the address given in the exception vector is

fetched, and normal instruction decoding and execution is started.

Memory Management

Units The full address ing r ange of t he TS6804 0 is 4G bytes ( 4,294,9 67,296 b ytes) . However ,

most TS68040 systems implement a much smaller physical memory. Nonetheless, by

using virtual memory techniques, the system can be made to appear to have a full

4G bytes of ph ysic al mem ory availa ble to each user program . The in depende nt inst ruc-

tion and data MMUs fully support demand paged virtual-memory operating systems with

either 4K or 8K page sizes. In addition to its main function of memory management,

each MMU protects supervisor areas from accesses by user programs and also pro-

vides write protection on a page-by-page basis. For maximum efficiency, each MMU

operates in parallel with other processor activities.

Translation Mechanism Because logical-to-physical address translation is one of the most frequently executed

opera tions of the TS68 040 MMUs, th is task ha s bee n optimiz ed. Each MM U in itiates

address translation by se arching for a descr iptor containi ng the address tr anslation

informa tion in th e ATC. If the desc riptor does not reside in the ATC, the n the MMU pe r-

forms external bus cycles via the bus controller to search the translation tables in

physical memory. After being located, the page descriptor is loaded into the ATC, and

the add ress is cor rectly tr anslat ed for the acce ss, prov ided no exc eption c onditio ns are

encountered.

TS68040

2116A–HIREL–09/02

Address Translation Cache An integ ral part of th e trans lation fu nction pre viously descr ibed is the dual cac he mem-

ory that stores recentl y used logical-to-phys ical address translation infor mation (page

descriptors) for instruction and date accesses. These caches are 64-entry, four-way, set

associative. Each ATC compare the logical address of the incoming access against its

entries. If one of the entries matches, there is a hit, and the ATC sends the physical

address to the bus controller , which then starts the external bus cycle (provided there

was no hit in the corresponding cache for the access).

Translation Tables The translation tables of the TS68040 have a three level tree structure and reside in

main me mory. S ince onl y a po rtion of the c omple te tree nee ds to e xist at an y one tim e,

the tree structure min imizes the amount of m emory necessary to set up the tables for

most programs. As shown in Figure 20, either the user root pointer or the supervisor root

pointer points to the first level table, depending on the values of the function code for an

access . Table ent ries at the se cond level of the tree (p ointer tabl es) contai n pointers to

the third level (page tables). Entries in the page tables contain either page descriptors or

indirect pointers to page descriptors. The mechanism for performing table search opera-

tions uses portions of the lo gical addres s (as indic es) at each lev el of the sear ch. All

addresses in the translation table entries are physical addresses.

Figure 22. Translation Table Structure

There are two variations of table searches for both 4K and 8K page sizes: normal

searches and indirect searches . An indirect search differ s in that the entry in the third

level page tabl e cont ains a p ointe r to a page des cripto r rat her than the p age descr iptor

itself.

Entries in the trans l ati on tabl es c on tai n c on tro l and s tatu s in format ion on a ddi tio n to th e

physical addr ess in for ma tio n. Contr ol bits spe ci fy wri te protec ti on, li mit acc es s to supe r-

visor only, and determine cachability of data in each memory page. Each page

descriptor also has two user-programmable bits that appear on the UPA0 and UPA1 sig-

nals during an external access for use as address modifier bits.

42 TS68040 2116A–HIREL–09/02

A global bit can be set in each page descriptor to prevent flushing of the ATC entry for

that page by some PFLUSH instruction variants, allowing system ATC entries to remain

resident during task swaps. If these special PFLUSH instructions are not used, this bit

can be user define d. The MMUs automaticall y maintain acces s history information for

the pages by updating the used (U) and modified (M) status bits.

MMU Instructions The MMU instr ucti ons supp orted by the TS68040 are as follows:

PFLU SH: Allows flushing o f either sel ected AT C entries by fu nction c ode and lo gical

address or the entire ATCs.

PTEST: Takes an address and function code and searches the translation tables for the

corresponding entry, which is then loaded into the ATC. The results of the searc h are

available in the MMU status register and are often useful in determining the cause of a

fault.

All of the TS68040 MMU instructions are privileged and can only be executed from the

supervisor mode.

Transparent Translation Four t ra nspar en t tr ansl ati on r e gist ers , tw o ea ch for ins tr uct io n a nd d ata ac ce ss es, h av e

been provided on the TS68040 MMU to allow portions of the logical address space to be

transparently mapped and accessed without the need for corresponding entries resident

in the ATC. Each register can be used to define a range of logical addresses from

16M bytes to 4G bytes with a base addr ess and a mask. All addresses within thes e

ranges are not mapped, and are optionally protected against user or supervisor

access es and wr ite acce sses. Logic al addre sses in the se areas become the physi cal

addresses for memory access. The transparent translation feature allows rapid move-

ment of large blocks of data in memory or I/O space without disturbing the context of the

on-chip ATCs or incurring delays associated with translation table searches.

Preparation For

Delivery

Packaging Microcircuits are prepared for d elivery in accordance with MIL-M-38510 or Atmel

standard.

Certific ate of Compl iance Atmel offers a certificate of compliances with each shipment of parts, affirming the prod-

ucts are in co mpliance ei ther with MIL-ST D-883 or Atme l standard and guarantyi ng the

parameters not tested at temperature extremes for the entire temperature range.

Handling MOS devices must be handled with certain precautions to avoid damage due to accu-

mulation of static charge. Input protection devices have been designed in the chip to

minimize the effect of this static buildup. However, the following handling practices are

recommended:

a) Devices should be handled on benches with conductive and grounded surfaces.

b) Ground test equipment, tools and operator.

c) Do not handle devices by the leads.

d) Store devices in conductive foam or carriers.

e) Avoid use of plastic, rubber, or silk in MOS areas.

f) Maintain relative humidity above 50 percent if practical.

TS68040

2116A–HIREL–09/02

Package Mechanical

Data

179 pins – PGA

Dim

Millimeters Inches

Min Max Min Max

A 46.863 47.625 1.845 1.875

B 46.863 47.625 1.845 1.875

C 2.3876 1.875 0.094 0.116

D 4.318 4.826 0.170 0.190

E 1.143 1.4 0.045 0.055

F 1.143 1.4 0.045 0.055

G 2.54 BSC 0.100 BSC

H(1) 0.432 0.483 0.017 0.019

Note: 1. For untinned leads (gold)

44 TS68040 2116A–HIREL–09/02

196 pins – Tie Bar CQFP

Cavity Up (on request)

Dim Millimeters Inches

A 3.30 max 0.130 max

B 0.23 +0.05

0.23 -0.038 0.009 +0.002

0.009 -0.015

C 0.635 typ. .025 typ.

D1 33.91 ± 0.25 1.335 ± 0.01

J 0.89 ± 0.1 3 0.03 5 ± 0.0 05

L 63.5 ± 0.5 1 2.5 ± 0.02

TS68040

2116A–HIREL–09/02

196 pins – Gullwing

CQFP cavity up

* Reduce pin count shown for clarity, 49 pins per side

Symbol Millimeters Inches

A 4.19 ma x 0.165 max

A1 0.673 ± 0.2 .0265 ±.008

b0.23 +0.05

0.23 -0.038 .009 +.002

.009 -.0015

c0.127 +0.05 .005 +.002

0.127 -0. 025 .005 -.001

D/E 33.91 ±0.25 1.335 ±.01

e .635 BSC .025 BSC

e1 30.4 8 ±0.13 1.2 ±.005

HD/HE 38.8 ±0.18 1.528 ±.007

L 0.813 ±0.2 .032 ±.008

N 196 196

R 0 .55 ±0.2 5 .022 ±.01

R1 0.23 min .009 min

46 TS68040 2116A–HIREL–09/02

Ordering Information

MIL-STD-883 C and

Internal Standard

Notes: 1. On request.

2. Standard process.

3. Non request for small quantity.

DESC Drawing 5962-93143

Device

Temperature range:

M: Tc = -55; Tj = +125°C

V: Tc = -40; Tj = +110°C

Package:

F: CQFP/Gullwing leads

R: PGA

FT: CQFP Flat tie-bar(3)

Standard lead finish

Gold

TS68040 MR1B/C25 A

Operating frequency:

25: 25 MHz

33: 33 MHz

Revision level

Screening level:

B/C: MIL-STD-883, class B

D/T: Internal standard with burn-in

U: Upscreening

U/T: Upscreening + burn-in

___: Internal standard

Lead finish:

1: Hot solder dip(1)

__: Gold(2)

Device

DESC Screening

Speed:

01: 25 MHz

02: 33 MHz

TS68040 DESC 01 XA

Lead finish:

A: Hot solder dip

C: Gold

Package:

X: PGA

Y: CQFP Flat tie-bar

Z: CQFP Gullwing leads

Revision level

TS68040

2116A–HIREL–09/02

Detailed TS68 04 0 Part

List

Hi-REL Product

Commercial Atmel

Part Number Norms Package Temperature range (°C) Frequency

(MHz) Drawing number

TS68040MRB/C25A MIL-STD-883 PGA 179 TC = -55/+TJ = +125 25 Atmel datasheet

TS68040MRB/C33A MIL-STD-883 PGA 179 TC = -55/+TJ = +125 33 Atmel datasheet

TS68040MFB/C25A MIL-STD-883 CQFP 196 TC = -55/+TJ = +125 25 Atmel datasheet

TS68040MFB/C33A MIL-STD-883 CQFP 196 TC = -55/+TJ = +125 33 Atmel datasheet

TS68040DESC01XAA DESC PGA 179 tin TC = -55/+TJ = +125 25 5962-9314301MXA

TS68040DESC02XAA DESC PGA 179 tin TC = -55/+TJ = +125 33 5962-9314302MXA

TS68040DESC01XCA DESC PGA 179 gold TC = -55/+TJ = +125 25 5962-9314301MXC

TS68040DESC02XCA DESC PGA 179 gold TC = -55/+TJ = +125 33 5962-9314302MXC

TS68040DESC01YCA DESC CQFP 196 ti e

bar gold TC = -55/+TJ = +125 25 5962-9314301MYC

TS68040DESC02YCA DESC CQFP 196 ti e

bar gold TC = -55/+TJ = +125 33 5962-9314302MYC

TS68040DESC01ZAA DESC CQFP 196

gullwing tin TC = -55/+TJ = +125 25 5962-9314301MZA

TS68040DESC01ZCA DESC CQFP 196

gullwing gold TC = -55/+TJ = +125 25 5962-9314301MZC

TS68040DESC02ZAA DESC CQFP 196

gullwing tin TC = -55/+TJ = +125 33 5962-9314302MZA

TS68040DESC02ZCA DESC CQFP 196

gullwing gold TC = -55/+TJ = +125 33 5962-9314302MZC

TS68040MFB/C25A MIL-STD-883 CQFP 196 TC = -55/+TJ = +125 25 Atmel datasheet

TS68040MFB/C33A MIL-STD-883 CQFP 196 TC = -55/+TJ = +125 33 Atmel datasheet

TS68040MRD/T25A BURN IN PGA 179 TC = -55/+TJ = +125 25 Atmel datasheet

TS68040MRD/T33A BURN IN PGA 179 TC = -55/+TJ = +125 33 Atmel datasheet

TS68040MFD/T25A BURN IN CQFP 196 TC = -55/+TJ = +125 25 Atmel datasheet

TS68040MFD/T33A BURN IN CQFP 196 TC = -55/+TJ = +125 33 Atmel datasheet

48 TS68040 2116A–HIREL–09/02

Note: FT: available on request.

Standard Product

Commercial Atmel

Part Number Norms Package Tem p erat ur e Ra nge (°C ) Frequency

(MHz) Drawing Number

TS68040VR25A Atmel standard PGA 179 TC = -40/+TJ = +110 25 Atmel datasheet

TS68040VR33A Atmel standard PGA 179 TC = -40/+TJ = +110 33 Atmel datasheet

TS68040MR25A Atmel standard PGA 179 TC = -55/+TJ = +125 25 Atmel datasheet

TS68040MR33A Atmel standard PGA 179 TC = -55/+TJ = +125 33 Atmel datasheet

TS68040VF25A Atmel standard CQFP 196 TC = -40/+TJ = +110 25 Atmel datasheet

TS68040VF33A Atmel standard CQFP 196 TC = -40/+TJ = +110 33 Atmel datasheet

TS68040MF25A Atmel standard CQFP 196 TC = -55/+TJ = +125 25 Atmel datasheet

TS68040MF33A Atmel standard CQFP 196 TC = -55/+TJ = +125 33 Atmel datasheet

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2116A–HIREL–09/02 0M

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