7-494
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD4099BMS
CMOS 8-Bit Addressable Latch
Features
• High Voltage Type (20V Rating)
• Serial Data Input
• Active Parallel Output
• Storage Register Capability
• Master Clear
• Can Function as Demultiplexer
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Multi-Line Decoders
• A/D Converters
Description
CD4099BMS 8-bit addressable latch is a serial input, parallel
output storage register that can perform a variety of functions.
Data are inputted to a particular bit in the latch when that bit
is addressed (by means of inputs A0, A1, A2) and when
WRITE DISABLE is at a low level. When WRITE DISABLE is
high, data entry is inhibited; however, all 8 outputs can be
continuously read independent of WRITE DISABLE and
address inputs.
A master RESET input is available, which resets all bits to a
logic “0” level when RESET and WRITE DISABLE are at a
high level. When RESET is at a high level, and WRITE DIS-
ABLE is at a low level, the latch acts as a 1 of 8 demulti-
plexer; the bit that is addressed has an active output which
follows the data input, while all unaddressed bits are held to
a logic “0” level.
The CD4099BMS is supplied in these 16-lead outline packages:
Braze Seal DIP H4X
Frit Seal DIP H1F
Ceramic Flatpack H6W
December 1992
File Number 3333
Pinout
CD4099BMS
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q7
RESET
DATA
WRITE DISABLE
A0
A1
VSS
A2
VDD
Q5
Q4
Q3
Q2
Q1
Q0
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Q6
Q7
14
13
12
11
10
9
15
1
4
3
DECODER
DATA
WRITE DISABLE
2
RESET
VDD = 16
VSS = 8
A2
A1
A0
7
6
58
8 LATCHES
7-495
Specifications CD4099BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K). . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . .Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-10µA
2 +125oC - 1000 µA
VDD = 18V, VIN = VDD or GND 3 -55oC-10µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >
VDD/2 VOL <
VDD/2 V
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low
(Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
Input Voltage High
(Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
Input Voltage Low
(Note 2) VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC- 4 V
Input Voltage High
(Note 2) VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC11 - V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
7-496
Specifications CD4099BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Propagation Delay
Data to Output TPHL1
TPLH1 VDD = 5V, VIN = VDD or GND 9 +25oC - 400 ns
10, 11 +125oC, -55oC - 540 ns
Propagation Delay
Write Disable to Output TPHL2
TPLH2 VDD = 5V, VIN = VDD or GND 9 +25oC - 400 ns
10, 11 +125oC, -55oC - 540 ns
Propagation Delay
Reset to Output TPHL3 VDD = 5V, VIN = VDD or GND 9 +25oC - 350 ns
10, 11 +125oC, -55oC - 473 ns
Propagation Delay
Address to Output TPHL4
TPLH4 VDD = 5V, VIN = VDD or GND 9 +25oC - 450 ns
10, 11 +125oC, -55oC - 608 ns
Transition Time TTHL
TTLH VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
10, 11 +125oC, -55oC - 270 ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA
+125oC - 150 µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA
+125oC - 300 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA
+125oC - 600 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,
-55oC-50mV
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,
-55oC-50mV
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,
-55oC4.95 - V
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,
-55oC9.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
-55oC - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -1.6 mA
7-497
Specifications CD4099BMS
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
-55oC - -4.2 mA
Input Voltage Low VIL VDD = 10V, VOH > 9V , VOL < 1V 1, 2 +25oC, +125oC,
-55oC-3V
Input Voltage High VIH VDD = 10V, VOH > 9V , VOL < 1V 1, 2 +25oC, +125oC,
-55oC+7 - V
Propagation Delay
Data to Output TPHL1
TPLH1 VDD = 10V 1, 2, 3 +25oC - 150 ns
VDD = 15V 1, 2, 3 +25oC - 100 ns
Propagation Delay
Write Disable to Output TPHL2
TPLH2 VDD = 10V 1, 2, 3 +25oC - 160 ns
VDD = 15V 1, 2, 3 +25oC - 120 ns
Propagation Delay
Reset to Output TPHL3 VDD = 10V 1, 2, 3 +25oC - 160 ns
VDD = 15V 1, 2, 3 +25oC - 130 ns
Propagation Delay
Address to Output TPHL4
TPLH4 VDD = 10V 1, 2, 3 +25oC - 200 ns
VDD = 15V 1, 2, 3 +25oC - 150 ns
Transition Time TTHL
TTLH VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns
Minimum Hold time Data
to Write Disable TH VDD = 5V 1, 2, 3 +25oC - 150 MHz
VDD = 10V 1, 2, 3 +25oC - 75 MHz
VDD = 15V 1, 2, 3 +25oC - 50 MHz
Minimum Data Setup
Time Data to Write
Disable
TS VDD = 5V 1, 2, 3 +25oC - 100 ns
VDD = 10V 1, 2, 3 +25oC - 50 ns
VDD = 15V 1, 2, 3 +25oC - 35 ns
Minimum Pulse Width
Data TW VDD = 5V 1, 2, 3 +25oC - 200 ns
VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns
Minimum Pulse Width
Address TW VDD = 5V 1, 2, 3 +25oC - 400 ns
VDD = 10V 1, 2, 3 +25oC - 200 ns
VDD = 15V 1, 2, 3 +25oC - 125 ns
Minimum Pulse Width
Reset TW VDD = 5V 1, 2, 3 +25oC - 150 ns
VDD = 10V 1, 2, 3 +25oC - 75 ns
VDD = 15V 1, 2, 3 +25oC - 50 ns
Input Capacitance CIN Any inputs 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC-25µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
7-498
Specifications CD4099BMS
N Threshold Voltage
Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage
Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >
VDD/2 VOL <
VDD/2 V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL
TPLH VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x
+25oC
Limit
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER SYMBOL DELTA LIMIT
Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP MIL-STD-883
METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS MIL-STD-883
METHOD
TEST READ AND RECORD
PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
7-499
Specifications CD4099BMS
Logic Diagram
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION OPEN GROUND VDD 9V ± -0.5V
OSCILLATOR
50kHz 25kHz
Static Burn-In 1
Note 1 1, 9-15 2-8 16
Static Burn-In 2
Note 1 1, 9-15 8 2-7, 16
Dynamic Burn-
In Note 1 - 5-8 16 1, 9-15 2, 4 3
Irradiation
Note 2 1, 9-15 8 2-7, 16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
A0
A1 A2 LATCH
0
D
WD
R
9Q0
A0
A1 A2 LATCH
1
D
WD
R
10Q1
A0
A1 A2 LATCH
2
D
WD
R
11 Q2
A0
A1 A2 LATCH
3
D
WD
R
12Q3
A0
A1 A2 LATCH
4
D
WD
R
13 Q4
A0
A1 A2 LATCH
5
D
WD
R
14Q5
A0
A1 A2 LATCH
6
D
WD
R
15Q6
A0
A1 A2 LATCH
7
D
WD
R
1Q7
A0
A0
A0 5*
A1
A1
A1 6*
A2
A2
A2 7*
DDATA 3*
WDWRITE DISABLE 4*
RRESET 2*
VSS = 8
VDD = 16
R
ADDRESS
WD
DATA p
n
p
n
QVDD
VSS
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
7-500
CD4099BMS
FIGURE 2. DEFINITION OF WRITE DISABLE ON TIME
FIGURE 3. MASTER TIMING DIAGRAM
FIGURE 4. 1 OF 16 DECODER/DEMUL TIPLEXER FIGURE 5. MULTIPLE SELECTION DECODING - 4 x 4 CROSSPOINT SWITCH
70%
30%
70%
30%
70%
tW
A0
A1
A2
WD
MODE SELECTION
WD R ADDRESSED
LATCH UNADDRESSED
LATCH
0 0 Follows Data Holds Previous
State
0 1 Follows Data Reset to “0”
(Active High 8-Channel Demultiplexer)
1 0 Holds Previous State
1 1 Reset to “0” Reset to “0”
WD = Write Disable R = Reset
tW
8
tW
4
tS
6
tH
7
tW
5
tP
2
tP
3
tP
1
tP
9
A0, A1, A2
WRITE DISABLE
DATA
RESET
Q0
Q7
tP
Q7 tPtP
A0
A1
A2
A3
DATA IN
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0A0
A1
A2
WD
DATA
CD4099BMS
9
10
11
12
13
14
15
1
DO 9
DO 10
DO 11
DO 12
DO 13
DO 14
DO 15
DO 16
5
6
7
4
3
2
VDD
*
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0A0
A1
A2
WD
DATA
CD4099BMS
9
10
11
12
13
14
15
1
DO 1
DO 2
DO 3
DO 4
DO 5
DO 6
DO 7
DO 8
5
6
7
4
3
R
2
VDD
R
*1/6 CD4069
Q0
Q1
R
WD
D0
1
2
3
X
IN/OUT
0123
Y
IN/OUT
1/4 CD4016
S1 S2S0
S5
CD4099BMS
Q15
R
WD
D
CD4099BMS
DATA
A0
A1
A2
A3
WD
WD
7-501
CD4099BMS
FIGURE 6. A/D CONVERTER
Typical Performance Characteristics
FIGURE 7. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS FIGURE 8. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
146129875
VDD
13
1 2 3
C R R-C
AST OSC
OUT
CD4047
330Ω
100
470pF
4
1
23
*
6
54
*
CD4001
*HYCOMP HC210SLD-2R
**OR EQUIVALENT
8
910
*
13
12 11
*
t2 16151092
VDD
3 4 5
Q1A Q2A Q3A
CLOCK RCD4520
1
5 6 7
7
Q7
WD RCD4099BMS 2
Q6Q5Q4Q3Q2Q1Q0
4
DATA
3
A2A1A0
1 4 82 3 5 6 7
R2R
LADDER NETWORK**
131211109
16
OUT
LSB
CD4099BMS
OUTPUTS
TO DISPLAY
MSB
CA3130
+
-
3
2
8
451
10kΩ
56pF
100
kΩ
6
VDD
10kΩ
7
ANALOG
IN
START
CONVERSION
t1
(t1 < t2) kΩ
912 110 11 13 14 15
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLT AGE (VGS) = 15V
0 5 10 15
15
10
5
20
25
30
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLT AGE (VGS) = 15V
0 5 10 15
7.5
5.0
2.5
10.0
12.5
15.0
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
7-502
CD4099BMS
FIGURE 9. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS FIGURE 10. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 11. TYPICAL PROPAGATION DELAY TIME (DATA TO Qn)
vs LOAD CAPACITANCE FIGURE 12. TYPICAL TRANSITION TIME vs LOAD
CAPACITANCE
FIGURE 13. TYPICAL DYNAMIC POWER DISSIPATION vs ADDRESS CYCLE TIME
Typical Performance Characteristics (Continued)
-10V
-15V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLT AGE (VGS) = -5V
0
-5
-10
-15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-20
-25
-30
0-5-10-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T A) = +25oC0
-5
-10
-15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 0-5-10-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
GATE-TO-SOURCE VOLT AGE (VGS) = -5V
AMBIENT TEMPERATURE (T A) = +25oC
LOAD CAPACITANCE (CL) (pF)
0
SUPPLY VOLT AGE (VDD) = 5V
10V
15V
50
PROPAGATION DELAY TIME (tPLH, tPHL) (ns)
150
250
100
200
300
10 20 30 40 50 60 70 80 90 100
AMBIENT TEMPERATURE (T A) = +25oC
LOAD CAPACITANCE (CL) (pF)
0 40 60 80 10020
0
50
100
150
200
SUPPLY VOLT AGE (VDD) = 5V
10V
5V
TRANSITION TIME (tTHL, tTLH) (ns)
SUPPLY VOLTAGE (VDD) = 15V
10V
5V
10V
8642
ADDRESS CYCLE TIME (µs)
100101
6
4
2
101
100
POWER DISSIPATION PER GATE (PD) (µW)
8642 1028642 1038642 1048642 105
6
4
2
102
6
4
2
103
6
4
2
104
6
4
2
105
6
4
2AMBIENT TEMPERATURE (TA) = +25oC
CL = 50pF
LOAD CAPACITANCE (CL ) = 15pF
503
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
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Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
CD4099BMS
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ−14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
File Number
