CY62256V25L-100ZC - Cypress Semiconductor

PRELIMINARY

32K x 8 Static RAM

ax id: 1069

CY62256V

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

March 1996 – Revised April 1998

Features

• Low voltage range:

—2.7V − 3.6V (6225 6V)

—2.3V − 2.7V (62256V25)

—1.6V − 2.0V (62256V18)

• Low active power and standby power

• Easy memory expansi on with CE and OE features

• TTL-compatible inputs and outputs

• Autom atic power-down wh en deselected

• CMOS for optimum speed/power

Functional Description

The CY622 56V fami ly i s com posed of t hree hi gh-per fo rmance

CMOS static RAM’ s organized as 32,768 words by 8 bits. Easy

memory expansi on is provided by an active LOW chip enable

(CE) and act iv e LO W output enabl e ( OE) and thr ee-sta te driv-

ers. These devices have an automatic power-down feature,

reducing the power consumption by over 99% when desel ect-

ed. The CY62256V family is available in the standard

450-mil-wide (300-mil body width) SOIC, TSOP, and reverse

TSOP packages.

An active LOW write enable signal (WE) controls the writ-

ing/reading oper ation of t he memory . When CE and WE inputs

are both LOW, data on the eight data input/output pins (I/O0

throug h I/O7) is writt en int o the memory l ocati on addre ssed b y

the address present on the address pins (A0 through A14).

Reading the device is accomplished by selecting the device

and enabling the outputs, CE and OE active LOW, while WE

remains inactive or HIGH. Under these conditions, the con-

tents of the location addressed by the information on address

pins are present on the eight data input/output pins.

The inpu t/output pins remain in a hi gh-impedance state u nless

the chip is selected, outputs are enabled, and write enable

(WE) is HIGH .

COLUMN

DECODER

INPUTBUFFER

POWER

DOWN

I/O0

I/O1

I/O2

I/O3

14 15

Top View

SOIC

GND

A10

A11

A12

A13

VCC

I/O7

I/O6

I/O5

I/O4

A14

I/O0

I/O1

I/O2

I/O3

512x512

ARRA

I/O7

I/O6

I/O5

I/O4

A10

C62256V–1

C62256V–2

510

VCC

I/O7

I/O6

I/O5

GND

I/O2

I/O1

I/O4

I/O0

A14

A10

A11 A13

A12

C62256V–3

I/O3

510

VCC

I/O7

I/O6

I/O5

GND

I/O2

I/O1

I/O4

I/O0

A14

A10

A11 A13

A12

C62256V–4

I/O3

TSOP I

Top Vie w

(no t to sc al e)

TSOP I

Top View

(not to scale)

Reverse Pinout

LogicBlock Diagram Pin Configurations

CY62256V

PRELIMINARY

Maximum Ratings

(Above which the useful l ife may be impaired. For user gui de-

li nes, not tes ted.)

Storage Temperature ....................................−65°C to + 150°C

Ambient Tempera ture with

Power Applied..................................................0°C to + 70°C

Supply Voltage to Ground Potential

(Pin 28 to Pin 14)................................................−0.5V to + 4.6V

DC Voltag e Appli ed to Outputs

in High Z State[1] ....................................... −0.5V to VCC + 0.5V

DC Input Voltage[1].................................... −0.5V to VCC + 0.5V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage .......................................... >2001V

(per MIL- STD-883, Method 3015 )

Latch-Up Current........... ....... .. ....... ....... ...... .. ....... ... >200 mA

Operating Range

Range Ambient Temperature VCC

Commercial 0°C to +70°C 1.6V to 3.6V

Industrial −40°C to +85°C 1.6V to 3.6V

Note:

1. VIL (min.) = -2.0V for pulse durations of less than 20 ns.

Pr oduc t Portfolio

Product Vcc Range Speed

Power Dissipation ( LL Devices)

Operating(Icc)Standby (ISB2)

Min. Typ. Max. Typical Maximum Typical Maximum

CY62256V 2.7V 3.0 3.6V 70 ns 11 m A 30 m A 0.1 uA 5 uA

CY62256V25 2.3V 2.5V 2.7V 100 ns 9 mA 15 m A 0.1 uA 4 uA

CY62256V18 1.6V 1.8V 2.0V 200 ns 5 mA 10 m A 0.1 uA 3 uA

Electrical Characteristics Ov er the Operating Range

Test Conditions

CY62256V-70

Parameter Description Min. Typ.[2] Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = −1.0 mA 2.4 V

VOL Output LOW Voltage VCC = Min., I OL = 2.1 mA 0.4 V

VIH Input HIGH Voltage 2.2 VCC

+0.3V V

VIL Input LOW Voltage −0.5 0.8 V

IIX Input Load Current GND < V I < V CC −1+1 uA

IOZ Output Leakage Current GND < V O < VCC, Output Disabled −1+1 uA

ICC VCC O perating Supply

Current VCC = Max., IOUT = 0 m A,

f = fMAX = 1/tRC Com’l Std/L

/LL 11 30 mA

ISB1 Automatic CE Po wer-Down

Current — TTL I nputs Max. VCC, CE > VIH, VIN > VIH

or V IN < VIL, f = f MAX Com’l Std/L

/LL 100 300 uA

ISB2 Automatic CE

Po wer-Down Current—

CMOS Inputs

Max. VCC, C E > VCC - 0.3V

VIN > VCC - 0.3V or VIN < 0.3V ,

f = 0

Com’l Std/ L 0.1 50 uA

LL 5 uA

Ind’l LL 10 uA

Electrical Characteristics Ov er the Operating Range

CY62256V25-100

Parameter Description T est Conditions Min. Typ.[2] Max. Unit

VOH Output HIGH Volta ge VCC = Min., IOH = −0.1 mA 2 V

VOL O utput LOW Voltage VCC = Min., IOL = 0.1 m A 0.4 V

VIH Input HIGH Vol tage 1.7 Vcc +

0.3V V

VIL Input LOW Voltage −0.3 0.7 V

IIX Input Load Current GND < V I < V CC −1+1 uA

CY62256V

PRELIMINARY

IOZ Output Leakage Cur-

rent GND < V O < VCC, Output Disabled −1+1 uA

ICC VCC O perating Supply

Current VCC = Max., IOUT = 0 mA,

f = f MAX = 1/tRC Com’l Stnd/L

/LL 14 23 mA

ISB1 Automat ic CE Pow-

er-Down Current —

TTL In puts

Max. VCC, CE > VIH, VIN > VIH

or V IN < VIL, f = f MAX Com’l Stnd/L

/LL 75 225 uA

ISB2 Automatic CE

Power-Down Current

— CMOS Inputs

Max. VCC, C E > V CC − 0.3V

VIN > VCC - 0.3V or VIN < 0.3V ,

f = 0

Com’l Stnd/L 0.1 40 uA

LL 4 uA

Ind’l LL 8 uA

Electrical Characteristics Ov er the Operating Range

CY62256V18-200

Parameter Description T est Conditions Min. Typ.[2] Max. Unit

VOH Output HIGH Volta ge VCC = Min., IOH = −0. 1 m A 0.8*Vcc V

VOL O utput LOW Voltage VCC = Min., IOL = 0.1 mA 0.2 V

VIH Input HIGH Vol tage 0.7*Vcc VCC

+0.3V V

VIL Input LOW Voltage −0.5 0.2*Vcc V

IIX Input Load Current GND < VI < V CC −1+1 uA

IOZ Output Leakage

Current GND < VO < V CC, Output Disabled −1+1 uA

ICC VCC O perating Supply

Current VCC = M ax., I OUT = 0 mA,

f = fMAX = 1/tRC Com’l Stnd/L

/LL 10 17 mA

ISB1 Automat ic CE Pow-

er-Down Current— TTL

Inputs

Max. VCC, CE > VIH,

VIN > V IH or VIN < V IL, f = fMAX Com’l Stnd/L

/LL 56 165 uA

ISB2 Automatic CE

Power-Down Current—

CMOS Inputs

Max. VCC, CE > VCC - 0.3V

VIN > VCC - 0.3V or VIN < 0.3V ,

f = 0

Com’l Stnd/L 0.1 30 uA

LL 3 uA

Ind’l LL 6 uA

Electrical Characteristics Over the Operating Range (continue d)

CY62256V25-100

Parameter Description T est Conditions Min. Typ.[2] Max. Unit

Capacitance[3]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = 3.0V 6pF

COUT Output Capacitance 8 pF

Notes:

2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = Vcc Typ., TA = 25°C, and tAA=70ns.

3. Tested initially and after any design or process changes that may affect these parameters.

CY62256V

PRELIMINARY

AC Test Loads a nd Waveforms

Vcc

OUTPUT

50 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10% 90%

10%

<5ns <5ns

OUTPUT Vth

Equivalent to:THÉ

VENIN EQUIVALENT

ALL INPUT PULSES

C62256V–5 C62256V–6

Rth

A C Test Load

Vcc 3.3 V 2.5V 1.8V

R1 1103 16.6K 13.6K

R2 1554 15.4K 11.4K

RTH 645 8K 6.2K

VTH 1.75V 1.2V 0.82V

Data Retention Characteristics (Over the Operating Range)

Parameter Description Conditions[4] Min. Typ.[2] Max. Unit

VDR VCC for Data Retentio n 1.4 V

ICCDR Dat a Retention Current Coml Stnd/L VCC = 1.6

CE > VCC - 0.3V,

VIN > V CC - 0.3V or

VIN < 0.3V 0.1

30 uA

LL 3 uA

Ind. LL 6 uA

tCDR[3] Chip Deselect to Dat a

Retention Time 0 ns

tR[3] Operation Recovery Time tRC ns

Data Retention Waveform

C62256V–7

1.8V1.8V

tCDR

VDR >1.4V

DATA RETENTION MODE

VCC

CY62256V

PRELIMINARY

Swi tch i ng C h ara cter i sti cs Over the Operating Range[5]

CY62256V-70 CY62256V25-100 CY62256V18-200

Parameter Description Min. Max. Min. Max. Min. Max. Unit

READ CYCLE

tRC Read Cycle Time 70 100 200 ns

tAA Address to Data Valid 70 100 200 ns

tOHA Data Hold from Address Change 10 10 10 ns

tACE CE LOW to Data Valid 70 100 200 ns

tDOE OE LOW to Data Valid 35 75 125 ns

tLZOE OE LOW to Low Z[6] 5 5 10 ns

tHZOE OE HIGH to High Z[6, 7] 25 50 75 ns

tLZCE CE LOW to Low Z[6] 10 10 10 ns

tHZCE CE HIGH to High Z[6, 7] 25 50 75 ns

tPU CE LOW to Pow er-Up 0 0 0 ns

tPD CE HIGH to Power-Down 70 100 200 ns

WRITE C YCL E[8,9]

tWC Write Cycl e Time 70 100 200 ns

tSCE CE LOW to Write End 60 90 180 ns

tAW Address Set-Up to Write End 60 90 180 ns

tHA Address Hold f rom Writ e End 0 0 0 ns

tSA Address Set-Up to Write Star t 0 0 0 ns

tPWE WE Pulse Width 50 80 160 ns

tSD Data Set-Up to Write E n d 30 60 100 ns

tHD Data Hold from Write End 0 0 0 ns

tHZWE WE LOW to High Z[6, 7] 25 50 100 ns

tLZWE WE HIGH to Low Z[6] 10 10 10 ns

Notes:

4. No input may exceed VCC+0.3V.

5. Test conditions assume signal transition time of 5 ns or less timing reference levels of Vcc/2, input pulse levels of 0 to Vcc, and output loading of the specified

IOL/IOH and 100 -pF load c apa citance .

6. At any given temperature and voltage condition, tHZCE is less than t LZCE, tHZOE is less t han tLZOE, and tHZWE is less t han tLZWE for an y giv en dev ice.

7. tHZOE, tHZCE, and tHZWE are spec ified with CL = 5 pF as in p art (b) of AC Test Loa ds. Tran sition is m easured ±200 mV from steady -st ate v oltage .

Swi tch i ng Waveform s

Read Cycle No.1

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

C62256V–8

[10 , 11]

[10, 11]

CY62256V

PRELIMINARY

Notes:

8. The internal write time of the memory is defined by the overlap of CE LO W and WE LO W . Both signa ls m ust be LOW to initiate a write and ei ther signal can t erminate

a write by go in g HIGH. The data input set- up an d hold t iming should be ref e renced to the risin g edge of th e signal that terminates the wr ite.

9. The minimum write cycle time for write cycle #3 (WE controll ed, OE LOW) is the sum of t HZWE and tSD.

10. Device is continuously selected. OE, CE = VIL.

11. WE is HIGH fo r r ead cycle .

12. Address valid prior to or coincident with CE transit ion LO W.

Swi tch i ng Waveform s (continued)

Read Cycle No. 2

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

DATA OUT HIGH IMPEDANCE IMPEDANCE

ICC

ISB

tHZOE

tHZCE

tPD

HIGH

VCC

SUPPLY

CURRENT

C62256V–9

[11, 12]

Write Cycle No.1(WE Controlled)

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

DATA I/O

ADDRESS

tHZOE C62256V–10

DATAINVALID

[8, 13, 14 ]

NOTE 15

CY62256V

PRELIMINARY

Notes:

13. Data I/O is high impedance if OE = VIH.

14. If CE goes HIGH simultaneous ly with WE HIGH, t he out put remains in a high-impe dance s tate .

15. During this period, the I/Os are in output state and input signals should not be applied.

Swi tch i ng Waveform s (continued)

Write Cycle No. 2 (CEControlled)tWC

tAW

tSA tHA

tHD

tSD

tSCE

DATA I/O

ADDRESS

C62256V–11

DATAINVALID

[8, 13, 14 ]

Write Cycle No. 3 (WE Controlled,OE LOW)

DA TA I/O

ADDRESS

tHD

tSD

tLZWE

tSA

tHA

tAW

tWC

tHZWE C62256V–12

DATAINVALID

[ 9, 14]

NOTE 15

CY62256V

PRELIMINARY

Typical DC and A C Characte ris tics

1.6

1.8

1.0

0.6

0.4

0.2

1.6

1.4

1.2

1.0

0.8

−55 25 125

1.2

1.0

0.8

-14

-12

-10

-8

-6

-4

0.0 1.0 1.5 22.5

SUPPLY VOL TAGE (V)

NORMALIZED SUPPLY CURRENT

vs. SUPPLY VOLTAGE

NORMALIZED ACCESS TIME

vs. AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C)

NORMALIZED SUPPLY CURRENT

vs. AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C)

OUT PUT VOLT AGE (V)

OUTPUT SOURCE CURRENT

vs. OUTPUT VOLTAGE

0.8

1.5

1.0

0.5

1.65 2.1 2.6 3.1 3.6

SUPPLY VOL TAGE (V)

NORMALIZED ACCESS TIME

vs. SUPPLY VOLTAGE

0.0 1.0 2.0 3.0

OUTPUT VOLTAGE (V)

OUTPUT SINK CURRENT

vs.OUTPUTVOLTAGE

0.6

0.4

0.2

0.0

TA=25°C

0.6

0.0

2.5

2.0

TA=25°C

1.4

−55 25 105

2.5

2.0

1.5

CURRENT

vs. AMBIENT TEMPERATURE

AMBI ENT TEMPERATURE (°C)

1.0

0.5

0.0

-0.5

ISB

3.0

STANDBY

Vcc=3.0V

Vcc=2.5V

Vcc=1.8V

1.4

1.2

Vcc=1.8V

Vcc=3.0V

Vcc=2.5V

0.5

TA=25°C

Vcc=2.5V

Vcc=2.5 V

CY62256V

PRELIMINARY

Typical DC and A C Characte ris tics (continued)

1.5

1.0

0.5

0.0 1.0 2.0 3.0

SUPPLY VOL TAGE (V)

TYPICAL POWER-ON CURRENT

vs. SUPPLY VOLTAGE 30.0

25.0

20.0

15.0

10.0

5.0

0 200 400 600 800

CAPACITANCE (pF)

TYPICAL ACCESS TIME CHANGE

vs.OUTPUTLOADING 1.25

1.00

0.75

10 20 30

CYCLE FREQUENCY (MHz)

NORMALIZED ICC vs.CYCLETIME

0.0 4.0 0.0 1000 0.50

TA=25°C

VIN =0.5V

TA=25°C

Vcc =3V

Vcc=1.8V

Vcc=3.0V

CY62256V

PRELIMINARY

Truth Table

CE WE OE Inputs/Outputs Mode Power

H X X High Z Deselect/Power-Down Standby (ISB)

L H L Da ta Out Read Active (ICC)

L L X Data In Write Active (ICC)

L H H High Z Deselect, Output Disabled Active (ICC)

Ordering Information

Speed

(ns) Or dering Code Package

Name P ackage Type Operating

Range

70 CY62256V -70SNC S22 28-Lead 450-Mi l ( 300-Mil Body Widt h) SOIC Commercial

CY62256V L-70SNC

CY62256V LL-70SNC

CY62256V -70ZRC ZR28 28-Lead Reverse Thin Small Outline Package

CY62256V L-70ZRC

CY62256V LL-70ZRC

CY62256V -70ZC Z28 28-Lead Thin Small Outline Package

CY62256V L-70ZC

CY62256V LL-70ZC

CY62256V -70ZI Z28 28-Lead Thin Smal l Outline P ackage Industrial

CY62256V L-70ZI

CY62256V LL-70ZI

CY62256V -70SNI S22 28-Lead 450-Mil (300-Mil Body Width) SOIC

CY62256VL -70SNI

CY62256VLL -70SNI

CY62256V -70ZRI ZR28 28-Lead Reverse Thi n Small Outline Package

CY62256V L-70ZRI

CY62256V LL-70ZRI

100 CY62256V25-100SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC Commercial

CY62256V25L-100SNC

CY62256V25LL-100SNC

CY62256V25-100ZRC ZR28 28-Lead Reverse Thi n Small Outline Package

CY62256V25L-100ZRC

CY62256V25LL-100ZRC

CY62256V25-100ZC Z28 28-Lead Thin Small Outline Package

100 CY62256V25L-100ZC Z28 28-Lead Thin Smal l Outline P ackage Commercial

CY62256V25LL-100ZC

200 CY62256V18-200SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC Commercial

CY62256V18L-200SNC

CY62256V18LL-200SNC

CY62256V18-200ZRC ZR28 28-Lead Reverse Thi n Small Outline Package

CY62256V18L-200ZRC

CY62256V18LL-200ZRC

CY62256V18-200ZC Z28 28-Lead Thin Small Outline Package

CY62256V18LL-200ZC

200 CY62256V18L-200ZC Z28 28-Lead Thin Smal l Outline P ackage Commercial

Shaded area contains advanced information.

Document #: 38-00519-A

CY62256V

PRELIMINARY

Package Di ag ra ms

28-Lead 450-Mil (300-Mil Body Width) SOIC S22

28-Lead ReverseThin Small Outline Package ZR28

CY62256V

PRELIMINARY

of any circui try other than circuitry embodied in a Cypress Semiconduc tor produc t. Nor does it conv ey or imply any license under patent or other rights. Cypress Semi conductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application i m plies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Di ag ra ms (continued)

28-Lead Thin Small Outline Package Z28