PCA9555
16-bit I2C and SMBus I/O port with interrupt
Product data
Supersedes data of 2001 May 07 2002 May 13
INTEGRATED CIRCUITS
Philips Semiconductors Product data
PCA955516-bit I2C and SMBus I/O port with interrupt
2
2002 May 13 853-2252 28188
FEATURES
•Operating power supply voltage range of 2.3 V–5.5 V
•5 V tolerant I/Os
•Polarity inversion register
•Active low interrupt output
•Low stand-by current
•Noise filter on SCL/SDA inputs
•No glitch on power-up
•Internal power-on reset
•16 I/O pins which default to 16 inputs
•0 to 400 kHz clock frequency
•ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V
MM per JESD22-A115, and 1000 V CDM per JESD22-C101
•Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
DESCRIPTION
The PCA9555 is a 24-pin CMOS device that provide 16 bits of
General Purpose parallel Input/Output (GPIO) expansion for
I2C/SMBus applications and was developed to enhance the Philips
family of I@C I/O expanders. The improvements include higher drive
capability, 5V I/O tolerance, lower supply current, individual I/O
configuration, and smaller packaging. I/O expanders provide a
simple solution when additional I/O is needed for ACPI power
switches, sensors, pushbuttons, LEDs, fans, etc.
The PCA9555 consist of two 8-bit Configuration (Input or Output
selection); Input, Output and Polarity inversion (Active high or Active
low operation) registers. The system master can enable the I/Os as
either inputs or outputs by writing to the I/O configuration bits. The
data for each Input or Output is kept in the corresponding Input or
Output register. The polarity of the read register can be inverted with
the Polarity Inversion Register. All registers can be read by the
system master. Although pin to pin and I2C address compatible with
the PCF8575, software changes are required due to the
enhancements and are discussed in Application Note AN469.
The PCA9555 open-drain interrupt output is activated when any
input state differs from its corresponding input port register state and
is used to indicate to the system master that an input state has
changed. The power-on reset sets the registers to their default
values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I2C address and
allow up to eight devices to share the same I2C/SMBus. The fixed
I2C address of the PCA9555 is the same as the PCA9554 allowing
up to eight of these devices in any combination to share the same
I2C/SMBus.
PIN CONFIGURATION
SU01438
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
INT
A1
A2
I/O0.0
I/O0.1
I/O0.2
I/O0.3
I/O0.4
I/O0.5
I/O0.6
I/O0.7
VDD
SDA
SCL
A0
I/O1.7
I/O1.6
I/O1.5
I/O1.3
I/O1.4
I/O1.2
I/O1.1
I/O1.0VSS
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
NUMBER SYMBOL FUNCTION
1 INT Interrupt output (open drain)
2 A1 Address input 1
3 A2 Address input 2
4–11 I/O0.0–I/O0.7 I/O0.0 to I/O0.7
12 VSS Supply ground
13–20 I/O1.0–I/O1.7 I/O1.0 to I/O1.7
20 I/O1.7 I/O1.7
21 A0 Address input 0
22 SCL Serial clock line
23 SDA Serial data line
24 VDD Supply voltage
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER
24-Pin Plastic SO –40 to +85 °C PCA9555D SOT137-1
24-Pin Plastic SSOP –40 to +85 °C PCA9555DB SOT340-1
24-Pin Plastic TSSOP –40 to +85 °C PCA9555PW SOT355-1
I2C is a trademark of Philips Semiconductors Corporation.
SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent.
Philips Semiconductors Product data
PCA955516-bit I2C and SMBus I/O port with interrupt
2002 May 13 3
BLOCK DIAGRAM
POWER-ON
RESET
INPUT
FILTER
I2C/SMBUS
CONTROL
INPUT/
OUTPUT
PORTS
WRITE pulse
READ pulse
A0
A1
A2
SCL
SDA
VDD
VSS
8-BIT
I/O0.0
I/O0.1
I/O0.2
I/O0.3
I/O0.4
I/O0.5
I/O0.6
I/O0.7
SU01439
NOTE: ALL I/Os ARE SET TO INPUTS AT RESET
VINT
INT
8-BIT INPUT/
OUTPUT
PORTS
I/O1.0
I/O1.1
I/O1.2
I/O1.3
I/O1.4
I/O1.5
I/O1.6
I/O1.7
WRITE pulse
READ pulse
LP FILTER
Figure 2. Block diagram
Philips Semiconductors Product data
PCA955516-bit I2C and SMBus I/O port with interrupt
2002 May 13 4
SIMPLIFIED SCHEMATIC OF I/Os
WRITE PULSE
DATA FROM
SHIFT REGISTER
VDD
I/O PIN
VSS
WRITE CONFIGURATION
PULSE
D
CK
FF
Q
D
CK
Q
FF
D
CK
Q
FF
D
CK
Q
FF
INPUT PORT
REGISTER
POLARITY
INVERSION
REGISTER
OUTPUT
PORT
REGISTER
DATA FROM
SHIFT REGISTER
DATA FROM
SHIFT REGISTER
WRITE
POLARITY
PULSE
CONFIGURATION
REGISTER
OUTPUT PORT
REGISTER DATA
INPUT PORT
REGISTER DATA
POLARITY
REGISTER DATA
READ PULSE
SU01473
Q
Q
Q
Q
TO INT
100 kΩ
Q1
Q2
NOTE: At Power-on Reset, all registers return to default values.
Figure 3. Simplified schematic of I/Os
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off,
creating a high impedance input with a weak pull-up to VDD. The
input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on,
depending on the state of the Output Port register. Care should be
exercised if an external voltage is applied to an I/O configured as an
output because of the low impedance path that exists between the
pin and either VDD or VSS.
Philips Semiconductors Product data
PCA955516-bit I2C and SMBus I/O port with interrupt
2002 May 13 5
REGISTERS
Command Byte
Command Register
0Input port 0
1Input port 1
2Output port 0
3Output port 1
4Polarity inversion port 0
5Polarity inversion port 1
6Configuration port 0
7Configuration port 1
The command byte is the first byte to follow the address byte during
a write transmission. It is used as a pointer to determine which of the
following registers will be written or read.
Registers 0 and 1 — Input Port Registers
This register is an input-only port. It reflects the incoming logic levels
of the pins, regardless of whether the pin is defined as an input or an
output by Register 3. Writes to this register have no effect.
Registers 2 and 3 — Output Port Registers
bit O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0
default 11111111
bit O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0
default 11111111
This register is an output-only port. It reflects the outgoing logic
levels of the pins defined as outputs by Register 6 and 7. Bit values
in this register have no effect on pins defined as inputs. In turn,
reads from this register reflect the value that is in the flip-flop
controlling the output selection, NOT the actual pin value.
Registers 4 and 5 — Polarity Inversion Registers
bit N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0
default 0 0 0 0 0 0 0 0
bit N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0
default 0 0 0 0 0 0 0 0
This register allows the user to invert the polarity of the Input Port
register data. If a bit in this register is set (written with ‘1’), the Input
Port data polarity is inverted. If a bit in this register is cleared (written
with a ‘0’), the Input Port data polarity is retained.
Registers 6 and 7 — Configuration Registers
bit C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0
default 1 1 1 1 1 1 1 1
bit C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0
default 1 1 1 1 1 1 1 1
This register configures the directions of the I/O pins. If a bit in this
register is set (written with ‘1’), the corresponding port pin is enabled
as an input with high impedance output driver. If a bit in this register
is cleared (written with ‘0’), the corresponding port pin is enabled as
an output. Note that there is a high value resistor tied to VDD at each
pin. At reset the device’s ports are inputs with a pull-up to VDD.
POWER-ON RESET
When power is applied to VDD, an internal power-on reset holds the
PCA9555 in a reset state until VDD has reached VPOR. At that point,
the reset condition is released and the PCA9555 registers and
SMBus state machine will initialize to their default states.
DEVICE ADDRESS
0 1 0 0A2A1A0
slave address
su01441
fixed programmable
R/W
Figure 4. PCA9555 address
BUS TRANSACTIONS
Writing to the port registers
Data is transmitted to the PCA9555 by sending the device address
and setting the least significant bit to a logic 0 (see Figure 4 for
device address). The command byte is sent after the address and
determines which register will receive the data following the
command byte.
The eight registers within the PCA9555 are configured to operate
as four register pairs. The four pairs are Input Ports, Output Ports,
Polarity Inversion Ports, and Configuration Ports. After sending data
to one register, the next data byte will be sent to the other register in
the pair (see Figures and ). For example, if the first byte is sent to
Output Port (register 3), then the next byte will be stored in Output
Port 0 (register 2). There is no limitation on the number of data bytes
sent in one write transmission. In this way, each 8-bit register may
be updated independently of the other registers.
Reading the port registers
In order to read data from the PCA9555, the bus master must first
send the PCA9555 address with the least significant bit set to a
logic 0 (see Figure 4 for device address). The command byte is sent
after the address and determines which register will be accessed.
After a restart, the device address is sent again but this time, the
least significant bit is set to a logic 1. Data from the register defined
by the command byte will then be sent by the PCA9555 (see
Figures 7 and 8). Data is clocked into the register on the falling edge
of the acknowledge clock pulse. After the first byte is read,
additional bytes may be read but the data will now reflect the
information in the other register in the pair. For example, if you read
Input Port 1, then the next byte read would be Input Port 0. There is
no limitation on the number of data bytes received in one read
transmission but the final byte received, the bus master must not
acknowledge the data.
Interrupt Output
The open-drain interrupt output is activated when one of the port
pins change state and the pin is configured as an input. The
interrupt is deactivated when the input returns to its previous state or
the input port register is read (see Figure 8). A pin configured as an
output cannot cause an interrupt. Since each 8-bit port is read
independently, the interrupt caused by Port 0 will not be cleared by a
read of Port 1 or the other way around.
Note that changing an I/O from an output to an input may cause a
false interrupt to occur if the state of the pin does not match the
contents of the Input Port register.
Philips Semiconductors Product data
PCA9555
16-bit I2C and SMBus I/O port with interrupt
62002 May 13
12
SCL
WRITE TO
PORT
DATA OUT
FROM PORT 0
345678
SDA AA A
DATA 0
slave address data to port 0
start condition R/W acknowledge
from slave acknowledge
from slave acknowledge
from slave
tpv
SU01442
9
00000001
command byte
0.7 0.0 DATA 11.7 1.0 A
data to port 1
S 0 1 0 0 A2 A1 A0 0
DATA OUT
FROM PORT 1 DATA VALID
tpv
P
Figure 5. WRITE to output port registers
12
SCL 345678
SDA AA A
DATA 0
slave address data to register
start condition R/W acknowledge
from slave acknowledge
from slave acknowledge
from slave
SU01443
9
00000011
command byte
MSB LSB DATA 1MSB LSB A
data to register
S 0 1 0 0 A2 A1 A0 0
12345678912345678912345
P
Figure 6. WRITE to configuration registers
Philips Semiconductors Product data
PCA9555
16-bit I2C and SMBus I/O port with interrupt
72002 May 13
1 0 A2 A1 A00 00 0 A2 A1 A00 1
S0A A A
COMMAND BYTE
acknowledge
from slave
R/W
acknowledge
from slave
A
PNA
acknowledge
from slave acknowledge
from master
SDATA
DATA
R/W first byte
at this moment master-transmitter
becomes master-receiver and
slave-receiver becomes
slave-transmitter
last byte
SU01463
no acknowledge
from master
1
slave address
data from upper
or lower byte of
register
data from lower
or upper byte
of register
slave address
MSB LSB
MSB LSB
NOTE: T ransfer can be stopped at any time by a STOP condition. Figure 7. READ from register
123456789
S0100A2 A1 A0 1 A 76543210A
I0.x
76543210A
I1.x
76543210A
I0.x
765432101
I1.x
P
R/W ACKNOWLEDGE
FROM SLAVE
SCL
SDA
ACKNOWLEDGE
FROM MASTER ACKNOWLEDGE
FROM MASTER ACKNOWLEDGE
FROM MASTER
NON ACKNOWLEDGE
FROM MASTER
READ FROM PORT 0
DATA INTO PORT 0
READ FROM PORT 1
DATA INTO PORT 1
INT
tIR
tIV
SU01464
NOTES: T ransfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
It is assumed that the command byte has previously been set to 00 (read input port port register).
Figure 8. READ input port register — scenario 1
Philips Semiconductors Product data
PCA9555
16-bit I2C and SMBus I/O port with interrupt
82002 May 13
123456789
S0100A2 A1 A0 1 A A
I0.x
A
I1.x
A
I0.x
1
I1.x
P
R/W ACKNOWLEDGE
FROM SLAVE
SCL
SDA
ACKNOWLEDGE
FROM MASTER ACKNOWLEDGE
FROM MASTER ACKNOWLEDGE
FROM MASTER
NON ACKNOWLEDGE
FROM MASTER
READ FROM PORT 0
DATA INTO PORT 0
READ FROM PORT 1
DATA INTO PORT 1
INT
tIR
tIV
SU01651
tph
DATA 00 DATA 10 DATA 03 DATA 12
DATA 00 DATA 01 DATA 02 DATA 03
tps
tph tps
DATA 10 DATA 11 DATA 12
NOTES: T ransfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
It is assumed that the command byte has previously been set to 00 (read input port port register).
Figure 9. READ input port register — scenario 2
Philips Semiconductors Product data
PCA955516-bit I2C and SMBus I/O port with interrupt
2002 May 13 9
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
VDD Supply voltage –0.5 6.0 V
VI/O DC input current on an I/O VSS – 0.5 6 V
II/O DC output current on an I/O —± 50 mA
IIDC input current —± 20 mA
IDD Supply current — 160 mA
ISS Supply current — 200 mA
Ptot Total power dissipation — 200 mW
Tstg Storage temperature range –65 +150 °C
Tamb Operating ambient temperature –40 +85 °C
Philips Semiconductors Product data
PCA955516-bit I2C and SMBus I/O port with interrupt
2002 May 13 10
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take
precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”
Handling MOS devices
”.
DC CHARACTERISTICS
VDD = 2.3 to 5.5 V ; V SS = 0 V; Tamb = –40 to +85 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
Supplies
VDD Supply voltage 2.3 — 5.5 V
IDD Supply current Operating mode; VDD = 5.5 V; no load;
fSCL = 100 kHz — 135 200 µA
Istbl Standby current Standby mode; VDD = 5.5 V ; no load;
VI = VSS; fSCL = 0 kHz; I/O = inputs — 1.1 1.5 mA
Istbh Standby current Standby mode; VDD = 5.5 V ; no load;
VI = VDD; fSCL = 0 kHz; I/O = inputs — 0.25 1 µA
VPOR Power-on reset voltage No load; VI = VDD or VSS — 1.5 1.65 V
input SCL; input/output SDA
VIL LOW level input voltage –0.5 —0.3 VDD V
VIH HIGH level input voltage 0.7 VDD — 5.5 V
IOL LOW level output current VOL = 0.4V 3 — — mA
ILLeakage current VI = VDD = VSS –1 — +1 µA
CIInput capacitance VI = VSS — 6 10 pF
I/OsVIL LOW level input voltage –0.5 — 0.8 V
VIH HIGH level input voltage 2.0 — 5.5 V
IO
LOW level out
p
ut current
VOL = 0.5 V ; VDD = 2.3–5.5 V; Note 1 8 8–20 — mA
I
OL
LOW
le
v
el
o
u
tp
u
t
c
u
rrent
VOL = 0.7 V ; VDD = 2.3–5.5 V; Note 1 10 10–24 — mA
IOH = –8 mA; VDD = 2.3 V ; Note 2 1.8 — — V
IOH = –10 mA; VDD = 2.3 V ; Note 2 1.7 — — V
VO
HIGH level out
p
ut voltage
IOH = –8 mA; VDD = 3.0 V ; Note 2 2.6 — — V
V
OH
HIGH
le
v
el
o
u
tp
u
t
v
oltage
IOH = –10 mA; VDD = 3.0 V ; Note 2 2.5 — — V
IOH = –8 mA; VDD = 4.75 V ; Note 2 4.1 — — V
IOH = –10 mA; VDD = 4.75 V ; Note 2 4.0 — — V
IIH Input leakage current VDD = 3.6 V; VI = VDD — — 1 µA
IIL Input leakage current VDD = 5.5 V; VI = VSS — — –100 µA
CIInput capacitance — 3.7 5 pF
COOutput capacitance — 3.7 5 pF
Interrupt INT
IOL LOW level output current VOL = 0.4 V 3 — — mA
Select Inputs A0, A1, A2
VIL LOW level input voltage –0.5 — 0.8 V
VIH HIGH level input voltage 2.0 — 5.5 V
ILI Input leakage current –1 — 1 µA
NOTES:
1. The total current sunk by all I/Os must be limited to 200 mA.
2. The total current sourced by all I/Os must be limited to 160 mA.
Philips Semiconductors Product data
PCA955516-bit I2C and SMBus I/O port with interrupt
2002 May 13 11
SDA
SCL
SU01469
tHD;STA
tF
S
tLOW tR
tHD;DAT
tSU;DAT
tHIGH
tF
tSU;STA SR
tHD;STA tSP
tSU;STD P
tRtBUF
S
Figure 10. Definition of timing
AC SPECIFICATIONS
SYMBOL PARAMETER STANDARD MODE
I2C BUS FAST MODE
I2C BUS UNITS
MIN MAX MIN MAX
fSCL Operating frequency 0 100 0 400 kHz
tBUF Bus free time between STOP and START conditions 4.7 — 1.3 — µs
tHD;STA Hold time after (repeated) ST ART condition 4.0 — 0.6 — µs
tSU;STA Repeated START condition setup time 4.7 — 0.6 — µs
tSU;STO Setup time for ST OP condition 4.0 — 0.6 — µs
tVD;ACK Valid time of ACK condition20.3 3.45 0.1 0.9 µs
tHD;DAT Data in hold time 0 — 0 — ns
tVD;DAT Data out valid time3300 — 50 — ns
tSU;DAT Data setup time 250 — 100 — ns
tLOW Clock LOW period 4.7 — 1.3 — µs
tHIGH Clock HIGH period 4.0 — 0.6 — µs
tFClock/Data fall time — 300 20 + 0.1Cb 1300 ns
tRClock/Data rise time — 1000 20 + 0.1Cb 1300 ns
tSP Pulse width of spikes that must be suppressed by the input
filters — 50 — 50 ns
Port Timing
tPV Output data valid — 200 — 200 ns
tPS Input data setup time 150 — 150 — ns
tPH Input data hold time 1 — 1 — µs
Interrupt Timing
tIV Interrupt valid — 4 — 4 µs
tIR Interrupt reset — 4 — 4 µs
NOTES:
1. Cb = total capacitance of one bus line in pF.
2. tVD;ACK = time for Acknowledgement signal from SCL low to SDA (out) low.
3. tVD;DAT = minimum time for SDA data out to be valid following SCL low.
Philips Semiconductors Product data
PCA955516-bit I2C and SMBus I/O port with interrupt
2002 May 13 12
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
Philips Semiconductors Product data
PCA955516-bit I2C and SMBus I/O port with interrupt
2002 May 13 13
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
Philips Semiconductors Product data
PCA955516-bit I2C and SMBus I/O port with interrupt
2002 May 13 14
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
Philips Semiconductors Product data
PCA955516-bit I2C and SMBus I/O port with interrupt
2002 May 13 15
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Contact information
For additional information please visit
http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Koninklijke Philips Electronics N.V. 2002
All rights reserved. Printed in U.S.A.
Date of release: 05-02
Document order number: 9397 750 09818
Data sheet status[1]
Objective data
Preliminary data
Product data
Product
status[2]
Development
Qualification
Production
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
