TPIC82000 Series Tire Pressure Monitoring System TX Module Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLDS189 May 2012 TPIC82000 Series www.ti.com SLDS189 - MAY 2012 Contents 1 INTRODUCTION 1.1 1.2 2 PIN CONFIGURATION AND DESCRIPTIONS 2.1 2.2 2.3 3 3.3 ........................................................................... 8 Pin Configuration ............................................................................................................ 8 Pin Descriptions ............................................................................................................. 8 Pin Equivalent Circuits ..................................................................................................... 9 FUNCTION DESCRIPTION 3.1 3.2 2 .................................................................................................................. 6 Features ...................................................................................................................... 6 General Description ........................................................................................................ 6 ................................................................................................... 13 Functional Block Diagram (Whole Device) ............................................................................. MCU8051 core ............................................................................................................. 3.2.1 Memory Resource Map ........................................................................................ 3.2.2 Program Code Memory (ROM) ............................................................................... 3.2.3 Internal Data Memory (RAM) ................................................................................. 3.2.4 External Special Function Registers (ESFR) ............................................................... 3.2.4.1 ESFR Table ......................................................................................... 3.2.4.2 ESFR Table (Continued) .......................................................................... 3.2.4.3 ESFR Table (Continued) .......................................................................... 3.2.5 Battery Backup External-RAM (BuRAM) .................................................................... 3.2.5.1 CRC (Cyclic Redundancy Check) Generator Function ....................................... 3.2.5.2 BuRAM with CRC Generator Block Diagram ................................................... 3.2.5.3 8-bit CRC Polynomial Expression ............................................................... 3.2.5.4 Timing Chart of CRC Calculation from Start Address ......................................... 3.2.5.5 Timing Chart of CRC Calculation at the End Address ........................................ 3.2.5.6 Battery Backup External-RAM (BuRAM) Control ESFR ...................................... 3.2.6 Non-volatile EEPROM ......................................................................................... 3.2.6.1 EEPROM Block Diagram ......................................................................... 3.2.6.2 EEPROM Unit Structure and DATA/ECC Implementation ................................... 3.2.6.3 EEPROM Programming Procedure .............................................................. 3.2.6.4 EEPROM Control ESFR .......................................................................... 3.2.7 MCU8051 Registers ............................................................................................ 3.2.7.1 MCU8051 Core SFR Map ........................................................................ 3.2.7.2 I/O PORT (P0,P1,P2,P3) .......................................................................... 3.2.7.3 Stack Pointer (SP) ................................................................................. 3.2.7.4 Data Pointer (DPTR) .............................................................................. 3.2.7.5 8051 Power Control Register (PCON) .......................................................... 3.2.7.6 Timer/Counter Registers .......................................................................... 3.2.7.7 UART Registers .................................................................................... 3.2.7.8 Interrupt Registers ................................................................................. 3.2.7.9 Program Status Word (PSW) ..................................................................... 3.2.7.10 Accumulator (ACC) ................................................................................ 3.2.7.11 B Register (B) ...................................................................................... 3.2.8 Instruction Definitions .......................................................................................... 3.2.8.1 Addressing Modes ................................................................................. 3.2.8.2 Arithmetic Instructions ............................................................................. 3.2.8.3 Logic Instructions .................................................................................. 3.2.8.4 Data Transfers ...................................................................................... 3.2.8.5 Jump Instructions .................................................................................. 3.2.8.6 Boolean Instructions ............................................................................... 3.2.8.7 Flags ................................................................................................. 3.2.8.8 Instruction Table ................................................................................... System Power Controller and Status Monitor ......................................................................... Contents 13 13 14 14 15 15 16 17 18 19 19 19 20 20 21 21 22 23 24 25 27 28 28 29 29 29 30 31 33 34 36 37 37 37 37 38 38 38 38 39 39 40 42 Copyright (c) 2012, Texas Instruments Incorporated TPIC82000 Series www.ti.com 3.4 3.5 3.6 3.7 3.8 4 3.3.1 System Power Block Diagram ................................................................................ 3.3.2 System Wake-up Operation ................................................................................... 3.3.3 System Power Control ESFR ................................................................................. Internal Clocks System ................................................................................................... 3.4.1 Internal Clock System Block Diagram ....................................................................... 3.4.2 Timer Oscillator (Timer-OSC) ................................................................................. 3.4.2.1 Interval Timer ....................................................................................... 3.4.3 RC Oscillator (RC-OSC) ....................................................................................... 3.4.4 Crystal Oscillator ................................................................................................ RF Transmitter ............................................................................................................. 3.5.1 RF Power Amplifier ............................................................................................. 3.5.2 PLL Block ........................................................................................................ 3.5.3 315/434MHz Dual-band Quadrature Modulator (QMOD) ................................................. 3.5.4 Baseband Block (BB block) ................................................................................... LF Receiver ................................................................................................................ 3.6.1 LF AFE ........................................................................................................... 3.6.2 LF Baseband Processor ....................................................................................... 3.6.3 LF Pattern ........................................................................................................ 3.6.3.1 Protocol 1a .......................................................................................... 3.6.3.2 Protocol 1b .......................................................................................... 3.6.3.3 Protocol 1c .......................................................................................... 3.6.3.4 Protocol 1 Total Sniffing Abort Time ............................................................. 3.6.3.5 Protocol 1 Data Pattern Setting .................................................................. 3.6.3.6 Protocol 2 ........................................................................................... Sensor ...................................................................................................................... Debug Mode ............................................................................................................... 3.8.1 ESFR ............................................................................................................. ELECTRICAL SPECIFICATIONS 4.1 4.2 5 SLDS189 - MAY 2012 .......................................................................................... 83 Absolute Maximum Ratings .............................................................................................. 83 Recommended Operating Conditions .................................................................................. 83 ELECTRICAL CHARACTERISTICS 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 43 43 46 47 47 48 49 51 52 53 54 56 56 57 62 62 63 63 64 65 67 68 68 69 77 82 82 ....................................................................................... 85 Sensor ...................................................................................................................... 5.1.1 Pressure Sensor (Selection A) for (50 kPa to 635 kPa Range) .......................................... 5.1.2 Pressure Sensor (Selection B) for (50 kPa to 635 kPa Range) .......................................... 5.1.3 Temperature / Voltage / Acceleration Sensor ............................................................... Power Supply .............................................................................................................. Xtal-OSC ................................................................................................................... PLL .......................................................................................................................... Timer-OSC ................................................................................................................. 9.6 MHz RC-OSC ......................................................................................................... BB Modulator and RF PA ................................................................................................ LF Receiver ................................................................................................................ Voltage Regulator (VREG) ............................................................................................... Power-on-Reset and Hardware Reset .................................................................................. EEPROM ................................................................................................................... Copyright (c) 2012, Texas Instruments Incorporated Contents 85 85 85 86 86 86 87 87 87 88 88 89 89 90 3 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com List of Figures 2-1 Top View from Diaphragm ........................................................................................................ 8 3-1 ESFR Table (Address FF-D8) 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 4-1 5-3 4 ................................................................................................. ESFR Table (Address D7-AC) ................................................................................................. ESFR Table (Address AB-80) .................................................................................................. CRC Generator 8-bit Polynomial Expression ................................................................................. System Power Controller and Status Monitor ................................................................................ System Wake-up Timing ........................................................................................................ System Power On/Off State Diagram (Example) ............................................................................ Crystal Oscillator Block Diagram ............................................................................................... 315/434MHz Transmitter Block Diagram ...................................................................................... RF PA Block ...................................................................................................................... PLL Block.......................................................................................................................... Timing Diagram of 1-Byte FSK Data Transmission.......................................................................... Timing Diagram of 1-Byte ASK Data Transmission ......................................................................... LF Protocol 1a Pattern Example ............................................................................................... LF Sniffing Timing ................................................................................................................ Protocol 1b Pattern Example ................................................................................................... LF Sniffing Timing ................................................................................................................ Protocol 1c Pattern Example ................................................................................................... LF Sniffing Timing ................................................................................................................ Synchronization Pattern Example .............................................................................................. Wake-up ID Pattern Example ................................................................................................... Protocol 2 Example .............................................................................................................. LF Sniffing Timing ................................................................................................................ 13-bit SAR-ADC Sensor Block Diagram ...................................................................................... Relationship Between Package Diaphragm Side and Accelerator Measurement Direction ............................ Power-on-Reset and Hardware Reset ......................................................................................... List of Figures 16 17 19 20 43 45 45 53 54 55 56 60 60 65 65 66 66 67 67 68 69 69 70 77 84 89 Copyright (c) 2012, Texas Instruments Incorporated TPIC82000 Series www.ti.com SLDS189 - MAY 2012 List of Tables 3-1 Flags Instructions ................................................................................................................. 39 3-2 Instruction Table .................................................................................................................. 40 3-3 Protocol 1a (Manchester Coding) Timing Example .......................................................................... 65 3-4 Protocol 1b (Manchester Coding) Timing Example .......................................................................... 66 3-5 Protocol 1c (Manchester Coding) Timing Example .......................................................................... 68 3-6 Protocol 2 (PWM) Timing Example ............................................................................................ 70 Copyright (c) 2012, Texas Instruments Incorporated List of Tables 5 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com Tire Pressure Monitoring System TX Module Check for Samples: TPIC82000 Series 1 INTRODUCTION 1.1 Features 1 * Operating Voltage Range: 1.5 V to 3.5 V (315 MHz), 1.75 V to 3.5 V (434 MHz) * Operating Temperature Range : -40C to 125C * Low Current Consumption to Support a Coin Size Lithium Battery Operation * In Package Pressure Sensor (Operation Range: 50 kPa to 635 kPa) * In Package Accelerometer * On Chip Temperature Sensor * On Chip Battery Voltage Sensor * 13-bit ADC for Sensors * Dual Band 315/434 MHz Transmitter With One Crystal Oscillator * Fully Integrated PLL Synthesizer * ASK/FSK Baseband Modulator for 10K bits/s Manchester/BiPhase Coding, Capable up to 20K bits/s for FSK 1.2 * Dual Band Quadrature Modulator for Transmit Frequency Tuning (~ 700 kHz) * 125 kHz LF ASK Receiver (4K bits/s Manchester/BiPhase Code) * LF Antenna Q Tuning Function * Selectable LF Format * 8051 Compatible Microcontroller * 16KB ROM (for Program Code) * 43 Words (7-bit x 43 Word) EEPROM * 128-byte Battery Backed up RAM (BuRAM) (Uninitialized RAM at MCU Sleep Mode) * 8-bit CRC Generator for BuRAM * 16 PIN Ceramic Package with Diaphragm for Pressure Sensor (Shielded for EMI Protection) General Description The TPIC82000 series integrates the functions required for a transmit (TX) module in Tire Pressure Monitoring System (TPMS) into a single ceramic package. The functions required for TPMS applications such as measurement functions (tire pressure, tire temperature, tire acceleration, battery voltage), RF data transmission, and LF command receiving functions are integrated in one device. The device consists of a ceramic package with diaphragm for pressure sensing, an accelerometer, and an LSI. The LSI integrates an 8051 microcontroller, RF transmitter, LF receiver, and Analog Front-End (AFE) with a 13-bit ADC for sensor measurements. To minimize the power consumption and maximize the battery life of the system, the device can wake up periodically for measurements and RF transmissions using an internal ultra low power programmable timer or the 125 kHz LF trigger signal detector. Also, to support maximum usage of battery energy, the device can operate over the wide power supply range from 3.5 V to 1.5 V. (For 434 MHz RF transmission, the minimum voltage is 1.75 V) The LF receiver enables control of this device remotely using a 125 kHz LF signal. The 315 and/or 434 MHz local carrier signal is generated by the internal PLL synthesizer with one external crystal resonator. The RF transmit frequency tuning is achieved using a baseband signal generator and a quadrature modulator. The baseband signal generator can control the baseband frequency up to 700 kHz. The device supports automotive temperature range (-40C to 125C) and quality. In the TPIC82000 series, the accelerometer is an optional component, and for the pressure sensor there are two selections: A and B at TI-TEST factory. For the RF transmission characteristic of 315 and 434 MHz band, one of the RF bands is tested at TI-TEST factory. The device names are defined below. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright (c) 2012, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TPIC82000 Series www.ti.com SLDS189 - MAY 2012 Device Name Accelerometer Type / Pressure Sensor Selection A and B TPIC820X00 X 0: No Accelerometer 1: 1-Axis (Z) Accelerometer TPIC8200Y0 Y 0: Passenger car (Selection A) 2: Passenger Car (Selection B) TPIC82000Z Z 3: 315 MHz 4: 434 MHz INTRODUCTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 7 TPIC82000 Series www.ti.com 2.1 Pin Configuration CK 16 RFOUT PIN CONFIGURATION AND DESCRIPTIONS VOUT 2 15 GND3 SLDS189 - MAY 2012 14 1 LD 13 12 GND2 LFIN 2 11 VDD LFINB 3 10 RESET_TEST VREG 4 TVO 5 6 7 GND1 DI XTAL 9 8 DO Figure 2-1. Top View from Diaphragm 2.2 Pin Descriptions PIN NO. TYPE PULL UPDOWN CK 1 I Pull down LFIN 2 I LFINB 3 I RESET_ TEST 4 I Pull down DI 5 I Pull up TVO 6 O TVO output terminal XTAL 7 I XTAL component connection terminal GND1 8 GND NAME 8 DESCRIPTION SPI CK input terminal LF receiver input terminal 1 LF receiver input terminal 2 H/W reset and Test Mode input terminal SPI DATA input terminal at EN_UART = 0 UART RXD output terminal at EN_UART = 1 GND (Common GND) PIN CONFIGURATION AND DESCRIPTIONS Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series Copyright (c) 2012, Texas Instruments Incorporated TPIC82000 Series www.ti.com SLDS189 - MAY 2012 PIN NAME PULL UPDOWN DESCRIPTION NO. TYPE DO 9 O SPI DO output terminal at EN_UART = 0 UART TXD output terminal at EN_UART = 1 VREG 10 O Internal voltage regulator output A decoupling capacitor (0.1 F) needs to be connected between this terminal and GND. VREG should not be used to supply external loads. VDD 11 Supply GND2 12 GND LD 13 I GND3 14 GND RFOUT 15 O RF PA output terminal VOUT 16 O VDD for load of PA (connected to VDD internally) 2.3 Battery supply voltage GND (RF block except PA) Pull down SPI CS input terminal GND (RF PA) Pin Equivalent Circuits PIN NAME NO. VDD 11 GND1 8 GND2 12 GND3 14 TYPE PULL UPDOWN EQUIVALENT CIRCUITS VOUT VDD GND1 Supply VOUT 16 GND2 GND3 SLDS189-002 Copyright (c) 2012, Texas Instruments Incorporated PIN CONFIGURATION AND DESCRIPTIONS Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 9 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com PIN NAME NO. TYPE PULL UPDOWN EQUIVALENT CIRCUITS VDD VREG 10 VREG O GND1 SLDS189-003 VDD RESET_TEST GND1 RESET_ TEST 4 I Pull down VDD GND1 SLDS189-004 VDD CK 1 I Pull down CK GND SLDS189-005 VDD LD 13 I Pull down LD GND SLDS189-006 10 PIN CONFIGURATION AND DESCRIPTIONS Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series Copyright (c) 2012, Texas Instruments Incorporated TPIC82000 Series www.ti.com SLDS189 - MAY 2012 PIN NAME NO. TYPE PULL UPDOWN EQUIVALENT CIRCUITS VDD DI 5 I Pull up DI GND SLDS189-007 VDD DO 9 DO O GND1 SLDS189-008 VDD XTAL XTAL 7 I GND1 VDD GND SLDS189-009 VDD RFOUT 15 O RFOUT GND1 GND3 SLDS189-010 Copyright (c) 2012, Texas Instruments Incorporated PIN CONFIGURATION AND DESCRIPTIONS Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 11 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com PIN NAME NO. TYPE PULL UPDOWN EQUIVALENT CIRCUITS TVO TVO 6 O GND1 SLDS189-011 LFINB 3 VDD LFINB LFIN 2 I LFIN GND 1 SLDS189-012 12 PIN CONFIGURATION AND DESCRIPTIONS Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series Copyright (c) 2012, Texas Instruments Incorporated TPIC82000 Series www.ti.com SLDS189 - MAY 2012 3 FUNCTION DESCRIPTION 3.1 Functional Block Diagram (Whole Device) The block diagram below shows the overview of the whole TPIC82000 device. Battery The TPIC82000 consists of a pressure sensor which is structured within the ceramic package, an accelerometer for motion sensing, and a mixed signal LSI. The LSI integrates the 8051 microcontroller, a voltage regulator for internal block operation, an Analog Front-End for the sensor signal conditioning, clock generators for processor and internal blocks, an RF transmitter, and an LF signal receiver. The details of each block are described in the following sections. VDD VREG System Power VREG MCU8051 Timer POR Timer-OSC OTP RAM (EPROM) 16-kByte RAM 128-Byte Battery Backup RAM 128-Byte LFIN LFINB LF 125-kHz Receiver EEPROM 43 Words TVO ANT DAC TEST Interface RFOUT RFPA VOUT PLL Pressure Sensor Accelerator Sensor Matching Section RESET_TEST LD CK DI DO ANT ANT Tuning Capacitor BB-MOD (FSK/ASK) Senor Pressure Accelerator Temperature Voltage Crystal-OSC (19.7 MHz) MUX XTAL RC-OSC (9.6 MHz) IC Chip GND1 GND2 GND3 Package SLDS189-013 3.2 MCU8051 core The TPIC82000 integrates a high performance version 8-bit microcontroller that is software compatible with the industry standard 8051. The MCU8051 core uses an internal RC oscillator (about 9.6 MHz) or an external crystal (about 19.7 MHz) as the clock source. It uses a two-clock period machine cycle to realize faster operation. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 13 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com The MCU can address up to 16K bytes of program memory (ROM) and up to 128 bytes of internal data memory (RAM). The MCU can also access the integrated External Special Function Registers (ESFR) space up to 128 bytes. The control registers for built-in peripheral analog/logic circuit control, non-volatile EEPROM memory control and the Battery Backup External-RAM memory control are allocated in this ESFR space. The 43-word EEPROM (7bit x 43word) is prepared as a non-volatile data storage for the various variable parameters such as device ID and calibration parameters. The Battery Backup ExternalRAM is a volatile memory but the contents of the memory can be kept by the internal regulator when the device is in sleep mode. 3.2.1 Memory Resource Map Program Code Memory 0xFFFF Not Implemented 0x3FFF Program Code AREA 0x0000 Internal Data Memory 0xFF 0xF7 0xEF 0xE7 0xDF 0xD7 0xCF 0xC7 0xB4 0xB7 0xAF 0xA7 0x9F 0x97 0x8F 0x87 0x7F 0x77 0x6F 0x67 0x5F 0x57 0x4F 0x47 0x3F 0x37 0x2F 0x27 0x1F 0x17 0x0F 0x07 0xF8 0xF0 0xE8 0xE0 0xD8 0xD0 0xC8 0xC0 0xB8 0xB0 0xA8 0xA0 0x98 0x90 0x88 0x80 0x78 0x70 0x68 0x60 0x58 0x50 0x48 0x40 0x38 0x30 0x28 0x20 0x18 0x10 0x08 0x00 Battery-Backup External-RAM ESFRs Non-Volatile EEPROM Direct Addressing ESFRs 0x7F 0x77 0x6F 0x67 0x5F 0x57 0x4F 0x47 0x3F 0x37 0x2F 0x27 0x1F 0x17 0x0F 0x07 General Purpose Bit Addressable BANK3: R7:R0 BANK2: R7:R0 BANK1: R7:R0 BANK1: R7:R0 0x78 0x70 0x68 0x60 0x58 0x50 0x48 0x40 0x38 0x30 0x28 0x20 0x18 0x10 0x08 0x00 External-RAM 128-Byte 0x2A EEPROM 43 Words (1 Word = 7 bits) 0x00 SLDS189-014 3.2.2 Program Code Memory (ROM) The 16K byte program code memory is located in the address space from 0x0000 to 0x3FFF. This portion is configured by Mask ROM, which is locked by a hardware disabling the SPI DO output as default to protect the ROM code. NOTE If using the built-in firmware prepared by TI, the program code area for the application software becomes smaller than 16K bytes (Typically around half of 16K bytes are available for application software). 14 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 3.2.3 SLDS189 - MAY 2012 Internal Data Memory (RAM) The 128-bytes of RAM are available as the volatile data storage for standard 8051 application program. During MCU sleep mode, the RAM is powered off and their contents are lost. Right after the Power-OnReset or the Power-up of the MCU, the RAM data is not initialized. 3.2.4 External Special Function Registers (ESFR) The ESFRs are mapped on physical memory spaces 0x80 to 0xFF on the MCU8051 core to control and monitor the built-in peripherals. Figure 3-1, Figure 3-2, and Figure 3-3 show the register allocations. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 15 TPIC82000 Series SLDS189 - MAY 2012 3.2.4.1 www.ti.com ESFR Table Write Register Reset ( Note 1) Power on Timer ESFR Address Name FF FE FD FC FB FA F9 F8 EEpromCONT IP1 ( Not Usable ) F7 - - F6 F5 F4 F3 F2 F1 F0 EF EE ED EC EB EA E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 DF DE DD DC DB DA D9 D8 AntDac RFbias RFpower B SLoffset LFcont - Note 1 Note 2 Power on Timer 0 1 D U X S - X011 1111 0000 0000 X011 1111 0000 0000 0UUU UUUU 0000 0000 0000 0000 0000 0000 XXXU UUUU XXXS SSSS UUUU UUUU SSSS SSSS ACC BuRAM_CRC_Start_Adr BuRAM_CRC_End_Adr LFCarrierDet Lfabort Read Register Reset ( Note 1) Power on Timer - 0000 0000 0000 0000 0000 0000 0000 0000 IE1 ( Not Usable ) - Name 0000 0000 0000 0000 X000 0000 0000 0000 XXX0 0000 0000 0000 0000 0000 0000 0000 X000 0000 0000 0000 XXXD DDDD DDDD DDDD IP1 ( Not Usable ) B LFdataCount ModState SystemState Timer state IE1 ( Not Usable ) LocalState LFrxData LFanalogFE ACC BuRAM_CRC_Start_Adr BuRAM_CRC_End_Adr BuRAM_CRC_Status BuRAM_CRC_Result - 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 U1XX XXXX 0X11 1110 00XX 1110 0000 0000 DDDD DDDD U1XX XXXX 1XDD 1DD0 00XX DDDD 0000 0000 XXX0 00U0 XXX0 00D0 0000 0000 DDDD DDDD UUUU UUUU DDDD DDDD 0000 0000 0000 0000 X000 0000 X000 0000 0000 0000 0000 0000 0XXX XXXX 0XXX XXX 1111 1111 1111 1111 Initial value from Power-On-Reset Initial value from WAKEUP-EVENT (Timer / LF trigger / RF trigger) DATA 0 DATA 1 DATA 0 or DATA 1, depend on the EVENT/State Unknown, or DATA loss in MCU sleep state Not implemented DATA kept during SLEEP state Accessible ESFR on TPIC82000 Reserved ( Not Used ) Reserved ( by MCU Core ) Reserved (for FW & Internal use) Figure 3-1. ESFR Table (Address FF-D8) 16 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 3.2.4.2 SLDS189 - MAY 2012 ESFR Table (Continued) ESFR Address D7 D6 D5 D4 D3 D2 D1 D0 CF Write Register Reset ( Note 1) Power on Timer ( Note 2) 0000 1110 000S SSSS Name RC-OSC ModCONT ModScale ModOffset PSW 0X00 0000 0X00 0000 UUUU UUUU UUUU UUUU UUUU UUUU UUUU UUUU 0000 0000 0000 0000 - CE CD CC CB CA C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 BF BE BD BC BB BA B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 AF AE AD AC Note 1 Note 2 Power on Timer Name RC-OSC PSW Read Register Reset( Note 1) Power on Timer 0000 1110 000S SSSS 0000 0000 0000 0000 0000 0000 DDDD DDDD XX00 0000 XXDD DDDD DD00 0000 DD00 0000 - LFwake1H LFwake1L ModTxData ModRamAdd ModRamData UUUU UUUU UUUU UUUU UUUU UUUU XXUU UUUU UUUU UUUU SSSS SSSS SSSS SSSS UUUU UUUU XXUU UUUU UUUU UUUU LFmodeRSSI LFagcSET LFdataC TimerLFwake 0UUU UUXX 0SSS SSXX XXUU UUUU XXSS SSSS UUUU UUUU SSSS SSSS 1111 1111 SSSS SSSS PLLlocalOSC BuRAM_DATA 1000 0000 1000 0000 UUUU UUUU SSSS SSSS SensorDC6 SensorDC5 SensorDC4 SensorDC3 SensorDC2 SensorDC1 SensorDC0 IP SensorBaseH SensorBaseL SensorOffsetH SensorOffsetL SensorCONT LFANT LFwake0H P3 LFwake0L LFsync1 LFsync0 LFpLT 0000 0000 X000 0000 X000 0000 X000 0000 X000 0000 X000 0000 X000 0000 1111 1111 XXX0 0000 0000 0000 XX00 0000 0000 0000 0000 0000 UUUU UUUU UUUU UUUU 1111 1111 UUUU UUUU XUUU UUUU UUUU UUUU UUUU UUUU 0000 0000 X000 0000 X000 0000 X000 0000 X000 0000 X000 0000 X000 0000 1111 1111 XXX0 0000 0000 0000 XX00 0000 0000 0000 0000 0000 SSSS SSSS SSSS SSSS 1111 1111 SSSS SSSS XSSS SSSS SSSS SSSS SSSS SSSS LFstate LFagcSET TESTvector BuRAM_DATA SensorState IP P3 - UUUU UUUU SSSS SSSS 00UX XXXX 00UX XXXX 1111 1111 1111 1111 1111 1111 1111 1111 Initial value from Power-On-Reset Initial value from WAKEUP-EVENT (Timer / LF trigger / RF trigger) 0 1 D U X S DATA 0 DATA 1 DATA 0 or DATA 1, depend on the EVENT/State Unknown, or DATA loss in MCU sleep state Not implemented DATA kept during SLEEP state Accessible ESFR on TPIC82000 Reserved ( Not Used ) Reserved ( by MCU Core ) Reserved (for FW & Internal use) - Figure 3-2. ESFR Table (Address D7-AC) FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 17 TPIC82000 Series SLDS189 - MAY 2012 3.2.4.3 www.ti.com ESFR Table (Continued) Write Register Reset( Note 1) Power on Timer UUUU UUUU SSSS SSSS UUUU UUUU SSSS SSSS Read Register Reset( Note 1) Power on Timer ESFR Address Name AB AA A9 A8 A7 A6 A5 A4 LFpUT LFrssiVT IE LFOSC LFdelay LFbias LFmode A3 EEpromData X000 0000 X000 0000 EEpromData A2 A1 A0 9F 9E 9D 9C 9B 9A 99 98 97 96 95 94 93 92 91 90 8F 8E 8D 8C 8B 8A 89 88 87 86 85 84 83 82 81 80 RFdetCONT BuRAM_ADDR P2 ( Not Usable ) SBUF SCON TimerOSC TimerPre TimerPost SystemPower BPL BPU TESTvector P1 ( Not Usable ) TH1 TH0 TL1 TL0 TMOD TCON PCON XtalBias TESTmux1 TESTmux0 DPH DPL SP P0 ( Not Usable ) 000X XXXU 0000 0000 1111 1111 UUUX XXXU 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 100X XXXX 0000 0000 XX00 0000 0000 0000 1111 1111 0000 0000 0000 0000 0SSS SSSS SSSS SSSS SSSS SSSS 100X XXXX 0000 0000 XX00 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 XXXX 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 XXXX 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 BuRAM_ADDR P2 ( Not Usable ) SBUF SCON TimerPost P1 (Not Usable ) TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP P0 ( Not Usable ) Note 1 Note 2 Power on Timer 0 1 D U X S - 0000 0000 0000 0000 UUUU UUUU SSSS SSSS UUUU UUUU SSSS SSSS UUUU UUUU SSSS SSSS 0UUU UUUU 0SSS SSSS Name IE - 0000 0000 0000 0000 0UUU UUUU 0SSS SSSS (E2prom) (E2prom) 0000 0000 1111 1111 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 DDDD DDDD 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 1111 1111 Initial value from Power-On-Reset Initial value from WAKEUP-EVENT (Timer / LF trigger / RF trigger) DATA 0 DATA 1 DATA 0 or DATA 1, depend on the EVENT/State Unknown, or DATA loss in MCU sleep state Not implemented DATA kept during SLEEP state Accessible ESFR on TPIC82000 Reserved ( Not Used ) Reserved ( by MCU Core ) Reserved (for FW & Internal use) Figure 3-3. ESFR Table (Address AB-80) 18 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 3.2.5 SLDS189 - MAY 2012 Battery Backup External-RAM (BuRAM) On the TPIC82000 device, the 128-byte RAM area is prepared as the Battery Backup External-RAM on the device and can be used to store status parameters for TPMS applications while the device is in sleep mode. The BuRAM area is structured as the volatile memory but is backed up by internal regulator voltage while in sleep mode. Right after Power-on-Reset, the data contents of RAM are not initialized. 3.2.5.1 CRC (Cyclic Redundancy Check) Generator Function BuRAM has an 8-bit CRC generator of BuRAM memory, which is shown in Section 3.2.5.2. The CRC calculation is done through the following steps: 1. Set the CRC calculation start address (SAR) of BuRAM memory. 2. Set the CRC calculation end address (EAR) of BuRAM memory with CRCON = 1. - When CRCON is set to 1, CRC calculation starts from SAR to EAR data of the BuRAM memory. - Each CRC calculation is done by every system clock cycle. - CRC initial value is 0xFF. - If SAR and EAR are the same, the CRC calculation result is one address calculation. - If SAR > EAR, calculation starts from SAR to 127 and continuously calculates 0 to EAR. 3. When CRC calculation is done, the status bit (BuRAM_CRC_Status [7]) turns to 1. This flag is cleared by setting CRCON bit to 0. 4. The CRC calculation result appears in the BuRAM_CRC_Result register. 3.2.5.2 BuRAM with CRC Generator Block Diagram R/W R/W 0xA1<6:0> BuRAM_ADDR<6:0> 0xA1<7> EN_BuRAM R/W 0xA1<6:0> BuRAM_ADDR<6:0> R/W 0xC1<7:0> BuRAM_DATA<7:0> R/W R/W 0xDE<7> CRCON Rdata<6:0> Address Control A<6:0> R 128-Byte RAM R/W 0xDC<7:0> BuRAM_CRC_Result<7:0> R Wdata<6:0> R 0xDE<6:0> BuRAM_CRC_End_Adr<6:0> 0xDD<7> Status 0xDE<6:0> BuRAM_CRC_End_Adr<6:0> CRC Calculation 0xDF<6:0> BuRAM_CRC_Start_Adr<6:0> R/W 0xC1<7:0> BuRAM_DATA<7:0> Results/ Status CRC Start R/W 0xDF<6:0> BuRAM_CRC_Start_Adr<6:0> SLDS189-015 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 19 TPIC82000 Series SLDS189 - MAY 2012 3.2.5.3 www.ti.com 8-bit CRC Polynomial Expression The CRC generator uses the following 8-bit polynomial expression shown in Figure 3-4 8 2 1 Exclusive OR 8-bit polynomial expression: X + X + X + 1 CRC Generator CRC[7:0] is initialized at 0xFF before CRC Calculation Start. CRC[0] D CRC[1] Q D Q CRC[2] D Q CRC[3] D Q CRC[4] CRC[5] Q D D Q CRC[6] D Q CRC[7] D Q Serial Data Input (MSB First) Figure 3-4. CRC Generator 8-bit Polynomial Expression 3.2.5.4 Timing Chart of CRC Calculation from Start Address Calculation Start timing chart CLK MCUdatabus<7:0> SAR[6:0] EAR[6:0] CRCON 20 EAR SAR EAR calculation start RAM Addr<6:0> SAR SAR+1 CRC result<7:0> Preset CRC SAR FUNCTION DESCRIPTION SAR+2 SAR+3 CRC SAR+1 CRC SAR+2 Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 3.2.5.5 SLDS189 - MAY 2012 Timing Chart of CRC Calculation at the End Address Calculation End timing chart CLK EAR[6:0] EAR RAM Addr<6:0> EAR-1 CRC result<7:0> CRC EAR-2 EAR CRC EAR-1 CRC EAR CRCStatus 3.2.5.6 calculation end Battery Backup External-RAM (BuRAM) Control ESFR M Battery backup RAM Read/Write Address Control ESFR: 0xA1 BIT 7 BuRAM_ADDR BIT 6 Not Bit Addressable BIT 5 BIT 4 EN_BuRAM Access At Power on reset At Timer reset EN_BuRam r/w 0 0 BuRAM_ADDR<6:0> BIT 7 BIT 2 BIT 1 BIT 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 BIT 3 BIT 2 BIT 1 BIT 0 r/w U S r/w U S r/w U S r/w U S BIT 3 BIT 2 BIT 1 BIT 0 r/w 0 0 r/w 0 0 r/w r/w r/w 0 0 0 0 0 0 BuRAM Read/Write access control bit 1 = Access Enable 0 = Access Disable BuRAM Read/Write Address M Battery backup RAM Read/Write DATA Register ESFR: 0xC1 BIT 3 BuRAM_ADDR<6:0> BuRAM_DATA BIT 6 Not Bit Addressable BIT 5 BIT 4 BuRAM_DATA<7:0> Access At Power on reset At Timer reset r/w U S BuRAM_DATA<7:0> r/w U S r/w U S r/w U S BuRAM Read/Write DATA M Battery backup RAM CRC Start Address Register ESFR: 0xDF BIT 7 Not Bit Addressable BuRAM_CRC_Start_Adr BIT 6 BIT 5 - Access At Power on reset At Timer reset - x x BuRAM_CRC_Start_Adr<6:0> BIT 4 BuRAM CRC Start Adr<6:0> r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 CRC calculation start address FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 21 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com M Battery backup RAM CRC End Address Register ESFR: 0xDE BIT 7 Not Bit Addressable BuRAM_CRC_End_Adr BIT 6 BIT 5 BIT 4 CRCON Access At Power on reset At Timer reset r/w 0 0 CRCON BuRAM_CRC_End_Adr<6:0> r/w 0 0 r/w 0 0 BIT 7 r/w 0 0 r 0 At Timer reset 0 Status BIT 1 BIT 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 BIT 3 BIT 2 BIT 1 BIT 0 Not Bit Addressable BuRAM_CRC_Status BIT 6 BIT 5 BIT 4 Status Access At Power on reset BIT 2 CRC calculation: (1), Normal mode: (0) CRC calculation end address M Battery backup RAM CRC Status Register ESFR: 0xDD BIT 3 BuRAM CRC End Adr<6:0> -- - x - x - x - x - x - x - x x x x x x x x BIT 3 BIT 2 BIT 1 BIT 0 r 1 1 r 1 1 r 1 1 CRC calculation: Done: (1), BUSY: (0) Cleared to 0 when CRCON = 0 M Battery backup RAM CRC Result Register ESFR: 0xDC BIT 7 Not Bit Addressable BuRAM_CRC_Result BIT 6 BIT 5 BIT 4 BuRAM CRC Result<7:0> Access At Power on reset At Timer reset r 1 1 BuRAM_CRC_Result<7:0> 3.2.6 r 1 1 r 1 1 r 1 1 r 1 1 CRC calculation Result Non-volatile EEPROM In the TPIC82000 device, the 7-bits x 43-words of EEPROM are available as non-volatile data storage for the various variable parameters. All 7-bits can be used for data storage or the register can be configured for 3-bits Error Correction Code (ECC) + 4-bits of Data. NOTE This EEPROM area is also used for the trimming/calibration parameter storage by TI and firmware. Therefore, the actual accessible area for the user is limited for address 0x02 to 0x0F. The interface board and Support Software are prepared to support the EEPROM programming. 22 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 3.2.6.1 SLDS189 - MAY 2012 EEPROM Block Diagram EEPROM Block Diagram W 0xA 3 EEpromData<6:0> D<6:0> I/O R Address Decoder D<6:0> 0xA3 EEpromData<6:0> EEPROM Memory Rore Array ADR<39:0> 0xF9 W EEpromCONT<5:0> W W Write Enable Control 0xF9 EEpromCONT<6> 0x91 ON TESTvector<7:0>=0x3B VPP Programming Voltage Generator VREF Ibias W Ibias TVO RF Detector ANT DAC 0xA 2 RFdetCONT<7> W 0xF 3 AntDac<7:0> SLDS189-019 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 23 TPIC82000 Series SLDS189 - MAY 2012 3.2.6.2 www.ti.com EEPROM Unit Structure and DATA/ECC Implementation EEPROM is mapped on the ESFR space. It has a 43 words memory unit. Each unit has 7 bits (D6:D0). The upper three bits (D6:D4) are allocated for Error Correcting Code (ECC) and the lower four bits (D3:D0) are for data. The ECC contains Hamming codes. Hamming codes can detect up to two simultaneous bit errors, and correct single-bit errors. The Hamming codes are calculated by the following equations: D4 = D2 XOR D1 XOR D0 D5 = D3 XOR D1 XOR D0 D6 = D3 XOR D2 XOR D0 ECC DATA One Word D6 D5 D4 Hamming Codes 24 D3 D2 D1 D0 1 1 1 7 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 4 0 0 1 0 2 0 1 1 3 0 0 1 1 3 0 1 0 2 0 1 0 0 4 1 0 1 5 0 1 0 1 5 0 0 1 1 0 1 1 0 6 1 1 0 6 0 1 1 1 7 0 0 1 1 1 0 0 0 8 1 1 0 6 1 0 0 1 9 0 1 0 2 1 0 1 0 A 1 0 1 5 1 0 1 1 B 1 0 0 4 1 1 0 0 C 0 1 1 3 1 1 0 1 D 1 1 1 7 1 1 1 0 E 0 0 0 0 1 1 1 1 F FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 3.2.6.3 SLDS189 - MAY 2012 EEPROM Programming Procedure Start Step 0 Disable write protect bit Step 1 VREF input set to 0 V Step 2 Ibias supply to 12-V pump turns ON Step 3 Set the programming address with read mode Step 4 Set the programming data with ECC Setup Step 5 Wait 10 s Step 6 Enable the programming mode Step 7 VPP goes to 0.0 V (Set to initial voltage) Step 8 Wait 10 s Step 9 VPP goes to 12.4 V (Program start) Step 10 Wait 20 ms (Program time) Step 11 VPP goes to 0 V (Program END) Step 12 Wait 10 s Step 13 Disable the programming mode Step 14 Ibias supply to 12-V pump turns off Writing Release END SLDS189-021 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 25 TPIC82000 Series SLDS189 - MAY 2012 Step www.ti.com Register Setting Values TestVector 0x91 0X3B Disable write protect 1 AntDac 0xF3 0X00 (OFF) VREF input set to 0 V 2 RFdetCONT 0xA2 0X80 (ON) Ibias supply to 12 V PUMP turns on EEprom CONT 0xF9 0x00-0x2A (Write address) + 0x00 (Read mode) (1) Set the programming address with read mode EEprom Data 0xA3 0x00-0x7F (Write data) Set the programming data with ECC EEprom CONT 0xF9 0x00-0x2A (Write address) + 0x40 (Write mode) (1) Enable the programming mode AntDac 0xF3 0x00 (OFF) 0xC0 (ON) VPP goes to the initial voltage (0 V) AntDac 0xF3 0x17 (1.24 V) + 0xC0 (ON) 3 4 5 6 7 (2) Wait 10 s 8 9 Wait 10 s 11 AntDac 0xF3 0x00 (OFF) EEprom CONT 0xF9 0x00-0x2A (Write address) + 0x00 (Read mode) Disable the programming mode RFdet CONT 0xA2 0x00 (OFF) Ibias supply to 12 V PUMP turns off 12 13 14 26 VPP goes to 12.4 V (Programming voltage) Programming time 20 ms at typical is controlled by firmware. 10 (1) (2) Operation 0 VPP goes to 0 V (Forced to GND) Wait 10 s The user areas of EEPROM are assigned from 0x02 to 0x0F. The other areas are reserved for TI internal use and are not usable. For steps 7-9: The AntDac register should be set to the value of 0xC0 to define the initial voltage of TVO to 0 V. After the register setting, wait about 10 s. Then the AntDac register is set to the value of 0xD7 to bias the TVO voltage to 1.24 V. The programming voltage generator generates 12.4 V by using the TVO voltage of 1.24 V at typical condition, and the programming voltage can be changed by using the AntDac register. For step 10: programming time is set to 20 ms. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 3.2.6.4 SLDS189 - MAY 2012 EEPROM Control ESFR M EEprom Write Address Register ESFR: 0xF9 BIT 7 - Access At Power on reset At Timer reset - x x EEpromWrite EEpromWRadd<5:0> Not Bit Addressable EEpromCONT BIT 6 BIT 5 BIT 4 w 1 1 w 1 1 EEpromWrite BIT 1 BIT 0 w 1 1 w 1 1 w 1 1 W 1 1 BIT 3 BIT 2 BIT 1 BIT 0 w 0 0 w 0 0 w 0 0 ON: (1), OFF: (0) EEprom Write address Not Bit Addressable ESFR: 0xA3 BIT 7 EEpromData BIT 6 BIT 5 BIT 4 - Access At Power on reset At Timer reset - x x EEpromData<6:0> EEpromData<6:0> w 0 0 w 0 0 w 0 0 EEprom DATA Not Bit Addressable ESFR: 0xA3 BIT 7 EEpromData BIT 6 BIT 5 BIT 4 Testout Access At Power on reset At Timer reset r 0 0 Testout EEpromData<6:0> BIT 3 BIT 2 BIT 1 BIT 0 r U S r U S r U S EEpromData<6:0> r U S r U S r U S Test output EEprom DATA r U S Note: This Register is common to RFdetThres<7:0> M Test Mode Control Not Bit Addressable ESFR: 0x91 BIT 7 Access At Power on reset At Timer reset w 0 0 Note: This Register is common to RFdetThres<7:0> M EEprom DATA Register TESTvector BIT 6 - - w 0 0 w 0 0 TestVector<5:0> BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 w 0 0 w 0 0 TestVector<5:0> w 0 0 w 0 0 w 0 0 w 0 0 Test Vector Setting; M TestVector<5:0> = 0x3B; Enable to Write access of the EEprom (Upper address: 0x10 to 0x27) M RF Detector Control Not Bit Addressable ESFR: 0xA2 RFdetPower BIT 2 EEpromWRadd<5:0> w 0 0 M EEprom DATA Register Access At Power on reset At Timer reset BIT 3 BIT 7 RFdetCONT BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 RFdetPower - - - - - - - w 0 U w 0 U w 0 U - x x - x x - x x - x x w U U EEPROM Bias Power Control BIT 0 Note: This bit is consolidated with RF Detector Power Control. M1 = Power On, 0 = Power Off FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 27 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com M TX ANT-Tuning DAC control ESFR: 0xF3 BIT 7 ANTdacPower SEL_PumpCk w 0 U w 0 U Access At Power on reset At Timer reset ANTdacPower BIT 5 BIT 4 BIT 3 BIT 2 ANTDAC<5:0> BIT 1 BIT 0 w 0 U w 0 U ANTDAC<5:0> w 0 U w 0 U w 0 U Control the EEPROM programming voltage generator power On/Off M0 = Power Off, 1 = Power ON Charge Pump Clock select: MAlways keep to 1 (Internal Oscillator) EEPROM Programming Voltage Control MSet to 0x17 (= 1.24 V) for EEPROM programming SEL_PumpCK 3.2.7 Not Bit Addressable AntDac BIT 6 w 0 U Note: These Register bits are commonly used with Antenna Tuning DAC Control. MCU8051 Registers This section describes the internal registers used in the MCU. All I/O, timer/counter and UART operations for the MCU 8051 core are accessed via specific ESFRs. These registers occupy the direct internal data memory spaces of 0x80 to 0xFF. 3.2.7.1 MCU8051 Core SFR Map Description Port0 (1) Stack Pointer Label Address Reset Value Bit Addressable P0 0x80 0xFF O SP 0x81 0x07 Data Pointer Low Byte DPL 0x82 0x00 Data Pointer High Byte DPH 0x83 0x00 PCON 0x87 0x00 Power Control Register (1) Timer / Counter Control (1) Timer / Counter Mode Control Timer / Counter 0 Low Byte TCON 0x88 0x00 TMOD 0x89 0x00 TL0 0x8A 0x00 Timer / Counter 1 Low Byte TL1 0x8B 0x00 Timer / Counter 0 High Byte TH0 0x8C 0x00 Timer / Counter 1 High Byte TH1 0x8D 0x00 Port1 (1) O P1 0x90 0xFF O Serial Control Register SCON 0x98 0x00 O Serial Data Buffer SBUF 0x99 0x00 P2 0xA0 0xFF O Port2 (1) Interrupt Enable Register 0 Port3 (1) (1) Interrupt Priority Register 0 (1) Program Status Word Accumulator (1) 28 IE 0xA8 0x00 O P3 0xB0 0xFF O IP 0xB8 0xFF O PSW 0xD0 0x00 O A 0xE0 0x00 O The following functions and/or registers are not implemented on this device instead the standard 8051 core has: * Port 0 (0x80), Port 1 (0x98), Port 2 (0xA8) are not connected physically or usable. * Bit 2 to bit 6 of Port 3 are not physically connected or usable as a general I/O port. * Extended functions assigned on Port 3 at bit 3 (NINT1), bit 4 (TO), bit 5 (T1) are not connected or usable. * External Interrupt functions for IE1 and Extended Interrupt functions IE5 through IE13 are not supported or usable. * Based on 4), the Internal Enable Register 1 (IE1) (0xE8) is not configured or usable. * Based on 4), the Interrupt Priority Register 1 (IP1) (0xF8) is not configured or usable. * Based on 4), the control bits of External Interrupt 1 and 5 related functions on the Interrupt Enable Register 0 (IE) (0xA8), bit 2 (EX1) and bit 5 (EI5) are not configured or usable. * Based on 4), the control bits of External Interrupt 1 and 5 related functions on the Interrupt Priority Register 0 (IP) (0xB8), bit 2 (PX1) and bit 5 (PI5) are not configured or usable. * Based on 4), the related control bits of IE1 control on Timer/Counter Register (TCON), bit 2 (IT 1) and bit 3 (IE1) are not configured or usable. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 Description Interrupt Enable Register 1 (1) Label Address Reset Value Bit Addressable IE1 0xE8 0x00 O B 0xF0 0x00 O IP1 0xF8 0x00 O B Register Interrupt Priority Register 1 (1) 3.2.7.2 I/O PORT (P0,P1,P2,P3) On the 8051 MCU, P0, P1, P2 and P3 are assigned as the 32 quasi-bi-directional I/O lines. However, on the TPIC82000 device, only the ports P3<1:0> can be used for a general purpose I/O (GPIO), the others are not configured or usable. M I/O PORTS(P0,P1,P2,P3) (1) ESFR: 0xB0 Access At Power on reset At Timer reset Bit Addressable P3 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 - - - - - - P3<1> P3<0> r/w 1 1 r/w 1 1 r/w 1 1 r/w 1 1 r/w 1 1 r/w 1 1 w 1 1 r 1 1 Some of the Port 3 have alternate functions as shown below. BIT1: TXD BIT0: RXD (1) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 - - - - - NINT0 TXD RXD - - - - - input output Input output input Serial Transmit Data from UART and transmit clock in UART mode 0. Serial Receive Data to UART The functions NINT1, T0 and T1 originally assigned at bit 3, bit 4 and bit 5, respectively, on this extended register (on a standard 8051 core) are not supported or usable on the TPIC82000 device. 3.2.7.3 Stack Pointer (SP) The SP register contains the Stack Pointer. The Stack Pointer is used to load the program counter into internal data memory during LCALL and ACALL instructions and is used to retrieve the program counter from memory during RET and RETI instructions. Data may also be saved on or retrieved from the stack using PUSH and POP instructions. Instructions that use the stack automatically pre-increment or postdecrement the Stack Pointer. Therefore, the Stack Pointer always points to the last byte written to the stack, which is on the top of the stack. On reset, the Stack Pointer is set to 0x07. The programmer should ensure that the location of the stack in the internal data memory does not interfere with other data stored therein. M Stack Pointer (SP) Not Bit Addressable ESFR: 0x81 Access At Power on reset At Timer reset 3.2.7.4 SP BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SP<7> SP<6> SP<5> SP<4> SP<3> SP<2> SP<1> SP<0> r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 Data Pointer (DPTR) The Data Pointer (DPTR) is a 16-bit register that may be accessed via the two SFR locations, Data Pointer High Byte (DPH) and Data Pointer Low Byte (DPL). Two true 16-bit operations are allowed on the Data Pointer: load immediate and increment. The Data Pointer is used to form 16-bit addresses for the External Data Memory Accesses (MOVX), for program byte moves (MOVC) and for indirect program jumps (JMP @A+DPTR). On reset, the Data Pointer is set to 0x0000. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 29 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com M Data Pointer (DPTR) Not Bit Addressable ESFR: 0x82 BIT 7 Access At Power on reset At Timer reset BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DPTR<7> DPTR<6> DPTR<5> DPTR<4> DPTR<3> DPTR<2> DPTR<1> DPTR<0> r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 ESFR: 0x83 BIT 7 Access At Power on reset At Timer reset 3.2.7.5 DPL BIT 6 DPH BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DPTR<15> DPTR<14> DPTR<13> DPTR<12> DPTR<11> DPTR<10> DPTR<9> DPTR<8> r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 8051 Power Control Register (PCON) The Power Control Register (PCON) controls the power mode and Serial I/F Baud Rate of the 8051 core. The power supply for the 8051 core on this device is controlled by the System Power Control block and System Power Control Register (ESFR: 0x94). Refer to Section 3.3 for more detail about the device power control. M Power Control Register (PCON) ESFR: 0x87 BIT 7 Not Bit Addressable PCON BIT 6 BIT 5 BIT 4 r/w 0 0 r/w 0 0 SMOD Access At Power on reset At Timer reset r/w 0 0 r/w 0 0 BIT 3 BIT 2 BIT 1 BIT 0 GF1 GF0 PD IDL r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 The bit definitions for this register are: BIT7: SMOD Double baud rate bit. For use, see the Serial Interface section. BIT3: GF1 General purpose flag bit BIT2: GF0 General purpose flag bit BIT1: PD Power-Down bit. If 1, Power-Down mode is entered. BIT0: IDL Idle bit. If 1, Idle mode is entered. 30 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 3.2.7.6 SLDS189 - MAY 2012 Timer/Counter Registers Two 16-bit timer/counters are provided. TCON and TMOD are used to set the mode of operation and to control the running and interrupt generation of the timer/counters. The timer/counter values are stored in two pairs of 8-bit registers (TL0, TH0, and TL1, TH1). 3.2.7.6.1 Timer/Counter Control (TCON) M Timer/Counter Register (TCON) ESFR: 0x88 BIT 7 Access At Power on reset At Timer reset Bit Addressable TCON BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TF1 TR1 TF0 TR0 - - IE0 IT0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 The bit definitions for this register are: Timer 1 overflow flag. Set by hardware when Timer/Counter 1 overflows. Cleared by hardware when Timer1 BIT7: TF1 the processor calls the interrupt service routine. Timer1 BIT6: TR1 Timer 1 run control. If 1, timer runs; if 0, timer is halted. Timer 0 overflow flag. Set by hardware when Timer/Counter 0 overflows. Cleared by hardware when Timer0 BIT5: TF0 the processor calls the interrupt service routine. Timer0 BIT4: TR0 Timer 0 run control. If 1, timer runs; if 0, timer is halted. External BIT3: IE1 External Interrupt 1 edge flag. Set by hardware when an External Interrupt 1 edge is detected. Interrupt1 (1) External External Interrupt 1 control bit. If 1, External Interrupt 1 is edge-triggered; if 0, External Interrupt 1 is BIT2: IT1 Interrupt1 (1) level triggered. External Interrupt0 BIT1: IE0 External Interrupt 0 edge flag. Set by hardware when an External Interrupt 0 edge is detected. External Interrupt 0 control bit, if 1, External Interrupt 0 is edge-triggered; if 0, External Interrupt 0 is External Interrupt0 BIT0: IT0 level triggered. (1) External Interrupt related functions IE1 and IT1 that are assigned at bit 2 and bit 3, respectively, in the TCON register (in a standard 8051 core) are not supported or usable on the TPIC82000 device. 3.2.7.6.2 Timer/Counter Mode (TMOD) M Timer/Counter Mode (TMOD) ESFR: 0x89 BIT 7 Access At Power on reset At Timer reset Not Bit Addressable TMOD BIT 6 - - r/w 0 0 r/w 0 0 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 M1(1) M0(1) GATE0 CNT0 M1(0) M0(0) r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 The bit definitions for this register are: Timer1 (1) BIT7: GATE1 Timer1 (1) Timer1 Timer1 BIT6: CNT1 BIT5: M1(1) BIT4: M0(1) Timer0 BIT3: GATE0 Timer0 Timer0 Timer0 BIT2: CNT0 BIT1: M1(0) BIT0: M0(0) (1) Timer 1 gate flag. When TCON.6 is set and GATE1 = 1, Timer/Counter 1 only runs if the NINT1 pin is 1 (hardware control). When GATE1 = 0, Timer/Counter 1 only runs if TCON.6 = 1 (software control). Timer/Counter 1 selector, if 0, input is from the internal system clock; if 1, input is from the T1 pin. Timer 1 Mode control bit M1 Timer 1 Mode control bit M0 Timer 0 gate flag. When TCON.4 is set and GATE0 = 1, Timer/Counter 0 only runs if the NINT0 pin is 1 (hardware control). When GATE0 = 0, Timer/Counter 0 only runs if TCON.4 = 1 (software control). Timer/Counter 0 selector. If 0, input is from the internal system clock; if 1, input is from the T0 pin. Timer 0 Mode control bit M1 Timer 0 Mode control bit M0 On the TPIC82000 device, the interrupt pins NINT1 and T1 are not supported. Therefore, the GATE1 and CNT1 functions assigned at bit 7 and bit 6, respectively, in the TMOD register (in a standard 8051 core) are not usable. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 31 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com For both timer/counters, the mode bits M0 and M1 apply as shown in the following table: M1 M0 Operating Mode 0 0 13-bit timer/counter (M8048 compatible mode) 0 1 16-bit timer/counter 1 0 8-bit auto-reload timer/counter 1 1 Timer 0 is split into two halves. TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer/counter controlled by the standard Timer 1 control bits. TH1 and TL1 are held (Timer 1 is stopped). 3.2.7.6.3 Timer/Counter Data (TL0 TL1 TH0 TH1) TL0 and TH0 are the low and high bytes of Timer/Counter 0 respectively. TL1 and TH1 are the low and high bytes of Timer/Counter 1, respectively. In Mode 2, the TL register is an 8-bit counter and TH stores the reload value. On reset, all timer/counter registers are 0x00. M Timer/Counter Data (TL0 TL1 TH0 TH1) ESFR: 0x8A Access At Power on reset At Timer reset TL0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TL0<7> TL0<6> TL0<5> TL0<4> TL0<3> TL0<2> TL0<1> TL0<0> r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 ESFR: 0x8B Access At Power on reset At Timer reset TL1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TL1<7> TL1<6> TL1<5> TL1<4> TL1<3> TL1<2> TL1<1> TL1<0> r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ESFR: 0x8C BIT 7 Access At Power on reset At Timer reset TH0<6> TH0<5> TH0<4> TH0<3> TH0<2> TH0<1> TH0<0> r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 32 TH0 BIT 6 TH0<7> ESFR: 0x8D Access At Power on reset At Timer reset Not Bit Addressable TH1 BIT 6 TH1<7> TH1<6> TH1<5> TH1<4> TH1<3> TH1<2> TH1<1> TH1<0> r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 3.2.7.7 SLDS189 - MAY 2012 UART Registers The UART uses two SFRs, SCON and SBUF. SCON is the control register, and SBUF is the data register. Data is written to SBUF for transmission and SBUF is read to obtain received data. The received and transmitted data registers are independent. 3.2.7.7.1 UART Control (SCON) M UART Control (SCON) Bit Addressable ESFR: 0x98 Access At Power on reset At Timer reset BIT 7 SCON BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 SM0 SM1 SM2 REN TB8 RB8 TI RI r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 BIT 1 BIT 0 The bit definitions for this register are: BIT7: SM0 UART mode specifier BIT6: SM1 UART mode specifier BIT5: SM2 UART mode specifier BIT4: REN If 1, enables reception; if 0, disables reception. BIT3: TB8 In Modes 2 and 3, this is the ninth data bit sent. BIT2: RB8 In Modes 2 and 3, this is the ninth data bit received. In Mode 1, if SM2 = 0, this is the stop bit received. In Mode 0, this bit is not used. BIT1: TI Transmit interrupt flag. Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in other modes. Must be cleared by software. BIT0: RI Receive interrupt flag. Set by hardware at the end of the eighth bit in Mode 0, or at the half point of the stop bit in other modes. Must be cleared by software. The mode control bits operate as shown in the following table: SM0 SM1 Mode 0 0 0 Mode 0: 8-bit shift register Baud Rate = ftimer_clk / 2 Mode 1 0 1 Mode 1: 8-bit UART Baud Rate = (SMOD+1) * ftimer_clk / (32 * 2 * (256 - TH1)) Mode 2 1 0 Mode 2: 9-bit UART Baud Rate = (SMOD+1) * ftimer_clk / 64 Mode 3 1 1 Mode 3: 9-bit UART Baud Rate = (SMOD+1) * ftimer_clk / (32 * 2 * (256 - TH1)) (1) Operating Mode Baud Rate (1) Mode The ftimer_clk, is the frequency of the TIMER_CLK input (maximum = fcclk/2) and fcclk is the MCU clock frequency. SM2 enables multi-processor communication over a single serial line and modifies the above. In Modes 2 and 3, if SM2 is set then the receive interrupt is not generated if the received ninth data bit is 0. In Mode 1, the receive interrupt will not be generated unless a valid stop bit is received. In Mode 0, SM2 should be 0. 3.2.7.7.2 UART Data (SBUF) This register is used for both transmit and receive data. Transmit data is written to this location and receive data is read from this location, but the two paths are independent. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 33 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com M UART Data (SBUF) Not Bit Addressable ESFR: 0x99 BIT 7 Access At Power on reset At Timer reset 3.2.7.8 SBUF BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SBUF<7> SBUF<6> SBUF<5> SBUF<4> SBUF<3> SBUF<2> SBUF<1> SBUF<0> r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 Interrupt Registers The 8051 core on the TPIC82000 device provides the four standard 8051-compatible Legacy interrupts. The standard interrupts have separate enable register bits associated with them, allowing software control. They can also have two levels of priority assigned to them. The Standard Interrupts: The four standard interrupts are comprised of two timer overflow interrupts, an interrupt associated with the built-in serial interface for the core, and one external interrupt (referred to as Legacy external interrupts). The Two Timer Overflow Interrupts: TF0 and TF1, are set whenever Timer 0 or Timer 1, respectively, roll-over to zero. The states of these interrupts are also stored in the TCON register. TF0 and TF1 are automatically cleared by hardware on entry to the corresponding interrupt service routine. The Serial Interrupt: The serial interrupt source comprises the logical OR of the two serial interface status bits RI and TI in the register SCON. These are set automatically upon receipt or transmission of a data frame. These two bits are not cleared by hardware. The Legacy External Interrupts: NINT0 is driven from input PORT3 (see ). This interrupt may be either edge- or level-sensitive, depending on the settings within the TCON register. A further TCON register bit, IE0, acts as an interrupt flag. If the external interrupt is set to be edge-triggered, the corresponding register bit IE0 is set by a falling edge on NINT0 and cleared by hardware on entry to the corresponding interrupt service routine. If the interrupt is set to be level-sensitive, IE0 reflects the logic level on NINT0. (The TCON register is described in Section 3.2.7.6). NOTE 1. All events on NINT0, whether level-triggered or edge-triggered, are detected by sampling the relevant interrupt line on the rising edge of SCLK at the end of phase 1 of every machine cycle. Where NINT0 is level-triggered, a response is made to the signal being sampled low and, to ensure detection, the external source needs to hold the line low until the resulting interrupt is generated. (It also needs to ensure that the request is deactivated before the end of the associated service routine). Where NINT0 is edgetriggered, the response is made to a transition on the signal from high to low between successive samples. This means that to ensure detection, NINT0 needs to be high for at least two clocks before it goes low and then needs to be held low for at least two clocks after this transition. 2. On a standard 8051, the second Legacy External Interrupt (NINT1) is supported. However, on the TPIC82000 device, this function is not supported. The nine Extended Interrupts (IE5 through IE13) on standard MCU8051 are also not supported on the TPIC82000 device. 3.2.7.8.1 Interrupt Flag Clear If the Legacy External Interrupt (NINT0) is edge-triggered, the interrupt flag is cleared on vectoring to the service routine. If it is level-triggered, the flag is controlled by the external signal. Timer/counter flags are cleared on vectoring to the interrupt service routine but the serial interrupt flag is not affected by hardware. The serial interrupt flag should be cleared by software. Acknowledge signals are provided for clearing any registers used to source the nine additional interrupts. 34 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 3.2.7.8.2 Priority Levels / Interrupt Vectors One of two priority levels may be selected for each interrupt. An interrupt of a high priority may interrupt the service routine of a low priority interrupt and, if two interrupts of different priority occur at the same time, the higher level interrupt is serviced first. An interrupt cannot be interrupted by another interrupt of the same priority level. If two interrupts of the same priority level occur simultaneously, a polling sequence is observed. When an interrupt is serviced, a long call instruction is executed to one of the following locations, according to the interrupt source: Source Level Vector Address IE0 1 (Highest) External Interrupt 0 0x0003 TF0 2 Timer/Counter Interrupt 0 0x000B IE1 (1) 3 External Interrupt 1 0x0013 0x001B TF1 4 Timer/Counter Interrupt 1 RI+TI 5 Serial Interrupt 0x0023 IE5 (1) 6 External Interrupt 5 0x002B IE6 (1) 7 External Interrupt 6 0x0033 IE7 (1) 8 External Interrupt 7 0x003B IE8 (1) 9 External Interrupt 8 0x0043 IE9 (1) 10 External Interrupt 9 0x004B IE10 (1) 11 External Interrupt 10 0x0053 IE11 (1) 12 External Interrupt 11 0x005B IE12 (1) 13 External Interrupt 12 0x0063 14 (Lowest) External Interrupt 13 0X006B IE13 (1) Description (1) The Internal Interrupt 1 (IE1) and Extended Interrupts (IE5 through IE13) are not supported on TPIC82000 and are not usable. 3.2.7.8.3 Interrupt Latency The response time in a single interrupt system is between three and nine machine cycles. 3.2.7.8.4 Interrupt Enable Register 0 (IE) M Interrupt Enable Register 0 (IE) ESFR: 0xA8 Bit Addressable IE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 - ES r/w 0 0 r/w 0 0 r/w 0 0 EA Access At Power on reset At Timer reset r/w 0 0 BIT 2 BIT 1 BIT 0 ET1 - ET0 EX0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 For each bit in this register, a 1 enables the corresponding interrupt and a 0 disables it. BIT7: EA Enable or disable all interrupt bits BIT5: EI5 (1) Enable External Interrupt 5 BIT4: ES Enable Serial Port interrupt BIT3: ET1 Enable Timer 1 overflow interrupt BIT2: EX1 (1) Enable External Interrupt 1 BIT1: ET0 Enable Timer 0 overflow interrupt BIT0: EX0 Enable External Interrupt 0 (1) On the TPIC82000 device, the External Interrupt 1 (IE1) and Extended Interrupts (IE5 to ID13) are not supported. Therefore, the EX1 and EI5 function assigned at bit 2 and bit 5, respectively, on this IE register are not usable. Also, the Interrupt Enable Register 1 (IE1) Register (0xE8) is not configured or supported. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 35 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com 3.2.7.8.5 Interrupt Priority Register 0 (IP) M Interrupt Priority Register 0 (IP) ESFR: 0xB8 Bit Addressable IP BIT 7 Access At Power on reset At Timer reset BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 - - - PS PT1 - PT0 PX0 r/w 1 1 r/w 1 1 r/w 1 1 r/w 1 1 r/w 1 1 r/w 1 1 r/w 1 1 r/w 1 1 For each bit in this register, a 1 selects high priority for the corresponding interrupt and a 0 selects low priority. The allocation of interrupts to bits is: BIT5: PI5 (1) Select priority for External Interrupt 5 BIT4: PS Select priority for Serial Port interrupt BIT3: PT1 Select priority for Timer 1 overflow interrupt BIT2: PX1 (1) Select priority for External Interrupt 1 BIT1: PT0 Select priority for Timer 0 overflow interrupt BIT0: PX0 Select priority for External Interrupt 0 While an interrupt is being serviced, it may only be interrupted by a higher priority interrupt. (1) On the TPIC82000 device, the External Interrupt 1 (IE1) and Extended Interrupts (IE5 to ID13) are not supported. Therefore, the PX1 and PI5 functions assigned at bit 2 and bit 5, respectively, on this IE register are not usable. Also, the Interrupt Enable Register 1 (IE1) Register (0xE8) is not configured or supported. 3.2.7.9 Program Status Word (PSW) M Program Status Word (PSW) Bit Addressable ESFR: 0xD0 PSW BIT 6 BIT 7 Access At Power on reset At Timer reset BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CY AC F0 RS1 RS0 OV F1 P r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 This register contains status information resulting from CPU and ALU operation. The bit definitions are: BIT7: CY ALU carry flag BIT6: AC ALU auxiliary carry flag BIT5: F0 General purpose user-definable flag BIT4: RS1 Register Bank Select bit 1 BIT3: RS0 Register Bank Select bit 0 BIT2: OV ALU overflow flag BIT1: F1 User-definable flag BIT0: P Parity flag. Set each instruction cycle to indicate odd/even parity in the accumulator. The Register Bank Select bits operate as shown in the following table: 36 RS1 RS0 0 0 Register Bank Select RB0: Registers from 00 - 07 hex 0 1 RB1: Registers from 08 - 0F hex 1 0 RB2: Registers from 10 - 17 hex 1 1 RB3: Registers from 18 - 1F hex FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 3.2.7.10 Accumulator (ACC) This register provides one of the operands for most ALU operations. It is denoted as A in the instruction table. M Accumulator (ACC) Bit Addressable ESFR: 0xE0 BIT 7 Access At Power on reset At Timer reset ACC BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ACC<7> ACC<6> ACC<5> ACC<4> ACC<3> ACC<2> ACC<1> ACC<0> r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 3.2.7.11 B Register (B) This register provides the second operand for multiply or divide instructions, otherwise it may be used as a scratch pad register. M B Register (B) Bit Addressable ESFR: 0xF0 Access At Power on reset At Timer reset 3.2.8 B BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 B<7> B<6> B<5> B<4> B<3> B<2> B<1> B<0> r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 r/w 0 0 Instruction Definitions The MCU8051 Warp instruction set is shown in Table 3-2. Some of the features supported are outlined below. 3.2.8.1 Addressing Modes The instruction set provides a variety of addressing modes, which are outlined below. 3.2.8.1.1 Direct Addressing In direct addressing, the operand is specified by an 8-bit address field. Only internal data and SFRs may be accessed using this mode. 3.2.8.1.2 Indirect Addressing In indirect addressing, the operand is specified by an address contained in a register. Two registers (R0 and R1) from the current bank or the Data Pointer may be used for addressing in this mode. Both internal and external data memory may be indirectly addressed. 3.2.8.1.3 Register Addressing In register addressing, the operand is specified by the top 3 bits of the opcode, which selects one of the current bank of registers. Four banks of registers are available. The current bank is selected by bits 3 and 4 of the PSW. 3.2.8.1.4 Register Specific Addressing Some instructions only operate on specific registers. This is defined by the opcode. In particular many accumulator operations and some Stack Pointer operations are defined in this manner. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 37 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com 3.2.8.1.5 Immediate Data Instructions which use immediate data are 2 or 3 bytes long and the immediate operand is stored in program memory as part of the instruction. 3.2.8.1.6 Indexed Addressing Only program memory may be addressed using indexed addressing. It is intended for simple implementation of look-up tables. A 16-bit base register (either the PC or the DPTR) is combined with an offset stored in the accumulator to access data in program memory. 3.2.8.2 Arithmetic Instructions The M8051 Warp implements ADD, Add with Carry (ADDC), Subtract with Borrow (SUBB), Increment (INC) and Decrement (DEC) functions, which may be used in most addressing modes. There are three accumulator-specific instructions: Decimal Adjust A (DA A), Multiply A by B (MUL AB) and Divide A by B (DIV AB). 3.2.8.3 Logic Instructions The M8051 Warp implements AND Logical (ANL), OR Logical (ORL), and Exclusive-OR Logical (XRL) functions, which again may be used in most addressing modes. There are seven accumulator-specific instructions, Clear A (CLR A), Complement A (CPL A), Rotate Left A (RL A), Rotate Left through Carry A (RLC A), Rotate Right A (RR A), Rotate Right through Carry A (RRC A), and Swap Nibbles of A (SWAP A). 3.2.8.4 Data Transfers 3.2.8.4.1 Internal Data Memory Data may be moved from the accumulator to any internal data memory location, from any internal data memory location to the accumulator, and from any internal data memory location to any SFR or other internal data memory location. 3.2.8.4.2 External Data Memory Accessing to the external data memory is not supported by the TPIC82000 device. 3.2.8.5 Jump Instructions 3.2.8.5.1 Unconditional Jumps Four sorts of unconditional jump instructions are available. Short jumps (SJMP) are relative jumps (limited to -128 to +127 bytes), long jumps (LJMP) are absolute 16-bit jumps, and absolute jumps (AJMP) are absolute 11-bit jumps (in effect, within a 2K byte memory page). The last type is an Indexed jump (JMP @ A+DPTR) which jumps to a location contained in the DPTR register, and is offset by a value stored in the accumulator. 3.2.8.5.2 Subroutine Calls and Returns There are only two sorts of subroutine calls, absolute calls (ACALL) and long calls (LCALL). Two return instructions are provided: RET and RETI (RETI is for interrupt service routines). 3.2.8.5.3 Conditional Jumps Conditional jump instructions all use relative addressing, so they are also limited to the -128 to +127 byte range. 38 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 3.2.8.6 SLDS189 - MAY 2012 Boolean Instructions The bit-addressable registers in both direct and SFR space may be manipulated using boolean instructions. Logical functions are available which use the carry flag and an addressable bit as the operands and each addressable bit may be set, cleared, or tested in a jump instruction. 3.2.8.7 Flags The following instructions affect flags generated by the ALU: Table 3-1. Flags Instructions (1) Instruction (1) Flag C OV AC ADD ? ? ? ADDC ? ? SUBB ? ? MUL 0 DIV 0 DA Instruction Flag C CLRC 0 ? CPLC ? ? ANL C, bit ? ? ANL C, /bit ? ? ORL C, bit ? ? ORL C, /bit ? RRC ? MOV C, bit ? RLC ? CJNE ? SETB C 1 OV AC In this table, a 0 means the flag is always cleared, a 1 means the flag is always set and a ? means that the state of the flag depends on the result of the operation. The flag specified as blank means that the state is unknown. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 39 TPIC82000 Series SLDS189 - MAY 2012 3.2.8.8 www.ti.com Instruction Table Instructions are either 1, 2, or 3 bytes long, as listed in the Bytes column in Table 3-2. Each instruction takes either one, two, or four machine cycles to execute as listed in Table 3-2. One machine cycle comprises two CCLK clock cycles. Table 3-2. Instruction Table Mnemonic Description Bytes Cycles Hex code 28-2F ARITHMETIC ADD A,Rn Add register to A 1 1 ADD A,dir Add direct byte to A 2 1 25 ADD A,@Ri Add indirect memory to A 1 1 26-27 ADD A,#data Add immediate to A 2 1 24 ADDC A,Rn Add register to A with carry 1 1 38-3F ADDC A,dir Add direct byte to A with carry 2 1 35 ADDC A,@Ri Add indirect memory to A with carry 1 1 36-37 ADDC A,#data Add immediate to A with carry 2 1 34 SUBB A,Rn Subtract register from A with borrow 1 1 98-9F SUBB A,dir Subtract direct byte from A with borrow 2 1 95 SUBB A,@Ri Subtract indirect memory from A with borrow 1 1 96-97 SUBB A,#data Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08-0F INC dir Increment direct byte 2 1 05 INC @Ri Increment indirect memory 1 1 06-07 DEC A Decrement A 1 1 14 DEC Rn Decrement register 1 1 18-1F DEC dir Decrement direct byte 2 1 15 DEC @Ri Decrement indirect memory 1 1 16-17 INC DPTR Increment data pointer 1 2 A3 MUL AB Multiply A by B 1 4 A4 DIV AB Divide A by B 1 4 84 DA A Decimal Adjust A 1 1 D4 ANL A,Rn AND register to A 1 1 58-5F ANL A,dir AND direct byte to A 2 1 55 ANL A,@Ri AND indirect memory to A 1 1 56-57 ANL A,#data AND immediate to A 2 1 54 ANL dir,A AND A to direct byte 2 1 52 ANL dir,#data AND immediate to direct byte 3 2 53 ORL A,Rn OR register to A 1 1 48-4F ORL A,dir OR direct byte to A 2 1 45 ORL A,@Ri OR indirect memory to A 1 1 46-47 ORL A,#data OR immediate to A 2 1 44 ORL dir,A OR A to direct byte 2 1 42 ORL dir,#data OR immediate to direct byte 3 2 43 XRL A,Rn Exclusive-OR register to A 1 1 68-6F XRL A,dir Exclusive-OR direct byte to A 2 1 65 XRL A, @Ri Exclusive-OR indirect memory to A 1 1 66-67 XRL A,#data Exclusive-OR immediate to A 2 1 64 LOGICAL 40 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 Table 3-2. Instruction Table (continued) Mnemonic Description Bytes Cycles Hex code XRL dir,A Exclusive-OR A to direct byte 2 1 62 XRL dir,#data Exclusive-OR immediate to direct byte 3 2 63 CLR A Clear A 1 1 E4 CPL A Complement A 1 1 F4 SWAP A Swap Nibbles of A 1 1 C4 RL A Rotate A left 1 1 23 RLC A Rotate A left through carry 1 1 33 RR A Rotate A right 1 1 03 RRC A Rotate A right through carry 1 1 13 E8-EF DATA TRANSFER MOV A,Rn Move register to A 1 1 MOV A,dir Move direct byte to A 2 1 E5 MOV A,@Ri Move indirect memory to A 1 1 E6-E7 MOV A,#data Move immediate to A 2 1 74 MOV Rn,A Move A to register 1 1 F8-FF MOV Rn,dir Move direct byte to register 2 2 A8-AF MOV Rn,#data Move immediate to register 2 1 78-7F MOV dir,A Move A to direct byte 2 1 F5 MOV dir,Rn Move register to direct byte 2 2 88-8F MOV dir,dir Move direct byte to direct byte 3 2 85 MOV dir,@Ri Move indirect memory to direct byte 2 2 86-87 MOV dir,#data Move immediate to direct byte 3 2 75 MOV @Ri,A Move A to indirect memory 1 1 F6-F7 MOV @Ri,dir Move direct byte to indirect memory 2 2 A6-A7 MOV @Ri,#data Move immediate to indirect memory 2 1 76-77 MOV DPTR,#data Move immediate to data pointer 3 2 90 MOVC A,@A+DPTR Move code byte relative DPTR to A 1 2 93 MOVC A,@A+PC Move code byte relative PC to A 1 2 83 MOVX A,@Ri (1) Move external data (A8) to A 1 2 E2-E3 MOVX A,@DPTR (1) Move external data (A16) to A 1 2 E0 MOVX @Ri,A (1) Move A to external data (A8) 1 2 F2-F3 MOVX @DPTR,A (1) Move A to external data (A16) 1 2 F0 PUSH dir Push direct byte onto stack 2 2 C0 POP dir Pop direct byte from stack 2 2 D0 XCH A,Rn Exchange A and register 1 1 C8-CF XCH A,dir Exchange A and direct byte 2 1 C5 XCH A,@Ri Exchange A and indirect memory 1 1 C6-C7 XCHD A,@Ri Exchange A and indirect memory nibble 1 1 D6-D7 BOOLEAN CLR C Clear carry 1 1 C3 CLR bit Clear direct bit 2 1 C2 SETB C Set carry 1 1 D3 SETB bit Set direct bit 2 1 D2 CPL C Complement carry 1 1 B3 CPL bit Complement direct bit 2 1 B2 ANL C,bit AND direct bit to carry 2 2 82 (1) Since the accessing of External Memory is not supported on TPIC82000, the related instructions: MOVX A,@Ri, MOVX A, @DPTR, MOVX @Ri, A and MOVX DPTR,A are not usable. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 41 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com Table 3-2. Instruction Table (continued) Mnemonic Description Bytes Cycles Hex code ANL C,/bit AND direct bit inverse to carry 2 2 B0 ORL C,bit OR direct bit to carry 2 2 72 ORL C,/bit OR direct bit inverse to carry 2 2 A0 MOV C,bit Move direct bit to carry 2 1 A2 MOV bit,C Move carry to direct bit 2 2 92 BRANCHING ACALL addr 11 Absolute jump to subroutine 2 2 11F1 LCALL addr 16 Long jump to subroutine 3 2 12 RET Return from subroutine 1 2 22 RETI Return from interrupt 1 2 32 AJMP addr 11 Absolute jump unconditional 2 2 01E1 LJMP addr 16 Long jump unconditional 3 2 02 SJMP rel Short jump (relative address) 2 2 80 JC rel Jump on carry = 1 2 2 40 JNC rel Jump on carry = 0 2 2 50 JB bit,rel Jump on direct bit = 1 3 2 20 JNB bit,rel Jump on direct bit = 0 3 2 30 JBC bit,rel Jump on direct bit = 1 and clear 3 2 10 JMP @A+DPTR Jump indirect relative DPTR 1 2 73 JZ rel Jump on accumulator = 0 2 2 60 JNZ rel Jump on accumulator 0 2 2 70 CJNE A,dir,rel Compare A, direct jne relative 3 2 B5 CJNE A,#d,rel Compare A, immediate jne relative 3 2 B4 CJNE Rn,#d,rel Compare register, immediate jne relative 3 2 B8-BF CJNE @Ri,#d,rel Compare indirect, immediate jne relative 3 2 B6-B7 DJNZ Rn,rel Decrement register, jnz relative 2 2 D8-DF DJNZ dir,rel Decrement direct byte, jnz relative 3 2 D5 NOP No operation 1 1 00 MISCELLANEOUS In the Table 3-2, an entry such as E8-EF indicates a continuous block of hex opcodes used for eight different registers, the register numbers of which are defined by the lowest 3 bits of the corresponding code. Non-continuous blocks of codes, shown as 11F1 (for example), are used for absolute jumps and calls, the top 3 bits of the code are used to store the top 3 bits of the destination address. The CJNE instructions use the abbreviation #d for immediate data; other instructions use #data. 3.3 System Power Controller and Status Monitor The system power block controls the power on/off of the MCU and peripheral blocks. The system power block consists of a power supply block, a system power control block to control the MCU operation, wakeup trigger detectors, and control registers. The system can be awakened by one of the following trigger events: Power-on-Reset at the first time connection of the external power supply such as a lithium battery, LF receiver when the LF wake-up trigger signal is detected or Wake-up Timer which initiates the wake-up trigger signal periodically according to the preset interval timer value. 42 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 3.3.1 SLDS189 - MAY 2012 System Power Block Diagram Power Supply VDD_Peripheral VREG_MCU Ready Power-On-Reset RESET_TEST Pin (*) Timer-OSC and Wake-up Timer LF Signal H/W Reset Input Wake-up Timer Time Out Received LF Signal Wake-up Trigger Detector 0xEA Wakeup POR Wakeup H/W Reset (*) Wakeup Timer Wakeup LF trigger RD LF Receiver EN W 0x94 LFON WR 0x94 McuPower McuCKselect System Power Control Trigger Event Power-On-Reset MCU Power Control MCUON MCU Reset Control _InitMCU MCU CLK Selector SEL_CLK (*) RESET_TEST pin and H/W Reset function is available only on Mask ROM version. Figure 3-5. System Power Controller and Status Monitor 3.3.2 System Wake-up Operation To minimize the power dissipation of the system, the device can be programmed to stay in sleep mode and then wake up periodically to measure and transmit the necessary data using either the internal ultra low power timer or by detecting the LF trigger signal from the external control units. All mode transitions are controlled by the software, and therefore, the total power dissipation of the system will depend on the user's application program. This section describes the basic device state sequences shown in Figure 3-7 and Figure 3-6. Power-on-Reset: Just after the battery is attached, the device generates an internal Power_On_Reset signal to initialize the necessary blocks of the device. After the release of Power_On_Reset, the internal regulator starts up and then the internal clock system starts up following the Ready_VREG signal which indicates the regulator voltage is sufficient for system operation. Then, the MCU wakes up and starts the system initialization programs. After the completion of the system initialization sequence and necessary programs, the device enters into sleep mode, sets the appropriate registers and waits for the next wakeup timing signal from the internal timer. Timer Wake-up: If the system is set to measure and transmit the necessary data periodically, the device will wake up automatically with the pre-programmed internal timer, complete each required program for the sensor measurements and data transmission, and to go into sleep mode again. Since no external trigger signals are required to wake up the device, this operation sequence may provide the simplest system configuration. LF Wake-up: The device has an LF signal detection feature to wake up the device when the LF trigger command from the external system (Body Control ECU) is detected. This feature enables the device to sniff and compare the corresponding LF signals with the pre-configured internal logic circuit without waking up the MCU, which may consume more power for trigger event detection. Once the LF signal is detected and the ID and/or data pattern match is confirmed, the MCU wakes up and completes the required programmed operations. G-Detect Wake-up: The device can also start the programmed operations after the detection of the accelerator signals. In this mode, the MCU needs to be awakened by the internal timer first to start the accelerometer output measurement. Then, if the accelerometer output exceeds the preset value, the device performs the programmed operations, otherwise it will return to sleep mode. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 43 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com Wake-up from POR Sleep State Wake-up from Timer VDD VDD (Battery) GND 5 ms (TYP) Power-On-Reset GND MCUON GND Tvreg Tvreg 1.55 V (TYP) VREG_MCU (Internal) GND Flag: Ready_VREG GND SEL_CLK GND XTAL_CLK (2.4MHz) GND RC_CLK (2.4MHz) GND _initMCU GND System_CLK (2.4MHz) GND Set to Sleep Mode GND McuPower: 0x94<7> GND Wake-up Timer (Tpost) GND POR: oxEA<7> GND Wake-up LF trigger: 0xEA<5> GND Wake-up Timer: 0xEA<4> GND Figure 3-6. System Wake-up Timing 44 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 Battery Attach LF Detecting Mode: POR Release LF Pattern Matched Initialization Mode Internal Regulator ON LF Pattern Not Matched LF Pattern Detection LF Signal Exist Timer Wake-Up Time Out RC-OSC Start Timer-OSC Start G-Sense Wake-Up Time Out System Clock to MCU LF Signal Detect LF Signal Not Exist LF OSC On LF Wake-Up Time Out Interval Timer Timeout Interval Timer Reset and Start Sleep Mode If G Detect Mode Sleep G-Detect Mode G-Sensor CKT Enable MCU Start Read G-Sensor Value No G Detected G Detected Measurement/ Processing Mode: Measure and Data Processing Complete All Program and Set MCUON = L Not Send Data Tx Mode Need to Send Data Enable RF-Tx Block and X-Tal Oscillator Send Data Turn off RF-Tx Block and X-Tal Oscillator Main Flow Timer Wake-up Flow LF Wake-up Flow G -Sense Wake-up Flow Initial Setup Flow Figure 3-7. System Power On/Off State Diagram (Example) FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 45 TPIC82000 Series SLDS189 - MAY 2012 3.3.3 www.ti.com System Power Control ESFR M System Power control Register ESFR: 0x94 BIT 7 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 McuPower McuCKselect LFON - - - - - w 1 1 w 0 0 w 0 0 - x x - x x - x x - x x - x x Access At Power on reset At Timer reset McuPower Not Bit Addressable SystemPower BIT 6 Main Power (for MCU and Peripheral Analog Function) Off Control: To turn off the main power of the device and go into the sleep mode, set this bit to 0. At the following rising edge of the System Clock, the Power of the device is turned off. This bit is cleared (preset to 1) automatically by the internal logic circuit. The wake-up of the device is controlled by the Wakeup Events (POR, Timer, LF trigger) automatically. Main Clock (for MCU and Peripheral Analog Function) Select: XTAL-OSC (1), RC-OSC (0) LF Receiver ON: ON (1), OFF (0) Turn on the LF Receiver while the MCU is on. (LF Receiver wakes up only one time when this bit is set to 1, and aborted if no LF signal is detected.) McuCKselect LFON M System state Register Not Bit Addressable ESFR: 0xEA SystemState BIT 6 BIT 7 Wakeup POR Access At Power on reset At Timer reset r 0 1 Wakeup POR Wakeup H/W Reset FLAG Xtal clock - BIT 5 Wakeup LF trigger - x x r 1 D Status Flag of Wakeup by POR Status Flag of Wakeup by H/W Reset XTAL-OSC status: BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Wakeup Timer-1 Wakeup H/W Reset Flag Invalid Wakeup Timer-2 FLAG Xtal clock r 1 D r 0 0 r 1 D r 1 1 r 1 D Active (0), Not Active (1) Active (0), Not Active (1) Active (1), Not Active (0) (Valid for ROM version only) Bit 5 Bit 4 Bit 2 Bit 1 Wakeup LF Trigger Wakeup Timer-1 Flag_Inv alid Wakeup Timer 2 Status 0 1 1 1 A Standard LF Wakeup (Need to check whether status B occurs or not before going into sleep mode) (1) 0 0 1 1 B Timer Wakeup occurred after the standard LF Wakeup (Detect if this status is occurring or not before going into sleep mode) 1 0 1 0 C Standard Timer Wakeup 0 1 1 0 D Timer Wakeup and LF Wakeup occurs almost at the same time. 0 0 1 0 E 1 0 0 0 F Timer Wakeup occurs twice while the MCU is on. 0 0 0 0 G Timer Wakeup occurs twice while the MCU on by LF trigger. (4) (1) (2) (3) (4) 46 MCU Wakeup Status (When reading the System State just after MCU start up) (except status B) (1) (2) (3) (4) If the Timer Wakeup event occurs while processing LF command, the Timer Wakeup event won't affect the operation but the SystemState register bit 4 (Wakeup Timer-1) is set to 0. So, confirm the status of Wakeup Timer-1 after the completion of LF command processing and if the bit is set to 0, proceed with the Timer Wake-up operation. With this sequence, both LF Wakeup and Timer Wakeup functions are achieved at the same time without conflicts. If the reading of SystemState register is either D or E state, the LF Wakeup and Timer Wakeup occurs at almost the same time. In this case, make the application program process the LF Wakeup operation first and then complete the Timer Wakeup operation. The D status occurs when the LF Wakeup trigger is detected just after the down edge of the Timer Wakeup signal (before the MCU startup). And the E status occurs when the LF Wakeup trigger is detected just after the rising edge of the Timer Wake-up signal (before the MCU startup). In either case, the recommendation is to process the Timer Wakeup operation after the completion of the LF Wakeup command processes. The F and G status do not occur in normal application. They indicate that the MCU is not going into sleep mode properly and requires the Error Process by the application software. Status F indicates that the error condition is occuring while the MCU is on and status G indicates that the error condition occurs after the LF Wakeup. In addition, no other status except A to G should occur in the system. Therefore, if such a condition is detected, proceed to the Error Process. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 3.4 SLDS189 - MAY 2012 Internal Clocks System The TPIC82000 device has three main oscillator/clock systems: timer oscillator (Timer-OSC), RC oscillator (RC-OSC), and crystal oscillator (Xtal-OSC). An ultra low power Timer-OSC is used for the interval count for the periodical wake up of the whole system. The RC-OSC is mainly used for the MCU clock when operating the sensor blocks and processing the normal program. The Xtal-OSC is used for the MCU clock when operating the RF transmitter block and also to trim the Timer-OSC and RC-OSC. 3.4.1 Internal Clock System Block Diagram The Timer-OSC generates a 450 Hz (typical) clock for the interval time count of the system wake-up (PreTimer and Post-Timer) timing and LF Wakeup Timing. The RC-OSC generates a 9.6 MHz clock for the MCU main clock and sensor measurements. The Xtal-OSC generates a 19.7 MHz clock for the MCU main clock and for the RF data transmission. A multiplexor is used to select either the RC-OSC or the 1/2 divided Xtal-OSC outputs for the main clock of the MCU depending on the operation mode. In idle mode of the MCU, a 1/32 divided Xtal-OSC clock can be used at MCU for power savings. The Xtal-OSC output will also be used for the calibration of the Timer-OSC and RC-OSC to ensure the accuracy of the clock system. This trimming function can be achieved by the software. Preset Preset Timer-OSC 450 Hz Pre-Timer Timer Wakeup To System Power Control Post-Timer Trim LF Wakeup LF Wake-up Timer To LF Block Preset RC-OSC 9.6 MHz To MCU (For Auto Frequency Trimming) Div 256 en EN_Trim_RES (ESFR: 0xD7) Trim MUX1 XTAL Xtal-OSC 19.7 MHz Div 2 MUX2 0 Trim Div 32 Div 2 To System Power Control Div 2 To Clock Monitor 1 To MCU (Main Clock) 0 1 McuCKselect (ESFR: 0x94) Div 16 To MCU (For Auto Frequency Trimming) en EN_XTALdiv (ESFR: 0xD7) SEL_XTALdiv (ESFR: 0xD7) To PLL FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 47 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com NOTE: The sequences below must be followed when switching the MCU clock source between RCOSC and Xtal-OSC. 1) MCU Clock Source [RC-OSC Xtal-OSC (Div 2)]: a) MUX1 (0): MUX2 : MCU is Running at RC-OSC (0) b) : Start the Xtal-OSC and Standby c) MUX1 (0 1) 2) MCU Clock Source [Xtal-OSC (Div 2) RC-OSC]: a) MUX1 (1): MUX2 : MCU is Running at Xtal-OSC (Div 2) (0) [McuCKselect = 1, EN_XTALdiv, SEL_XTALdiv = 0] b) MUX1 (1 0) [McuCKselect = 0] c) : The MCU clock is switched to XtalOSC (Div 2). : The MCU clock is switched to RCOSC. [McuCKselect = 1] : Power-OFF Xtal-OSC 3) MCU Clock Source [RC-OSC Xtal-OSC (Div 32)]: a) MUX1 (0): MUX2 : MCU is Running at RC-OSC. (0) b) [McuCKselect = 0, EN_XTALdiv, SEL_XTALdiv = 0] : Start the Xtal-OSC and Standby c) MUX1 (0 1) : The MCU clock is switched to XtalOSC (Div 2). [McuCKselect = 1] d) MUX2 (0 1) : [EN_XTALdiv, SEL_XTALdiv = 1] e) MUX1 (0 0) : The MCU clock is switched to XtalOSC (Div 32). [McuCKselect = 0] 4) MCU Clock Source [Xtal-OSC (Div 32) RC-OSC]: a) MUX1 (0): MUX2 : MCU is Running at Xtal-OSC (Div 32) [ McuCKselect = 0 , EN_XTALdiv, (1) SEL_XTALdiv = 1] b) MUX1 (0 1) : The MCU clock is switched to XtalOSC (Div 2). [McuCKselect = 1] c) MUX2 (1 0) : [EN_XTALdiv, SEL_XTALdiv = 0] d) MUX1 (10 0) : The MCU clock is switched to RCOSC. [McuCKselect = 0] e) 3.4.2 [McuCKselect = 0, EN_XTALdiv, SEL_XTALdiv = 0] : Power-OFF Xtal-OSC Timer Oscillator (Timer-OSC) The Timer-OSC is used for periodical wake up and abort functions. Since the Timer-OSC always runs even if the MCU is in sleep mode, the Timer-OSC has low current consumption. The oscillation frequency of the Timer-OSC should be calibrated by using the Xtal-OSC periodically. A register of TimerOSC<3:0> (0x97), can control current and oscillation frequency of the Timer-OSC. A register of TimerOSC_DIV<2:0> (0x97), can also control the oscillation frequency of the Timer-OSC by changing a number of divider. 48 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 0x97 W TimerOSC_DIV<2:0> Timer-OSC W 0x97 TimerOSC<3:0> 1/2 1/8 1/16 MUX 1/4 Clock output 1/32 1/64 1/128 M Timer-OSC Not Bit Addressable ESFR: 0x97 BIT 7 TimerOSC BIT 6 TM BIT 5 BIT 4 w 0 0 TM TimerOSC_DIV<2:0> Test Mode. Always set to 0. Frequency divider setting of the Timer-OSC output. 3.4.2.1 w 0 S w 0 S BIT 2 BIT 1 BIT 0 TimerOSC<3:0> Access At Power on reset At Timer reset TimerOSC<3:0> BIT 3 TimerOSC_DIV<2:0> W 0 S w 0 S w 0 S w 0 S TimerOSC_DIV<2> TimerOSC_DIV<1> TimerOSC_DIV<0> DIV 1 1 1 1 1 1 0 1/2 1 0 1 1/4 1 0 0 1/8 0 1 1 1/16 0 1 0 1/32 0 0 1 1/64 0 0 0 1/128 w 0 S Bias current setting of the Timer-OSC. The oscillation frequency is proportional to the current. TimerOSC<3:0> = F provides the maximum bias current and the fastest oscillation frequency TimerOSC<3:0> = 0 provides the minimum bias current an the slowest oscillation frequency Interval Timer The interval timer consists of three dividers that are used to generate clocks that provide the required time period for several functions such as the wake-up interval time, and the LF wake-up interval. The clock period (dividing ratio) of the Pre-Timer, Post-Timer, and LF Wake-up Timer can be changed by using ESFRs: TimerPre (0x96: TPRE<7:0>), TimerPost (0x95: TPOST<7:0>) and TimerLFwake (0xC4: TLFwake<7:0>). The APIs are prepared to support this timer setting and can be called by the application software. For detail about the timer setting, refer to the SW Application manual. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 49 TPIC82000 Series SLDS189 - MAY 2012 W www.ti.com 0x97 TimerOSC_DIV<2:0> W 0x97 TimerOSC<3:0> W 0x96 TPRE<7:0> W 0x95 TPOST<7:0> Timer State Monitor Timer-OSC Pre-Timer Tpost Post-Timer T_TimerOSC Tpre Tpre T_TimerOSC LF Wake-up Timer T_LFwake Tpost TLFwake R 0xE9 Timer-OSC R 0xE9 PreCount R 0xE9 PostCount R 0xE9 LFwakeCount W 0xC4 TLFwake<7:0> M Timer PreCounter Divider ESFR: 0x96 BIT 7 Not Bit Addressable TimerPre BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 w 1 S w 1 S w 1 S w 1 S BIT 3 BIT 2 BIT 1 BIT 0 r/w 1 D S r/w 1 D S r/w 1 D S r/w 1 D S BIT 3 BIT 2 BIT 1 BIT 0 w 1 S w 1 S w 1 S TPRE<7:0> Access At Power on reset At Timer reset TPRE<7:0> w 1 S w 1 S w 1 S w 1 S Timer Pre-Counter Divider ratio. PreTimer Period: MTpre = T_TimerOSC * (TPRE<7:0> +1) M Timer PostCounter Divider ESFR: 0x95 BIT 7 Not Bit Addressable TimerPost BIT 6 BIT 5 BIT 4 r/w 1 D S r/w 1 D S TPOST<7:0> Access At Power on reset At Timer reset for r At Timer reset for w TPost<7:0> r/w 1 D S r/w 1 D S Timer Post-Counter Divider ratio. PostTimer Period: MTpost = Tpre * (TPOST<7:0> +1) M Timer LFwakeCounter Divider ESFR: 0xC4 BIT 7 Not Bit Addressable TimerLFwake BIT 6 BIT 5 BIT 4 TLFwake<7:0> Access At Power on reset At Timer reset TLFwake<7:0> 50 w 1 S w 1 S w 1 S w 1 S w 1 S Timer LFwake-Counter Divider ratio. LFwakeTimer Period: MTLFwake = T_TimerOSC * (TLFwake<7:0> +1) FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 M Timer State / RC-OSC State ESFR: 0xE9 BIT 7 Access At Power on reset At Timer reset RC-OSC XTALosc LFwakeCount PostCount PreCount Timer-OSC 3.4.3 Not Bit Addressable TimerState BIT 6 RC-OSC XTALosc r 0 0 r 0 0 BIT 5 - x x RC-OSC output monitor, MRC-OSC output divided by 256 is monitored. XTALosc output monitor, Xtal-OSC output divided by 512 is monitored. Timer LFwake Counter output monitor Timer Post-Counter output monitor Timer Pre-Counter output monitor Timer-OSC output monitor BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LFwakeCount PostCount PreCount Timer-OSC r 1 D r 1 D r 1 D r 0 D - x x Refer to Section 3.4.3 Refer to Section 3.4.4 RC Oscillator (RC-OSC) The RC oscillator (RC-OSC) is used for generating an MCU clock of 2.4 MHz. Most of the operations use this clock because of the low current consumption and fast start up. The RC-OSC consists of a 3-stage ring oscillator and an RC low pass filter. A 5-bit variable resistor is used as a resistor of the low pass filter to control oscillation frequency of 9.6 MHz precisely. The 5-bit variable resistor can be controlled by using a register of RC-OSC<4:0> (0xD7:RC-OSC). The oscillation frequency can be monitored by using a register of RC-OSC (0xE9: TimerState). A register of EN_Trim_RES (0xD7:RC-OSC) is able to monitor the output of RC-OSC which is divided by 256 for the clock frequency tuning. Since the oscillator has dependencies on the operation voltage and temperature, it is recommended to calibrate the oscillation frequency using the Xtal-OSC. The firmware is prepared to support this trimming function and can be called by the application software. For more details about the RC-OSC trimming, refer to the SW Application manual. R/W 0xD7 RC-OSC<4:0> R/W 0xD7 EN_Trim_RES R 1/256 0xE9 RC-OSC 1/256 Output (To MCU for Clock Frequency Timing) R Output (To MCU and System) C C FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 51 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com M RC-OSC Not Bit Addressable ESFR: 0xD7 BIT 7 Access At Power on reset At Timer reset EN_XTALdiv SEL_XTALdiv EN_Trim_RES RC-OSC<4:0> RC-OSC BIT 6 BIT 5 EN_XTALdiv SEL_XTALdiv EN_Trim_RES r/w 0 0 r/w 0 0 r/w 0 0 ESFR: 0xE9 BIT 7 RC-OSC XTALosc LFwakeCount PostCount PreCount Timer-OSC 3.4.4 BIT 3 BIT 2 BIT 1 BIT 0 r/w 1 S r/w 0 S RC-OSC<4:0> r/w 0 S r/w 1 S r/w 1 S Enable the switch of the Xtal-OSC 1/32 and 1/16 divider: M0 = Divider Off M1 = Divider On (Enables both 1/32 and series connected 1/16 divider) Select the Xtal-OSC output 1/2 divided or 1/32 divided: M0 = 1/2 divided (Default and Normal operation) M1 = 1/32 divided clock (Needs to be set with EN_XTALdiv=1) Enable RC-OSC trim: M0 = Disable RC-OSC Trim M1 = Enable RC-OSC Trim 5-bit variable resister control: M1F = Maximum Resistance and generate Lowest Frequency M00 = Minimum Resistance and generate Fastest Frequency M Timer State / RC-OSC State Access At Power on reset At Timer reset BIT 4 Refer to Section 3.4.4 Refer to Section 3.4.4 Not Bit Addressable TimerState BIT 6 RC-OSC XTALosc r 0 0 r 0 0 BIT 5 BIT 4 - x x BIT 3 BIT 2 BIT 1 BIT 0 LFwakeCoun t PostCount PreCount Timer-OSC r 1 D r 1 D r 1 D r 0 D - x x RC-OSC output monitor, MRC-OSC output divided by 256 is monitored. XTALosc output monitor, Refer Xta Oscillator output divided by 512 is monitored. Timer LFwake Counter output monitor Refer Timer Post Counter output monitor Refer Timer Pre Counter output monitor Refer Timer-OSC output monitor Refer to Section 3.4.4 to Section to Section to Section to Section 3.4.2.1 3.4.2.1 3.4.2.1 3.4.2.1 Crystal Oscillator The crystal oscillator (Xtal-OSC) consists of the crystal driver, the clock dividers, and the selectors. A crystal with a resonant frequency around 19.7 MHz is required. Since the current consumption of the XtalOSC is larger than that of the RC-OSC, the Xtal-OSC is recommended only for use of the operations that require a precise clock such as RF transmitting and oscillator calibration (Timer-OSC, RC-OSC, and LFOSC). Bias current of the Xtal-OSC can be controlled by a register of XtalBIAS<3:0> (0x86) with a step of 20 A. The state of the Xtal-OSC can be detected by monitoring a register of FLAG_XtalOSC (0xE3). NOTE Xtal frequency should be adjusted by the application, which may use a specific RF transmitting frequency. In this manual, the Tx frequency (433.920 MHz and 314.980 MHz) and other timing tuning adjustments are expected based on the crystal of 19.707894 MHz. If the Xtal frequency is changed, the Timer-OSC and RC-OSC trimming parameters must be tuned since they refer to the Xtal-OSC frequency. 52 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 To Bias Circuit VDD RD 0xE3 FLAG_XtalOSC Detector Crystal Resonant freq. = 19.7 MHz Output WR 0x86 XtalBIAS<3:0> Figure 3-8. Crystal Oscillator Block Diagram M Xtal-OSC bias Control Not Bit Addressable ESFR: 0x86 BIT 7 Access At Power on reset At Timer reset XtalBIAS< 3:0> XtalBias BIT 6 BIT 5 BIT 4 - - - - - x x - x x - x x - x x ESFR: 0xE3 BIT 7 FLAG_XtalOSC VCOgain FLAG_PLL_LKD 3.5 BIT 2 BIT 1 BIT 0 XtalBIAS< 3:0 > w 0 0 w 0 0 w 0 0 W 0 0 Bias current control of the Xtal-OSC M PLL local OSC State / RF trigger state Access At Power on reset At Timer reset BIT 3 LocalState BIT 6 Not Bit Addressable BIT 5 BIT 4 FLAG_XtalOSC BIT 3 VCOgain BIT 2 BIT 1 FLAG_PLL LKD BIT 0 - - - Reserved - - - r r r r r x x x 0 0 0 0 0 x x x 0 0 0 0 0 Xtal-OSC: Oscillating (1), Not Oscillating (0) Higher (1), Lower(0) Locked(1), Unlocked (0) RF Transmitter The RF transmitter offers 434 MHz and 315 MHz RF data transmission and consists of a Power Amplifier (PA) block, a PLL synthesizer block, and the baseband (BB) modulator block. External components such as the LC resonator load of PA, impedance matching circuit and antenna are required to complete the transmitter hardware. The external LC resonator components and the impedance matching circuit should be changed for 315 MHz and 434 MHz band operation, respectively. * Key features of RF 315/434 MHz transmitter - RF 315/434 MHz dual band transmitter with one crystal oscillator - Variable transmit frequency around 315/434 MHz 700 kHz FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 53 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com From Crystal Oscillator 19.7 MHz BB Block 4.93 MHz BB Modulator DIV 1/4 IQ-DAC PFD R CP RF Detector UP QMOD VOUT (VDD) LC resonator RFOUT VCO LPF DIV 1/16 for 315 MHz 1/22 for 434 MHz PA Block PLL Block RF PA V->I V DOWN 315 MHz or 434 MHz Matching Circuit LKD ANT Figure 3-9. 315/434MHz Transmitter Block Diagram 3.5.1 RF Power Amplifier The RF Power Amplifier amplifies the modulated output signal from the QMOD and drives the external antenna circuits. The LC resonator load, matching circuit, and an antenna are required externally to complete the transmitter circuits. RFpower at 0xF1: RFpower is used to turn the power supply (VDD) on/off for the RF PA block. The output power can be set by register RFPAbias<7:0> at 0xF2: RFbias. PrePAbias<1:0> at 0xF1: RFpower controls the bias current of Pre-Amp for the 434 MHz and 315 MHz operation. The RF output power can be adjusted in the OTP version while debugging. However, once the output power is fixed on the Mask ROM version, the output power is adjusted while in the TI final test. For more information about the output power adjustment, refer to the HW Application Note. 54 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 W 0xF1 RFPApower W 0xF1 PrePA bias<1:0> VOUT LC resonator 315 MHz or 434 MHz From VCO PA RFOUT Matching Circuit W 0xF2 RFPAbias<7:0> ANT Figure 3-10. RF PA Block M Tx RF-PA Control Not Bit Addressable ESFR: 0xF1 BIT 7 RFPApower Access At Power on reset At Timer reset RFPApower PrePA bias<1:0> W 0 0 RFpower BIT 6 Reserved BIT 5 BIT 4 BIT 3 PrePA bias<1> w 0 0 BIT 2 BIT 1 Reserved w 0 0 w 0 0 BIT 0 PrePA bias<0> w 0 0 w 0 0 w 0 0 w 0 0 BIT 2 BIT 1 BIT 0 w 0 0 w 0 0 W 0 0 RFPA Power: M1 = RFPA On M0 = RFPA Off Current control of pre-PA stages: M(0, 0) = Lowest current, (0, 1) = Mid-low current M(1, 0) = Mid-high current, (1, 1) = Highest current M Tx RF-PA bias Not Bit Addressable ESFR: 0xF2 BIT 7 RFbias BIT 6 BIT 5 BIT 4 BIT 3 RFPAbias<7:0> Access At Power on reset At Timer reset RFPAbias<7:0> W 0 0 w 0 0 w 0 0 w 0 0 w 0 0 RF-PA bias setting (Refer to HW Application Note for the relation between value and output Power). FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 55 TPIC82000 Series SLDS189 - MAY 2012 3.5.2 www.ti.com PLL Block The PLL block consists of a Phase/Frequency Detector (PFD), a Charge Pump (CP), a Low Pass Filter (LPF), and a Voltage Controlled Oscillator (VCO). The PFD detects phase and frequency differences between the reference signal generated by the crystal oscillator and the 315 MHz or 434 MHz CCO signal divided by 16 or 22, respectively. The PFD output pulses drive two switched current sources of the CP to charge or discharge the capacitors of LPF. And the output voltage of the LPF controls the output frequency of the VCO. Bias Current Control QMOD From Crystal-OSC DIV 1/16 for 315 MHz 1/22 for 434 MHz REF VCO Control CP PFD IQ-BB Signal LPF Control UP VCO UP LPF DOWN VI-Converter DOWN To PA CCO VER Lock Band Select PLL Lock Status Indicator Figure 3-11. PLL Block 3.5.3 315/434MHz Dual-band Quadrature Modulator (QMOD) The QMOD block consists of two double balanced mixers and a 315/434 MHz adjustable 90 phaseshifter. The 90 phase-shifter consists of an RC high/low pass filter. The capacitance of the LPF capacitor is configured using a MOS varactor to achieve a 90 phase shift for both 315 MHz and 434 MHz bands. The QMOD generates the desired differential RF signal by mixing the I/Q differential baseband signal and differential 315/434 MHz band local signal. In order to achieve low spurious performance, highly balanced 90 phase difference and equal amplitude of I/Q baseband and 315/434 MHz local signal are required. This QMOD can calibrate I/Q characteristics of the baseband and 315/434 MHz local signals, respectively. BB Block QMOD Block I DAC I BB Signal Generator RF OUT From LO VCO LO RF OUT 90deg. Q DAC Q 56 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 3.5.4 SLDS189 - MAY 2012 Baseband Block (BB block) The BB block operates by synchronizing with 4.93 MHz double of the MCU system clock which is generated by the crystal oscillator (19.7MHz/ 4). To activate baseband modulation, set the register bit (0xD3: EN_Modulation) to 1. The 9-bit digital BB signal is generated using a 128-byte ROM data which stores sine and cosine waveforms for quarter period. The I and Q DACs convert this 9-bit digital BB signal to I and Q analog BB signals, respectively. The register, (0xD1: ModOffset<7:0>) controls BB signal frequency with Equation 1. 4 ModOffset < 7 : 0 > (0xD1) BBclock(4.93MHz), BB Freq.(Hz) = 4096 (1) Where the BB clock is equal to the sampling clock and 4096 is the number of steps to count in one period. From Equation 1, maximum and minimum BB frequencies are defined as 1227.7 kHz (at 0xD1: ModOffset<7:0> = 255) and 4.8 kHz (at 0xD1: ModOffset<7:0> = 1). The FSK and ASK modulated signals can be generated using the data in the register (0xC9: ModRAMdata<7:0>) which stores the 64-byte Tx-RAM data based on the address the register (0xCA: ModRamAdd<5:0>) points to. When using FSK modulation, the frequency deviation can be calculated with Equation 2. ModRAMdata < 7 : 0 > (0xC9) DFreq. deviation of FSK(Hz) = BBclock(4.93MHz), 4096 (2) Where ModRAMData<7:0> (0xC9) is the data stored in the 64-byte RAM. From Equation 2, the maximum and minimum frequency deviations of FSK modulation are defined as 306.9 kHz (at ModRAMdata<7:0> (0xC9) = 255) and 0.6 kHz (at ModRAMdata<7:0> (0xC9) = 1). The frequency deviation can be adjusted with 1.2 kHz steps. For ASK modulation, register ModRAMdata<7:0> (0xC9) should be set as all the same value for constant BB frequency. The bit rate is controlled by the registers (0xD2: ModScale<7:0>) and (0xCA: ModRamAdd<5:0>) with Equation 3. 1 BB clock(4.93MHz) 1 Bit rate (bps) = , 2 ModScale < 7 : 0 > (0xD2) ModRAMAdd < 5 : 0 > (0xCA) (3) Where ModRAMAdd<5:0> (0xCA) can set the number of addresses of 64-byte RAM for 1 bit, ModScale<7:0> (0xD2) can set the sampling speed of 64-byte RAM for 1 bit. The FSK modulated signal frequency with BB signal can be described as the combination of BB frequency and frequency deviation using Equation 4. ModRAMData < 7 : 0 > (0xC9) + 4 ModOffset < 7 : 0 > (0xD1) BBclock Modulated signal Freq.(Hz) = 4096 (4) The register bit (0xD3: Polarity) is assigned as a switch to change the BB signal phase between I and Q. This signal also defines whether to take the upper side or lower side frequency from the local carrier frequency (16x or 22x of Xtal-OSC frequency which is defined by register bit (0xC2: BAND)). To select between FSK or ASK modes, set register (0xD3: Modulation mode). If this bit is set to 1, ASK mode is selected. FSK mode is selected if the bit is set to 0. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 57 TPIC82000 Series SLDS189 - MAY 2012 W www.ti.com 0xD3 EN_Modulation MCU Clock (4.93 MHz) Modulator I 9bit cos DAC To QMOD I RAM (64-Byte) ROM (128-Byte) Q 9bit TX Data W 0xCB ModTxData<7:0> W 0xC2 BAND W 0xD3 Modulation_Mode sin To QMOD DAC Q W 0xD2 ModScale<7:0> W W 0xCA ModRamAdd<5:0> W 0xD1 ModOffset<7:0> W 0xEB Busy 0xD3 Polarity 0xC9 W ModRamData<7:0> 58 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com * SLDS189 - MAY 2012 Setting Example - Xtal-OSC frequency: 19.707894 MHz - Desired carrier frequency: 314.980 MHz * ModRAMData<7:0> (0xC9) = 28, ModOffset<7:0> (0xD1) = 65 28 + 4 65 19.707894MHz = 346.4 (kHz) Modulated signal Freq. (kHz) = 4096 4 Carrier Freq. (MHz) = 19.707894MHz 16 - 346.4 (kHz) = 314.980 (MHz) Where Polarity (0xD3) = 1, select the lower side frequency from the local carrier frequency. BAND (0xC2) = 1 (315 MHz). - Desired carrier frequency: 433.920 MHz * ModRAMData<7:0> (0xC9) = 28, ModOffset<7:0> (0xD1) = 65 28 + 4 65 19.707894MHz = 346.4 (kHz) Modulated signal Freq. (kHz) = 4096 4 Carrier Freq. (MHz) = 19.707894MHz 22 - 346.4 (kHz) = 433.920 (MHz) Where Polarity (0xD3) = 0, select the upper side Freq. from the Local Carrier Freq. BAND (0xC2) = 0 (434 MHz). - Frequency deviation of FSK: 25 kHz * ModRAMData<7:0> (0xC9) = 7, 28 (center), 49 7 19.707894MHz 28 19.707894MHz = 8.42 (kHz), = 33.68 (kHz), 4096 4 4096 4 49 19.707894MHz = 58.94 (kHz) 4096 4 Freq. deviation of FSK (kHz) = - For bit rate: 4.8K bits/s (ModScale<7:0> (0xD2) = 16, ModRAMAdd<5:0> (0xCA) = 32) 1 19.707894MHz 1 1 Bit rate (bps) = = 4.81 (kbps) 2 4 16 32 - For bit rate: 9.6K bits/s (ModScale<7:0> (0xD2) = 8, ModRAMAdd<5:0> (0xCA) = 32) 1 19.707894MHz 1 1 Bit rate (bps) = = 9.62 (kbps) 2 4 8 32 - For bit rate: 19.2K bits/s (ModScale<7:0> (0xD2) = 4, ModRAMAdd<5:0> (0xCA) = 32) 1 19.707894MHz 1 1 Bit rate (bps) = = 19.25 (kbps) 2 4 4 32 - For bit rate: 10K bits/s (ModScale<7:0> (0xD2) = 8, ModRAMAdd<5:0> (0xCA) = 31) 1 19.707894MHz 1 1 Bit rate (bps) = = 9.93 (kbps) 2 4 8 31 - For bit rate: 20K bits/s (ModScale<7:0> (0xD2) = 4, ModRAMAdd<5:0> (0xCA) = 31) FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 59 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com 1 19.707894MHz 1 1 = 19.87 (kbps) 2 4 4 31 Bit rate (bps) = Start to shift the TxData buffer D0<7:0>=0xCB Reset D1<7:0>=0x53 D2 Reset D0 <0> D0<1> D 0<2 > D 0 <3> D0<4> D0<5> D 0<6> D 0 <7> D1<0 > D1<1> D 1<2> D 1 <3> D1<4 > D1<5> D 1<6> D 1<7> D 2<0> 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 0 0 Tx Data Buffer Stop to shift the TxData buffer Manchester Code 1 1 0 1 0 0 1 0 1 IQ BaseBand Tx RAM Address<5:0> 0 0 Transmitter Output FL FL: Lower Side FSK Frequency FH: Higher Side FSK Frequency 31 31 0 0 31 0 31 FH FH FL FL FH FL FH 1 2 3 4 5 6 7 31 0 31 0 FH FL FH FL 8 1 2 3 31 0 0 31 FH FL FL FH FH 4 5 6 7 8 31 0 FL Shift_CLK EN_SHIFT BUSY (ESFR:0 xEB<7>) WR_Tx Modulator Control (ESFR:0 xD3) EN_SHIFT=1 EN_SHIFT=0 WR_TxDATA Buffer (ESFR:0 xCB) 0 x35(D0) 0xA7(D1) 0x00( D2 ) Figure 3-12. Timing Diagram of 1-Byte FSK Data Transmission Start to shift the TxData buffer Reset 0 Tx Data Buffer Stop to shift the TxData buffer D0<7:0>=0xCB D1<7:0>=0x53 D2 D0 <0> D0<1> D 0<2 > D 0 <3> D0<4> D0<5> D 0<6> D 0 <7> D1<0 > D1<1> D 1<2> D 1 <3> D1<4 > D1<5> D 1<6> D 1<7> D 2<0> 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 0 Manchester Code 1 1 0 1 0 0 1 Reset 0 1 Transmitter Output OFF OFF: Transmit OFF ON: Transmit ON ON ON 1 OFF 2 OFF 3 ON 4 OFF 5 ON 6 ON 7 OFF 8 ON 1 OFF 2 ON 3 OFF 4 OFF 5 ON 6 ON 7 OFF 8 Shift_CLK EN_SHIFT BUSY (ESFR:0 xEB<7>) WR_Tx Modulator Control (ESFR:0 xD3) EN_SHIFT=1 EN_SHIFT=0 WR_TxDATA Buffer (ESFR:0 xCB) 0 x35(D0) 0xA7(D1) 0x00( D2 ) Figure 3-13. Timing Diagram of 1-Byte ASK Data Transmission M Tx DATA Buffer Not Bit Addressable ESFR: 0xCB BIT 7 ModTxData BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 w U U w U U w U U ModTxData<7:0> Access At Power on reset At Timer reset ModTxData<7:0> 60 w U U w U U w U U w U U w U U Transmit Data Buffer FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 M PLL Local OSC Not Bit Addressable ESFR: 0xC2 BIT 7 PLLlocalOSC BIT 6 BIT 5 BIT 4 BIT 3 BAND Access At Power on reset At Timer reset BAND BIT 2 BIT 1 BIT 0 w 0 0 w 0 0 w 0 0 w 0 0 BIT 3 BIT 2 BIT 1 BIT 0 Reserved w 1 1 w 0 0 w 0 0 w 0 0 VCO Frequency [dividing ratio] Selection: M0 = 434 MHz [1/22] M 1 = 315 MHz [1/16] M Tx Modulator Offset Frequency ESFR: 0xD1 BIT 7 Not Bit Addressable ModOffset BIT 6 BIT 5 BIT 4 ModOffset<7:0> Access At Power on reset w U w U w U w U w U w U w U w U At Timer reset U U U U U U U U BIT 2 BIT 1 BIT 0 w U U w U U w U U ModOffset<7:0> BB Frequency setting parameter: MBB Freq. (Hz) = 4 * ModOffset<7:0> / 4096 * BB clock (4.93 MHz) M Tx Modulator Scale Not Bit Addressable ESFR: 0xD2 BIT 7 ModeScale BIT 6 BIT 5 BIT 4 BIT 3 ModScale<7:0> Access At Power on reset At Timer reset ModScale<7:0> w U U w U U w U U Not Bit Addressable ESFR: 0xD3 Polarity EN_Modulation Modulation_Mode TxRAM Access EN_SHIFT w U U Sampling clock scaling factor of 64-byte TX-RAM MBit rate (bps) = 1/2 * (BB clock (4.93 MHz) / (ModScale<7:0> * ModRAMAdd<5:0>)) M Tx Modulator Control Access At Power on reset At Timer reset w U U BIT 7 ModCONT BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Reserved - Polarity EN_Modulation Modulation Mode TxRAM Access EN_SHIFT Reserved w 0 0 - x x w 0 0 w 0 0 w 0 0 w 0 0 w 0 0 w 0 0 I/Q phase switch: M0 = Positive and select upper side freq. from local carrier freq. M1 = Negative and select lower side freq. from local carrier freq. Modulation Active control M1 = Activate, M0 = Inactivate ASK/FSK modulation mode selector: M1 = ASK modulation, M0 = FSK modulation TX RAM Access Mode Control M1 = TX R/W Access, M0 = Normal Modulation Mode Enable shift of 8bit Tx Data Buffer M1 = Enable the Shift, M0 = Disable the Shift FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 61 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com M Tx Modulator state Not Bit Addressable ESFR: 0xEB BIT 7 Access At Power on reset At Timer reset BUSY ModState BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BUSY Reserved - - - - - - r U U r 1 1 - x x - x x - x x - x x - x x - x x BIT 3 BIT 2 BIT 1 BIT 0 BUSY Flag of Tx Data Buffer: M1 = Busy M0 = Ready to load next Tx-data M IQ BaseBand Tx RAM Data ESFR: 0xC9 BIT 7 Not Bit Addressable ModRamData BIT 6 BIT 5 BIT 4 ModRamData<7:0> Access At Power on reset w U w U w U w U w U w U w U w U At Timer reset U U U U U U U U BIT 1 BIT 0 w U U w U U ModRamData<7:0> 64-byte TX-RAM data setting activate with TxRAM Access = 1 (ESFR: 0xD3) M IQ BaseBand Tx RAM Address ESFR: 0xCA Access At Power on reset At Timer reset ModRamAdd<5:0> 3.6 Not Bit Addressable BIT 7 ModRamAdd BIT 6 - - - x x - x x BIT 5 BIT 4 BIT 3 BIT 2 ModRamAdd<5:0> w U U 64-byte TX-RAM address setting w U U w U U w U U activate with TxRAM Access = 1 (ESFR: 0xD3) LF Receiver An LF receiver is implemented on the device to trigger the wake-up of the device or to control the operation of the device externally. The LF receiver consists of an Analog Front-End (AFE) and a baseband processor block. External LF antenna circuits are required to complete the receiver system. The LF receiver on the device can detect ASK modulated 125 kHz LF signals. To minimize the power dissipation of the device, this LF receiver wakes up periodically as defined by the (0xC4: TLFwake<7:0>) register in the interval timer block. The device can recognize four types of pre-fixed protocols (three Manchester coded patterns and one PWM coded pattern) without waking up the MCU. 3.6.1 LF AFE The LF AFE consists of a variable capacitor and resistor (attenuator) for LF antenna Q tuning and LF signal gain control, Receiving Signal Strength Indicator (RSSI), data slicer for ASK signal demodulating, signal level detector, LF-OSC (300 kHz typically), and bias and timing control blocks. Each parameter such as RSSI gain, antenna tuning parameters, and the data slicer threshold, can be programmed via the appropriate registers. NOTE The variable capacitor and resistor (attenuator) are set to a default values and can be neglected as isolated from the LF input. 62 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 LF Receiver Analog Front-End Frequency Trim Setting Parameters/ Instructions Bias Control LF Block RC Oscillator To LF AFE Analog Circuits LF Ant Q Tuning Level Detector Gain Control Tune Cap Trim Timing Control LF Ant LFIN 10 k Att C-tune LF Receiver Baseband Processor Threshold Trim V-Att RSSI Carrier Detector EN LFINB Data Slicer Gain Adjust Slicer LPF Trim Slicer Offset Trim 3.6.2 LF Baseband Processor The LF baseband processor decodes the demodulated signal from the LF AFE and determines if the input pattern matches the ID, pattern, or commands from the remote controller. The device supports four types of LF patterns (three Manchester coded and one PWM coded). Once one of the basic protocols (1a,1b,1c, or 2) is programmed on the device, then the customer can define their own synchronization pattern, Wake-up ID, and MCU start program via the corresponding registers. CLK Register Setting Register/Latch Data Bus Register Setting Attenuation Level Control Signal LF Signal Input AFE ON Register Setting From Level Detector Preamble Detector VATT Control Register Setting LF-OSC From Data Slicer Register Setting Register Setting CLK EN 300 kHz Decoded Data Pre-Valid ON Register Setting Decoder Protocol: 1a,1b,1c, 2 Sync/ID Valid Data Monitor LF Wake-up Pulse from Timer Data Bus Wake up/ Abort Control MCU ON 3.6.3 LF Pattern The TPIC82000 device recognizes four types of LF patterns. Three of these LF patterns are Manchester coded patterns and one is a PWM coded pattern. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 63 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com The user can select the LF protocol by setting the register (0xA4: LFprotocol<1:0>) in the application program. To ensure LF detection while minimizing the power dissipation of the device, the LF sniffing timing needs to be carefully considered. The user also can define the MCU wake-up timing after the corresponding synchronization pattern detection. This can be set by the register (0xA4: WakeupTiming<1:0>). The following sections show the examples of different LF patterns and associated sniffing timings. 3.6.3.1 WakeupTiming<1> WakeupTiming<0> Operation mode 0 0 Not used (Not start) 0 1 MCU start after Sync pattern matching 1 0 MCU start after Wakeup_ID pattern matching 1 1 MCU start after the first Data pattern matching LFprotocol<1> LFprotocol<0> 0 0 Protocol pattern 2 0 1 Protocol pattern 1a 1 0 Protocol pattern 1b 1 1 Protocol pattern 1c Operation mode Protocol 1a In Protocol 1a, the transmitted data frame consists of the preamble, synchronization pattern, Wake-up ID and command/data periods. The data frame begins with a pre-defined duration of the preamble pattern which indicates the data period (1TBIT) with periodical On-Off LF signals, then the synchronization pattern which consists of 9 TBIT length data is transmitted. Next, the Wake-up ID pattern consisting of 16 TBIT length data is sent, and then the command or data consisting of 8 TBIT x N length data should be transferred to the device. The Protocol 1a and the LF sniff example timing diagrams are shown in Figure 3-14 and Figure 3-15. The device checks if the LF preamble signal exists or not by waking up the LF AFE and baseband block every period as defined by the LF timer setting. If no LF signals are detected while in TSNIFF-ON period, the device goes back into sleep mode and wakes up again at the next sniffing period. If LF signals are detected while in TSNIFF-ON period, the device continues to check if the LF patterns match with the synchronization pattern, Wake-up ID patterns, and/or first data pattern. When matching patterns are recognized, the device wakes up the MCU and the MCU starts the remaining data receiving process. The timing of the MCU wake-up can be selected by application software as after the preamble, the synchronization pattern, the Wake-up ID or the first data depending on user preference. To ensure the detection of the LF patterns without fail even when one shot LF frame is applied, it is recommended to set the LF sniffing period to be shorter than the preamble period and the Sniffing-On duration (TSNIFF-ON) to be longer than TBIT/2. To minimize the power consumption in the LF signal detection, it is recommended to minimize the duty cycle of the sniff-on period. Even though, the device is designed so it is able to detect only 1 shot of the LF frame, it is recommended to repeat the entire LF frame a few times to ensure the communication. 64 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 Preamble TPRE Wake-up ID 16TBIT Synchronization 9TBIT Data 0 8TBIT Data 1 8TBIT Data N 8TBIT LF Signal Demodulated Signal 0.5TBIT 0.5TBIT 1TBIT 1.5TBIT 1.5TBIT 1TBIT 1TBIT 1TBIT 1TBIT 0.5TBIT 0.5TBIT 0.5TBIT 0.5TBIT Figure 3-14. LF Protocol 1a Pattern Example TSNIFF-ON LF Sniff Enable TLFSNIFF Figure 3-15. LF Sniffing Timing Table 3-3. Protocol 1a (Manchester Coding) Timing Example Symbol Description Timing Example TPRE Preamble duration 4 mS (typical) (greater than 3mS) TBIT Duration for 1bit 256 S (typical) fLF LF Carrier frequency 125 kHz (typical) DRLF LF Data rate 3.906K bits/s (typical) TSNIFF-ON LF Sniffing Period 300 S (typical) (programmable) (1) TLFSNIFF LF Sniffing Interval 2.2 mS (typical) (programmable) (1) (2) 3.6.3.2 (2) The LF sniffing period is determined as the combination of the LF AMP set up time (typically 150 S) and LF carrier detect time which is programmable in 16 steps with every 26.4 S. TSNIFF-ON = LF AMP Set Up Time + LF Carrier Detect Time TSNIFF-ON = 150 s + (1+ LFcarrierDET<3:0>) * 8/F_LF-OSC, where F_LF-OSC is the frequency of LF-OSC. To change the LF sniffing interval, the Timer-OSC frequency needs to be trimmed. The specification of the trimmed Timer-OSC frequency is 400-500 Hz. (See Section 5.5 ) Set the register bits, TimerOSC<3:0> and TimerOSC_DIV<2:0>, in the TimerOSC register (0x97) to the appropriate value to achieve the fine adjusted sniffing interval. If any other blocks are using the Timer-OSC, the user needs to carefully confirm it won't affect any of these other functions. Protocol 1b Protocol 1b does not have the preamble signals from Protocol 1a but will repeat whole frames several times to ensure the signals and ID are detected. The transmission data frame consists of the synchronization pattern which consists of 9 TBIT length data, Wake-up ID pattern which consists of 16 TBIT length data and command or transmitting data consisting of 8 TBIT x N length data. The Protocol 1b and the LF sniff example timing diagrams are shown in Figure 3-16 and Figure 3-17. The device checks if the LF signal exists or not by waking up the LF AFE and the baseband block every period as defined by the LF timer setting. If no LF signals are detected while in TSNIFF-ON period, the device goes back into sleep mode and wakes up again at the next sniffing period. If the LF signals are detected while in TSNIFF-ON period, the device checks if the continuous five half-TBIT pattern or TBIT pattern is existing or not. If it detects the five consecutive patterns (five consecutive H and L changes of LF pattern), the FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 65 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com device assumes it is the preamble signal and then determines the TBIT width with the following two TBIT signal (H-L or L-H pattern of LF signal). Then the device checks the synchronization pattern, Wake-up ID patterns, and/or first data pattern. When matching patterns are recognized, the device wakes up the MCU and the MCU starts the remaining data receiving process. The timing of the MCU wake-up can be selected by application software as after the preamble, the synchronization pattern, the Wake-up ID or the first data depending on user preference. Due to the lack of the preamble pattern, the device may need the sniff-on duration to be at least one whole frame length to ensure the detection of the LF pattern without fail. Also, to minimize the power consumption in LF signal detection, it is recommended to send more than 10 times whole frames to reduce the duty of sniff-on period. First Telegram Frame Synchronization 9TBIT Subsequent Telegram Frame Wake-up ID 16TBIT Data 0 8TBIT Data N 8TBIT Synchronization 9TBIT Wake-up ID 16TBIT Data 0 8TBIT Data N 8TBIT LF Signal Demodulated Signal 1.5TBIT 1.5TBIT 1TBIT 1TBIT 1TBIT 1TBIT 0.5TBIT 0.5TBIT 0.5TBIT 0.5TBIT Figure 3-16. Protocol 1b Pattern Example TSNIFF-ON LF Sniff Enable TLFSNIFF Figure 3-17. LF Sniffing Timing Table 3-4. Protocol 1b (Manchester Coding) Timing Example Symbol Description Timing Example TBIT Duration for 1bit 256 S (typical) fLF LF Carrier frequency 125 kHz (typical) DRLF LF Data rate 3.906K bits/s (typical) Nframe Data Frame repeat > 3 (recommended more than 10) TSNIFF-ON LF Sniffing Period PREAMBLEabort<2:0> * 128 * 4/F_LF-OSC (programmable) (1) where F_LF-OSC is the frequency of LF-OSC TLFSNIFF LF Sniffing Interval < (Nframe-1)*Tframe - TSNIFF-ON (programmable) (2) (1) (2) 66 The device can set the sniff-on duration in 7 steps with 1.7 mS intervals by setting the PREAMBLEabort<2:0> bit in the LFabort register (0xDC). Tframe: Time period of one Telegram Frame [Synchronizing pattern + Wake-up ID + Data0+ ... +Data N]. Nframe = N (The repeated LF frame number) * Tframe To change LF sniffing interval, set the TLFwake<7:0> in TimerLFwake register (0xC4) to the appropriate value. Since the LF sniffing interval is much longer than Timer-OSC frequency (typically 450 Hz), there is no need to preadjust the register bits, TimerOSC<3:0> and TimerOSC_DIV<2:0>, in the TimerOSC register (0x97). FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 3.6.3.3 SLDS189 - MAY 2012 Protocol 1c Protocol 1c is similar to that of Protocol 1a but there is a leading start marker (burst signal) before the preamble pattern. After the certain duration of the start mark, the preamble pattern which indicates the data period (1TBIT) with periodical On-Off LF signals is sent, then the synchronization pattern which consists of 9 TBIT length data is transmitted. Next, the Wake-up ID pattern consisting of 16 TBIT length data is sent and then the command or transmitting data which consists of 8 TBIT x N length data should be transferred to the device. The Protocol 1c and the LF sniff example timing diagrams are shown in Figure 3-18 and Figure 3-19. The device checks if the LF signal is existing or not by waking up the LF AFE and baseband block in every certain period. If no LF signal is detected while in TSNIFF-ON period, the device goes into sleep and wakes up again at the next sniffing period. If LF signal is detected while in TSNIFF-ON period, the device continues to check if the continuous five half-TBIT pattern is existing or not. If it detects the five consecutive half-TBIT pattern (five consecutive H and L changes of LF pattern with same pulse width), the device assumes it is the preamble signal and determines the TBIT width with the following two half TBIT signal (H-L or L-H pattern of LF signal). Then, the device checks synchronization pattern, Wake-up ID patterns and/or first data pattern. When the matching patterns are recognized, the device wakes up the MCU and the MCU starts the remaining data receiving. The timing of the MCU wake-up can be selected by the application software as after the preamble, the synchronization pattern, the Wake-up ID or the first data depending on user preference. Even though the device is designed to be able to detect only 1 shot of the LF frame, it is recommended to repeat the entire LF frame a few times to ensure the communication. Start Mark TBURST Preamble TPRE Synchronization 9TBIT Wake-up ID 16TBIT Data 0 8TBIT Data 1 8TBIT Data N 8TBIT LF Signal Demodulated Signal 0.5TBIT 1TBIT 0.5TBIT 1.5TBIT 1.5TBIT 1TBIT 1TBIT 1TBIT 1TBIT 0.5TBIT 0.5TBIT 0.5TBIT 0.5TBIT Figure 3-18. Protocol 1c Pattern Example TSNIFF-ON LF Sniff Enable TLFSNIFF Figure 3-19. LF Sniffing Timing FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 67 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com Table 3-5. Protocol 1c (Manchester Coding) Timing Example Symbol Description Timing Example TBURST Start Mark (Burst) signal width > 3 mS TPRE Preamble duration > TBIT * 5 TBIT Duration for 1bit 256 S (typical) fLF LF Carrier frequency 125 kHz (typical) DRLF LF Data rate 3.906K bits/s (typical) TSNIFF-ON LF Sniffing Period 150 S (Programmable) TLFSNIFF LF Sniffing Interval 2.2 mS < ( TBURST-TSNIFF-ON ) (Programmable) (2) (1) (2) 3.6.3.4 (1) Minimum LF sniffing period is determined as the LF AMP set up time (typically 150 S). To change LF sniffing interval, the Timer-OSC frequency needs to be trimmed. The specification of the trimmed Timer-OSC frequency is 400-500 Hz. (See Section 5.5) Set the register bits, TimerOSC<3:0> and TimerOSC_DIV<2:0>, in the TimerOSC register (0x97) to the appropriate value to achieve the fine adjusted sniffing interval. If any other blocks are using the Timer-OSC, the user needs to carefully confirm it will not affect any of these other functions. Protocol 1 Total Sniffing Abort Time To prevent the continuous LF sniff-on situation, the device has the ability to set a total time limit for the LF sniffing. It can be defined by setting the register bits, LFabort<7:3>, in the LFabort register (0xDC). The time limit can be adjusted using 31 steps with a 6.8 mS interval. 3.6.3.5 Protocol 1 Data Pattern Setting Synchronization Pattern: The device can compare up to 17x0.5TBIT synchronization pattern. Since the synchronization pattern may have a special pulse pattern which should not occur in normal Manchester coded communication, the device enables defining the matching pattern with each 0.5TBIT. This can be achieved by setting the SYNC<7:0> and SYNC<14:8> register bits in the LFsync0 (0xAD) and LFsync1 (0xAE) registers. An example of the synchronization pattern is shown in Figure 3-20. Bit 17 Bit 16 1 1 Bit 15 Bit 14 Bit 13 1 0 0 Bit 12 Bit 11 Bit 10 0 1 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 0 0 1 1 0 0 1 0 Synchronization 9TBIT Preamble LF Signal Demodulated Signal 1.5TBIT 1.5TBIT 1TBIT 1TBIT 1TBIT 1TBIT 0.5TBIT 0.5TBIT 0.5TBIT 0.5TBIT Synchronization pattern example Figure 3-20. Synchronization Pattern Example Wake-up ID: The device can recognize up to a 16-bit length Wake-up ID. The matching pattern can be defined for each 1-bit (1 TBIT) by setting the WAKE0<7:0> and WAKE0<15:8> register bits in the LFwake0L (0xAF) and LFwake0H (0xB1) registers, respectively. An example of the Wake-up ID is shown in Figure 3-21. 68 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 Bit 15 Bit 14 Bit 13 1 0 0 1 0 Bit 12 Bit11 Bit10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 1 0 0 1 1 1 0 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 0 Wake-up ID 1TBIT 16TBIT Figure 3-21. Wake-up ID Pattern Example Command Data: The device can define the first 8-bit or 16-bit length data as either a command data, normal transmitting data, or a part of the initial Wake-up ID/command. The matching pattern for this data portion can be defined for each 1-bit (1 TBIT) by setting the bits WAKE1<7:0> in LFwake1L (0xCC) and WAKE1<15:8> in LFwake1H (0xCD). 3.6.3.6 Protocol 2 Protocol 2 supports PWM coded data streams. The data frame consists of the wake-up signal (burst signal), pause and preamble periods, and data periods. Once the device detects the LF signal while in the sniff-on (TSNIFF) period, the device wakes up the MCU. After the MCU start-up, all decisions for unit pulse width and data decoding is determined by the MCU and application programs. The application program needs to determine the data unit pulse width (TUNIT) from the pause and preamble period. Then it must decide the data code (1 or 0) by comparing the data pulse length with the unit pulse width. If the data pulse width is longer than TUNIT, the device recognizes it as 1. If the data pulse length is shorter than TUNIT, the device recognizes it as 0. Each data needs to be separated with a pause period. Figure 3-22 and Figure 3-23 show the Protocol 2 and the LF sniff example timing diagrams. Pause and Preamble Wake-up Signal Data Preamble 1 1 0 0 1 Pause LF Signal MCU Wakeup (Internal) N_Data (Internal) Reset (Internal) TWAKE TPAUSE TPRE TD TDATA1 TEND TDATA0 Figure 3-22. Protocol 2 Example FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 69 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com TSNIFF-ON LF Sniff Enable TLFSNIFF Figure 3-23. LF Sniffing Timing Table 3-6. Protocol 2 (PWM) Timing Example Symbol Description Timing Example TWAKE Wake up time (include LF detection and AGC) > 5 mS TPAUSE (1) LF Pause 1 mS 25% TPRE (1) Preamble Signal (Decision time reference for data demodulation) 1mS 25% TDATA1 (1) LF Presence (LF Data duration for data 1) 1.5 mS 25% (TDATA1 > TPRE) TDATA0 (1) LF Presence (LF Data duration for data 0) 0.5 mS 25% (TDATA0 < TPRE) fLF LF Carrier frequency 125 kHz (typical) (119 kHz-131 kHz) DRLF LF Data rate 0.5K bits/s (typical) TEND Time out for end transmission detection > 3x TPRE TSNIFF-ON LF Sniffing Period 150 S (programmable) (2) TLFSINFF LF Sniffing Interval 2.2 mS < ( TWAKE-TSNIFF-ON ) (programmable) (3) (1) (2) (3) Each timing variation of TPAUSE, TPRE, TDATA1, TDATA0 has the same polarity and value of the variation. For example, if TPAUSE has +25% variation, the others also have the +25% variation. Minimum LF sniffing period is determined as the LF Amp set up time (typically 150 S). To change LF sniffing interval, Timer-OSC frequency needs to be trimmed. Set the register bits, TimerOSC<3:0> and TimerOSC_DIV<2:0>, in the Timer-OSC register (0x97) to the appropriate value to achieve the fine adjusted sniffing interval. If any other blocks are using the Timer-OSC, the user needs to carefully confirm it won't affect any of these other functions. McLF ANT Tuning CAP Value ESFR: 0xB2 BIT 7 Not Bit Addressable LFANT BIT 6 BIT 5 BIT 4 BIT 3 LF_Test<1:0> Access At Power on reset At Timer reset LF_Test<1:0> LFANT<5:0> 70 w U S BIT 2 BIT 1 BIT 0 W U S w U S LFANT<5:0> w U S w U S w U S LF test monitor selector LF antenna tuning capacitor setting w U S w U S Can be updated with LFmode<6> = 1 LF_Test< 1 > LF_Test< 0 > Operation mode 0 0 Test mode Disabled 0 1 Test Monitor of LF sampling clock monitor (RC-OSC 300 kHz) 1 0 Test Monitor of LF ASK carrier 1 1 Test Monitor of LF RSSI ASK discriminator Output FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 MLF AGC Control Not Bit Addressable ESFR: 0xC6 LFagcSET BIT 6 BIT 7 Access At Power on reset for r/w At Timer reset for r/w At Reset AGCenable agcSET<3:0> BIT 5 BIT 4 - - AGCenable - - - r/w - r/w r/w r/w r/w x x 0/U - 0/U 0/U 0/U 0/U x x D/S - D/S D/S D/S D/S - - 0 - 0 0 0 0 BIT 2 BIT 1 BIT 0 BIT 2 BIT 1 agcSET<3:0> LF input variable attenuator setting: ON (1), OFF (0) LF input variable attenuator setting agcSET<3:0> = 0x0 Open (highest gain) agcSET<3:0> = 0xF Short (lowest gain) MLF Mode Control Not Bit Addressable ESFR: 0xA4 BIT 7 Access At Power on reset At Timer reset BIT 3 LFmode BIT 6 BIT 5 BIT 4 LFload LDregister Purge&AMPpow er LF_AMPpower w 0 0 w U S w U S w U S BIT 3 WakeupTiming<1:0> w U S LFload LDregister LDregister setting: enable (1), disable (0) LF register setting: enable (1), disable (0) Load signal for LFANT, LFbias, LFdelay, LFpLT, LFpUT, LFsync0, LFsync1, LFwake0L, LFwake0H, LFwake1L, LFwake1H, SLoffset, LFcont, LFOSC 1: For LF trim (except for slicer dc-offset trim) 0: For slicer dc-offset trim Purge&AMPpower LF detector register purge and Disable AMP power LF_AMPpower LF AMP power control: Continuously ON (1) TimerInterval ON (0) WakeupTiming<1:0> MCU Wake up timing select LFprotocol<1:0> LF Rx Protocol select w U S BIT 0 LFprotocol<1:0> W U S w U S Can be updated with LFload = 1. Can be Can be Can be Can be updated with bit7(LFload) updated with bit7(LFload) updated with bit7(LFload) updated with bit7(LFload) WakeupTiming<1> WakeupTiming<0> 0 0 Not used (Not start) 0 1 MCU start after Sync pattern matching 1 0 MCU start after Wakeup_ID pattern matching 1 1 MCU start after the first Data pattern matching LFprotocol<1> LFprotocol<0> 0 0 Protocol pattern 2 0 1 Protocol pattern 1a 1 0 Protocol pattern 1b 1 1 Protocol pattern 1c = 1. = 1. = 1. = 1. Operation mode Operation mode FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 71 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com M LF Bias Trim Control Not Bit Addressable ESFR: 0xA5 LFbias BIT 6 BIT 7 BIT 5 BIT 4 BIT 3 LF_RSSIdisc<2:0> Access At Power on reset At Timer reset LF_RSSIdisc<2:0> LFBIAS<4:0> w U S w U S w U S w U S w U S LF slicer LPF trim LF AFE bias control BIT 7 BIT 1 BIT 0 w U S w U S w U S Can be updated with LFmode<6> = 1 Can be updated with LFmode<6> = 1 M LF AMP Setup Delay timer Trim ESFR: 0xA6 BIT 2 LFBIAS<4:0> Not Bit Addressable LFdelay BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 w U w U w U S S S LFdelay<7:0> Access At Power on reset At Timer reset LFdelay<7:6> LFdelay<5:0> w U w U w U w U w U S S S S S Delay Timer Value Trim: A Delay Timer Value Trim: B Can be updated with LFmode<6> = 1 Can be updated with LFmode<6> = 1 M LF-OSC (300 kHz) Not Bit Addressable ESFR: 0xA7 BIT 7 LFOSC BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 w U S w U S w U S LFOSC<7:0> Access At Power on reset At Timer reset LFOSC<7:0> w U S w U S w U S w U S Bias current setting of the LF-OSC to Trim M LF AMP RSSI Threshold voltage setting ESFR: 0xAA BIT 7 w U S Can be updated with LFmode<6> = 1 Not Bit Addressable LFrssiVT BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 w U S w U S w U S LFrssiVT<7:0> Access At Power on reset At Timer reset LFrssiVT<7:0> w U S w U S w U S ESFR: 0xED BIT 7 SLoffset<4:0> 72 w U S RSSI Threshold Voltage Setting Can be updated with LFmode<6> = 1 M Slicer Offset Trim Setting 0 to 4 Access At Power on reset At Timer reset w U S Not Bit Addressable SLoffset BIT 6 BIT 5 - - - - x x - x x - x x BIT 4 BIT 3 w U S w U S BIT 2 BIT 1 BIT 0 w U S w U S SLoffset<4:0> Slicer offset trim setting w U S Can be updated with LFmode<6> = 1 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 M LF Control Not Bit Addressable ESFR: 0xEC BIT 7 LFcont BIT 6 BIT 5 BIT 4 VATT<3:0> Access At Power on reset At Timer reset VATT <3:0> Slicer_shunt Carrier AMP on VT monitor Bias monitor w U S w U S w U S BIT 0 Bias monitor w U S w U S w U S w U S w U S Can be updated with LFmode<6> = 1 Can be updated with LFmode<6> = 1 Can be updated with LFmode<6> = 1 Can be updated with LFmode<6> = 1 Can be updated with LFmode<6> = 1 BIT 7 LFmodeRSSI BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 loadregister loadRSSIVT loadAGCset Abortdisable loadDataC LF AMPGain - - w 0 0 0 w U S 0 w U S 0 w U S 0 w U S - W U S - - x x - - x x - Access At Power on reset At Timer reset At Reset LFmode RSSI register setting LFrssiVT register setting AGC (input variable attenuator) register setting Abort function enable (0), disable (1) LFdataC register setting LF AMP Gain setting: High gain (1)/ Low gain (0) M LF Data width count Can be Can be Can be Can be Can be Can be updated with bit7 updated with bit7 updated with bit7 updated with bit7 updated with bit7 updated with bit7 (loadregister) (loadregister) (loadregister) (loadregister) (loadregister) (loadregister) =1 =1 =1 =1 =1 =1 Not Bit Addressable ESFR: 0xC5 BIT 7 LFdataC BIT 6 BIT 5 BIT 4 dataCEN dataCEN DataCount<6:0> BIT 1 VT monitor Not Bit Addressable ESFR: 0xC7 Access At Power on reset At Timer reset BIT 2 Carrier AMP on 10 k shunt resistor between LFIN and LFINB trimming 0.5 k step, 6 k at VATT<3:0> = 1111, Open at VATT<3:0> = 0000 Slicer input shunt switch for dc-offset trimming ON (1): Slicer dc-offset trimming OFF (0): At LF slicer LPF trimming (LFbias<2:0>) OFF(0): At LF Receiver operation LF carrier out AMP: ON (1), OFF (0) switch RSSI VT reference voltage monitor LF bias setting voltage monitor M LF RSSI mode Control loadregister loadRSSIVT loadAGCset AbortDisable loadDataC LF_AMPgain BIT 3 Slicer_shunt BIT 3 w U S w U S w U S w U S w U S LF data count setting: Auto (0), Fixed (1) LF data width count<6:0>. Active with dataCEN = 1 M LF PreAmble Width UpperTimeLimit ESFR: 0xAB BIT 7 BIT 2 BIT 1 BIT 0 w U S w U S w U S DataCount<6:0> Can be updated with LFmodeRSSI<3> = 1 Can be updated with LFmodeRSSI<3> = 1 Not Bit Addressable LFpUT BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 w U S w U S w U S LFpUT<7:0> Access At Power on reset At Timer reset LFpUT<7:0> w U S w U S w U S w U S w U S PreAmble Cycle count Upper Time Limit: LFpUT<7:0> Can be updated with LFmode<6> = 1 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 73 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com M LF PreAmble Width LowerTimeLimit ESFR: 0xAC BIT 7 Not Bit Addressable LFpLT BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 w U S w U S w U S LFpLT<7:0> Access At Power on reset At Timer reset LFpLT<7:0> w U S w U S w U S w U S w U S PreAmble Cycle count LowerTime Limit: LFpLT<7:0> M LF SYNC Tail pattern Can be updated with LFmode<6> = 1 Not Bit Addressable ESFR: 0xAD BIT 7 LFsync0 BIT 6 BIT 5 BIT 4 w U S w U S BIT 3 BIT 2 BIT 1 BIT 0 w U S w U S w U S SYNC<7:0> Access At Power on reset At Timer reset SYNC<7:0> w U S w U S SYNC Tail Pattern Can be updated with LFmode<6> = 1 M LF SYNC Head pattern Not Bit Addressable ESFR: 0xAE BIT 7 LFsync1 BIT 6 BIT 5 BIT 4 - Access At Power on reset At Timer reset SYNC<14:8> w U S BIT 3 - x x w U S w U S w U S w U S SYNC Head Pattern BIT 7 BIT 1 BIT 0 w U S w U S w U S Can be updated with LFmode<6> = 1 M LF Wake ID #0 Tail pattern ESFR: 0xAF BIT 2 SYNC<14:8> Not Bit Addressable LFwake0L BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 w U S w U S w U S WAKE0<7:0> Access At Power on reset At Timer reset WAKE0<7:0> w U S w U S w U S w U S w U S WAKE ID Tail Pattern Can be updated with LFmode<6> = 1 M LF Wake ID #0 Head pattern ESFR: 0xB1 BIT 7 Not Bit Addressable LFwake0H BIT 6 BIT 5 BIT 4 w U S w U S BIT 3 BIT 2 BIT 1 BIT 0 w U S w U S w U S WAKE0<15:8> Access At Power on reset At Timer reset WAKE0<15:8> 74 w U S w U S w U S WAKE ID Head Pattern Can be updated with LFmode<6> = 1 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 M LF Wake ID #1 Tail pattern ESFR: 0xCC BIT 7 Not Bit Addressable LFwake1L BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 w U S w U S w U S WAKE1<7:0> Access At Power on reset At Timer reset WAKE1<7:0> w U S w U S w U S w U S w U S WAKE ID Tail Pattern Can be updated with LFmode<6> = 1 M LF Wake ID #1 Head pattern ESFR: 0xCD BIT 7 Not Bit Addressable LFwake1H BIT 6 BIT 5 BIT 4 w U S w U S BIT 3 BIT 2 BIT 1 BIT 0 w U S w U S w U S WAKE1<15:8> Access At Power on reset S WAKE1<15:8> w U S w U S WAKE ID Head Pattern Can be updated with LFmode<6> = 1 M LF Receiver State Not Bit Addressable ESFR: 0xC8 BIT 7 Access At Power on reset At Timer reset Ready Rx Data Valid ID Valid SYNC Valid SYNC Head Valid Preamble Valid Abort LF-OSC/32 LFstate BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Ready Rx DATA Valid ID Valid SYNC Valid SYNC Head_Valid Preamble Valid Abort LF-OSC/32 r 0 D r 0 D r 0 D r 0 D r 0 D r 0 D r 0 D r 0 D Rxdata Ready Data (Sync, Wakeup ID, Data) matching flag: 1 when matched Valid Wake-ID detection Valid SYNC pattern detection Valid SYNC head 111 pattern Valid Preamble Detection LF Receiver abort flag LF-OSC output divided by 32 M LF Analog FrontEnd Status ESFR: 0xE1 BIT 7 Access At Power on reset At Timer reset w U S Bit Addressable LFanalogFE BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Ready_AMP Monitor_BIA S RSSI by VT RSSI by average LF Carrier OUT LF-OSC Sample BIT0 r U D r U D r U D r U D r U D r U D r U D r U D Ready AMP Monitor BIAS RSSI by VT RSSI by average LF AMP Ready Flag Bias Current TRIM Monitor RSSI Threshold Comparator output RSSI Average Slicer output LF Carrier OUT LF-OSC Sample BIT0 LF AMP Carrier output LF-OSC (300 kHz) clock output Sample timing Incoming Data BIT0 monitor At Slicer offset trim, LFmode<BIT6> = 0 At Slicer LPF trim, LFmode<BIT6> = 1 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 75 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com M LF RX data buffer Not Bit Addressable ESFR: 0xE2 LFrxData BIT 6 BIT 7 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 r 0 D r 0 D r 0 D r 0 D BIT 3 BIT 2 BIT 1 BIT 0 r 0 D r 0 D r 0 D RxData<7:0> Access At Power on reset At Timer reset RxData<7:0> r 0 D r 0 D r 0 D r 0 D LF Rx Data M LF data count Not Bit Addressable ESFR: 0xEC BIT 7 LFdataCount BIT 6 BIT 5 BIT 4 r 0 D r 0 D r 0 D Wake-ID Access At Power on reset At Timer reset Wake-ID LFdataCount<7:0> LFdataCount<6:0> r 0 D r 0 D Wake-ID indicator 1bit Data width counted by 300 kHz OSC M LF Abort Timing Not Bit Addressable ESFR: 0xDC BIT 7 LFabort BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 OVERALLabort<4:0> Access At Power on reset At Timer reset w 0 D OVERALLabort<4:0> PREAMBLEabort<2:0 > w 0 D w 0 D LFcarrierDET<3:0> 76 w 0 D w 0 D w 0 D w 0 D w 0 D Not Bit Addressable ESFR: 0xDD PreVALID BIT 0 LF Sniffing overall time limit setting: Time = (OVERALLabort<4:0> * 512 + 257) * 4 * 3.3 s Preamble detecting time limit setting: Time = PREAMBLEabort<2:0> * 128 * 4 * 3.3 s If PREAMBLEabort<2:0> = 0, do not abort preamble detection M LF Carrier Detect Access At Power on reset At Timer reset BIT 1 PREAMBLEabort<2:0> BIT 7 LFCarrierDET BIT 6 BIT 5 BIT 4 - - - PreVALID x x x x x x x x x w 0 D BIT 3 BIT 2 BIT 1 BIT 0 LFcarrierDET<3:0> w 0 D w 0 D w 0 D w 0 D Prevalid signal timing select: 1 = 3 continuous preamble signal Prevalid signal timing select: 0 = 5 continuous preamble signal Carrier Signal detection time (for Protocol 1a): Time = (1+LFcarrierDET<3:0>)* 8 * 3.3 S Protocol 1b, 1c, and 2, should be set to LFcarrierDE<3:0> = 0 FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 3.7 SLDS189 - MAY 2012 Sensor The basic architecture of the sensor block is shown in Figure 3-24. All measurements of pressure, acceleration, temperature and battery voltage are achieved with the comparison of the capacitance (or electric charges stored in the capacitor) between the reference capacitor and the sensing capacitor. First, the sensing bias point (VS) is biased at the neutral voltage by closing the switch of sense amp. At the same time, the other side of sensing capacitor (Csense) and reference capacitor (Cref) are biased at the low side and high side of the reference pulse driver output voltage, respectively. After opening the switch, the polarity of the pulse input for each capacitor is changed to the opposite side. If the capacitances of Csense and Cref are the same, the sensing output voltage (VS) will not change. If the capacitances are different, the output of the sense amp falls into H or L. The sensor capacitance is determined by finding the neutral point when changing the reference capacitor value. The measurements are processed automatically by the internal sequencer just after setting the reference capacitor value with the appropriate registers. With this configuration and calibration, the sensor ADC achieves 13-bit equivalent performance. External Capacitors VDD Pressure Pressure Cp 0.2 V Acceleration Acceleration Ca Measurement Block Diode Voltage Ct (=2.176pF) Temperature VDD Cv (=0.32pF) Battery Voltage Cref Select Drive Voltage Reference Block Cbase Comparator Result Charge Pulse Coffset Digital Control Logic Coffset 13-Bit Register Cbase 13-Bit Register Switch Control Sequencer Figure 3-24. 13-bit SAR-ADC Sensor Block Diagram The following describes the measurement techniques used for each sensor elements: 1. Pressure measurement: Tire pressure can be measured by comparing the capacitance of the FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 77 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com diaphragm (Cp) on the ceramic package and the capacitance of the internal 13-bit reference capacitors, Cref. At pressure measurement, Cref is charged by the battery voltage. The LSB of the Cref capacitor is 0.5 fF. 2. Acceleration measurement: Tire acceleration can be measured by comparing the capacitance of the external accelerator capacitor (Ca) and the capacitance of the internal 13-bit reference capacitors, Cref. At acceleration measurement Cref is charged by 0.2 V. The external acceleration capacitor module has two capacitors to detect two acceleration directions. 3. Temperature measurement: Tire temperature can be measured by comparing the capacitance of an internal capacitor charged by using PN junction diode (Ct) and the capacitance of the internal 13-bit reference capacitors, Cref. At temperature measurement, Cref is charged by using band gap reference voltage which is independent to temperature. Since PN junction has temperature characteristics of -2 mV/C, the temperature can be detected from the charged voltage of the reference block, the ratio of the measured capacitance, and Ct of 2.176 pF. The designed measurable temperature resolution is 0.05C in typical condition. 4. Battery voltage measurement: Battery voltage can be measured by comparing the capacitance (Cv) of the internal capacitor charged by supply voltage and the capacitance of the internal 13-bit reference capacitors, Cref. At battery voltage measurement, Cref is charged by using band gap reference voltage, which is independent to battery voltage. The battery voltage can be detected from the charged voltage of the reference block and the ratio of the measured capacitance and Cv of 0.32 pF. The designed measurable voltage resolution is 0.625 mV under typical conditions. Most of the measurement functions and adjustment parameters are pre-fixed by hardware and firmware. Therefore, the user can obtain the measured value by calling the APIs. For the detail of usage of APIs, refer to the Software Application Note. M Sensor Control Not Bit Addressable ESFR: 0xB3 SensorCONT BIT 6 BIT 7 Power Access At Power on reset At Timer reset Power SMODE<2:0> PostWait<1:0> PreWait<1:0> 78 BIT 5 BIT 4 SMODE<2:0> w 0 0 w 0 0 BIT 3 BIT 2 PostWait<1:0> w 0 0 w 0 0 w 0 0 w 0 0 BIT 1 BIT 0 PreWait<1:0> w 0 0 w 0 0 Power Control ON(1) OFF(0) Sensor Mode Control Sensor Wait Time Sensor Wait Time SMODE<2> SMODE<1> SMODE<0> 1 1 1 Operation Calibration Mode 1 1 0 Do not use this mode. (Pressure Reference Measurement mode) 1 0 1 Pressure Measurement mode 1 0 0 Acceleration 2 Measurement 0 1 1 Acceleration 1 Measurement 0 1 0 Temperature Measurement 0 0 1 Do not use this mode. (Shock Sensor Measurement) 0 0 0 BATT voltage Measurement PreWait<1> PreWait<0> Operation( 1 1 10 clock cycle 1 0 6 clock cycle 0 1 4 clock cycle FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 PreWait<1> PreWait<0> Operation( 0 0 3 clock cycle PostWait<1> PostWait<0> Operation( 1 1 16 clock cycle 1 0 8 clock cycle 0 1 4 clock cycle 0 0 2 clock cycle M Sensor OffsetL Not Bit Addressable ESFR: 0xB4 SensorOffsetL BIT 6 BIT 7 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 w 0 0 w 0 0 w 0 0 SensorOffset<7:0> Access At Power on reset At Timer reset SensorOffset<7:0> w 0 0 w 0 0 w 0 0 w 0 0 SensorOffset lower Value M Sensor OffsetH Not Bit Addressable ESFR: 0xB5 BIT 7 Access At Power on reset At Timer reset EN AnalogOUT SensorOffset<12:8> SensorOffsetH BIT 6 BIT 5 - - EN AnalogOUT - x x - x x w 0 0 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 w 0 0 w 0 0 SensorOffset<12:8> w 0 0 w 0 0 w 0 0 Enable (1), Disable (0) SensorOffset higher Value Operation (1) PreWait< 0 > (1) w 0 0 1 Test Monitor of 0.40 V Internal Voltage Reference to DO terminal 0 Test Monitor of 1.24 V Internal Voltage Reference to DO terminal Valid with EN_AnalogOUT = H, the check byte signal that comes from SPI is lost during this mode. M Sensor BaseL Not Bit Addressable ESFR: 0xB6 BIT 7 SensorBaseL BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 w 0 0 w 0 0 w 0 0 BIT 2 BIT 1 BIT 0 w 0 0 w 0 0 SensorBase<7:0> Access At Power on reset At Timer reset SensorBase<7:0> w 0 0 w 0 0 w 0 0 Not Bit Addressable ESFR: 0xB7 SensorBase<12:8> w 0 0 SensorBase lower Value M Sensor BaseH Access At Power on reset At Timer reset w 0 0 BIT 7 SensorBase H BIT 6 BIT 5 - - - - x x - x x - x x BIT 4 BIT 3 SensorBase<12:8> w 0 0 w 0 0 w 0 0 SensorBase higher Value FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 79 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com M Sensor Compensation BIT6 ESFR: 0xB9 BIT 7 Not Bit Addressable SensorDC0 BIT 6 BIT 5 BIT 4 - Access At Power on reset At Timer reset SensorDC0<6:0> - x x w 0 0 w 0 0 ESFR: 0xBA BIT 7 w 0 0 BIT 5 - x x BIT 7 BIT 4 w 0 0 w 0 0 - x x BIT 7 BIT 5 w 0 0 BIT 4 w 0 0 BIT 2 BIT 1 BIT 0 w 0 0 w 0 0 w 0 0 BIT 3 BIT 2 BIT 1 BIT 0 w 0 0 w 0 0 w 0 0 BIT 2 BIT 1 BIT 0 w 0 0 w 0 0 w 0 0 BIT 2 BIT 1 BIT 0 w 0 0 w 0 0 w 0 0 SensorDC2<6:0> w 0 0 w 0 0 w 0 0 w 0 0 Not Bit Addressable SensorDC3 BIT 6 BIT 5 BIT 4 - - x x BIT 3 SensorDC3<6:0> w 0 0 w 0 0 w 0 0 w 0 0 Compensation for BIT9 of SensorOffset<12:0> for TEST. Do not use for the Measurement. M Sensor Compensation BIT10 ESFR: 0xBD BIT 7 Not Bit Addressable SensorDC4 BIT 6 BIT 5 BIT 4 w 0 0 w 0 0 - 80 w 0 0 Compensation for BIT8 of SensorOffset<12:0> for TEST. Do not use for the Measurement. ESFR: 0xBC Access At Power on reset At Timer reset 3 SensorDC4<6:0> w 0 0 Not Bit Addressable SensorDC2 BIT 6 M Sensor Compensation BIT9 SensorDC3<6:0> BIT 3 w 0 0 - Access At Power on reset At Timer reset w 0 0 Compensation for BIT7 of SensorOffset<12:0> for TEST. Do not use for the Sensor Measurement. ESFR: 0xBB SensorDC2<6:0> BIT 0 SensorDC1<6:0> M Sensor Compensation BIT8 Access At Power on reset At Timer reset BIT 1 Not Bit Addressable SensorDC1 BIT 6 - SensorDC1<6:0> BIT 2 Compensation for BIT6 of SensorOffset<12:0> for TEST. Do not use for the Sensor Measurement. M Sensor Compensation BIT7 Access At Power on reset At Timer reset BIT 3 SensorDC0<6:0> - x x BIT 3 SensorDC4<6:0> w 0 0 w 0 0 Compensation for BIT10 of SensorOffset<12:0> for TEST. Do not use for the Measurement. FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 M Sensor Compensation BIT11 Not Bit Addressable ESFR: 0xBE SensorDC5 BIT 6 BIT 7 BIT 5 BIT 4 - Access At Power on reset At Timer reset SensorDC5<6:0> BIT 3 - x x w 0 0 w 0 0 w 0 0 SensorDC6 BIT 6 BIT 7 Access At Power on reset At Timer reset w 0 0 w 0 0 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 w 0 0 w 0 0 w 0 0 SensorDC6<6:0> w 0 0 w 0 0 w 0 0 w 0 0 w 0 0 Activate to add Sensor Compensation Data (SensorDC6-SensorDC0): Enable (1), Disable (0), must be set to SensorDC6<6:0> = 0 when Disable (0). Compensation for BIT12 of SensorOffset<12:0> for TEST. Do not use for the Measurement. M Sensor State Not Bit Addressable ESFR: 0xC0 BIT 7 Ready_BG BUSY Conversion Result_A/D w 0 0 w 0 0 Activate_SensorDC Access At Power on reset At Timer reset BIT 0 Not Bit Addressable ESFR: 0xBF SensorDC6<6:0> BIT 1 Compensation for BIT11 of SensorOffset<12:0> for TEST. Do not use for the Measurement. M Sensor Compensation BIT12 Activate_SensorDC BIT 2 SensorDC5<6:0> SensorState BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Ready BG BUSY Conversion Result_A/D - - - - - r 0 0 r 0 0 r U U - x x - x x - x x - x x - x x Ready Flag of Bandgap Reference Regulator Status Flag of A/D Conversion A/D conversion Result FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 81 TPIC82000 Series SLDS189 - MAY 2012 3.8 3.8.1 www.ti.com Debug Mode ESFR M TEST Mode control0 Not Bit Addressable ESFR: 0x84 BIT 7 BIT 5 BIT 4 EN UART Reserved EN_Interrupt EN BP Interrupt w 0 0 w 0 0 w 0 0 w 0 0 Access At Power on reset At Timer reset EN UART EN_Interrupt EN BP Interrupt TESTmux0 BIT 6 BIT 7 w 0 0 BIT 0 Reserved w 0 0 w 0 0 0: Disable, 1: Enable 0: Disable, 1: Enable TESTvector BIT 6 BIT 5 BIT 4 BIT 3 Reserved w 0 0 BIT 2 BIT 1 BIT 0 w 0 0 w 0 0 w 0 0 BIT 2 BIT 1 BIT 0 TestVector<5:0> w 0 0 w 0 0 w 0 0 w 0 0 To be used as a TEST Vector when Micro restarts M Upper Breakpoint Register ESFR: 0x92 BIT 7 Access At Power on reset At Timer reset w 0 0 BIT 1 Not Bit Addressable ESFR: 0x91 TestVector<5:0> BIT 2 Enable UART debug interface Interrupt IE0 from RESET_TEST Interrupt IE0 from RESET TEST M TEST Mode Control Access At Power on reset At Timer reset BIT 3 Not Bit Addressable BPU BIT 6 - - - x x - x x BIT 5 BIT 7 BIT 3 BPU<5:0> w 0 0 M Lower Breakpoint Register ESFR: 0x93 BIT 4 w 0 0 w 0 0 w 0 0 w 0 0 w 0 0 BIT 3 BIT 2 BIT 1 BIT 0 w 0 0 w 0 0 w 0 0 Not Bit Addressable BPL BIT 6 BIT 5 BIT 4 BPL<7:0> Access At Power on reset At Timer reset BPU<5:0> BPL<7:0> 82 w 0 0 w 0 0 w 0 0 w 0 0 w 0 0 Upper Breakpoint Register Lower Breakpoint Register BreakPoint Address BP<13:0> = BPU<5:0> * 256 + BPL<7:0> FUNCTION DESCRIPTION Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 4 ELECTRICAL SPECIFICATIONS 4.1 Absolute Maximum Ratings (TA = -40C to 125C, unless otherwise specified) (1) (2) MIN VDD VDD-GND RESET_ TEST PP1 PP2 VI Supply Voltage Diaphragm Pressure Sensor Input Pressure (Absolute) DI Input Voltage Range TYP MAX -0.3 3.6 -0.3 7 0 1100 -0.3 VDD+0.3 XTAL -0.3 VDD+0.3 RFOUT -0.3 VDD+0.3 VILD LD -0.3 VDD+0.3 VICK CK -0.3 VDD+0.3 IOST RFOUT Output Current 20 DO Diaphragm Direction (z) Adp Dynamic Acceleration Mechanical shock Any Direction (< 10 mS) TJ Operating Junction Temperature Range TA Tstg All pins (1) (2) V kPa V mA 10 Static Acceleration Mechanical shock Adc V 10 TVO As UNIT 2000 Package-side Direction (x, y) G 100 7000 G -40 150 C Operating Ambient Temperature Range -40 125 C Storage Temperature Range -65 150 C 260 C Lead Temperature (Soldering, 10 s) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Note all voltage values are with respect to GND. Recommended Operating Conditions (1) 4.2 (TA = -40C to 125C, VDD = 1.5 V to 3.5 V, unless otherwise specified) VDD VDD-GND Supply Voltage PP1 Diaphragm Input Pressure Range (for Section 5.1.1) After software adjustment PP2 Diaphragm Input pressure range (for Section 5.1.2) After software adjustment MM Accelerometer Input Acceleration Range CK, LD, DI VIH RESET_TEST CK, LD, DI VIL RESET_TEST FCLK CK FXTAL XTAL FCLF LFIN TA (1) Measurement Withstand H Level Input Voltage Range L Level Input Voltage Range MIN TYP MAX 1.5 3 3.5 V 50 635 kPa 50 635 kPa -2 10 -1600 1600 0.8xVDD VDD VDD+3 6.9 0 0.2xVDD 0 VDD+0.8 10 Input Frequency Operating Ambient Temperature Range UNIT G V V MHz 19.68 19.70 19.72 120 125 130 kHz -40 25 125 C The accelerometer characteristic is applied only for TPIC8201XX. ELECTRICAL SPECIFICATIONS Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 83 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com Figure 4-1 shows the relationship between the package diaphragm side and the accelerator measurement direction. Accelerator Negative Direction ( G) Accelerator Positive Direction (+G) Diaphragm IC G Sensor (MEMS) Front Side Back Side Figure 4-1. Relationship Between Package Diaphragm Side and Accelerator Measurement Direction 84 ELECTRICAL SPECIFICATIONS Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 5 ELECTRICAL CHARACTERISTICS 5.1 Sensor There are two specifications available at the TEST (selection A and B) of the same pressure sensor shown in Section 5.1.1, Section 5.1.2, Figure 5-1 and Figure 5-2. 5.1.1 Pressure Sensor (Selection A) for (50 kPa to 635 kPa Range) TA = -40C to 125C, VDD = 1.5 V to 3.5 V (unless otherwise specified) PARAMETERS PSR1 TEST CONDITIONS Pressure Measurement Resolution MIN PPS = 50 kPa to 635 kPa TYP MAX UNITS 0.86 200 kPa PPS < 450 kPa -30C TA < 100C kPa -7 7 kPa -10 10 kPa -15 15 kPa -20 20 kPa 200 kPa PPS < 450 kPa PSA1 -40C TA < -30C Pressure Measurement Accuracy (After Software Compensation) 100C TA < 120C 100 kPa PPS < 200 kPa -40C TA < 120C Other than above 5.1.2 Pressure Sensor (Selection B) for (50 kPa to 635 kPa Range) TA = -40C to 125C, VDD = 1.5 V to 3.5 V (unless otherwise specified) PARAMETERS PSR2 TEST CONDITIONS Pressure Measurement Resolution 100 kPa PPS < 450 kPa -40C TA < 0C 100 kPa PPS < 450 kPa PSA2 Pressure Measurement Accuracy (After Software Compensation) 0C TA < 50C 100 kPa PPS < 450 kPa 50C TA < 125C Other than above 635 MAX UNITS 0.86 kPa -15 15 kPa -8 8 kPa -15 15 kPa -20 20 kPa 635 600 600 20 kPa 20 KPa 500 200 20 kPa 7 kPa 10 kPa 400 Pressure (kPa) 500 10 kPa Pressure (kPa) TYP Pressure Sensor Accuracy Pressure Sensor Accuracy 300 MIN PPS = 50 kPa to 635 kPa 400 300 15 kPa 8 kPa 15 kPa 200 15 kPa 100 50 100 20 kPa 20 kPa 50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100110 120 125 Temperature (C) Figure 5-1. Pressure Sensor (Selection A) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110120125 Temperature (C) Figure 5-2. Pressure Sensor (Selection B) ELECTRICAL CHARACTERISTICS Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 85 TPIC82000 Series SLDS189 - MAY 2012 5.1.3 www.ti.com Temperature / Voltage / Acceleration Sensor TA = -40C to 125C, VDD = 1.5 V to 3.5 V (unless otherwise specified) PARAMETER TSR TEST CONDITIONS Temperature Measurement Resolution TSA Voltage Measurement Resolution VSA Voltage Measurement Accuracy GSR Acceleration Measurement Resolution (1) GSA Acceleration Measurement Accuracy (1) (1) TYP TTS = -40C to 125C Temperature Measurement Accuracy VSR MIN MAX 0.05 C -40C TA < -20C -5 5 -20C TA < 70C -3 3 70C TA 125C -5 5 0.625 C mV -0.1xVDD 0.1xVDD 0.0625 Detection of acceleration at 5 G UNIT V G -3 3 G The accelerometer characteristic is applied only for TPIC8201XX. 5.2 Power Supply TA = -40C to 125C, VDD = 1.5 V to 3.5 V (unless otherwise specified) PARAMETER Consumption Current IDD PIN NAME VDD TYP MAX Standby Timer-OSC only (TA = 25C, VDD = 3 V) TEST CONDITIONS MIN 0.1 0.4 A Standby with LF receiving LF AMP + Carrier detection (TA = 25C, VDD = 3 V) For Protocol 1a,1c,2 4.5 12 A Standby with LF receiving LF AMP + Pattern detection (TA = 25C, VDD = 3 V) For Protocol-1b 11 18 A Measurement State (TA = 25C, VDD = 3 V) 1.53 Measurement State MCU Power On mode with Xtal-OSC (TA = 25C, VDD = 3 V) MCU Power On mode with Xtal-OSC (1) mA 1.53 2.1 mA 1.3 1.6 mA 2.9 mA 10 mA (1) 315 MHz Transmitting State, Po = 5 dBm (TA = 25C, VDD = 3 V) (1) UNIT 9 315 MHz Transmitting State, Po = 5 dBm 9 12 mA 434 MHz Transmitting State, Po = 5 dBm (TA = 25C, VDD = 3 V) 10.5 11.5 mA 434 MHz Transmitting State, Po = 5 dBm 10.5 14 mA Xtal-OSC bias <3:0> = 8 5.3 Xtal-OSC TA = -40C to 125C, VDD = 1.5 V to 3.5 V (unless otherwise specified) PARAMETER PIN NAME Fxtal Oscillation Frequency XTAL Fstart Oscillation Start-up time (1) XTAL Fmargin Oscillation Margin XTAL Cxtal XTAL Input Capacitance (2) XTAL (1) (2) 86 TEST CONDITIONS MIN KYOCERA CX3225SA XTAL = 19.707894 MHz, ESR(CI) = 30 KYOCERA CX3225SA XTAL = 19.707894MHz, ESR(CI) = 30 TYP MAX 19.70789 MHz 4 10 5 UNIT ms Times 6.7 10 pF Reference data Included package capacitance. Design specified. ELECTRICAL CHARACTERISTICS Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com 5.4 SLDS189 - MAY 2012 PLL TA = -40C to 125C, VDD = 1.5 V to 3.5 V, except 25C < TA< 125C, 1.75 V VDD (unless otherwise specified) PARAMETER Tlock PIN NAME Lock up time Phase Noise RFOUT Fvcomin Minimum VCO Oscillation Frequency (1) RFOUT (1) (2) (3) MIN TYP MAX UNIT s RFOUT PN Fvcomax TEST CONDITIONS Maximum VCO Oscillation Frequency (1) 315 MHz (2) 434 MHz (3) 10 100 10 kHz offset -80 -60 100 kHz offset -80 -70 dBc/Hz 1 MHz offset -90 -80 150 MHz 350 25C < TA < 125C, 1.75 V VDD RFOUT MHz 450 Design specified The 315 MHz characteristic is applied for TPIC820XX3. The 434 MHz characteristic is applied for TPIC820XX4. 5.5 Timer-OSC TA = -40C to 125C, VDD = 1.5 V to 3.5 V (unless otherwise specified) PARAMETER PIN NAME (1) Ftm Oscillation Frequency Ftmeror Oscillation Frequency Adjustment Error Ftmdrift (1) 5.6 Oscillation Frequency Temperature Drift MIN TYP MAX UNIT After software adjustment TEST CONDITIONS 400 450 500 Hz After software adjustment -10% 10% t = 20C 80C TA 125C 2 t = 20C -40C TA 80C 0.5 1 %/C LF sniffing interval is determined by oscillation frequency. For LF pattern Protocol 1a and 1c, use LF sniffing interval including variation (should be trimmed shorter than preamble period). 9.6 MHz RC-OSC TA = -40C to 125C, VDD = 1.5 V to 3.5 V, (unless otherwise specified) PARAMETER Frco PIN NAME Oscillation Frequency TEST CONDITIONS After software adjustment MIN TYP MAX UNIT 7.68 9.6 11.52 MHz ELECTRICAL CHARACTERISTICS Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 87 TPIC82000 Series SLDS189 - MAY 2012 5.7 www.ti.com BB Modulator and RF PA TA = -40C to 125C, VDD = 1.5 V to 3.5 V, except 25C < TA< 125C, 1.75 V VDD (unless otherwise specified) PARAMETERS (1) fTXC1 Carrier Frequency (FSK Center Frequency) fTXC2 PIN NAME TEST CONDITIONS 315 MHz RFOUT fXTAL = 19.707894 MHz, DIV = 1/16 (2) 434 MHz RFOUT fXTAL = 19.707894 MHz, DIV = 1/22 (2) fOF1 Minimum Carrier Offset Adjustment Frequency 315 MHz RFOUT fXTAL = 19.707894 MHz fOF2 Maximum Carrier Offset Adjustment Frequency 434 MHz RFOUT fXTAL = 19.707894 MHz Pout Output Power (After adjustment to 5 dBm) TA = 25C, VDD = 3 V, Load = 50 315 MHz RFOUT Load = 50 434 MHz Fdr Frequency Deviation Range RFOUT Fda Frequency Deviation Accuracy RFOUT fXTAL = 19.707894 MHz, FSK mode Fdstep Frequency Shift Adjustment Step RFOUT fXTAL = 19.707894 MHz Fspeed Fobw Data Speed RFOUT Occupied Bandwidth ETXS Spurious ETXS (1) (2) (3) 434 MHz TYP MAX 314.977 314.980 314.983 433.917 433.920 433.923 UNIT MHz -700 700 kHz kHz 4 5 6 dBm 1 (3) 5 7 dBm 0.5 (3) 5 7 dBm 150 kHz 3 kHz -150 -3 1.2 fXTAL = 19.707894 MHz, At register setting: ModScale <7:0> = 8, ModRAMAdd <5:0> = 31, FSK/ASK mode 9.62 fXTAL = 19.707894 MHz, At register setting : ModScale <7:0> = 4, ModRAMAdd <5:0> = 31 FSK mode only 19.25 9.93 kHz 10.26 K bits/s 19.87 20.53 RFOUT TA = 25C, VDD = 3 V, Load = 50 , Span = 3 MHz, 99%, RBW = 30 kHz 400 RFOUT F < 315.25 MHz, On the test board, TA = 25C, VDD = 3 V, Load = 50 -25 RFOUT f > 315.25 MHz, On the test board, TA = 25C, VDD = 3 V, Load = 50 -30 RFOUT On the test board, TA = 25C, VDD = 3 V, Load = 50 -25 315 MHz ETXS MIN kHz dBc For the electrical characteristic of the BB modulator and RF PA: The 315 MHz characteristic is applied for TPIC820XX3. The 434 MHz characteristic is applied for TPIC820XX4. With register setting: ModRAMData <7:0> (0xC9) = 28, ModOffset <7:0> (0xD1) = 65 at 315 MHz band, 65 at 434 MHz band. 25C < TA < 125C, 1.75 V VDD 5.8 LF Receiver TA = -40C to 125C, VDD = 1.5 V to 3.5 V (unless otherwise specified) PARAMETERS PIN NAME TEST CONDITIONS TA = 25C, VDD = 3 V MIN TYP 120 125 fLF Carrier Frequency LFIN ModASK AM Modulation Degree (1) LFIN Strig1a Minimum Input Sensitivity1 LFIN For Protocol 1b Strig1b Minimum Input Sensitivity2 LFIN For Protocol 1a, 1c, 2 Strig2 Maximum Input Sensitivity LFIN For Protocol 1a, 1b, 1c, 2 303 LFosc LF Oscillator Frequency After Software Adjustment 285 LFsn Signal-to-noise ratio (1) (1) 88 LFIN 50% TA = 25C, VDD = 3 V 6 MAX UNITS 130 kHz 100% 0.5 1.2 mVpp 0.7 1.7 mVpp 300 360 mVpp kHz dB Design specified ELECTRICAL CHARACTERISTICS Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series TPIC82000 Series www.ti.com SLDS189 - MAY 2012 TA = -40C to 125C, VDD = 1.5 V to 3.5 V (unless otherwise specified) PARAMETERS PIN NAME TEST CONDITIONS MIN TYP MAX UNITS T1a Protocol 1a LFIN TA = 25C, VDD = 3 V 2.2 ms T1b Protocol 1b LFIN TA = 25C, VDD = 3 V 205 ms Protocol 1c LFIN TA = 25C, VDD = 3 V 2.2 ms T2 Protocol 2 LFIN TA = 25C, VDD = 3 V, TWAKE = 5 mS 2.2 ms TW1a Protocol 1a LFIN TA = 25C, VDD = 3 V TW1b Protocol 1b LFIN TA = 25C, VDD = 3 V LF Sniffing Interval (2) T1c LF Sniff-On Period (2) TW1c 280 mS Protocol 1c LFIN TA = 25C, VDD = 3 V 150 270 TW2 Protocol 2 LFIN TA = 25C, VDD = 3 V 150 270 fLFp1 Protocol 1a, 1b, 1c LFIN TA = 25C, VDD = 3 V 3.8 Protocol 2 Data Speed fLFp2 LFIN TA = 25C, VDD = 3 V LFrin Input Resistance (1) LFIN TA = 25C, VDD = 3 V CI Input Capacitance (1) LFIN (2) s 450 7 3.9 4 s s kbits/s 100 bps 1000 k 1.6 2 2.4 pF Refer to each timing example of Protocol 1a (see Section 3.6.3.1), 1b (see Section 3.6.3.2), 1c (see Section 3.6.3.3), and 2 (see Section 3.6.3.6). 5.9 Voltage Regulator (VREG) TA = -40C to 125C, VDD = 1.5 V to 3.5 V (unless otherwise specified) (1) (2) PARAMETER PIN NAME TEST CONDITIONS Vreg VREG Output Voltage VREG ILoad = 0 mA, CL = 0.1 F 10% (3) Tvreg VREG Startup Time VREG Ipeak Peak current at VREG Startup VDD (1) (2) (3) MIN TYP MAX 1.45 1.55 UNIT 1.65 V ILoad = 0 mA, CL = 0.1 F 10% (3) 0.5 ms ILoad = 0 mA, CL = 0.1 F 10% (3) 5 mA This voltage regulator is only for the supply voltage of the internal circuit. It is not designed to be the power supply source of any external circuitry. Recommended decoupling capacitor: 0.1 F, Capacitor tolerance: max 10% Temperature variation: max 15% over TA = -40C to 125C, ESR: max 1 CL (Decoupling capacitor) should be connected between the VREG pin and GND. 5.10 Power-on-Reset and Hardware Reset TA = -40C to 125C, VDD = 1.5 V to 3.5 V (unless otherwise specified) PARAMETER PIN NAME tr-VDD Rising time of VDD VDD off-VDD Interval of VDD power on VDD tW-RST Reset Pulse width RESET-TEST Pull-down resistance RESET-TEST TEST CONDITIONS MIN TYP MAX UNIT 1 8 ms 1 VIN (RESET-TEST) = 1 V 30 ms s 50 80 k Figure 5-3 shows the Power-on-Reset and the Hardware Reset. Power-on-Reset tr-VDD Hardware Reset toff-VDD tW-RST RESET_TEST VDD VIH Figure 5-3. Power-on-Reset and Hardware Reset ELECTRICAL CHARACTERISTICS Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series 89 TPIC82000 Series SLDS189 - MAY 2012 www.ti.com 5.11 EEPROM Read:TA = -40C to 125C, VDD = 1.5 V to 3.5 V: Program: TA = 0C to 50C, VDD = 2.5 V to 3.5 V (unless otherwise specified) MIN TYP MAX VPP Program voltage PARAMETER 12 12.4 14 Teeprom Program time 10 20 100 Neeprom Number of Program times 10 times Leeprom Storage life time 10 years 90 PIN NAME TEST CONDITIONS ELECTRICAL CHARACTERISTICS UNIT V ms Copyright (c) 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPIC82000 Series PACKAGE OPTION ADDENDUM www.ti.com 5-Dec-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPIC82000FFE PREVIEW LCCC FFE 16 416 TBD Call TI Call TI -40 to 125 TPIC82000FFER PREVIEW LCCC FFE 16 1000 TBD Call TI Call TI -40 to 125 TPIC82010FFE PREVIEW LCCC FFE 16 416 TBD Call TI Call TI -40 to 125 TPIC82010FFER ACTIVE LCCC FFE 16 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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