19-3871; Rev 2; 5/06 KIT ATION EVALU LE B A IL A AV Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC The MAX5550 dual, 10-bit, digital-to-analog converter (DAC) features high-output-current capability. The MAX5550 sources up to 30mA per DAC, making it ideal for PIN diode biasing applications. Outputs can also be paralleled for high-current applications (up to 60mA typ). Operating from a single +2.7V to +5.25V supply, the MAX5550 typically consumes 1.5mA per DAC in normal operation and less than 1A (max) in shutdown mode. The MAX5550 also features low output leakage current in shutdown mode (1A max) that is essential to ensure that the external PIN diodes are off. Additional features include an integrated +1.25V bandgap reference, and a control amplifier to ensure high accuracy and low-noise performance. A separate reference input (REFIN) allows for the use of an external reference source, such as the MAX6126, for improved gain accuracy. A pin-selectable I2C-/SPITM-compatible serial interface provides optimum flexibility for the MAX5550. The maximum programmable output current value is set using software and an adjustment resistor. The MAX5550 is available in a (3mm x 3mm) 16-pin thin QFN package, and is specified over the extended (-40C to +85C) temperature range. Applications PIN Diode Biasing RF Attenuator Control Features Pin-Selectable or SPI-Compatible Interface Guaranteed Low Output Leakage Current in Shutdown (1A max) Guaranteed Monotonic over Extended Temperature Range Dual Outputs for Balanced Systems I2C- Current Outputs Source Up to 30mA per DAC Parallelable Outputs for 60mA Applications Output Stable with RF Filters Internal or External Reference Capability Digital Output (DOUT) Available for Daisy Chaining in SPI Mode +2.7V to +5.25V Single-Supply Operation 16-Pin (3mm x 3mm) Thin QFN Package Programmable Output Current Range Set by Software and Adjustment Resistor Ordering Information PART PKG CODE TOP MARK T1633F-3 ACZ PIN-PACKAGE MAX5550ETE 16 Thin QFN-EP* *EP = Exposed paddle. Note: Device is specified over the -40C to +85C operating range. VCO Tuning Functional Diagram VDD REFIN +1.25V REF BUFFER P 10-BIT CURRENT-STEERING DAC A OUTA FSADJA VDD MAX5550 P 10-BIT CURRENT-STEERING DAC B SPI is a trademark of Motorola, Inc. DAC REGISTER A SPI/I2C Pin Configuration appears at end of data sheet. DAC REGISTER B OUTB FSADJB 16-BIT INPUT REGISTER SCLK/SCL DIN/SDA CS/A0 DOUT/A1 GND ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX5550 General Description MAX5550 Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC ABSOLUTE MAXIMUM RATINGS VDD to GND .............................................................-0.3V to +6V OUTA, OUTB to GND .................................-0.3V to (VDD + 0.3V) REFIN, CS/AO, DOUT/AI, SPI/I2C, FSADJA, FSADJB to GND ......................................-0.3V to (VDD + 0.3V) SCLK/SCL, DIN/SDA ................................................-0.3V to +6V Continuous Power Dissipation (TA = +85C) 16-Pin Thin QFN (derate 17.5mW/C above +70C) ..1398.6mW Operating Temperature Range ...........................-40C to +85C Junction Temperature .....................................................+150C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +5.25V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20k; compliance voltage = (VDD - 0.6V), VSCLK/SCL = 0, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +3.0V and TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE--ANALOG SECTION Resolution 10 Integral Nonlinearity INL IOUT_ = 1mA to 30mA (Note 2) Differential Nonlinearity DNL Guaranteed monotonic Offset IOS Bits 2 LSB 1 -50 Zero-Scale Error IOUT_ = 1mA to 30mA, code = 0x000 Full-Scale Error IOUT_ = 1mA to 30mA, code = 0x3FF, includes offset -16 LSB LSB 1 -16 A LSB REFERENCE Internal Reference Range 1.21 Internal Reference Tempco 1.25 1.29 30 External Reference Range 0.5 External Reference Input Current 108 V ppm/C 1.5 V 225 A 30 mA 1 A DAC OUTPUTS Full-Scale Current (Note 3) 1 Output Current Leakage in Shutdown Output Capacitance 10 IOUT_ = 30mA Current Source Dropout Voltage (VDD - VOUT_) IOUT_ = 20mA pF 1 TA = +25C 0.55 TA = -40C to +85C 0.6 Output Impedance at Full-Scale Current V 100 k Capacitive Load to Ground CLOAD 10 nF Series Inductive Load LLOAD 100 nH CFSADJ_ 75 pF 30 s 2 nVs Maximum FSADJ_ Capacitive Load DYNAMIC PERFORMANCE Settling Time Digital Feedthrough 2 tS CLOAD = 24pF, LLOAD = 27nH (Note 4) _______________________________________________________________________________________ Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC (VDD = +2.7V to +5.25V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20k; compliance voltage = (VDD - 0.6V), VSCLK/SCL = 0, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +3.0V and TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Digital-to-Analog Glitch Impulse 40 nVs DAC-to-DAC Current Matching 2 % Wake-Up Time VDD = +3V 400 VDD = +5V 10 s POWER SUPPLIES Supply Voltage VDD Supply Current IDD +2.70 VDD = +5.25V, no load 3 Shutdown Current +5.25 V 6 mA 1.2 A LOGIC AND CONTROL INPUTS Input High Voltage (Note 5) VIH Input Low Voltage VIL +2.7V VDD +3.4V +3.4V < VDD +5.25V 0.7 x VDD V 2.4 (Note 5) 0.8 VHYS 0.1 x VDD Input Capacitance CIN 10 Input Leakage Current IIN Input Hysteresis Output Low Voltage VOL ISINK = 3mA Output High Voltage VOH ISOURCE = 2mA V V pF 1 A 0.6 V VDD 0.5 V I2C TIMING CHARACTERISTICS (Figure 2) SCL Clock Frequency fSCL 400 kHz Setup Time for START Condition tSU:STA 600 ns Hold Time for START Condition tHD:STA 600 ns tLOW 130 ns ns SCL Pulse-Width Low SCL Pulse-Width High tHIGH 600 Data Setup Time tSU:DAT 100 Data Hold Time tHD:DAT 0 SCL Rise Time tRCL SCL Fall Time ns 70 ns 20 + 0.1 x CB 300 ns tFCL 20 + 0.1 x CB 300 ns SDA Rise Time tRDA 20 + 0.1 x CB 300 ns SDA Fall Time tFDA 20 + 0.1 x CB 300 ns _______________________________________________________________________________________ 3 MAX5550 ELECTRICAL CHARACTERISTICS (continued) MAX5550 Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +5.25V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20k; compliance voltage = (VDD - 0.6V), VSCLK/SCL = 0, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +3.0V and TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Bus Free Time Between a STOP and START Condition tBUF 1.3 s Setup Time for STOP Condition tSU:STO 160 ns Maximum Capacitive Load for Each Bus Line CB 400 pF SPI TIMING CHARACTERISTICS (Figure 6) SCLK Clock Period tCP 100 ns SCLK Pulse-Width High tCH 40 ns SCLK Pulse-Width Low tCL 40 ns CS Fall to SCLK Rise Setup Time tCSS 25 ns SCLK Rise to CS Rise Hold Time tCSH 50 ns DIN Setup Time tDS 40 ns DIN Hold Time tDH 0 ns SCLK Fall to DOUT Transition tDO1 CLOAD = 30pF 40 ns CS Fall to DOUT Enable tCSE CLOAD = 30pF 40 ns CS Rise to DOUT Disable tCSD CLOAD = 30pF 40 SCLK Rise to CS Fall Delay tCS0 50 ns ns CS Rise to SCLK Rise Hold Time tCS1 40 ns CS Pulse-Width High tCSW 100 ns SPI TIMING CHARACTERISTICS FOR DAISY CHAINING (Figure 6) SCLK Clock Period tCP 200 ns SCLK Pulse-Width High tCH 80 ns SCLK Pulse-Width Low tCL 80 ns CS Fall to SCLK Rise Setup Time tCSS 25 ns SCLK Rise to CS Rise Hold Time tCSH 50 ns DIN Setup Time tDS 40 ns DIN Hold Time tDH 0 ns SCLK Fall to DOUT Transition tDO1 CLOAD = 30pF 40 ns CS Fall to DOUT Enable tCSE CLOAD = 30pF 40 ns CS Rise to DOUT Disable tCSD CLOAD = 30pF 40 SCLK Rise to CS Fall Delay tCS0 50 ns ns CS Rise to SCLK Rise Hold Time tCS1 40 ns CS Pulse-Width High tCSW 100 ns Note 1: Note 2: Note 3: Note 4: Note 5: 4 100% production tested at TA = +25C. Limits over temperature are guaranteed by design. INL linearity is guaranteed from code 60 to code 1024. Connect a resistor from FSADJ_ to GND to adjust the full-scale current. See the Reference Architecture and Operation section. Settling time is measured from (0.25 x full scale) to (0.75 x full scale). The device draws higher supply current when the digital inputs are driven with voltages between (VDD - 0.5V) and (GND + 0.5V). See the Supply Current vs. Digital Input Voltage graph in the Typical Operating Characteristics. _______________________________________________________________________________________ Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC DNL vs. CODE 3.0 0.25 2.5 0 INL (LSB) 0.50 0.5 0 2.0 -0.25 1.5 -1.0 -0.50 1.0 -1.5 -0.75 0.5 -2.0 -1.00 128 256 384 512 640 768 896 1024 CODE 0 0 128 256 384 512 640 768 896 1024 CODE MAXIMUM INL ERROR vs. OUTPUT CURRENT RANGES DNL vs. TEMPERATURE 2.5 0.30 2.0 INL (LSB) 0.25 0.20 0.15 1.5 1.0 0.10 60 85 4.0 0.5 0.05 10 35 TEMPERATURE (C) 4.5 ZERO-SCALE CURRENT (nA) 0.35 -15 ZERO-SCALE OUTPUT CURRENT vs. TEMPERATURE MAX5550 toc05 3.0 MAX5550 toc04 0.40 -40 MAX5550 toc06 0 DNL (LSB) 3.5 1.0 -0.5 3.5 3.0 VDD = 5V 2.5 2.0 1.5 VDD = 3V 1.0 0.5 0 0 -40 -15 10 35 TEMPERATURE (C) 60 85 FULL-SCALE CURRENT vs. TEMPERATURE 0 1-2 2-5 8-16 15-30 1.5-3 4.5-9 OUTPUT CURRENT RANGE (mA) -40 -15 10 35 VDD = 5V 29.84 85 SETTLING TIME (FULL-SCALE POSITIVE STEP) SETTLING TIME (FULL-SCALE NEGATIVE STEP) MAX5550 toc09 MAX5550 toc07 29.86 60 TEMPERATURE (C) MAX5550 toc08 29.88 FULL-SCALE CURRENT (mA) 4.0 MAX5550 toc02 MAX5550 toc01 0.75 DNL (LSB) INL (LSB) 1.5 INL vs. TEMPERATURE 1.00 MAX5550 toc03 INL vs. CODE 2.0 MAX5550 Typical Operating Characteristics (VDD = +3.0V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20k, TA = +25C. unless otherwise noted). CS 2V/div 29.82 CS 2V/div RLOAD = 65 CLOAD = 24pF 29.80 29.78 VDD = 3V 29.76 RLOAD = 65 CLOAD = 24pF 29.74 29.72 -40 -15 10 35 TEMPERATURE (C) 60 VOUT_ 1V/div VOUT_ 1V/div 85 10s/div 10s/div _______________________________________________________________________________________ 5 Typical Operating Characteristics (continued) (VDD = +3.0V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20k, TA = +25C. unless otherwise noted). SHUTDOWN CURRENT vs. SUPPLY VOLTAGE GLITCH IMPULSE MAX5548 toc10 MAX5550 toc11 620 SHUTDOWN CURRENT (nA) NO LOAD, CODE = 0x00 CS 1V/div VOUT_ AC-COUPLED 10mV/div 520 420 320 RLOAD = 65 CLOAD = 24pF 220 2.5 40ns/div 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE SHUTDOWN CURRENT vs. TEMPERATURE NO LOAD, CODE = 0x00 INTERNAL REFERENCE VOLTAGE (V) NO LOAD, CODE = 0x00 MAX5550 toc13 1.25100 MAX5550 toc12 620 SHUTDOWN CURRENT (nA) 520 VDD = 5V 420 VDD = 3V 320 1.25075 1.25050 1.25025 1.25000 220 -40 -15 10 35 60 2.5 85 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) TEMPERATURE (C) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX5550 toc14 1.252 NO LOAD, CODE = 0x00 INTERNAL REFERENCE VOLTAGE (V) MAX5550 Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC 1.251 1.250 1.249 1.248 1.247 1.246 -40 -15 10 35 60 85 TEMPERATURE (C) 6 _______________________________________________________________________________________ Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE MAX5550 toc16 NO LOAD, CODE = 0x00 NO LOAD, CODE = 0x00 2.755 SUPPLY CURRENT (mA) 2.75 INTERNAL REFERENCE 2.70 VDD = 5V 2.750 2.745 VDD = 3V 2.740 2.65 2.735 EXTERNAL REFERENCE 2.730 2.60 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 -15 SUPPLY VOLTAGE (V) 10 35 60 85 TEMPERATURE (C) WAKE-UP TIME IOUT vs. VOUT MAX5550 toc17 MAX5550 toc18 35 30 CS 2V/div 25 IOUT (mA) VOUT_ 1V/div 20 VDD = 5V VDD = 3V 15 10 RLOAD = 65 CLOAD = 24pF 5 0 400s/div 0 SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE 1 2 3 VOUT (V) 4 5 DIGITAL FEEDTHROUGH MAX5550 toc20 MAX5550 toc19 10 NO LOAD, CODE = 0x00 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 2.760 MAX5550 toc15 2.80 SCLK 2V/div VDD = 5V VOUT_ AC-COUPLED 10mV/div VDD = 3V RLOAD = 65 CLOAD = 24pF 1 0 1 2 3 4 DIGITAL INPUT VOLTAGE (V) 5 400s/div _______________________________________________________________________________________ 7 MAX5550 Typical Operating Characteristics (continued) (VDD = +3.0V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20k, TA = +25C. unless otherwise noted). Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC MAX5550 Pin Description PIN NAME 1 SCLK/SC Serial Clock Input. Connect SCL to VDD through a 2.4k resistor in I2C mode. FUNCTION 2 DIN/SDA Serial Data Input. Connect SDA to VDD through a 2.4k resistor in I2C mode. 3 CS/A0 Chip-Select Input in SPI Mode/Address Select 0 in I2C Mode. CS is an active-low input. Connect A0 to VDD or GND to set the device address in I2C mode. 4 SPI/I2C SPI/I2C Select Input. Connect SPI/I2C to VDD to select SPI mode, or connect SPI/I2C to GND to select I2C mode. 5 DOUT/A1 Serial Data Output in SPI Mode/Address Select 1 in I2C Mode. Use DOUT to daisy chain the MAX5550 to other devices or to read back in SPI mode. The digital data is clocked out on SCLK's falling edge. Connect A1 to VDD or GND to set the device address in I2C mode. 6, 13, 15 N.C. 7 REFIN 8, 16 GND 9 OUTB No Connection. Leave unconnected or connect to GND. Reference Input. Drive REFIN with an external reference source between +0.5V and +1.5V. Leave REFIN unconnected in internal reference mode. Bypass with a 0.1F capacitor to GND as close to the device as possible. Ground DACB Output. OUTB provides up to 30mA of output current. 10 FSADJB DACB Full-Scale Adjust Input. For maximum full-scale output current, connect a 20k resistor between FSADJB and GND. For minimum full-scale current, connect a 40k resistor between FSADJB and GND. 11 FSADJA DACA Full-Scale Adjust Input. For maximum full-scale output current, connect a 20k resistor between FSADJA and GND. For minimum full-scale current, connect a 40k resistor between FSADJA and GND. 12 OUTA 14 VDD -- EP DACA Output. OUTA provides up to 30mA of output current. Power Supply Input. Connect VDD to a +2.7 to +5.25V power supply. Bypass VDD to GND with a 0.1F capacitor as close to the device as possible. Exposed Pad. Connect to GND. Do not use as a substitute ground connection. Detailed Description Architecture The MAX5550 10-bit, dual current-steering DAC (see the Functional Diagram) operates with DAC update rates up to 10Msps in SPI mode and 400ksps in I2C mode. The converter consists of a 16-bit shift register and input DAC registers, followed by a current-steering array. The current-steering array generates full-scale currents up to 30mA per DAC. An integrated +1.25V bandgap reference, control amplifier, and an external resistor determine each data converter's full-scale output range. Reference Architecture and Operation The MAX5550 provides an internal +1.25V bandgap reference or accepts an external reference voltage source between +0.5V and +1.5V. REFIN serves as the input for an external low-impedance reference source. Leave REFIN unconnected in internal reference mode. Internal or external reference mode is software selectable through the SPI/I2C serial interface. 8 The MAX5550's reference circuit (Figure 1) employs a control amplifier to regulate the full-scale current (IFS) for the current outputs of the DAC. This device has a software-selectable full-scale current range (see the command summary in Table 4). After selecting a current range, an external resistor (RFSADJ_) sets the full-scale current. See Table 1 for a matrix of IFS and RFSADJ selections. During startup, when the power is first applied, the MAX5550 defaults to the external reference mode, and to the 1mA-2mA full-scale current-range mode. DAC Data The 10-bit DAC data is decoded as offset binary, MSB first, with 1 LSB = IFS / 1024, and converted into the corresponding current as shown in Table 2. Serial Interface The MAX5550 features a pin-selectable SPI/I 2C serial interface. Connect SPI/I2C to GND to select I2C mode, or connect SPI/I2C to VDD to select SPI mode. SDA and SCL (I2C mode) and DIN, SCLK, and CS (SPI mode) facilitate communication between the MAX5550 and the master. The serial interface remains active in shutdown. _______________________________________________________________________________________ Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC The MAX5550 is compatible with existing I2C systems (Figure 2). SCL and SDA are high-impedance inputs; SDA has an open-drain output that pulls the data line low during the ninth clock pulse. SDA and SCL require pullup resistors (2.4k or greater) to V DD. Optional resistors (24) in series with SDA and SCL protect the device inputs from high-voltage spikes on the bus lines. Series resistors also minimize crosstalk and undershoot of the bus signals. The communication protocol supports standard I2C 8-bit communications. The device's address is compatible with 7-bit I2C addressing protocol only. Ten-bit address formats are not supported. Only write commands are accepted by the MAX5550. Note: I2C readback is not supported. Bit Transfer One data bit transfers during each SCL rising edge. The MAX5550 requires nine clock cycles to transfer data into or out of the DAC register. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are read as control signals (see the START and STOP Conditions section). Both SDA and SCL idle high. START and STOP Conditions The master initiates a transmission with a START condition (S), (a high-to-low transition on SDA with SCL high). The master terminates a transmission with a STOP condition (P), (a low-to-high transition on SDA while SCL is high) (Figure 3). A START condition from the master signals the beginning of a transmission to the MAX5550. The master terminates transmission by issuing a STOP condition. The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active. Table 1. Full-Scale Output Current and RFSADJ_ Selection Based on a +1.25V (typ) Reference Voltage FULL-SCALE OUTPUT CURRENT (mA)* RFSADJ (k) 1mA-2mA 1.5mA-3mA 2.5mA-5mA 4.5mA-9mA 8mA-16mA 15mA-30mA Calculated 1% EIA Std 1.00 1.500 2.500 4.500 8.00 15.00 40 40.2 1.25 1.875 3.125 5.625 10.00 18.75 35 34.8 1.50 2.250 3.750 6.750 12.00 22.50 30 30.1 1.75 2.625 4.375 7.875 14.00 26.25 25 24.9 2.00 3.000 5.000 9.000 16.00 30.00 20 20.0 *See the command summary in Table 4. Table 2. DAC Output Code Table DAC CODE +1.25V REFERENCE VDD OUT_ FSADJ_ IFSADJ IOUT_ 11 1111 1111 I 1023 x FS - | IOS | 1024 10 0000 0000 I 512 x FS - | IOS | 1024 CURRENT-SOURCE ARRAY DAC RFSADJ 00 0000 0001* IFS - | IOS | 1024 00 0000 0000 0 GND Figure 1. Reference Architecture and Output Current Adjustment *Negative output current values = 0 _______________________________________________________________________________________ 9 MAX5550 I2C Compatibility (SPI/I2C = GND) MAX5550 Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC S Sr P tRDA SDA tFDA tHD:DAT tSU:STA tSU:STO tHD:STA tSU:DAT SCL tFCL tRCL tFCL tHIGH tLOW tHIGH tLOW tRCL Figure 2. I2C Serial-Interface Timing Diagram Early STOP Conditions The MAX5550 recognizes a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition (Figure 4). This condition is not allowed in the I2C format. Repeated START Conditions A repeated START (Sr) condition is used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX5550's serial interface supports continuous write operations with an Sr condition separating them. Acknowledge Bit (ACK) Successful data transfers are acknowledged with an acknowledge bit (ACK). Both the master and the MAX5550 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledgerelated clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 5). Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the master should reattempt communication at a later time. S Sr SDA SCL Figure 3. START and STOP Conditions SCL SDA STOP START LEGAL STOP CONDITION SCL SDA START ILLEGAL STOP ILLEGAL EARLY STOP CONDITION Figure 4. Early STOP Conditions 10 ______________________________________________________________________________________ P Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC MAX5550 S SDA ACKNOWLEDGE 1 SCL 2 8 9 Figure 5. Acknowledge Condition Table 3. Write Operation S T A R T Master SDA S ADDRESS BYTE COMMAND/DATA BYTE DATA BYTE S T O P D7 D6 D5 D4 D3 D2 D1 D0 P R/ W* 0 1 1 0 0 A1 A0 0 C5 C4 C3 A C K Slave SDA C2 C1 C0 D9 D8 A C K A C K *Read operation not supported. Slave Address A master initiates communication with a slave device by issuing a START condition followed by a slave address (see Table 3). The slave address consists of 7 address bits and a read/write bit (R/W). When idle, the device continuously waits for a START condition followed by its slave address. When the device recognizes its slave address, it acquires the data and executes the command. The first 5 bits (MSBs) of the slave address have been factory programmed and are always 01100. Connect A1 and A0 to VDD or GND to program the remaining 2 bits of the slave address. Set the least significant bit (LSB) of the address byte (R/W) to zero to write to the MAX5550. After receiving the address, the MAX5550 (slave) issues an acknowledge by pulling SDA low for one clock cycle. I2C read commands (R/W = 1) are not acknowledged by the MAX5550. pulse. Prematurely aborting the write cycle does not update the DAC. See Table 4 for a command summary. Write Cycle The write command requires 27 clock cycles. In write mode (R/W = 0), the command/data byte that follows the address byte controls the MAX5550 (Table 3). The registers update on the rising edge of the 26th SCL The MAX5550 has a software shutdown mode that reduces the supply current to less than 1A. Shutdown mode disables the DAC outputs. The serial interface remains active in shutdown. This provides the flexibilty to update the registers while in shut down. Recycling the power supply resets the device to the default settings. SPI Compatibility (SPI/I2C = VDD) The MAX5550 is compatible with the 3-wire SPI serial interface (Figure 6). This interface mode requires three inputs: chip-select (CS), data clock (SCLK), and data in (DIN). Drive CS low to enable the serial interface and clock data synchronously into the shift register on each SCLK rising edge. The MAX5550 requires 16 clock cycles to clock in 6 command bits (C5-C0) and 10 data bits (D9-D0) (Figure 7). After loading data into the shift register, drive CS high to latch the data into the appropriate DAC register and disable the serial interface. Keep CS low during the entire serial data stream to avoid corruption of the data. See Table 4 for a command summary. Shutdown Mode ______________________________________________________________________________________ 11 MAX5550 Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC tCSW CS tCSO tCSS tCP tCS1 tCSH SCLK tCH tDS tCL tDH LSB MSB DIN tCSE tDO1 DOUT tCSD MSB Figure 6. SPI-Interface Timing Diagram CS SCLK 1 DIN 2 C5 3 C4 4 C3 5 C2 C1 6 C0 7 8 9 10 11 12 13 14 15 16 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 7. SPI-Interface Format Applications Information Daisy Chaining (SPI/I2C = VDD) In standard SPI-/QSPITM-/MICROWIRETM-compatible systems, a microcontroller (C) communicates with its slave devices through a 3- or 4-wire serial interface. The typical interface includes a chip-select signal (CS), a serial clock (SCLK), a data input signal (DIN), and sometimes a data signal output (DOUT). In this system, the C allots an independent slave-select signal (SS_) to each slave device so that they can be addressed individually. Only the slaves with their CS inputs asserted low acknowledge and respond to the activity on the serial clock and data lines. This is simple to implement when there are very few slave devices in the system. An alternative method is daisy chaining. Daisy chaining, in serial-interface applications, is the method of propagating commands through devices connected in series (see Figure 8). Daisy chain devices by connecting the DOUT of one device to the DIN of the next. Connect the SCLK of all devices to a common clock and connect the CS of all devices to a common slave-select line. Data shifts out of DOUT 16.5 clock cycles after it is shifted into DIN on the falling edge of SCLK. In this configuration, the C only needs three signals (SS, SCK, and MOSI) to control all of the slaves in the network. The SPI-/QSPI-/MICROWIREcompatible serial interface normally works at up to 10MHz, but must be slowed to 5MHz if daisy chaining. DOUT is high impedance when CS is high. QSPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. 12 ______________________________________________________________________________________ Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC SERIAL DATA INPUT FUNCTIONS C5 C4 C3 C2 C1 C0 D9-D0 0 0 0 0 0 0 XXXXXXXXXX 0 0 0 0 0 1 10-bit DAC data Load DAC data to both DAC registers and both input registers from the shift register. 0 0 0 0 1 0 10-bit DAC data Load DAC register A and input register A from the shift register. 0 0 0 0 1 1 10-bit DAC data Load DAC register B and input register B from the shift register. 0 0 0 1 0 0 10-bit DAC data Load both channel input registers from the shift register, both DAC registers are unchanged. 0 0 0 1 0 1 10-bit DAC data Load input register A from the shift register; DAC register A is unchanged. 0 0 0 1 1 0 10-bit DAC data Load input register B from the shift register; DAC register B is unchanged. 0 0 0 1 1 1 XXXXXXXXXX Update both DAC registers from their corresponding input registers. 0 0 1 0 0 1 XXXXXXXXXX Update DAC register A from input register A. 0 0 1 0 1 0 XXXXXXXXXX Update DAC register B from input register B. 0 0 1 0 1 1 XXXXXXXXXX Internal reference mode. 0 0 1 1 0 0 XXXXXXXXXX External reference mode (default mode at power-up). 0 0 1 1 0 1 XXXXXXXXXX Shut down both DACs. 0 0 1 1 1 0 XXXXXXXXXX Shut down DACA. 0 0 1 1 1 1 XXXXXXXXXX Shut down DACB. 0 1 0 0 0 0 XXXXXXXXXX DACA 1mA-2mA full-scale current range mode (default mode at power-up) 0 1 0 0 0 1 XXXXXXXXXX DACA 1.5mA-3mA full-scale current range mode. 0 1 0 0 1 0 XXXXXXXXXX DACA 2.5mA-5mA full-scale current range mode. 0 1 0 0 1 1 XXXXXXXXXX DACA 4.5mA-9mA full-scale current range mode. 0 1 0 1 0 0 XXXXXXXXXX DACA 8mA-16mA full-scale current range mode. 0 1 0 1 0 1 XXXXXXXXXX DACA 15mA-30mA full-scale current range mode. 1 0 1 1 0 1 XXXXXXXXXX Power up both DACs. 1 0 1 1 1 0 XXXXXXXXXX Power up DACA. 1 0 1 1 1 1 XXXXXXXXXX Power up DACB. No operation. 1 1 0 0 0 0 XXXXXXXXXX DACB 1mA-2mA full-scale current range mode (default mode at power-up) 1 1 0 0 0 1 XXXXXXXXXX DACB 1.5mA-3mA full-scale current range mode. 1 1 0 0 1 0 XXXXXXXXXX DACB 2.5mA-5mA full-scale current range mode. 1 1 0 0 1 1 XXXXXXXXXX DACB 4.5mA-9mA full-scale current range mode. 1 1 0 1 0 0 XXXXXXXXXX DACB 8mA-16mA full-scale current range mode. 1 1 0 1 0 1 XXXXXXXXXX DACB 15mA-30mA full-scale current range mode. ______________________________________________________________________________________ 13 MAX5550 Table 4. Command Summary MAX5550 Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC MAX5550 DIN(1) SCLK DOUT(1) CS FSADJB OUTB TOP VIEW FSADJA CONTROLLER DEVICE MAX5550 DIN(0) SCLK DOUT(0) CS OUTA Pin Configuration 12 11 10 9 N.C. 13 8 GND VDD 14 7 REFIN 6 N.C. 5 DOUT/A1 MAX5550 N.C. 15 3 4 SPI/I2C 2 CS/AO 1 DIN/SDA MAX5550 DIN(2) SCLK DOUT(2) CS SCLK/SCL GND 16 THIN QFN (3mm x 3mm) Figure 8. Daisy-Chain Configuration Chip Information Power Sequencing Ensure that the voltage applied to REFIN does not exceed VDD at any time. If proper power sequencing is not possible, connect an external Schottky diode between REFIN and VDD to ensure compliance with the absolute maximum ratings. PROCESS: BiCMOS Power-Supply Bypassing and Ground Management Digital or AC transient signals on GND create noise at the analog output. Return GND to the highest quality ground plane available. For extremely noisy environments, bypass REFIN and VDD to GND with 1F and 0.1F capacitors with the 0.1F capacitor as close to the device as possible. Careful PC board ground layout minimizes crosstalk between the DAC outputs and digital inputs. 14 ______________________________________________________________________________________ Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC 12x16L QFN THIN.EPS (NE - 1) X e E MARKING E/2 D2/2 (ND - 1) X e AAAA D/2 e CL D D2 k CL b 0.10 M C A B E2/2 L E2 0.10 C C L 0.08 C C L A A2 A1 L L e e PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm 21-0136 PKG 8L 3x3 12L 3x3 16L 3x3 REF. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 b 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 D 2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10 E 2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10 e L 0.65 BSC. 0.35 0.55 0.50 BSC. 0.75 0.45 0.30 0.40 N 8 12 16 ND 2 3 4 2 NE 0 A1 A2 k 0.02 3 0.05 0 0.20 REF 0.25 - 0.05 0 0.20 REF - 0.25 - 0.50 0.02 0.05 0.20 REF - 0.25 - PKG. CODES TQ833-1 D2 2 E2 PIN ID MIN. NOM. MAX. MIN. NOM. MAX. 0.25 0.70 1.25 0.25 0.70 1.25 0.35 x 45 0.35 x 45 JEDEC WEEC T1233-1 0.95 1.10 1.25 0.95 1.10 1.25 T1233-3 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45 WEED-1 T1233-4 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45 WEED-1 T1633-2 4 0.02 1 EXPOSED PAD VARIATIONS 0.50 BSC. 0.65 0.55 I 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45 WEED-1 WEED-2 T1633F-3 0.65 0.80 0.95 0.65 0.80 0.95 0.225 x 45 WEED-2 T1633FH-3 0.65 0.80 0.95 0.65 0.80 0.95 0.225 x 45 WEED-2 T1633-4 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45 WEED-2 T1633-5 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45 WEED-2 - NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. N IS THE TOTAL NUMBER OF TERMINALS. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS . DRAWING CONFORMS TO JEDEC MO220 REVISION C. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. WARPAGE NOT TO EXCEED 0.10mm. PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm 21-0136 I 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 1 (c) 2006 Maxim Integrated Products Freed 7/13/05 Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX5550 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)