The MPC7455 and MPC7445 are imple m ent at ion s of t he Power PC™ mic ropr oc ess or f amil y
of reduced instruction set computer (RISC) microprocessors. This document is primarily
concerned with the MPC7455; however, unless otherwise noted, all information here also
applies to the MPC7445. This document describes pertinent electrical and physical
characteristics of the MPC7455. For functional characteristics of the processor, refer to the
MPC7450 RISC Microprocessor Family User’s Manual.
This document contains the following topics:
Topic Page
Section 1.1, “Overview” 1
Section 1.2, “Features” 2
Section 1.3, “Comparison with the MPC7400, MPC7410, MPC7450,
MPC7451, and MPC7441” 7
Section 1.4, “General Parameters” 10
Section 1.5, “Electrical and Thermal Characteristics” 10
Section 1.6, “Pin Assignments” 33
Section 1.7, “Pinout Listings” 35
Section 1.8, “Package Description” 41
Section 1.9, “System Design Information” 47
Section 1.10, “Document Revision History” 60
Section 1.11, “Ordering Information” 62
To loc ate any publi shed up dates for this document, refer to the website at
http://www.motorola.com/semiconductors.
1.1 Overview
The MPC7455 i s the third implementat ion of the fou rth generation (G4) micr oprocessors from
Motorola. The MPC7455 implements the full PowerPC 32-bit architecture and is targeted at
networki ng and computing sy ste m s appl ic at ion s. The MPC7455 consists of a pr oces sor core,
a 256-Kbyte L2, and an internal L3 tag and controller which support a glueless backside L3
cache through a dedicated high-bandwidth interface. The MPC7445 is identical to the
MPC7455 except it does not support the L3 cache interface.
Advance Information
MPC7455EC
Rev. 4, 9/2003
MPC7455
RISC Microprocessor
Hardware Specifications
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2MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Features
Figure 1 shows a block diagram of the MPC7455. The core is a high-performance superscalar design
supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage
subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to main memory and other
system resources. The L3 interface supports 1 or 2 Mbytes of external SRAM for L3 cache data.
Note that the MPC7455 is footprint-compatible with the MPC7450 and MPC7451, and the MPC7445 is
footprint-compatible with the MPC7441.
1.2 Features
This section summarizes features of the MPC7455 implementation of the PowerPC architecture.
Major features of the MPC7455 are as follows:
• High-performance, superscalar microprocessor
— As many as four instructions can be fetched from the instruction cache at a time
— As many as three instructions can be dispatched to the issue queues at a time
— As many as 12 instructions can be in the instruction queue (IQ)
— As many as 16 instructions can be at some stage of execution simultaneously
— Single-cycle execution for most instructions
— One instruction per clock cycle throughput for most instructions
— Seven-stage pipeline control
• Eleven independent execution units and three register files
— Branch processing unit (BPU) features static and dynamic branch prediction
– 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a
cache of branch instructions that have been encountered in branch/loop code sequences. If
a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner
than it can be made available from the instruction cache. Typically, a fetch that hits the
BTIC provides the first four instructions in the target stream.
– 2048-entry branch history table (BHT) with two bits per entry for four levels of
prediction—not-taken, strongly not-taken, taken, and strongly taken
– Up to three outstanding speculative branches
– Branch instructions that do not update the count register (CTR) or link register (LR) are
often removed from the instruction stream.
– Eight-entry link register stack to predict the target address of Branch Conditional to Link
Register ( bclr) i nstructions
— Four inte ger units (IU s) that share 32 GPR s for integer operands
– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except
multiply, divide, and move to/from special-purpose register instructions
– IU2 executes miscellaneous instructions including the CR logical operations, integer
multiplication and division instructions, and move to/from special-purpose register
instructions
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 3
Features
Figure 1. MPC7455 Block Diagram
+
Integer
Reservation
Station
Unit 2
+
Integer
Reservation
Station
Unit 2
Additional Feature s
• Time Base Counter/Decrem enter
• Clock Multiplier
• JTAG/COP Inter f a ce
• Thermal/Power Managem ent
• Performance Monitor
+
+
x ÷
FPSCR
FPSCR
PA
+x÷
Instruction Unit Instruction Que ue
(12-Word)
96-Bit (3 Instructions)
Reservation
Integer
128-Bit (4 Instr uct ions)
32-Bit
Floating-
Point Unit
64-Bit
Reservation
Load/Store Unit
(EA Calculation)
Finished
32-Bit
Completion Unit
Completion Queue
(16-Entry)
Tags 32-Kbyte
D Cache
L3 Cache C on trol ler
System Bus Interface
36-Bit Address Bus 64-Bit Data Bus
18-Bit 64-Bit Data
Integer
Stations (2)
Reservation
Station
Reservation
Stations (2) FPR File
16 Rename
Buffers
Stations (2-Entry)
GPR File
16 Rename
Buffers
Reservation
Station VR File
16 Rename
Buffers
64-Bit
128-Bit128-Bit
Completes up to three instructions per clock
Completed
Instruction MMU
SRs
(Shadow) 128-Entry
IBAT Array
ITLB Tags 32-Kbyte
I Cache
Stores
Stores
Load Miss
Vector
Touch
Queue
(3)
VR Issue FPR Issue
Branch Processing Unit
CTR
LR
BTIC (128-Entry)
BHT (2048-Entry)
Fetcher
GPR Issue
(6-Entry/3-Issue) (4-Entry/2-Issue) (2-Entry/1-Issue)
Dispatch
Unit
256-Kbyte Unified L2 Cache/Cache Controller
Data MMU
SRs
(Original) 128-Entry
DBAT Array
DTLB
Vector Touch E ngine
32-Bit
EA
L1 Castout
Status
L2 Store Queue (L2SQ)
External SRAM
L3CR
(8-Bit Parity)
Address
Vector
FPU
Reservation
Station
Reservation
Station
Reservation
Station
Vector
Integer
Unit 1
Vector
Integer
Unit 2
Vector
Permute
Unit
Line
StatusTags
Bus Accumulator
Tags Block 0 (32-Byte) Status
Block 1 (32-Byte)
Block 0/1 Line
Memory Subsystem
L1 Load Queue (LLQ)
L1 Lo ad Miss (5)
Cacheable Store
Instruction Fetch (2)
Request (1)
L1 Service Queues
Snoop Push/
Interventions
L1 Store Queue
L1 Castouts
Push
Castout
Queue
Bus Store Queue
L2 Prefetch (3)
Bus Accumulator
(1 or 2 Mbytes)
(LSQ)
L1 Push
(4)
(9)
Unit 2 Unit 1
Not in
MPC7445
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4MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Features
— Five-stage FPU and a 32-entry FPR file
– Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations
– Supports non-IEEE mode for time-critical operations
– Hardware support for denormalized numbers
– Thirty-two 64-bit FPRs for single- or double-precision operands
— Four vector units and 32-entry vector register file (VRs)
– Vector permute unit (VPU)
– Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as
vector add instructions (vaddsbs, vaddshs, and vaddsws, for example )
– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as
vector multiply add instructions (vmhaddshs, vmhraddshs, and vmladduhm, for
example)
– Vector floating-point unit (VFPU)
— Three-stage load/store unit (LSU)
– Supports integer, floating-point, and vector instruction load/store traffic
– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream
operations
– Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-cycle
throughput
– Four-cycle FPR load latency (single, double) with one-cycle throughput
– No additional delay for misaligned access within double-word boundary
– Dedicated adder calculates effective addresses (EAs)
– Supports store gathering
– Performs alignment, normalization, and precision conversion for floating-point data
– Executes cache control and TLB instructions
– Performs alignment, zero padding, and sign extension for integer data
– Supports hits under misses (multiple outstanding misses)
– Supports both big- and little-endian modes, including misaligned little-endian accesses
• Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions,
respectively, in a cycle. Ins truction dispatch r equires the follow ing:
— Instructions can be dispatched only from the three lowest IQ entries—IQ0, IQ1, and IQ2
— A maximum of three instructions can be dispatched to the issue queues per clock cycle
— Space must be avail able i n the CQ for a n in stru ction to dis patch (t his i nclude s inst ruct ions t hat
are assigned a space in the CQ but not in an issue queue)
• Rename buffers
— 16 GPR rename buffers
— 16 FPR rename buffers
— 16 VR rename buffers
• Dispatch unit
— Decode/dispatch stage fully decodes each instruction
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 5
Features
• Completion unit
— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all
instructions ahead of it have been completed, the instruction has finished execution, and no
exceptions are pending.
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
— Tracks unresolved branches and flushes instructions after a mispredicted branch
— Retires as many as three instructions per clock cycle
• Separate on-chip L1 instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set-associative instruction and data caches
— Pseudo least-recently-used (PLRU) replacement algorithm
— 32-byte (eight-word) L1 cache block
— Physically indexed/physical tags
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Instruction cache can provide four instructions per clock cycle; data cache can provide four
words per clock cycl e
— Caches can be disabled in software
— Caches can be locked in software
— ME SI data cache coherency maintained in hardware
— Separate copy of data cache tags for efficient snooping
— Parity support on cache and tags
— No snooping of instruction cache except for icbi instruction
— Data cache supports AltiVec LRU and transient instructions
— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word
forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical
double-word forwarding.
• Level 2 (L2) cache interface
— On-chip, 256-Kbyte, eight-way set-associative unified instruction and data cache
— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
— A total n ine-cycle load latency for an L1 data ca che miss that hits in L2
— PLRU replacement algorithm
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte, two-sectored line size
— Parity supp ort on cache
• Level 3 (L3) cache interface (not implemented on MPC7445)
— Provides critical double-word forwarding to the requesting unit
— Internal L3 cache controller and tags
— External data SRAMs
— Support for 1- and 2-Mbyte L3 caches
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6MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Features
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte (1M) or 128-byte (2M) sectored line size
— Private memory capability for half (1-Mbyte minimum) or all of the L3 SRAM space
— Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2 pipelined
synchronous Burst SRAMs, and pipelined (register-register) late write synchronous Burst
SRAMs
— Supports parity on cache and tags
— Configurable core-to-L3 frequency divisors
— 64-bit external L3 data bus sustains 64 bits per L3 clock cycle
• Separate memory management units (MMUs) for instructions and data
— 52-bit virtual address; 32- or 36-bit physical address
— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments
— Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and
memory coherency enforced/memory coherency not enforced on a page or block basis
— Separate IBATs and DBATs (eight each) also defined as SPRs
— Separate instructio n and data translat ion lookaside buffers (TLBs )
– Both TLBs are 128-entry, two-way set-associative, and use LRU replacement algorithm
– TLBs are hardware- or software-reloadable (that is, on a TLB miss a page table search is
performed in hardware or by system software)
• Efficient data flow
— Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows up to 256 bits
— The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs
— L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache
— As many as eight outstanding, out-of-order, cache misses are allowed between the L1 data
cache and L2/L3 bus
— As many as 16 out-of-order transactions can be present on the MPX bus
— Store merging for multiple store misses to the same line. Only coherency action taken
(address-only) for store misses merged to all 32 bytes of a cache block (no data tenure
needed).
— Three-entry finished store queue and five-entry completed store queue between the LSU and
the L1 data cache
— Separ ate addi tiona l queues for ef fic ient buffering of outboun d data (suc h as casto uts and write
through stores) from the L1 data cache and L2 cache
• Multiprocessing support features include the following:
— Hardware-enforced, MESI cache coherency protocols for data cache
— Load/store with reservation instruction pair for atomic memory references, semaphores, and
other multiprocessor operations
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 7
Comparison with the MPC7400, MPC7410, MPC7450, MPC7451, and MPC7441
• Power and thermal management
— 1.3-V processor core
— The following three power-saving modes are available to the system:
– Nap—Instruction fetching is halted. Only those clocks for the time base, decrementer, and
JTAG logic remain running. The part goes into the doze state to snoop memory operations
on the bus and then back to nap using a QREQ/QACK processor-syst em handsha ke
protocol.
– Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the
PLL in a locked and running state. All internal functional units are disabled.
– Deep sleep—When the part is in the sleep state, the system can disable the PLL. The
system can then disable the SYSCLK source for greater system power savings. Power-on
reset procedures for restarting and relo cki ng t he PLL must be f oll owed on exit in g th e deep
sleep state.
— Thermal management facility provides software-controllable thermal management. Thermal
management is performed through the use of three supervisor-level registers and an
MPC7455-specific thermal management exception.
— Instruction cache throttling provides control of instruction fetching to limit power
consumption
• Performance monitor can be used to help debug system designs and improve software efficiency
• In-system testability and debugging features through JTAG boundary-scan capability
• Testability
— LSSD scan design
— IEEE 1149.1 JTAG interface
— Array built-in self test (ABIST)—factory test only
• Re liability and service ability
— Parity checking on system bus and L3 cache bus
— Parity checking on the L2 and L3 cache tag arrays
1.3 Comparison with the MPC7400, MPC7410,
MPC7450, MPC7451, and MPC74 41
Table 1 compares the key features of the MPC7455 with the key features of the earlier MPC7400,
MPC7410, MPC7450, MPC74 51, and MPC7441. To achieve a higher f requency, the number of logic levels
per cycle is reduced. Also, to achieve this higher frequency, the pipeline of the MPC7455 is extended
(compare d to the MPC7400 ), wh il e mai nt aining th e sa me l eve l of performance as measu re d by t he number
of instructions executed per cycle (IPC).
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8MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Comparison with the MPC7400, MPC7410, MPC7450, MPC7451, and MPC7441
Table 1. Microarchitecture Comparison
Microarchitectural Specs MPC7455/MPC7445 MPC7450/MPC7451/
MPC7441 MPC7400/MPC7410
Basic Pipeline Functions
Logic inver sions per cycle 18 18 28
Pipeline stages up to execute 5 5 3
Total pipeline stages (minimum) 7 7 4
Pipeline maximum instruction
throughput 3 + Branch 3 + Br anch 2 + Branch
Pipeline Resou r ces
Instruction buffer size 12 12 6
Completion buffer size 16 16 8
Renames (integer, float, vector) 16, 16, 16 16, 16, 16 6, 6, 6
Maximum Execution Throughput
SFX 332
Vector 2 (Any 2 of 4 Units) 2 (Any 2 of 4 Units) 2 (Permute/Fixed)
Scalar floating-point 1 1 1
Out-of-Order Window Size in Execution Queues
SFX integer units 1 Entry × 3 Queues 1 Entry × 3 Queues 1 Entry × 2 Queues
Vector units In Order, 4 Queues In Order, 4 Queues In Order, 2 Queues
Scalar floating-point unit In Order In Order In Order
Branch Processing Resources
Prediction structures BTIC, BHT, Link Stack BTIC, BHT, Link Stack BTIC, BHT
BTIC size, associativity 128-Entry, 4-Way 128-Entry, 4-Way 64-Entry, 4-Way
BHT size 2K-Entry 2K-Entry 512-Entry
Link stack depth 8 8 None
Unresolved branches supported 3 3 2
Branch taken penalty (BTIC hit) 1 1 0
Minimum misprediction penalty 6 6 4
Execution Unit Timings (Latency-Throughput)
Aligned load (integer, float, vector) 3-1, 4-1, 3-1 3-1, 4-1, 3-1 2-1, 2-1, 2-1
Misaligned load (integer, float, vector) 4-2, 5-2, 4-2 4-2, 5-2, 4-2 3-2, 3-2, 3-2
L1 miss, L2 hit latency 9 Data/13 Instruction 9 Data/13 Instruction 9 (11) 1
SFX (aDd Sub, Shift, Rot, Cm p, logicals ) 1-1 1-1 1-1
Integer m ultiply (32 × 8, 32 × 16 , 32 × 32) 3-1, 3-1, 4-2 3-1, 3-1, 4-2 2-1, 3-2, 5-4
Scalar float 5-1 5-1 3-1
VSFX (vector simple) 1-1 1-1 1-1
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 9
Comparison with the MPC7400, MPC7410, MPC7450, MPC7451, and MPC7441
VCFX (vector complex) 4-1 4-1 3-1
VFPU (vector float) 4-1 4-1 4-1
VPER (vector permute) 2-1 2-1 1-1
MMUs
TLBs (instruction and data) 128-Entry, 2-Way 128-Entry, 2-Way 128-Entry, 2-Way
Tablewalk mechanism Hardware + Software Hardware + Software Hardware
Instruction BATs/data BATs 8/8 4/4 4/4
L1 I Cache/D Cache Features
Size 32K/32K 32K/32K 32K/32K
Associativity 8-Way 8-Way 8-Way
Locking granularity Way Way Full Cache
Parity on I cache Word Word None
Parity on D cache Byte Byte None
Number of D cache misses (load/store) 5/1 5/1 8 (Any Com bination)
Data stream touch engines 4 Streams 4 Streams 4 Streams
On-Chip Cache Features
Cache level L2 L2 L2 tags and c ontroller
only (see off-chip cache
support below)
Size/associativity 256-Kbyte/8-Way 256-Kbyte/8-Way
Access width 256 Bits 256 Bits
Number of 32-byte sectors/line 2 2
Parity Byte Byte
Off-Chip Cache Support 2
Cache level L3L3L2
On-chip tag logical size 1MB, 2MB 1MB, 2MB 0.5MB, 1MB, 2MB
Associativity 8-Way 8-Way 2-Way
Number of 32-byte sectors/line 2, 4 2, 4 1, 2, 4
Off-chip data SRAM support MSUG2 DDR, LW, PB2 MSUG2 DDR, LW, PB2 LW, PB2, PB3
Data path width 64 64 64
Direct mapped SRAM sizes 1 Mbyte, 2 Mbytes 1 Mbyte, 2 Mbytes 0.5 Mbyte, 1 Mbyte,
2Mbytes
3
Parity Byte Byte Byte
Notes:
1. Numb ers in p are nth es es are for 2:1 SRAM.
2. Not implemented on MPC7445 or MPC7441.
3. Private memory feature not implemented on MPC7400.
Table 1. Microarchitecture Comparison (continued)
Microarchitectural Specs MPC7455/MPC7445 MPC7450/MPC7451/
MPC7441 MPC7400/MPC7410
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10 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
General Parameters
1.4 General Parameters
The following list provides a summary of the general parameters of the MPC7455:
Technology 0.18 µm CMOS, six-layer metal
Die size 8.69 mm × 12.17 mm (106 mm2)
Transistor count 33 million
Logic design Fully-static
Packages MPC7445: Surface mount 360 ceramic ball grid array (CBGA)
MPC7455: Surface mount 483 ceramic ball grid array (CBGA)
Core power supply 1.3 V ± 50 mV DC nominal
I/O power supply 1.8 V ± 5% DC, or
2.5 V ± 5% DC, or
1.5 V ± 5% DC (L3 interface only)
1.5 Electrical and Thermal Characteristics
This sect ion provides the AC and DC electrical spe cification s and thermal chara cteristics fo r the MPC7455.
1.5.1 DC Electrical Characteristics
The tabl es in t his se ction de scribe t he MPC7455 DC electri cal char acteri stics. Table 2 provides th e absol ute
maximum ratings.
Table 2. Absolute Maximum Ratings 1
Characteristic Sym bol Maximum Value Unit Not es
Core supply voltage VDD –0.3 to 1.95 V 4
PLL supply voltage AVDD –0.3 to 1.95 V 4
Processor bus supply voltage BVSEL = 0 OVDD –0.3 to 1.95 V 3, 6
BVSEL = HRESET or OVDD OVDD –0.3 to 2.7 V 3, 7
L3 bus supply voltage L3VSEL = ¬HRESET GVDD –0.3 to 1.65 V 3, 8
L3VSEL = 0 GVDD –0.3 to 1.95 V 3, 9
L3VSEL = HRESET or GVDD GVDD –0.3 to 2.7 V 3, 10
Input voltage Processor bus Vin –0 .3 to OVDD + 0.3 V 2, 5
L3 bus Vin –0.3 to GVDD + 0.3 V 2, 5
JTAG signals Vin –0.3 to OVDD + 0.3 V
Input voltage Processor bus Vin –0 .3 to OVDD + 0.3 V 2, 5
JTAG signals Vin –0.3 to OVDD + 0.3 V
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 11
Electrical and Thermal Characteristics
Figure 2 shows the undershoot and overshoot voltage on the MPC7455.
Figure 2. Overshoot/Undershoot Volt age
The MPC7455 provides several I/O voltages to support both compatibility with existing systems and
migration to future systems. The MPC7455 core voltage must always be provided at nominal 1.3 V (see
Table 4 for actual recommended core voltage). Voltage to the L3 I/Os and processor interface I/Os are
provided through separate sets of supply pins and may be provided at the voltages shown in Table 3. The
input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the
negatio n of the s ignal HRESET. The output voltage wil l swing f rom GND to the maximum volt age appl ied
to the OVDD or GVDD power pins.
Storage temperature range Tstg –55 to 150 °C
Notes:
1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings
only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect
device reliability or cause permanent damage to the device.
2. Caution: Vin must not exceed OVDD or GVDD by more than 0.3 V at any time including during power-on reset.
3. Caution: OVDD/GVDD must not exceed VDD/AVDD by more than 2.0 V during norm al op erat ion; this limit ma y be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
4. Caution: VDD/AVDD must no t exc eed OVDD/GVDD by more th an 1.0 V during norm al op erat ion ; this lim it ma y be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
5. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6. BVSEL must be set to 0, such that the bus is in 1.8 V mode.
7. BVSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode.
8. L3VSEL must be set to ¬HRESET (i nvers e of HRESET), such that the bus is in 1.5 V mode.
9. L3VSEL must be set to 0, such that the bus is in 1.8 V mode.
10. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode.
Table 2. Absolute Maximum Ratings 1 (continued)
Characteristic Sym bol Maximum Value Unit Not es
VIH
GND
GND – 0.3 V
GND – 0.7 V Not to Exceed 10%
OVDD/GVDD + 20%
VIL
OVDD/GVDD
OVDD/GVDD + 5%
of tSYSCLK
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12 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Charact eristics
Table 4 provides the recommended operating conditions for the MPC7455.
Table 3. Input Threshold Voltage Setting
BVSEL Signal Processor Bus Input
Threshold is Relative to: L3VSEL Signal 5 L3 Bus Input Threshold is
Relative to: Notes
0 1.8 V 0 1.8 V 1, 4
¬HRESET Not Available ¬HRESET 1.5 V 1, 3
HRESET 2.5 V HRESET 2.5 V 1, 2
1 2.5 V 1 2.5 V 1
Notes:
1. Caution: The input threshold selection must agree with the OVDD/GVDD voltages supplied. See notes in Table 2.
2. To select the 2.5-V threshold option for the processor bus, BVSEL should be tied to HRESET so that the two
signals change state together. Similarly, to select 2.5 V for the L3 bus, tie L3VSEL to HRESET. This is the
preferred method for selecting this mode of operation.
3. Applicable to L3 bus interface only. ¬HRESET is the inverse of HRESET.
4. If used, pulldown resistors should be less than 250 Ω.
5. Not implemented on MPC7445.
Table 4. Recommended Operating Conditions 1
Characteristic Symbol Recommended Value Unit Notes
Min Max
Core supply voltage VDD 1.3 V ± 50 mV V
PLL supply voltage AVDD 1.3 V ± 50 mV V 2
Processor bus supply voltage BVSEL = 0 OVDD 1.8 V ± 5% V
BVSEL = HRESET or OVDD OVDD 2.5 V ± 5% V
L3 bus supply voltage L3VSEL = 0 GVDD 1.8 V ± 5% V
L3VSEL = HRESET or GVDD GVDD 2.5 V ± 5% V
L3VSEL = ¬HRESET GVDD 1.5 V ± 5% V
Input voltage Processor bus Vin GND OVDD V
L3 bus Vin GND GVDD V
JTAG signals Vin GND OVDD V
Die-junction temperature Tj0 105 °C
Notes:
1. These are the recommend ed and tested ope rating condi tions. Proper dev ice operation ou tside of the se conditio ns
is not guaranteed.
2. This voltage is the input to the filter discussed in Section 1.9.2, “PLL Power Supply Filtering,” and not necessarily
the voltage at the AVDD pin which may be reduced from VDD by the filter.
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 13
Electrical and Thermal Characteristics
Table 5 provides the package thermal characteristics for the MPC7455.
Table 6 provides the DC electrical characteristics for the MPC7455.
Table 5. Package Thermal Characteristics 6
Characteristic Symbol Value Unit Notes
MPC7445 MPC7455
Junction-to-ambient thermal resistance, natural
convection RθJA 22 20 °C/W 1, 2
Junction-to-ambient thermal resistance, natural
convection, four-layer (2s2p) board RθJMA 14 14 °C/W 1, 3
Junction-to-ambient thermal resistance, 200 ft/min
airflow, single-layer (1s) board RθJMA 16 15 °C/W 1, 3
Junction-to-ambient thermal resistance, 200 ft/min
airflow, four-layer (2s2p) board RθJMA 11 11 °C/W 1, 3
Juncti on-t o-bo ard thermal resis t a nce RθJB 6 6 °C/W 4
Junction-to-case thermal resistance RθJC <0.1 <0.1 °C/W 5
Notes:
1. Juncti on tempera ture is a fu nction of on-c hip pow er dissip ation, p ackage thermal res istan ce, moun ting site (b oard)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board
thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizont al .
4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1) with the calculated case tem perature. The actual value of RθJC for the part is less
than 0.1°C/W.
6. Refer to Section 1.9.8, “Thermal Management Information,” for more details about thermal management.
Table 6. DC Electrical Specifications
At recommended operating conditions. See Table 4.
Characteristic Nominal
Bus
Voltage 1Symbol Min Max Unit Notes
Input high voltage
(all inputs except SYSCLK) 1.5 VIH GVDD × 0.65 GVDD + 0.3 V 6
1.8 VIH OVDD/GVDD × 0.65 OVDD/GVDD + 0. 3 V
2.5 VIH 1.7 OVDD/GVDD + 0.3 V
Input low voltage
(all inputs except SYSCLK) 1.5 VIL –0.3 GVDD × 0.35 V 6
1.8 VIL –0.3 OVDD/GVDD × 0.35 V
2.5 VIL –0.3 0.7 V
SYSCLK input high voltage — CVIH 1.4 OVDD + 0.3 V
SYSCLK input low voltage — CVIL –0.3 0.4 V
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14 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Charact eristics
Table 7 provides the power consumption for the MPC7455.
Input leakage current,
Vin = GVDD/OVDD + 0.3 V —I
in —30µA2, 3
High impedance (off-state) leakage
current, Vin = GVDD/OVDD + 0.3 V —I
TSI —30µA2, 3, 5
Output high voltage, IOH = –5 mA 1.5 VOH GVDD – 0.45 — V 6
1.8 VOH OVDD/GVDD – 0.45 — V
2.5 VOH 1.7 — V
Output low voltage, IOL = 5 mA 1.5 VOL —0.45V6
1.8 VOL —0.45V
2.5 VOL —0.7V
Capacitance,
Vin = 0 V,
f = 1 MHz
L3 interface — Cin —9.5pF4
All other inputs — 8.0 pF 4
Notes:
1. Nominal voltages; see Table 4 for recommended operating conditions.
2. For processor bus signals, the reference is OVDD while GVDD is the reference for the L3 bus signals.
3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals.
4. Capacitance is periodically sampled rather than 100% tested.
5. The leakage is measured for nominal OVDD/GVDD and VDD, or both OVDD/GVDD and VDD must vary in the same
directi on (for exa mple, both OVDD and VDD v ary by either +5% or –5%).
6. Applicable to L3 bus interface only.
Table 7. Power Consumption for MPC7455
Processor (CPU) Frequency Unit Notes
733 MHz 867 MHz 933 MHz 1 GHz
Full-Power Mode
Typical 11.5 12.9 13.6 15.0 W 1, 3
Maximum 17.0 19.0 20.0 22.0 W 1, 2
Doze Mode
Typical ————W4
Nap Mode
Typical 8.0 8.0 8.0 8.0 W 1, 3
Sleep Mode
Typical 7.6 7.6 7.6 7.6 W 1, 3
Table 6. DC Electrical Specifications (continued)
At recommended operating conditions. See Table 4.
Characteristic Nominal
Bus
Voltage 1Symbol Min Max Unit Notes
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 15
Electrical and Thermal Characteristics
1.5.2 AC Electrical Characteristics
This section provi des the AC e le ctr ic al cha racterist ics for the MPC7455. After fabricati on, f unct ional parts
are sorted by maximum processor core frequency as shown in Section 1.5.2.1, “Clock AC Specifications,”
and tested for conformance to the AC specifications for that frequency. The processor core frequency is
determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold
by maximum processor core frequency; see Section 1.11, “Ordering Information.”
1.5.2.1 Clock AC Specifications
Table 8 provides the clock AC timing specifications as defined in Figure 3.
Deep Sleep Mode (PLL Disabled)
Typical 7.3 7.3 7.3 7.3 W 1, 3
Notes:
1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power
(OVDD and GVDD) or PL L sup ply pow er (AVDD). OVDD a nd GV DD power i s syste m depe ndent, bu t is typic ally <5%
of VDD power. Worst case po wer co nsumption for AVDD < 3 mW.
2. Maximum p ower is me asured at nominal VDD (see Table 4) while running an entirely cache-resident, contrived
sequence of instructions which keep the execution units, with or without AltiVec, maximally busy.
3. Typical power is an average value measured at the nominal recommended VDD (see Table 4) and 65°C in a
system while running a typical code sequence.
4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep
mode. As a result, power consumption for this mode is not tested.
Table 8. Clock AC Timing Speci fications
At recommended operating conditions. See Table 4.
Characteristic Symbol
Maximum Processor Core Frequency
Unit Notes733 MHz 867 MHz 933 MHz 1 GHz
Min Max Min Max Min Max Min Max
Processor frequency fcore 500 733 500 867 500 933 500 1000 MHz 1
VCO frequency fVCO 1000 1466 1000 1734 1000 1866 1000 2000 MHz 1
SYSCLK frequency fSYSCLK 33133331333313333133MHz 1
SYSCLK cycle time tSYSCLK 7.5307.5307.5307.530 ns
SYSCLK rise a nd fall time tKR, tKF —1.0—1.0—1.0—1.0 ns 2
SYSCLK duty cycle
measured at OVDD/2 tKHKL/
tSYSCLK
40 60 40 60 40 60 40 60 % 3
SYSCLK jitter — ± 150 — ± 150 — ± 150 — ± 150 ps 4, 6
Table 7. Power Consumption for MPC7455 (continued)
Processor (CPU) Frequency Unit Notes
733 MHz 867 MHz 933 MHz 1 GHz
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16 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Charact eristics
Figure 3 provides the SYSCLK input timing diagram.
Figure 3. SYSCLK Input Timing Diagram
1.5.2.2 Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7455 as defined in Figure 4 and
Figure 5. Timing specifications for the L3 bus are provided in Section 1.5.2.3, “L3 Clock AC
Specifications.”
Internal PLL relock time —100—100—100—100 µs5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK
(bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.9.1, “PLL
Configuration,” for valid PLL_CFG[0:4] settings.
2. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V.
3. Timing is guaranteed by design and characterization.
4. This represents total input jitter—short term and long term combined—and is guaranteed by design.
5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time
required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This
speci fic ati on a ls o ap plies when the PLL h as bee n disable d a nd s ub seq ue ntly re-e na ble d during sl eep mo de . Als o
note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the
power-on reset sequence.
6. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low
to allow cascade connected PLL-based devices to track SYSCLK drivers with the specified jitter.
Table 8. Clock AC Timing Specifications (continued)
At recommended operating conditions. See Table 4.
Characteristic Symbol
Maximum Processor Core Frequency
Unit Notes733 MHz 867 MHz 933 MHz 1 GHz
Min Max Min Max Min Max Min Max
SYSCLK VMVMVM CVIH
CVIL
VM = Midpoint Voltage (OVDD/2)
tSYSCLK
tKR tKF
tKHKL
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 17
Electrical and Thermal Characteristics
Table 9. Processor Bus AC Timing Specifications 1
At recommended operating conditions. See Table 4.
Parameter Symbol 2All Speed Grades Unit Notes
Min Max
Input setup times:
A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], TT[0:3], D[0 :63],
DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], QACK,
TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN,
SHD[0:1]
BMODE[0:1], BVSEL, L3VSEL
tAVKH
tIVKH
tMVKH
2.0
2.0
2.0
—
—
—
ns
8
Input hold times:
A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], TT[0:3], D[0 :63],
DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], QACK,
TA, TBEN, TEA, TS,EXT_QUAL, PMON_IN,
SHD[0:1]
BMODE[0:1], BVSEL, L3VSEL
tAXKH
tIXKH
tMXKH
0
0
0
—
—
—
ns
8
Output val id times:
A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], TT[0:3], WT, CI
TS
D[0:63], DP[0:7]
ARTRY/SHD0/SHD1
BR, CKSTP_OUT, DRDY, HIT, PMON_OUT, QREQ]
tKHAV
tKHTSV
tKHDV
tKHARV
tKHOV
—
—
—
—
—
2.5
2.5
2.5
2.5
2.5
ns
Output hol d time s:
A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], TT[0:3], WT, CI
TS
D[0:63], DP[0:7]
ARTRY/SHD0/SHD1
BR, CKSTP_OUT, DRDY, HIT, PMON_OUT, QREQ
tKHAX
tKHTSX
tKHDX
tKHARX
tKHOX
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
ns
SYSCLK to output enable tKHOE 0.5 — ns
SYSCLK to output hi gh impedance (all ex cept TS, ARTR Y,
SHD0, SHD1)tKHOZ —3.5ns
SYSCLK to TS high impedance after precharge tKHTSPZ —1t
SYSCLK 3, 4, 5
Maximum delay to ARTRY/SHD0/SHD1 precha rge tKHARP —1t
SYSCLK 3, 5,
6, 7
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18 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Charact eristics
Figure 4 provides the AC test load for the MPC7455.
Figure 4. AC Test Load
SYSCLK to ARTRY/SHD0/SHD1 high impedance after
precharge tKHARPZ —2t
SYSCLK 3, 5,
6, 7
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge
of the i nput SYSCLK. Al l output specificati ons are mea sured from the midpo int of the rising e dge of SYSCLK to the
midpoi nt of the sig nal in questi on. All output timin gs assum e a purely resisti ve 50-Ω load (see Figure 4). Input and
output timi ngs are measu red at the pin; time-of -flight del ays must be add ed for trace lengths, via s, and connectors
in the system.
2. The sym bology us ed for timing spe cificati ons herein follows the p attern of t (signal)(state)(reference)(state) for inpu ts and
t(reference)(state)(signal)(state) for outputs. For example, tIVKH sym bolizes t he time in put signa ls (I) rea ch the val id sta te
(V) relati ve to th e SYSCLK refere nc e (K) g oin g to the high (H) sta te or input se tup time . And tKHOV symbolizes the
time fro m SYSCLK(K) going hi gh (H) until output s (O) are valid (V) or outp ut valid time. Inpu t hold time c an be rea d
as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of
the reference and its state for inputs) and output hold time can be read as the time from the rising edge (KH) until
the output went invalid (OX).
3. tsysclk is th e p eri od of the e xte rnal c lo ck (SYSCL K ) i n n s. Th e n umbers giv en in th e tab le must be m ult ipl ied b y the
period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then
precharg ed hi gh before return ing to hig h im ped anc e as sho wn in Fi gure 6. The nomin al pr ech arg e wi d th for TS is
0.5 × tSYSCLK, that is, less than the minimum tSYSCLK period, to ensure that another master asserting TS on the
following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal
asserted. Output valid time is tested for precharge. The high-impedance behavior is guaranteed by design.
5. Guaranteed by design and not tested.
6. Accordi ng to the bus p rotocol, AR TR Y can be dr iven by multi ple bus ma sters th rough the cl ock perio d immedia tely
following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any
master asserting it low in the first clock following AACK will then go to high impedance for one clock before
precharging it high during the second cycle after the assertion of AACK. The nom ina l precharge wid th for ARTR Y
is 1.0 tSYSCLK; that is, it should be high impedance as shown in Figure 6 before the first opportunity for another
master to assert AR TRY. Output va lid and o utput hold ti ming is test ed for the sig nal asser ted. The high -impedanc e
behavior is guaranteed by design.
7. Accordi ng to the MPX bus p rotocol, SHD 0 and SHD1 can be driven by mult iple bus ma sters begi nning th e cycle of
TS. Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for
up to an enti re cycle (crossing a bus cycle boundary) before being three-st ated again. The nominal precharge wid th
for SHD0 and SHD1 is 1.0 tSYSCLK. The edges of the precha rge vary depe ndi ng on the prog ram me d ratio of
core-to-b us (PLL co nfig ura tion s).
8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These
paramenters represent the input setup and hold times for each sample. These values are guaranteed by design
and not tested. These inputs must remain stable after the second sample. See Figure 5 for sample timing.
Table 9. Processor Bus AC Timing Specifications 1 (continued)
At recommended operating conditions. See Table 4.
Parameter Symbol 2All Speed Grades Unit Notes
Min Max
Output Z0 = 50 ΩOVDD/
2
RL = 50 Ω
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 19
Electrical and Thermal Characteristics
Figure 5 provides the mode select input timing diagram for the MPC7455.
Figure 5. Mode Input Timing Diagram
Figure 6 provides the input/output timing diagram for the MPC7455.
Figure 6. Input/Output Timing Diagram
HRESET
M
ode Signals
VM = Midpoint Voltage (OVDD/2)
SYSCLK
Firs t Sample Second Sample
VM VM
SYSCLK
All Inputs
VM
VM = Midpoint Voltage (OVDD/2)
All Outputs tKHOX
VM
tKHDV
(Except TS,
ARTRY, SHD0, SHD 1)
All Outputs
TS
ARTRY,
(Except TS,
ARTRY, SHD0, SHD 1)
VM
t
KHOE
t
KHOZ
t
KHTSPZ
t
KHARPZ
t
KHARP
SHD1
SHD0,
tKHOV
tKHAV
tKHDX
tKHAX
tIXKH
tAXKH
tKHTSX
t
KHTSV
tKHTSV
t
KHARV
t
KHARX
tIVKH
tAVKH
tMVKH tMXKH
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20 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Charact eristics
1.5.2.3 L3 Clock AC Specifications
The L3_CLK frequency is programmed by the L3 configuration register (L3CR[6:8]) core-to-L3 divisor
ratio. See Table 18 for exampl e core a nd L3 freq uenc ies at variou s divis ors. Table 10 provides the pot entia l
range of L3_CLK output AC timing specifications as defined in Figure 7.
The maximum L3_CLK frequency is the core frequency divided by two. Given the high core frequencies
available in the MPC7455, however, most SRAM designs will be not be able to operate in this mode using
current technology and, as a result, will select a greater core-to-L3 divisor to provide a longer L3_CLK
period for read and write access to the L3 SRAMs. Therefore, the typical L3_CLK frequency shown in
Table 10 is consider ed to be the pract ical maximum in a typic al syst em. The maximum L3_CLK frequenc y
for any appl i cat ion of the MPC7455 wil l be a fun cti on of the AC timings of the MPC7455 , the AC timings
for the SRAM, bus loading, and pri nted-ci rcuit boar d trace length, and may be gr eater or le ss than the valu e
given in Table 10.
Motorola is similarly limited by system constraints and cannot perform tests of the L3 interface on a
sockete d part on a functional tester at the maximum frequencies of Table 10. Therefo re, functional operation
and AC timing information are tested at core-to-L3 divisors which result in L3 frequencies at 200 MHz or
less.
Table 10. L3_CLK Output AC Timing Specifications
At recommended operating conditions. See Table 4.
Parameter Symbol All Speed Grades Unit Notes
Min Typ Max
L3 clock frequency fL3_CLK 75 250 — MHz 1
L3 clock cycle time tL3_CLK — 4.0 13.3 ns
L3 clock duty cycle tCHCL/tL3_CLK 50 % 2
L3 clock ou tput-to- output s kew (L1_C LK0 to
L1_CLK1) tL3CSKW1 ——200ps3
L3 clock output-to-output skew (L1_CLK[0:1]
to L1_ECHO_CLK[2:3]) tL3CSKW2 ——100ps 4
L3 clock jitter — — ±50 ps 5
Notes:
1. The maximum L3 clock frequency will be system dependent. See Section 1.5.2.3, “L3 Clock AC Specifications,”
for an explanation that this maximum frequency is not functionally tested at speed by Motorola.
2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.
3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control
signals which are common to both SRAM chips in the L3.
4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3
for PB2 or late write SRAM. This parameter is critical to the write data signals which are separately latched onto
each SRAM p art by the se p ai rs of sig nal s.
5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3
address/data/control signals equally and, therefore, is already comprehended in the AC timing and does not
have to be c ons id ered in the L3 ti mi ng a nal ys is . The clo ck -to-c lo ck jitt er sh ow n h ere is un certainty in the interna l
clock period caused by supply voltage noise or thermal effects. This must be accounted for, along with clock
skew, in any L3 timing analysis.
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 21
Electrical and Thermal Characteristics
The L3_CLK timing diagram is shown in Figure 7.
Figure 7. L3_CLK_OUT Output Timing Diagram
1.5.2.4 L3 Bus AC Specifications
The MPC7455 L3 interface supports three different types of SRAM: source-synchronous, double data rate
(DDR) MSUG2 SRAM, late write SRAMs, and pipeline burst (PB2) SRAMs. Each requires a different
protocol on the L3 interface and a different routing of the L3 clock signals. The type of SRAM is
programmed in L3CR[22:23] and the MPC7455 then follows the appropriate protocol for that type. The
designer must connect and route the L3 signals appropriately for each type of SRAM. Following are some
observatio ns about the chip-to-SRAM interface.
• The routing for the point-to-point signals (L3_CLK[0:1], L3DATA[0:63], L3DP[0:7], and
L3_ECHO_CLK[0:3]) to a particular SRAM should be delay matched. If necessary, the length of
traces can be altered in order to intenti onally skew the ti ming a nd pr ovide additional setup or hold
time margin.
• For a 1-Mbyte L3, use address bits 16:0 (bit 0 is LSB).
• No pull-up resistors are req uired for the L3 interface.
• For high speed operations, L3 interface address and control signals should be a ‘T’ with minimal
stubs t o the t wo load s; dat a and clock si gnals shoul d be p oin t-to- point t o t heir singl e loa d. Figur e 8
shows the AC test load for the L3 interface.
Figure 8. AC Test Load for the L3 Interface
In general, if routing is short, delay-matched, and designed for incident wave reception and minimal
reflection, there is a high probability that the AC timing of the MPC7455 L3 interface will meet the
maximum frequency operation of appropriately chosen SRAMs. This is despite the pessimistic,
guard-ba nded AC spe cific ation s (see Table 12, Table 13, and Table 14), t he limi tations of func tiona l test ers
L3_CLK0 VM
t
L3CR
t
L3CF
VM
VMVM
L3_CLK1
VM
VM
tL3_CLK
tCHCL
VM
tL3CSKW1
L3_ECHO_CLK1
L3_ECHO_CLK3 VMVM VM VM
tL3CSKW2
VMVM VM VM
tL3CSKW2
For PB2 or Late Write:
Output Z0 = 50 ΩGVDD/
2
RL = 50 Ω
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22 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Charact eristics
descri bed in Section 1.5.2.3, “L3 Clock AC Specificat ions,” and the uncertainty of clocks and signals which
inevitably make worst-case critical path timi ng analysis p essimistic.
More specifically, certain signals within groups should be delay-matched with others in the same group
while intergroup routing is less critical. Only the address and control signals are common to both SRAMs
and additional timing margin is available for these signals. The double-clocked data signals are grouped
with individual clocks as shown in Figure 9 or Figure 11, depending on the type of SRAM. For example,
for the MSUG2 DDR SRAM (see Figure 9); L3DATA[0:31], L3DP[0:3], and L3_CLK[0] form a closely
coupled group of outputs from the MPC7455; while L3DATA[0:15], L3DP[0:1], and L3_ECHO_CLK[0]
form a closely coupled group of inputs.
The MPC7450 RISC Micr oprocessor Famil y User’s Manual refers to log ical set tings cal led ‘sampl e poin ts’
used in the synchronization of reads from the receive FIFO. The computation of the correct value for this
setti ng is sys tem-dependent and is descr ibed in the MPC7450 RISC Mic r opr oce ssor Family User’s Manual .
Three specifications are used in this calculation and are given in Table 11. It is essential that all three
specifications are included in the calculations to determine the sample points, as incorrect settings can result
in error s and unpred ictable behavior. For more information, see the MPC7450 RISC Micr opr ocessor Family
User ’s Manual.
1.5.2.4.1 L3 Bus AC Specifications for DDR MSUG2 SRAMs
When using DDR MSUG2 SRAMs at the L3 i nterface, t he parts should b e connected as sho wn in Figure 9.
Outputs from the MPC7455 are actually launched on the edges of an internal clock phase-aligned to
SYSCLK (adjusted for core and L3 frequency divisors). L3_CLK0 and L3_CLK1 are this internal clock
output with 90° phase delay, so outputs are shown synchronous to L3_CLK0 and L3_CLK1. Output valid
times are typically negative when referenced to L3_CLKn because the data is launched one-quarter period
before L3_CLKn to provide adequate setup time at the SRAM after the delay-matched address, control,
data, and L3_CLKn signals have propagated across the printed-wiring board.
Inputs t o the MPC7455 are source- synchronous wit h the CQ clock generat ed by the DDR MSUG2 SRAMs.
These CQ clocks are received on the L3_ECHO_CLKn inputs of the MPC7455. An internal circuit delays
the inc oming L3_ECHO_CLKn sign al such tha t it is positione d within t he valid da ta window at the inter nal
receiving latches. This delayed clock is used to capture the data into these latches which comprise the
Table 11. Sample Points Calculation Parameters
Parameter Symbol Max Unit Notes
Delay from processor clock to internal_L3_CLK tAC 3/4 tL3_CLK 1
Delay from internal_L3_CLK to L3_CLKn output pins tCO 3ns2
Delay from L3_ECHO_CLKn to receive latch tECI 3ns3
Notes:
1. This specification describes a logical offset between the internal clock edge used to launch the L3 address and
control signals (this clock edge is phase-aligned with the processor clock edge) and the internal clock edge used
to launch the L3_CLKn signa ls. With proper boa rd routing , this of fse t ensure s that the L 3_CL Kn edge w ill arrive at
the SRAM with in a valid addres s wind ow and prov ide adeq uate setup an d hol d tim e. Thi s offset is ref lec ted in the
L3 bus interface AC timing specifications, but must also be separately accounted for in the calculation of sample
points and, thus, is specified here.
2. This specification is the delay from a rising or falling edge on the internal_L3_CLK signal to the corresponding
rising or falling edge at the L3CLKn pins.
3. This specification is the delay from a rising or falling edge of L3_ECHO_CLKn to data valid and ready to be
sampled from the FIFO.
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 23
Electrical and Thermal Characteristics
receive FIFO. This clock is asynchronous to all other processor clocks. This latched data is subsequently read out of the FIFO synchronously to the
processor clock. The time between writing and reading the data is set by the using the sample point settings defined in the L3CR register.
Table 12 provide s the L3 bus int erface AC timing s pecifica tions for the config uration as shown in Figure 9, assumin g the timing r elation ships shown
in Figure 10 and the loading shown in Figure 8.
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2
At recommended operating conditions. See Table 4.
Parameter Symbol
All Speed Grades 8
Unit NotesL3OH0 = 0, L3OH1 = 0 L3OH0 = 0, L3OH1 =1 L3OH0 = 1, L3OH1 = 0 L3OH0 = 1, L3OH1 = 1
Min Max Min Max Min Max Min Max
L3_CLK rise and fall time tL3CR,
tL3CF
—1.0—1.0—1.0—1.0ns1
Setup times: Data and parity tL3DVEH,
tL3DVEL
– 0.1 — – 0.1 — – 0.1 — – 0.1 — ns 2, 3,
4
Input hold times: Data and
parity tL3DXEH,
tL3DXEL
tL3_CLK/4
+ 0.30 —t
L3_CLK/4
+ 0.30 —t
L3_CLK/4
+ 0.30 —t
L3_CLK/4
+ 0.30 —ns2, 4
Valid times: Data and parity tL3CHDV,
tL3CLDV
—(– t
L3_CLK/4)
+ 0.60 —(– t
L3_CLK/4)
+ 0.40 —(– t
L3_CLK/4)
+ 0.20 —(– t
L3_CLK/4)
+ 0.00 ns 5, 6,
7
Valid times: All other outputs tL3CHOV —t
L3_CLK/4
+ 0.80 —t
L3_CLK/4
+ 0.60 —t
L3_CLK/4
+ 0.40 —t
L3_CLK/4
+ 0.20 ns 5, 7
Output hold times: Data and
parity tL3CHDX,
tL3CLDX,
tL3_CLK/4
– 0.40 —t
L3_CLK/4
– 0.60 —t
L3_CLK/4
– 0.80 —t
L3_CLK/4
– 1.00 —ns5, 6,
7
Output hold times: All other
outputs tL3CHOX tL3_CLK/4
– 0.20 —t
L3_CLK/4
– 0.40 —t
L3_CLK/4
– 0.60 —t
L3_CLK/4
– 0.80 —ns5, 7
L3_CLK to high impedance:
Data and parity tL3CLDZ —t
L3_CLK/2 — tL3_CLK/2 — tL3_CLK/2 — tL3_CLK/2 ns
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24 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Electrical and Thermal Characteristics
L3_CLK to high impedance: All
other outputs tL3CHOZ —t
L3_CLK/4
+ 2.0 —t
L3_CLK/4
+ 2.0 tL3_CLK/4
+ 2.0 —t
L3_CLK/4
+ 2.0 —ns
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising or falling edge of the input
L3_ECHO_CLKn (see Figure 10). Input timings are measured at the pins.
3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10. For consistency with other input setup time specifications, this
will be treated as negative input setup time.
4. tL3_CLK/4 is on e-fo urth the period of L3_ CLK n. Thi s parame ter i ndi cates that th e M PC7455 can la tch an inp ut s ig nal tha t i s v al id f or o nly a s ho rt ti me be fore and
a short time after the midpoint between the rising and falling (or falling and rising) edges of L3_ECHO_CLKn at any frequency.
5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling) edge of L3_CLK to the midpoint of the
signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 8).
6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10. For consistency with other output valid time specifications, this will be
treated as negative output valid time.
7. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched by an internal clock delayed in
phase by 90°. Therefore, there is a frequency component to the output valid and output hold times such that the specified output signal will be valid for
approximately one L3_CLK period starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending on e-fo urth of a clock period
after the edge it will be sampled.
8. These configuration bits allow the AC timing of the L3 interface to be altered via software. L3OH0 = L2CR[12], L30H1 = L3CR[12]. Revisions of the MPC7455
not described by this document may implement these bits differently. See Section 1.11.1, “Part Numbers Fully Addressed by This Document,” and
Section 1.11.2, “Part Numbers Not Fully Addre ssed by This Docu ment,” for more information on which devices are addressed by this document.
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2 (continued)
At recommended operating conditions. See Table 4.
Parameter Symbol
All Speed Grades 8
Unit NotesL3OH0 = 0, L3OH1 = 0 L3OH0 = 0, L3OH1 =1 L3OH0 = 1, L3OH1 = 0 L3OH0 = 1, L3OH1 = 1
Min Max Min Max Min Max Min Max
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 25
Electrical and Thermal Characteristics
Figure 9 shows the typica l connectio n diagram fo r the MPC7455 inter faced to MSUG2 SRAMs such as the
Motorola MCM64E83 6.
Figure 9. Typical Source Synchronous 2-Mbyte L3 Cache DDR Interface
Denotes
Receive (SRAM
to MPC7455)
Aligned Signals
{L3DATA[0:15],
{L3DATA[16:31],
{L3_DATA[32:47],
L3ADDR[17:0]
L3_CNTL[0]
L3_CLK[0]
L3_CLK[1]
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3ECHO_CLK[2]
L3_ECHO_CLK[3]
{L3DATA[48:63],
L3DP[0:1]}
L3DP[2:3]}
L3DP[4:5]}
L3DP[6:7]}
CQ
SA[17:0]
CK
B1
B2
SRAM 0
SRAM 1
CQ
D[0:17]
D[18:35]
CQ
SA[17:0]
CK
B1
B2
CQ
D[0:17]
D[18:35]
L3_CNTL[1]
NC
NC
GND
GND
GND
NC
NC
GND
GND
GND
MPC7455
Denotes
Receive (SRAM
to MPC7455)
Aligned Signals
Denotes
Transmit
(MPC7455 to
SRAM)
Aligned Signals
GVDD/2
1
GVDD/2
1
CQ
CK
B3
G
CQ
LBO
CQ
CK
B3
G
CQ
LBO
Note:
1. Or as recommended by SRAM manufacturer for single-ended clocking.
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26 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Charact eristics
Figure 10 shows the L3 bus timing diagrams for the MPC7455 interfaced to MSUG2 SRAMs.
Figure 10. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs
1.5.2.4.2 L3 Bus AC Specifications for PB2 and Late Write SRAMs
When using PB2 or late write SRAMs at the L3 interface, the parts should be connected as shown in
Figure 11. These SRAMs are sy nchr onous to the MPC7455; one L3_CLKn signal is output to each SRAM
to latch address, control, and write data. Read data is launched by the SRAM synchronous to the delayed
L3_CLKn signa l i t r ece ive d. The MPC74 55 ne eds a copy of that delayed c loc k which launched the SRAM
read data to know when the returning data will be valid. Therefore, L3_ECHO_CLK1 and
L3_ECHO_CLK3 must be routed halfway to the SRAMs and then returned to the MPC7455 inputs
L3_ECHO_CLK0 and L3_ ECHO_CLK2, respectiv ely . Thus , L3_ECHO_CLK0 and L3_ ECHO_CLK2 ar e
phase-aligned with the input clock received at the SRAMs. The MPC7455 will latch the incoming data on
the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2.
Table 13 provides the L3 bus interface AC timing specifications for the configuration shown in Figure 11,
assuming the timing relationships of Figure 12 and the loading of Figure 8.
L3_ECHO_CLK[0,1,2,3]
L3 Data and Dat a
VM
VM = Midpoint Voltage (GVDD/2)
Parity Inputs
L3_CLK[0,1]
ADDR, L3CNTL
VM
tL3CHOV tL3CHOX
VM
L3DATA WRITE
tL3CHOZ
VM
VM VM VM
tL3CHDV
tL3CHDX
VM VMVM
Outputs
Inputs
tL3CLDV
tL3CLDX
tL3CLDZ
tL3DVEH
tL3DXEL
tL3DVEL
tL3DXEH
Note: tL3DVEH and tL3DVEL as drawn here will be negative numbers, that is, input setup time will be
time after the clock edge.
Note: tL3CHDV and tL3CLDV as drawn here will be negative numbers, that is, output valid time will be
time before t he clo ck edge.
VM = Midpoint Voltage (GVDD/2)
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 27
Electrical and Thermal Characteristics
Table 13. L3 Bus Interface AC Ti ming Specifications for PB2 and Late Write SRAMs
At recommended operating conditions. See Table 4.
Parameter Symbol
All Speed Grades 6
Unit NotesL3OH0 = 0, L3OH1 = 0 L3OH0 = 0, L3OH1 =1 L3OH0 = 1, L3OH1 = 0 L3OH0 = 1, L3OH1 = 1
Min Max Min Max Min Max Min Max
L3_CLK rise and fall time tL3CR,
tL3CF
—1.0 —1.0—1.0—1.0ns1, 5
Setup times: Data and parity tL3DVEH 1.5—1.5—1.5—1.5—ns2, 5
Input hold times: Data and parity tL3DXEH —0.5—0.5—0.5—0.5ns2, 5
Valid times: Data and parity tL3CHDV —t
L3_CLK/4
+ 1.00 —t
L3_CLK/4
+ 0.80 —t
L3_CLK/4
+ 0.60 —t
L3_CLK/4
+ 0.40 ns 3, 4, 5
Valid times: All other outputs tL3CHOV —t
L3_CLK/4
+ 1.00 —t
L3_CLK/4
+ 0.80 —t
L3_CLK/4
+ 0.60 —t
L3_CLK/4
+ 0.40 ns 4
Output hol d time s: Dat a and
parity tL3CHDX tL3_CLK/4
– 0.40 —t
L3_CLK/4
– 0.60 —t
L3_CLK/4
– 0.80 —t
L3_CLK/4
– 1.00 —ns3, 4, 5
Output hol d time s: All othe r
outputs tL3CHOX tL3_CLK/4
– 0.40 —t
L3_CLK/4
– 0.60 —t
L3_CLK/4
– 0.80 —t
L3_CLK/4
– 1.00 —ns4, 5
L3_CLK to high impedance: Data
and parity tL3CHDZ —2.0—2.0—2.0—2.0ns5
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28 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Electrical and Thermal Characteristics
L3_CLK to high impedance: All
other outputs tL3CHOZ —2.0—2.0—2.0—2.0ns5
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input L3_ECHO_CLKn (see
Figure 10). Input timings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoi nt of th e sig nal in que st ion . The ou tpu t timi ng s are
measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 10).
4. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched by an internal clock delayed in
phase by 90°. Therefore, there is a frequency component to the output valid and output hold times such that the specified output signal will be valid for
approximately one L3_CLK period starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period
after the edge it will be sampled.
5. Timing behavior and characterization are currently being evaluated.
6. These configuration bits allow the AC timing of the L3 interface to be altered via software. L3OH0 = L2CR[12], L30H1 = L3CR[12]. Revisions of the MPC7455
not described by this document may implement these bits differently. See Section 1.11.1, “Part Numbers Fully Addressed by This Document,” and
Section 1.11.2, “Part Numbers Not Fully Addressed by This Document,” for more information on which devices are addressed by this document.
Table 13. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs (continued)
At recommended operating conditions. See Table 4.
Parameter Symbol
All Speed Grades 6
Unit NotesL3OH0 = 0, L3OH1 = 0 L3OH0 = 0, L3OH1 =1 L3OH0 = 1, L3OH1 = 0 L3OH0 = 1, L3OH1 = 1
Min Max Min Max Min Max Min Max
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 29
Electrical and Thermal Characteristics
Figure 11 shows the typical connection diagram for the MPC7455 interfaced to PB2 SRAMs, such as the
Motorola MCM63R737, or late write SRAMs, such as the Motorola MCM63R836A.
Figure 11. Typical Synchronous 1-MByte L3 Cache Late Write or PB2 Interface
L3_ADDR[16:0]
L3_CNTL[0] SA[16:0]
K
K
SS
SW
ZZ
G
SRAM 0
DQ[0:17]
DQ[18:36]
L3_CNTL[1]
GVDD/2
1
GND
GND
SRAM 1
GVDD/2
1
GND
GND
{L3_DATA[0:15],
{L3_DATA[16:31],
{L3_DATA[32:47],
L3_CLK[0]
L3_CLK[1]
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3_ECHO_CLK[2]
{L3_DATA[48:63],
L3_DP[0:1]}
L3_DP[2:3]}
L3_DP[4:5]}
L3_DP[6:7]}
Denotes
Receive (SRAM
to MPC7455)
Aligned Signals
MPC7455
Denotes
Transmit
(M PC7455 to
SRAM)
Aligned Signals
L3_ECHO_CLK[3]
SA[16:0]
K
K
SS
SW
ZZ
G
DQ[0:17]
DQ[18:36]
Note:
1. Or as recommended by SRAM manufacturer for single-ended clocking.
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30 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Charact eristics
Figure 12 shows the L3 bus timing diagrams for the MPC7455 interfaced to PB2 or late write SRAMs.
Figure 12. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs
1.5.2.5 IEEE 1149.1 AC T iming Specifi cations
Table 14 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 14 through
Figure 17.
Table 14. JTAG AC Timing Specifications (Independent of SYSCLK) 1
At recommended operating conditions. See Table 4.
Parameter Symbol Min Max Unit Notes
TCK frequen cy of operation fTCLK 033.3MHz
TCK cycl e time t TCLK 30 — ns
TCK clock pulse width measured at 1.4 V tJHJL 15 — ns
TCK rise and fall times tJR and tJF 02ns
TRST assert time tTRST 25 — ns 2
Input setup times:
Boundary-scan data
TMS, TDI tDVJH
tIVJH
4
0—
—
ns 3
Input hold times:
Boundary-scan data
TMS, TDI tDXJH
tIXJH
20
25 —
—
ns 3
L3_ECHO_CLK[0,2]
L3 Data and Data
VM
VM = Midpoint Voltage (GVDD/2)
tL3DVEH
tL3DXEH
Parity Inputs
L3_CLK[0,1]
ADDR, L3_CNTL
VM
tL3CHOV tL3CHOX
VM
L3DATA WRITE
tL3CHDZ
Outputs
Inputs
L3_ECHO_CLK[1,3]
tL3CHDV tL3CHDX
tL3CHOZ
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 31
Electrical and Thermal Characteristics
Figure 13 provides the AC test load for TDO and the boundary-scan outputs of the MPC7455.
Figure 13. Alternate AC Test Load for the JTAG Interface
Figure 14 provides the JTAG clock input timing diagram.
Figure 14. JTAG Clock Input Timing Diagram
Figure 15 provides the TRST timing diagram.
Figure 15. TRST Timing Diagram
Valid times:
Boundary-scan data
TDO tJLDV
tJLOV
4
420
25
ns 4
Output hol d time s:
Boundary-scan data
TDO tJLDX
tJLOX
TBD
TBD TBD
TBD
ns 4
TCK to output high impedance:
Boundary-scan data
TDO tJLDZ
tJLOZ
3
319
9
ns 4, 5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω loa d
(see Figure 13). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Table 14. JTAG AC Timing Specifications (Independent of SYSCLK) 1 (continued)
At recommended operating conditions. See Table 4.
Parameter Symbol Min Max Unit Notes
Output Z0 = 50 ΩOVDD/
2
RL = 50 Ω
VMVMVM
VM = Midpoint Voltage (OVDD/2)
tTCLK
tJR tJF
tJHJL
TCLK
TRST tTRST
VM = Midpoint Voltage (OVDD/2)
VM VM
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32 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
El ectrical and Thermal Charact eristics
Figure 16 provides the boundary-scan timing diagram.
Figure 16. Boundary-Scan Timing Diagram
Figure 17 provides the test access port timing diagram.
Figure 17. Test Access Port Timing Diagram
VMTCK
Boundary
Boundary
Boundary
Data Outputs
Data Inputs
Data Outputs
VM = Midpoint Voltage (OVDD/2)
tDXJH
tDVJH
tJLDV
tJLDZ
Input
Data Valid
Output Data Valid
Output Data Valid
tJLDX
VM
VM
TCK
TDI, TMS
TDO O utput Data Valid
VM = Midpoint Voltage (OVDD/2)
tIXJH
tIVJH
tJLOV
tJLOZ
Input
Data Valid
TDO Output Data Valid
tJLOX
VM
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 33
Pin Assignments
1.6 Pin Assignments
Figure 18 (in Part A) shows the pinout of the MPC7445, 360 CBGA package as viewed from the top surface.
Part B shows the side profile of the CBGA package to indicate the direction of the top surface view.
Figure 18. Pinout of the MPC7445, 360 CBGA Package as Viewed from the Top Surface
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1234 5678 910111213141516
Not to Scale
17 18 19
U
V
W
Part A
View
Part B
Die
Substrate Assembly
Encapsulant
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34 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Pin Assignments
Figure 19 (in Part A) shows the pinout of the MPC7455, 483 CBGA package as viewed from the top surface.
Part B shows the side profile of the CBGA package to indicate the direction of the top surface view.
Figure 19. Pinout of the MPC7455, 483 CBGA Package as Viewed from the Top Surface
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1234 5678 910111213141516
Not to Sc ale
17 18 19
U
V
W
20 21 22
Y
AA
AB
Part A
View
Part B
Die
Substrat e Assembly
Encapsulant
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 35
Pinout Listings
1.7 Pin out Listin gs
Table 15 provides the pinout listing for the MPC7445, 360 CBGA package. Table 16 provides the pinout
listing for the MPC7455, 483 CBGA package.
NOTE
This pi nout i s not c ompat ib le with the MPC750, MPC7400 , or MPC74 10,
360 BGA package.
Table 15. Pinout Listing for the MPC7445, 360 CBGA Pa ckage
Signal Name Pin Number Active I/O I/F Select 1Notes
A[0:35] E1 1, H1, C11, G3, F10, L2, D1 1, D1, C10,
G2, D12, L3, G4, T2, F4, V1, J4, R2, K5,
W2, J2, K4, N4, J3, M5, P5, N3, T1, V2,
U1, N5, W1, B12, C4, G10, B11
High I/O BVSEL 11
AACK R1 Low Input BVSEL
AP[0:4] C1, E3, H6, F5, G7 H igh I/O BVSEL
ARTRY N2 Low I/O BVSEL 8
AVDD A8 — Input N/A
BG M1 Low Input BVSEL
BMODE0 G9 Low Input BVSEL 5
BMODE1 F8 Low Input BVSEL 6
BR D2 Low Output BVSEL
BVSEL B7 High Input BVSEL 1, 7
CI J1 Low Output BVSEL 8
CKSTP_IN A3 Low Input BVSEL
CKSTP_OUT B1 Low Output BVSEL
CLK_OUT H2 High Output BVSEL
D[0:63] R15, W15, T14, V16, W16, T15, U15,
P14, V13, W13, T13, P13, U14, W14,
R12, T12, W12, V12, N11, N10, R11, U1 1,
W11, T11, R10, N9, P10, U10, R9, W10,
U9, V9, W5, U6, T5, U5, W 7, R6 , P7, V6,
P17, R19, V18, R18, V19, T19, U19, W19,
U18, W17, W18, T16, T18, T17, W3, V17,
U4, U8, U7, R7, P6, R8, W8, T8
High I/O BVSEL
DBG M2 Low Input BVSEL
DP[0:7] T3, W4, T4, W9, M6, V3, N8, W6 High I/O BVSEL
DRDY R3 Low Output BVSEL 4
DTI[0:3] G1, K1, P1, N1 High Input BVSEL 13
EXT_QUAL A11 High Input BVSEL 9
GBL E2 Low I/O BVSEL
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36 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Pinout Listings
GND B5, C3, D6, D13, E17, F3, G17, H4, H7,
H9, H11, H13, J6, J8, J10, J12, K7, K3,
K9, K11, K13, L6, L8, L10, L12, M4, M7,
M9, M11, M13, N7, P3, P9, P12, R5, R14,
R17, T7, T1 0, U3, U13, U17, V5, V8, V1 1,
V15
—— N/A
HIT B2 Low Output BVSEL 4
HRESET D8 Low Input BVSEL
INT D4 Low Input BVSEL
L1_TSTCLK G8 High Input BVSEL 9
L2_TSTCLK B3 High Input BVSEL 12
No Connect A6, A13, A14, A15, A16, A17, A18, A19,
B13, B14, B15, B16, B17, B18, B19, C13,
C14, C15, C16, C17, C18, C19, D14, D15,
D16, D17, D18, D19, E12, E13, E14, E15,
E16, E19, F12, F13, F14, F15, F16, F17,
F18, F19, G11, G12, G13, G14, G15,
G16, G19, H14, H15, H16, H17, H18,
H19, J14, J15, J16, J17, J18, J19, K15,
K16, K17, K18, K19, L14, L15, L16, L17,
L18, L19, M14, M15, M16, M17, M18,
M19, N12, N13, N14, N15, N16, N17,
N18, N19, P15, P16, P18, P19
—— — 3
LSSD_MODE E8 Low Input BVSEL 2, 7
MCP C9 Low Input BVSEL
OVDD B4, C2, C12, D5, E18, F2, G18, H3, J5,
K2, L5, M3, N6, P2, P8, P11, R4, R13,
R16, T6, T9, U2, U12, U16, V4, V7, V10,
V14
—— N/A
PLL_CFG[0:4] B8, C8, C7, D7, A7 High Input BVSEL
PMON_IN D9 Low Input BVSEL 10
PMON_OUT A9 Low Output BVSEL
QACK G5 Low Input BVSEL
QREQ P4 Low Output BVSEL
SHD[0:1] E4, H5 Low I/O BVSEL 8
SMI F9 Low Input BVSEL
SRESET A2 Low Input BVSEL
SYSCLK A10 — Input BVSEL
TA K6 Low Input BVSEL
TBEN E1 High Input BVSEL
TBST F11 Low Output BVSEL
Table 15. Pinout Listing for the MPC7445, 360 CBGA Package (continued)
Signal Name Pin Number Active I/O I/F Select 1Notes
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 37
Pinout Listings
TCK C6 High Input BVSEL
TDI B9 High Input BVSEL 7
TDO A4 High Output BVSEL
TEA L1 Low Input BVSEL
TEST[0:3] A12, B6, B10, E10 — Input BVSEL 2
TEST[4] D10 — Input BVSEL 9
TMS F1 High Input BVSEL 7
TRST A5 Low Input BVSEL 7, 14
TS L4 Low I/O BVSEL 8
TSIZ[0:2] G6, F7, E7 High Output BVSEL
TT[0:4] E5, E6, F6, E9, C5 High I/O BVSEL
WT D3 Low Output BVSEL 8
VDD H8, H10, H12, J7, J9, J11, J13, K8, K10,
K12, K14, L7, L 9, L1 1, L13 , M8, M10, M12 —— N/A
Notes:
1. OVDD supplies power to the processor bus, JTAG, and all control signals; and VDD supplies power to the
processor core and the PLL (after filtering to become AVDD). To program the I/O voltage, connect BVSEL to
either GND (selects 1.8 V) or to HRESET (selects 2.5 V). If used, the pulldown resistor should be less than
250 Ω. For actual recommended value of Vin or supply voltages see Table 4.
2. These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.
3. These signals are for factory use only and must be left unconnected for normal machine operation.
4. Ignored in 60x bus mode.
5. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at
HRESET going high.
6. This sig nal must be negated du rin g rese t, by pull -up to OVDD or negation by ¬HRESET (inverse of HRESET), to
ensure proper operation.
7. Internal pull-up on die.
8. These pins require weak pull-up resistors (for example, 4.7 kΩ) to maintain the control signals in the negated
state after they have been actively negated and released by the MPC7445 and other bus masters.
9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.
10. This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
11. Unused address pins must be pulled down to GND.
12. This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect
performance.
13. These signals must be pulled down to GND if unused, or if the MPC7445 is in 60x bus mode.
14. This signal must be asserted during reset, by pull-down to GND or assertion by HRESET, to ensure proper
operation.
Table 15. Pinout Listing for the MPC7445, 360 CBGA Package (continued)
Signal Name Pin Number Active I/O I/F Select 1Notes
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38 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Pinout Listings
Table 16. Pinout Listing for the MPC7455, 483 CBGA Package
Signal Name Pin Number Active I/O I/F Select 1Notes
A[0:35] E10, N4, E8, N5, C8, R2, A7, M2, A6, M1,
A10, U2, N2, P8, M8, W4, N6, U6, R5, Y4, P1,
P4, R6, M7, N7, AA3, U4, W2, W1, W3, V4,
AA1, D10, J4, G10, D9
High I/O BVSEL 11
AACK U1 Low Input BVSEL
AP[0:4] L5, L6, J1, H2, G5 High I/O BVSEL
ARTRY T2 Low I/O BVSEL 8
AVDD B2 — Input N/A
BG R3 Low Input BVSEL
BMODE0 C6 Low Input BVSEL 5
BMODE1 C4 Low Input BVSEL 6
BR K1 Low Output BVSEL
BVSEL G6 High Input N/A 3, 7
CI R1 Low Output BVSEL 8
CKSTP_IN F3 Low Input BVSEL
CKSTP_OUT K6 Low Output BVSEL
CLK_OUT N1 High Output BVSEL
D[0:63] AB15, T14, R14, AB13, V14, U14, AB14,
W16, AA11, Y11, U12, W13, Y14, U13, T12,
W12, AB12, R12, AA13, AB1 1, Y12, V1 1, T1 1,
R11, W10, T10, W11, V10, R10, U10, AA10,
U9, V7, T8, AB4, Y6, AB7, AA6, Y8, AA7, W8,
AB10, AA16, AB16, AB17, Y18, AB18, Y16,
AA18, W14, R13, W15, AA14, V16, W6,
AA12, V6, AB9, AB6, R7, R9, AA9, AB8, W9
High I/O BVSEL
DBG V1 Low Input BVSEL
DP[0:7] AA2, AB3, AB2, AA8, R8, W5, U8, AB5 High I/O BVSEL
DRDY T6 Low Output BVSEL 4
DTI[0:3] P2, T5, U3, P6 High Input BVSEL 13
EXT_QUAL B9 High Input BVSEL 9
GBL M4 Low I/O BVSEL
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 39
Pinout Listings
GND A22, B1, B5, B12, B14, B16, B18, B20, C3,
C9, C21, D7, D13, D15, D17, D19, E2, E5,
E21, F10, F12, F14, F16, F19, G4, G7, G17,
G21, H 13, H15, H19, H5, J3, J10, J12, J14,
J17, J21, K5, K9, K11, K13, K15, K19, L10,
L12, L14, L17, L21, M3, M6, M9, M11, M13,
M19, N10, N 12, N14, N 1 7, N2 1, P3 , P9, P11,
P13, P15, P19, R 17, R21, T1 3, T15, T19 , T4,
T7, T9, U17 , U21, V2, V5, V8, V12, V15 , V19,
W7, W17, W21 , Y3 , Y9, Y13 , Y15 , Y20 , AA5 ,
AA17, AB1, AB22
—— N/A
GVDD B13, B15, B17, B19, B21, D12, D14, D16,
D18, D21, E19, F13, F15, F17, F21, G19,
H12, H14, H17, H21, J19, K17, K21, L19,
M17, M21, N19, P17, P21, R15, R19, T17,
T21, U19, V17, V21, W19, Y21
—— N/A 15
HIT K2 Low Output BVSEL 4
HRESET A3 Low Input BVSEL
INT J6 Low Input BVSEL
L1_TSTCLK H4 High Input BVSEL 9
L2_TSTCLK J2 High Input BVSEL 12
L3VSEL A4 High Input N/A 3, 7
L3ADDR[17:0] F20, J16, E22, H18, G20, F22, G22, H20,
K16, J18, H 22, J20, J22, K18, K20 , L16, K22,
L18
High Output L3VSEL
L3_CLK[0:1] V22, C17 High Output L3VSEL
L3_CNTL[0:1] L20, L22 Low Outpu t L3VSEL
L3DATA[0:63] AA19, AB20, U16, W18, AA20, AB21, AA21,
T16, W20, U18, Y22, R16, V20, W22, T18,
U20, N18, N20, N16, N22, M16, M18, M20,
M22, R18, T20, U22, T22, R20, P18, R22,
M15, G18, D22, E20, H16, C22, F18, D20,
B22, G16, A21, G15, E17, A20, C19, C18,
A19, A18, G14, E15, C16, A17, A16, C15,
G13, C 14, A14, E13, C13, G12, A13, E12,
C12
High I/O L3VSEL
L3DP[0:7] AB19, AA22, P22, P16, C20, E16, A15, A12 High I/O L3VSEL
L3_ECHO_CLK[0,2] V18, E18 High Input L3VSEL
L3_ECHO_CLK[1,3] P20, E14 HIgh I/O L3VSEL
LSSD_MODE F6 Low Input BVSEL 2, 7
MCP B8 Low Input BVSEL
No Connect A8, A11, B6, B11, C11, D11, D3, D5, E11, E7,
F2, F11, G11, G2, H11, H9, J8 —— N/A 16
Table 16. Pinout Listing for the MPC7455, 483 CBGA Package (continued)
Signal Name Pin Number Active I/O I/F Select 1Notes
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40 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Pinout Listings
OVDD B3, C5, C7, C10, D2, E3, E9 , F5, G3, G9, H7,
J5, K3, L7, M5, N3, P7, R4, T3, U5, U7, U11,
U15, V3, V9, V13, Y2, Y5, Y7, Y10, Y17 , Y19,
AA4, AA15
—— N/A
PLL_CFG[0:4] A2, F7, C2, D4, H8 High Input BVSEL
PMON_IN E6 Low Input BVSEL 10
PMON_OUT B4 Low Output BVSEL
QACK K7 Low Input BVSEL
QREQ Y1 Low Output BVSEL
SHD[0:1] L4, L8 Low I/O BVSEL 8
SMI G8 Low Input BVSEL
SRESET G1 Low Input BVSEL
SYSCLK D6 — Input BVSEL
TA N8 Low Input BVSEL
TBEN L3 High Input BVSEL
TBST B7 Low Output BVSEL
TCK J7 High Input BVSEL
TDI E4 High Input BVSEL 7
TDO H1 High Output BVSEL
TEA T1 Low Input BVSEL
TEST[0:5] B10, H6, H10, D8, F9, F8 — Input BVSEL 2
TEST[6] A9 — Input BVSEL 9
TMS K4 High Input BVSEL 7
TRST C1 Low Input BVSEL 7, 14
TS P5 Low I/O BVSEL 8
TSIZ[0:2] L1,H3,D1 High Output BVSEL
TT[0:4] F1, F4, K8, A5, E1 High I/O BVSEL
WT L2 Low Output BVSEL 8
Table 16. Pinout Listing for the MPC7455, 483 CBGA Package (continued)
Signal Name Pin Number Active I/O I/F Select 1Notes
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 41
Packag e Desc ription
1.8 Package Description
The foll owing sections pr ovide the package parameters and mecha nical dimensions for the CBGA package.
1.8.1 Package Parameters for the MPC7445, 360 CBGA
The package parameters are as provided in the following list. The package type is 25 ×25 mm, 360-lead
ceramic ball grid array (CBGA).
Package outline 25 × 25 mm
Interconnects 360 (19 × 19 ball array – 1)
Pitch 1.27 mm (50 mil)
Minimum module height 2.72 mm
Maximum module height 3.24 mm
Ball diameter 0.89 mm (35 mil)
VDD J9, J11, J13 , J15, K 10, K12, K14, L9, L11,
L13, L15, M10, M12, M14, N9, N1 1, N13, N15,
P10, P12, P14
—— N/A
Notes:
1. OVDD supplies power to the processor bus, JTAG, and all control signals except the L3 cache controls
(L3CTL[0:1]); GVDD supplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7],
L3_ECHO _CL K [0:3 ], a nd L3 _CLK[0:1]) a nd the L3 control s ign als L 3_C NT L [0: 1]; and VDD supplies power to the
processor core and the PLL (after filtering to become AVDD). For actual recommended value of Vin or supply
voltages, see Table 4.
2. These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.
3. To program the processor interface I/O voltage, connect BVSEL to either GND (selects 1.8 V) or to HRESET
(selects 2.5 V). To program the L3 interface, connect L3VSEL to either GND (selects 1.8 V) or to HRESET
(selects 2.5 V) or to HRESET (selects 1.5 V). If used, pulldown resistors should be less than 250 Ω.
4. Ignored in 60x bus mode.
5. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at
HRESET going high.
6. This sig nal must be negated du rin g rese t, by pull -up to OVDD or negation by ¬HRESET (inverse of HRESET), to
ensure proper operation.
7. Internal pull-up on die.
8. These pins require weak pull-up resistors (for example, 4.7 kΩ) to maintain the control signals in the negated
state after they have been actively negated and released by the MPC7455 and other bus masters.
9. These input signals for factory use only and must be pulled down to GND for normal machine operation.
10. This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
11. Unused address pins must be pulled down to GND.
12. This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect
performance.
13. These signals must be pulled down to GND if unused or if the MPC7455 is in 60x bus mode.
14. This signal must be asserted during reset, by pull-down to GND or assertion by HRESET, to ensure proper
operation.
15. Power must be supplied to GVDD, even when the L3 interface is disabled or unused.
16. These signals are for factory use only and must be left unconnected for normal machine operation.
Table 16. Pinout Listing for the MPC7455, 483 CBGA Package (continued)
Signal Name Pin Number Active I/O I/F Select 1Notes
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42 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Package Description
1.8.2 Mechanical Dimensions for the MPC7445, 360 CBGA
Figure 20 provides the mechanical dimensions and bottom surface nomenclature for the MPC7445, 360
CBGA package.
Figure 20. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7445,
360 CBGA Package
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M, 1994.
2. DIMENSIO NS IN MILLIME TE RS.
3. TOP SIDE A1 CORNER INDEX IS A
METALIZED FEATURE WITH VARIOUS
SHAPES. BOTTO M SIDE A1 CORNER IS
DESIGNATED WITH A BALL MISSING
FROM THE ARRAY.
0.2
C
A
360X
D
2X
A1 CORNER
E
e
0.2
2X
C
B
12345678910111213141516
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
B0.3 A
0.15
b
A
0.15 A
171819
U
W
V
Millimeters
DIM MIN MAX
A 2.72 3.20
A1 0.80 1.00
A2 1.10 1.30
A3 — 0.6
b 0.82 0.93
D 25.00 BSC
D1 — 6.15
D2 12.15 12.45
e 1.27 BSC
E 25.00 BSC
E1 — 11.1
E2 7.45 —
E3 8.75 9.20
Capacitor Region
1
D1
E2
E1
AA1
A2
A3
E3
D2
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 43
Packag e Desc ription
1.8.3 Substrate Capacitors for the MPC7445, 360 CBGA
Figure 21 shows the connectivity of the substrate capacitor pads for the MPC7445, 360 CBGA. All
capacitors are 100 nF.
Figure 21. Substrate Bypass Capacitors for the MPC7445, 360 CBGA
Capacitor Pad Number
-1 -2
C1 OVDD GND
C2 VDD GND
C3 OVDD GND
C4 VDD GND
C5 OVDD GND
C6 VDD GND
1
C3-1
C3-2 C2-2 C1-2
C1-1C2-1
A1 Corner
C4-1
C4-2 C5-2 C6-2
C6-1C5-1
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44 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Package Description
1.8.4 Package Parameters for the MPC7455, 483 CBGA
The package parameters are as provided in the following list. The package type is 29 ×29 mm, 483-lead
ceramic ball grid array (CBGA).
Package outline 29 × 29 mm
Interconnects 483 (22 × 22 ball array – 1)
Pitch 1.27 mm (50 mil)
Minimum module height —
Maximum module height 3.22 mm
Ball diameter 0.89 mm (35 mil)
1.8.5 Mechanical Dimensions for the MPC7455, 483 CBGA
Figure 21 provides the mechanical dimensions and bottom surface nomenclature for the MPC7455, 483
CBGA package.
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 45
Packag e Desc ription
Figure 22. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7455,
483 CBGA Package
0.2
2X
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ASME Y14. 5M , 1994.
2. DIMENSIONS IN MILLIMETERS.
3. TOP S IDE A1 CORN ER IND EX I S A
MET ALIZED FEA TURE WITH V ARIOU
S
SHAPES. BOTTOM SIDE. A1 CORNE
R
IS DESI GN ATED WITH A BALL
MISS ING FROM THE A R R AY.
D
A1 CORNER
E
e
0.2
2X
C
B
12345678910111213141516
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
AA1
A2
A
0.15 A
171819
U
W
V
Millimeters
DIM MIN MAX
A 2.72 3.20
A1 0.80 1.00
A2 1.10 1.30
A3 -- 0.60
b 0.82 0.93
D 29.00 BSC
D1 — 11.6
D2 8.94 —
D3 — 7.1
D4 12.15 12.45
e 1.27 BSC
E 29.00 BSC
E1 — 11.6
E2 8.94 —
E3 — 6.9
E4 8.75 9.20
CA
483X
B0.3 A
0.15
b
202122
Y
AA
AB
Capacitor Region
1
D1
D3
E1
E3
D2
E2
A3
D4
E4
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46 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Package Description
1.8.6 Substrate Capacitors for the MPC7455, 483 CBGA
Figure 23 shows the connectivity of the substrate capacitor pads for the MPC7455, 483 CBGA. All
capacitors are 100 nF.
Figure 23. Substrate Bypass Capacitors for the MPC7455, 483 CBGA
Capacitor Pad Numbe r
-1 -2
C1 OVDD GND
C2 VDD GND
C3 OVDD GND
C4 OVDD GND
C5 VDD GND
C6 OVDD GND
C7 AVDD GND
C8 OVDD GND
C9 GVDD GND
C10 GVDD GND
C11 VDD GND
C12 GVDD GND
1
C3-1
C3-2 C2-2 C1-2
C1-1C2-1
A1 Corner
C7-2
C7-1 C8-1 C9-1
C9-2C8-2
C12-1
C12-2 C11-2 C10-2
C10-1C11-1
C4-2
C4-1 C5-1 C6-1
C6-2C5-2
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 47
System Design Information
1.9 System Design Information
This section provides system and thermal design recommendations for successful application of the
MPC7455.
1.9.1 PLL Configuration
The MPC7455 PLL is configur ed b y the PLL_CFG[0:4 ] signal s. For a give n SYSCLK (bus ) frequency, the
PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration
for the MPC7455 is shown in Table 17 for a set of example frequencies. In this example, shaded cells
represent settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not
comply with the 1-GHz co lumn in Table 8. Note that these conf igurat ions wer e dif fer ent in dev ices pri or to
Rev F ; see S ect ion 1. 11.2, “Par t Nu mber s N ot Ful ly A ddre sse d by This D oc umen t,” for more infor mat ion
regarding documentation of prior revisions.
Table 17. MPC7455 Microprocessor PLL Configuration Example for 1.0 GHz Parts
PLL_
CFG[0:4]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus (SYSCLK) Frequency
33.3
MHz 50
MHz 66.6
MHz 75
MHz 83
MHz 100
MHz 133
MHz
01000 2x 2x
10000 3x 2x
10100 4x 2x 532
(1064)
10110 5x 2x 500
(1000) 667
(1333)
10010 5.5x 2x 550
(1100) 733
(1466)
11010 6x 2x 600
(1200) 800
(1600)
01010 6.5x 2x 540
(1080) 650
(1300) 866
(1730)
00100 7x 2x 525
(1050) 580
(1160) 700
(1400) 931
(1862)
00010 7.5x 2x 500
(1000) 563
(1125) 623
(1245) 750
(1500) 1000
(2000)
11000 8x 2x 533
(1066) 600
(1200) 664
(1328) 800
(1600)
01100 8.5x 2x 566
(1132) 638
(1276) 706
(1412) 850
(1700)
01111 9x 2x 600
(1200) 675
(1350) 747
(1494) 900
(1800)
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48 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
System Design Information
01110 9.5x 2x 633
(1266) 712
(1524) 789
(1578) 950
(1900)
10101 10x 2x 500
(1000) 667
(1333) 750
(1500) 830
(1660) 1000
(2000)
10001 10.5x 2x 525
(1050) 700
(1400) 938
(1876) 872
(1744)
10011 11x 2x 550
(1100) 733
(1466) 825
(1650) 913
(1826)
00000 11.5x 2x 575
(1150) 766
(532) 863
(1726) 955
(1910)
10111 12x 2x 600
(1200) 800
(1600) 900
(1800) 996
(1992)
11111 12.5x 2x 600
(1200) 833
(1666) 938
(1876)
01011 13x 2x 650
(1300) 865
(1730) 975
(1950)
11100 13.5x 2x 675
(1350) 900
(1800)
11001 14x 2x 700
(1400) 933
(1866)
00011 15x 2x 500
(1000) 750
(1500) 1000
(2000)
11011 16x 2x 533
(1066) 800
(1600)
00001 17x 2x 566
(1132) 850
(1900)
00101 18x 2x 600
(1200) 900
(1800)
00111 20x 2x 667
(1334) 1000
(2000)
01001 21x 2x 700
(1400)
01101 24x 2x 800
(1600)
11101 28x 2x 933
(1866)
00110 PLL bypass PLL off, SYSCLK clocks core circuitry directly
Table 17. MPC7455 Microprocessor PLL Configuration Example for 1.0 GHz Parts (continued)
PLL_
CFG[0:4]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus (SYSCLK) Frequency
33.3
MHz 50
MHz 66.6
MHz 75
MHz 83
MHz 100
MHz 133
MHz
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 49
System Design Information
The MPC7455 gene rates th e clock for t he exte rnal L3 synchr onous da ta SRAMs b y divid ing the core c lock
frequency of the MPC7455. The core-to-L3 frequency divisor for the L3 PLL is selected through the
L3_CLK bits of the L3CR register. Generally, the divisor must be chosen according to the frequency
supported by the external RAMs, the frequency of the MPC7455 core, and timing analysis of the circuit
board rout ing. Table 18 shows various exa mple L3 clo ck frequ encies that ca n be obtai ned for a gi ven set of
core frequencies.
11110 PLL of f PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0:4] settings not listed are reserved.
2. The samp le bu s-to-co re freq uenci es sh own are fo r refere nce o nly. So me PLL conf igu rations may s elec t bus, core,
or VCO frequencies which are not useful, not supported, or not tested for by the MPC7455; see Section 1.5.2.1,
“Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled.
However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must
be driv en at o ne-hal f the fre quenc y of SYSCL K and o ffs et in phase to m eet the require d input s etup t IVKH an d hold
time tIXKH (see Table 9). The result will be that the processor bus frequency will be one-half SYSCLK while the
internal processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use
only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In PLL-off mode, no clocking occurs inside the MPC7455 regardless of the SYSCLK input.
Table 18. Sample Core-to-L3 Frequencies
Core Frequency
(MHz) ÷2 ÷2.5 ÷3 ÷3.5 ÷4 ÷5 ÷6
500 250 200 167 143 125 100 83
533 266 213 178 152 133 107 89
550 275 220 183 157 138 110 92
600 300 240 200 171 150 120 100
6502325 260 217 186 163 130 108
6662333 266 222 190 167 133 111
7002350 280 233 200 175 140 117
7332367 293 244 209 183 147 122
8002400 320 266 230 200 160 133
8672433 347 289 248 217 173 145
9332467 373 311 266 233 187 156
Table 17. MPC7455 Microprocessor PLL Configuration Example for 1.0 GHz Parts (continued)
PLL_
CFG[0:4]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus (SYSCLK) Frequency
33.3
MHz 50
MHz 66.6
MHz 75
MHz 83
MHz 100
MHz 133
MHz
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50 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
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1.9.2 PLL Power Supply Filtering
The AVDD power signal is provided on the MPC7455 to provide power to the clock generation PLL. To
ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any
noise in th e 500 kHz to 10 MHz resonant frequen cy range of the PLL. A circuit si milar to the one sho wn in
Figure 22 using s urface mount capacitor s with minimum effective series inductance (ESL) is recommended.
The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby
circuits. It is often possible to route directly from the capacitors to the AVDD pi n, whi ch is on the peri phery
of the 360 CBGA footprint and very close to the periphery of the 483 CBGA footprint, without the
inductance of vias.
Figure 24. PLL Power Supply Filter Circuit
1.9.3 Decoupling Recommendations
Due to the MPC7455 dynami c power management feat ure, large ad dress and data buse s, and high operati ng
frequencies, the MPC7455 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC7455 system, and the MPC7455 itself requires a clean, tightly regulated source of
power . Therefore , it is recommended that the system designer place at least one decouplin g capacitor at each
VDD, OVDD, and GVDD pin of the MPC7455. It is also recommended that these decoupling capacitors
receive their power from separate VDD, OVDD/GVDD, and GND power planes in the PCB, utilizing short
traces to minimize inductance.
These capacitors should have a value of 0.01 or 0.1 µ F. Only ceramic surface mount technology (SMT)
capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where
connections are made along the length of the part. Consistent with the recommendations of Dr. Howard
Johnson in High Speed Digital Design: A Handbook of Black Magic (Prent ice H all , 1993 ) an d cont rary to
previous recommendations for decoupling Motorola microprocessors, multiple small capacitors of equal
value are recommended over using multiple values of capacitance.
10002500 400 333 285 250 200 166
Notes:
1. The core and L3 freq uen ci es are for refe renc e onl y. Note t hat ma xi mu m L3 freq uen cy is d es ign de pen dent. Some
examples may represent core or L3 frequencies which are not useful, not supported, or not tested for the
MPC7455; see Section 1.5.2.3, “L3 Clock AC Specifications,” for valid L3_CLK frequencies and for more
information regarding the maximum L3 frequency. Shaded cells do not comply with Table 10.
2. These core frequencies are not supported by all speed grades; see Table 8.
Table 18. Sample Core-to-L3 Frequencies (continued)
Core Frequency
(MHz) ÷2 ÷2.5 ÷3 ÷3.5 ÷4 ÷5 ÷6
VDD AVDD
10 Ω
2.2 µF 2.2 µF
GND Low E SL Sur face M ount Capacitor
s
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 51
System Design Information
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feed ing the VDD, GVDD, a nd OVDD planes, t o enable quic k rechar ging of th e smaller chi p capacitor s. These
bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response
time necessary. They should also be conne cted to the power and ground planes through two v ias to minimize
inductance. Suggested bulk capacitors: 100–330 µF (AVX TPS tantalum or Sanyo OSCON).
1.9.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unus ed act i ve low inputs shou ld be t ied to OVDD. Unused acti ve hi gh inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, GVDD, and GND pins in the
MPC7455. If the L3 interface is not used, GVDD should be connected to the OVDD power plane, and
L3VSEL should be connected to BVSEL.
1.9.5 Output Buffer DC Impedance
The MPC7455 processor bus and L3 I/O drivers are characterized over process, voltage, and temperature.
To meas ure Z0, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of
each resistor is varied until the pad voltage is OVDD/2 (see Figure 2 3).
The output impedance is the average of two components, the resistances of the pull-up and pull-down
devic es. When d ata is held low, SW2 is clos ed (SW1 is open), and R N is trimmed until the voltage at the
pad equa ls OVDD/2. RN then become s the resistance of the pull- down devices. When data is held high, SW1
is closed (SW2 is open), and RP is tri mmed un til the volta ge at the pad eq uals OV DD/2. RP then becomes
the resistance of the pull-up devices. RP and RN are designe d to be cl ose t o each other i n valu e. Then, Z0 =
(RP + RN)/2.
Figure 25. Driver Impedance Measurement
Table 19 summarizes the si gnal i mpeda nce re sults . The impe dance i nc reases with junc tion t emperat ure a nd
is relatively unaffected by bus voltage.
OVDD
OGND
RP
RN
Pad
Data
SW
1
SW
2
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52 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
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1.9.6 Pull-Up/Pull-Down Resistor Requirements
The MPC7455 requires high-resistive (weak: 4.7-kΩ) pull-up resistors on several control pins of the bus
interface to maintain the control signals in the negated state after they have been actively negated and
released by the MPC7455 or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.
Some pin s designated as bei ng for factory t est must be pull ed up to OVDD or down to GND to ensur e proper
device ope ration. For the MPC7445, 360 BGA, the pins that must be pulle d up to OV DD are: LSSD_MODE
and TEST[0:3]; the pins that must be pulled down to GND are: L1_TSTCLK and TEST[4]. For the
MPC7455, 483 BGA, the pin s that must be pull ed up t o OVDD ar e: LSSD_MODE and TEST[0 :5]; the pin s
that mus t be pulle d down are: L1_TSTCLK a nd TEST[6]. The CKS TP_IN si gnal should li kewise, be pulled
up through a pull-up resistor (weak or stronger: 4.7–1 kΩ) to prevent erroneous assertions of this signal
In addit ion, the MPC74 55 has one open- drain style output tha t require s a pull-up resistor (weak or strong er:
4.7–1 kΩ) if it is used by the system. This pin is CKSTP_OUT.
If pul l-down resi stors are us ed to co nfigure BVSEL o r L3VSEL, the res istors sho uld be less than 250 Ω (see
Table 16). Because PLL_CFG[0:4] must remain stable during normal operation, strong pull-up and
pull-down resistors (1 kΩ or less) are recommended to configure these signals in order to protect against
erroneous switching due to ground bounce, power supply noise or noise coupling.
During i nactive periods on the bus, the ad dress and t ra nsf er at tr ibutes may not be dri ven by any mas te r a nd
may, ther efore , float in the high-i mpedan ce state fo r relat ively long perio ds of ti me. Because the MPC7455
must continually monitor these signals for snooping, this float condition may cause excessive power draw
by the input receivers on the MPC7455 or by other receivers in the system. These signals can be pulled up
through weak (10 -kΩ) pull -up re sisto rs by the sys tem , addre ss bus driven mode ena bled ( see t he MPC7450
RISC Micr o por ce ssor Family Users’ Manual for more information on this mode), or they may be otherwise
driven by the system during inactive periods of the bus to avoid this additional power draw. Preliminary
studies have shown th e addit ional po wer dr aw by the MPC7455 inp ut rece ivers to be negli gible and, in any
event, none of these measures are necessary for proper device operation. The snooped address and transfer
attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.
If extended addressing is not used, A[0:3] are unused and must be pulled low to GND through weak
pull-do wn resistors. If the MPC7455 i s in 60x bu s mode, DTI[0:3] must be pulled low t o GND through weak
pull-down resistors.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore,
do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require
pull-up s, or tha t those sign als be otherwise dr iven by the sy stem during ina ctive per iods by th e sys tem. The
data bus signals are: D[0:63] and DP[0:7].
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and
should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity
checking shoul d al so be disabled t hr ough HID0, and al l pa ri ty pins may be left unconnected by the s yst em.
Table 19. Impedan ce Character ist ics
VDD = 1.5 V, OVDD = 1.8 V ± 5%, Tj = 5°–85°C
Impedance Processor Bus L3 Bus Unit
Z0Typical 33–42 34–42 Ω
Maximum 31–51 32–44 Ω
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 53
System Design Information
The L3 interface does not normally require pull-up resistors.
1.9.7 JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture.
While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more
reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.
Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,
simply tyi ng TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interf ace connect s primarily thr ough the JTAG port of the pro cessor , with s ome additional status monito ring
signals . The COP port requires the ability to independently assert HRESET or TRST in order to fully control
the proce ssor . If the tar get system has independent reset source s, such as voltage monitors, watchdog timers,
power sup ply failures, or push-button s witches, then t he COP reset signals must be mer ged into t hese signals
with logic.
The arr angement sho wn in Figur e 24 allo ws the COP port to inde pendentl y assert HRESET or TRST, while
ensurin g t hat t he target can drive HRESET as well . If the JTAG interface and COP heade r will not be use d,
TRST should be ti ed to HRESET through a 0-Ω isolati on resistor so th at it is assert ed when the system re set
signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during power-on. While
Motoro la recommend s that the COP header be des igned into th e system as shown in Figure 24, if this is not
possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need
to be wired onto the system in debug situations.
The COP header shown in Figure 24 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has
pin 14 removed as a connector key.
There is no standardized way to number the COP head er shown in Figure 24; conseq uent ly, many differen t
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 24 is common to all known emulators.
The QACK signal shown in Figure 24 is usually connected to the PCI bridg e chip in a system and is an input
to the MPC7455 informing it that it can go into the quiescent state. Under normal operation this occurs
during a low-power mode selection. In order for COP to work, the MPC7455 must see this signal asserted
(pulled down). While shown on the COP header, not all emulator products drive this signal. If the product
does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator products
implement open-drain ty pe outputs and can only drive QACK asser ted; for these tool s, a pull-u p resistor can
be implemented to ensure this signal is de-asserted when it is not being driven by the tool. Note that the
pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never necessary to
populate both in a system. To preserve correct power-down operation, QACK should be merged via logic
so that it also can be driven by the PCI bridge.
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54 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
System Design Information
Figure 2 6. JTAG Interface Connection
HRESET HRESET
From Target
Board Sources
HRESET
13 SRESET
SRESET SRESET
NC
NC
11
VDD_SENSE
6
5 1
15
2 kΩ10 kΩ
10 k Ω
10 k Ω
OVDD
OVDD
OVDD
OVDD
CHKSTP_IN CHKSTP_IN
8TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4TRST
7
16
2
10
12
(if any)
COP Header
14 2
Key
QACK
OVDD
OVDD
10 kΩOVDD
TRST
10 kΩOVDD
10 kΩ
10 kΩ
QACK
QACK
CHKSTP_OUT
CHKSTP_OUT
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
No Pin
COP Connector
Physical Pin Out
10 k Ω 4OVDD
1
2 kΩ 3
0 Ω 5
Notes:
1. RUN/STOP, norma lly found on pin 5 of the CO P head er, is not implement ed on the MPC745 5. C
on
pin 5 of the COP header to OVDD wi th a 10-kΩ pull-up resistor.
2. Key location; pin 14 is not physically present on the COP header.
3. Component not populated. Populate only if debug tool does not drive QACK.
4. Populate only if debug tool uses an open-drain type output and does not actively de-assert QAC
K
5. If the JTAG interface is implemented, connect HRESET from the targ et sou rce to TRST from th
e C
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, c
on
HRESET from the target source to TRST of the part through a 0-Ω isolati on reis is tor.
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 55
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1.9.8 Thermal Management Information
This sec tion provi des therma l management i nformation f or the cer amic ball g rid arra y (CBGA) package for
air-cooled applications. Proper thermal control design is primarily dependent on the system-level
design— the heat sink, air fl ow, and therma l i nterface material. To reduce t he d ie- j unction te mper ature, hea t
sinks may be attached to the package by several methods—spring clip to holes in the printed-circuit board
or packa ge, and mounting c lip and scre w assembly (see Figure 25); however , due to the potent ial lar ge mass
of the heat sink, attachment through the pri nted-circuit board is suggeste d. If a spring clip is used, the spring
force should not exceed 10 pounds.
Figure 27. Package Exploded Cross-Sectional View with Several Heat Sink Options
The board designer can choose between several types of heat sinks to place on the MPC7455. There are
several commercially available heat sinks for the MPC7455 provided by the following vendors:
Aavid Thermall oy 603-224-9 988
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
Alpha Novatech 408-749-7601
473 Sapena Ct. #15
Santa Clara, CA 95054
Internet: www.alphanovatech.com
International Electronic Research Corporation (IERC) 818-842-7277
413 North Moss St.
Burbank, CA 91502
Internet : www.ctscorp.com
Tyco Electronics 800-522-6 752
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com
Thermal Interface Material
Heat Sink CBGA Package
Heat Sink
Clip
Printed-Circuit Board
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Wakefield Engineering 603-635-5102
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.c om
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal
performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
1.9.8.1 Internal Package Conduction Resistance
For the exposed-die packaging technology, shown in Table 3, the intrinsic conduction thermal resistance
paths are as follows:
• The die junction-to-case (actually top-of-die since silicon die is exposed) thermal resistance
• The die junction-to-ball thermal resistance
Figure 26 depicts the primary heat transfer path for a package with an attached heat sink mounted to a
printed-circui t board.
Figure 28. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink
attach mate rial (or t he rmal i nte rface materi al), and final ly to th e heat sink wh ere it i s remov ed b y forc ed-ai r
convection.
Because the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the
silicon may be neglected. Thus, the thermal interface material and the heat sink conduction/convective
thermal resistances a re the dominant terms.
1.9.8.2 Thermal Interface Materials
A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the
thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism,
Figure 27 shows the thermal performance of three thin-sheet thermal-interface materials (silicone,
graph ite/o il, flo roethe r oil) , a bar e join t, and a joi nt with therm al gr ease as a fun ction of co ntact pressu re.
As shown, the per fo rmanc e of these ther ma l in terface mater ia ls improves with incr ea si ng con tac t pressure.
External Resistance
External Resistance
Internal R esi st anc e
Radiation Convection
Radiation Convection
Heat Sink
Printed-Circuit Board
Thermal Interface Material
Package/Leads
Die Junction
Die/Package
(Note the internal versus external package resistance.)
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 57
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The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results
in a thermal resistance approximately seven times greater than the thermal grease joint.
Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board
(see Figure 25). Therefore, the synthetic grease offers the best thermal performance, considering the low
interface pressure and is recommended due to the high power dissipation of the MPC7455. Of course, the
selection of any thermal interface material depends on many factors—thermal performance requirements,
manufacturability, service temperature, dielectric properties, cost, etc.
Figure 29. Thermal Performance of Select Thermal Interface Material
The board designer can choose between several types of thermal interface. Heat sink adhesive materials
should be selected based on high conductivity, yet adequate mechanical strength to meet equipment
shock/vibration requirements. There are several commercially available thermal interfaces and adhesive
materials provided by the following vendors:
The Bergquist Company 800-347-4572
18930 West 78th St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
Chomerics, Inc. 781-935-4850
77 Dragon Ct.
Woburn, MA 01888-4014
Internet: www.chomerics.com
0
0.5
1
1.5
2
0 1020304050607080
Silicone Sheet (0.006 in.)
Bare Joint
Floroether Oil Sheet (0.007 in.)
Graphite/Oil Sheet (0.005 in.)
Synthetic Grease
Cont a ct Pressure (psi)
Specific Thermal Resistance (K-in.2/W)
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58 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
System Design Information
Dow-Corning Corporation 800-248-2481
Dow-Corning Electronic Materials
2200 W. Salzburg Rd.
Midland, MI 48686-0997
Internet: www.dow.com
Shin-Etsu MicroSi, Inc. 888-642-7674
10028 S. 51st St.
Phoenix, AZ 85044
Internet: www.microsi.com
Thermagon Inc. 888-246-9050
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
The following section provides a heat sink selection example using one of the commercially available heat
sinks.
1.9.8.3 Heat Sink Selection Example
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
Tj = Ta + Tr + (RθJC + Rθint + Rθsa) × Pd
where:
Tj is the die-junction temperature
Ta is the inlet cabinet ambien t temperature
Tr is the air temperature rise within the computer cabinet
RθJC is the junction-to-case thermal resistance
Rθint is the adhesive or interface mate rial thermal resistance
Rθsa is the heat sink base-to-ambient thermal resistance
Pd is the power dissipated by the device
During operation, the die-junction temperatures (Tj) shou ld be m aintain ed less than t he valu e specif ied in
Table 4. The te mpera ture of ai r cool ing th e compone nt great ly depe nds on the ambi ent i nlet air t emperat ure
and the air temper ature r ise with in the e lectron ic cabi net. An electr onic cabinet inlet-a ir temp erature (Ta)
may range from 30° to 40°C. The air temperature rise within a cabinet (T r) may be in the range of 5° to 10°C.
The thermal resistance of the thermal interface material (Rθint) is typically about 1.5°C/W. For example,
assumi ng a Ta of 30°C, a Tr of 5°C, a CBGA pac kag e RθJC = 0.1, and a typic al powe r c ons ump ti on (P d) o f
15.0 W, the following expression for Tj is obtained:
Die-jun ction tempera tur e: Tj = 30°C + 5°C + (0.1°C/W + 1.5°C/W + Rθsa) × 15 W
For th is example, a Rθsa value of 3.1°C/W or less i s required to maint ain the die-j unction temperat ure below
the maximum value of Table 4.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common
figure-of-merit used for comparing the thermal performance of various microelectronic packaging
technol ogi es, one sh oul d e x er cis e caut i on when only us ing this metri c i n determini ng t h er mal mana gemen t
because no single parameter can adequately describe three-dimensional heat flow. The final die-junction
operati ng temperature is not only a function of the compo nent-level t hermal resist ance, but the syste m-level
design an d its operat ing condit ions. In addi tion to th e component's power consumpt ion, a number of f actors
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 59
System Design Information
affect the final operating die-junction temperature—airflow, board population (local heat flux of adjacent
components ), heat sin k effi ciency, heat sink attach , heat sink pl acement, next- level inte rconnect te chnology,
system air temperatur e rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today's
microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection,
and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models
for the board, as well as system-level designs.
For system thermal modeling, the MPC7445 and MPC7455 thermal model is shown in Figure 28. Four
volumes will be used to represent this device. Two of the volumes, solder ball, and air and substrate, are
modeled usi ng the package out line size of the pa ckage. The other two, di e, and bump and underfi ll, have the
same size as the di e. Dimensi ons for t hese vol umes for the MPC7445 and MPC7455 are giv en in Figu re 20
and Figure 21, respectively. The silicon die shou ld be modeled 9.10 × 12.25 × 0.74 mm with t he heat source
applied as a unifor m sour ce at the bott om of the volu me. T he bump and un derfi ll l ayer is modeled as 9. 10 ×
12.25 × 0.069 mm (or as a collapsed volume) with orthotropic material properties: 0.6 W/(m • K) in the
xy-plane and 2 W/(m • K) in the direction of the z-axis. The substrate volume is 25 × 25 × 1.2 mm
(MPC7445) or 29 × 29 × 1.2 mm (MPC7455), and this volume has 18 W/(m • K) isotropic conductivity.
The sold er ball and a ir l ayer i s model ed wit h the same ho rizon tal d imen sions as th e subs trat e and is 0.9 mm
thick. It can als o be model ed as a col la pse d volume using orth otropic materi al pro perties: 0.03 4 W/(m • K)
in the xy-pl ane direction and 3.8 W/(m • K) in th e direction o f the z-axis.
Figure 30. Recommended Thermal Model of MPC7445 and MPC7455
Bump and Underfill
Die
Substrate
Solder and Air
Die
Substrate
Side View of Model (Not to Scale)
Top View of Model (Not to Scale)
x
y
z
Conductivity Value Unit
Bump and Underfill
kx0.6 W /(m • K)
ky0.6
kz2
Substrate
k18
Solder Ball and Air
kx0.034
ky0.034
kz3.8
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60 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Document Revision History
1.10 Document Revision History
Table 20 provides a revision history for this hardware specification.
Table 20. Document Revision History
Rev. No. Substantive Change(s)
0 Initi al rele as e.
1 Updated for Rev F devices; informatio n specific to Rev C devices is now documented in a separ ate part
number specifications; see Section 1 .11.2 for more information.
Removed 600 and 800 MHz speed grades.
Increased leakage current specifications in Table 6 from 10 to 30 µA.
Changed core voltage to 1.3 V; all ins tances of VDD and AVDD updated.
Updated po wer co nsumpt ion specifications in Table 7.
Reduced I/O power guidance in Table 7 from <20% to <5%.
Added footnote 1 to Figures 9 and 11.
Removed CI and WT from Input Setup and Input Hold lists in Table 10; these are output-only signals.
Removed INT, HRESET, MCP, SRESET, and SMI from Input Setup and Input Hold lists in Table 10;
these are asynchronous inputs.
Added TT[0:3] to Input Setup, Input Hold, Output Valid, and Output Hold lists in Table 10; these were
mistakenly omitted in Rev 0.
Updated Tables 13 and 14 to reflect new L3 AC timing in Rev F devices.
Corrected Note 10 in Tables 16 and 17; this is an event pin, not an enable pin.
Corrected entries for L3_ECHO_CLK[1,3] in Table 17; these are I/O pins, not input-only.
Added Note 16 to Table 17; all No Connect pins must be left unconnected.
Changed name of P LL_EXT to PLL_CFG[4] and updated all instances .
Updated Table 18 to reflect PLL configuration settings for Rev F devices.
Added dimensions D2 and E3 to Figure 20.
Transposed dimensions D4 and E4 in Figure 21 (dimensions were reversed).
Revised Figure 24 and Section 1.9.7.
Revised format of Section 1.11.2 and added Tables 23 through 26.
Revised Section 1.9.8.3 and added additional thermal modeling information, including Figure 28.
Changed maximum heat sink clip spring force in Section 1.9.8, from 5.5 lbs to 10 lbs.
Changed substrate marking for MPC7445 in Figure 29; all MPC744x device substrates are marked
MPC7440.
Changed substrate marking for MPC7455 in Figure 29; all MPC745x device substrates are marked
MPC7450.
1.1 Remov ed referenc e to Note 4 for DTI signa ls in Tables 15 and 16: these sign als are unus ed in 60x bus
mode and must be pulled down (see Note 13); they are not ignored.
Improved precision o f die and package dimensions in Figures 20 a nd 21.
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 61
Document Revision History
2 Corrected ent ries in Table 17 for 33 MHz and 50 MHz bus freq uencies with multipliers of 24x and higher .
Corrected typographical errors in heatsink selection example in Section 1.9.8.3.
Removed erroneous instances of PLL_EXT signal name and changed remaining instances of
PLL_CFG[0:3] to PLL_CFG[0:4]. (These were artifacts from older revisions; see entry for Rev 1.0.)
Corrected erroneous instances (artifacts) mentioning 1.6 V core voltage. Core voltage for devices
completely covered by this revision (and revisio ns 1.x) of this document is 1.3 V.
Corrected errors in PLL multipliers in Table 17: 32x and 25x are not supported ratios, 3x and 4x are
supported, 10.5x and 12.5x PLL settings were incorrect.
Replaced notes at bottom of Table 17 (erroneously missing in revisions 1.x).
Updated coplanarity specifications in Figures 20 and 21 from 0.2 mm to 0.15 mm.
3 Added Revision G (Rev 3.4) devices to specifications.
Added new PowerPC trad ema r ki ng inform ati on.
4 Added substrate capacitor information in Sections 1.8.3 and 1.8.6.
Clarifi ed max im um and typical L3 cloc k fre que nc y in Sec t io n 1.5. 2.3. ; t ypi ca l L3 freq uen cy now st a ted
as 250 MHz based on changes to L3 AC timing.
Signific antly chan ged L 3 AC timi ng in Tables 12 a nd 13 . Thes e ch anges reflec t both upda tes b ased on
latest characterization and error corrections (effects of non-zero L3OH values were incorrectly
documented in earlier revisions of this document).
Clarified address bus pull-up resistor recommendations in Section 1.9.6.
Added pull-up/pull-down recommendations for CKSTP_IN and PLL_CFG[0:4] to Section 1.9.6.
Modified Table 9, Figure 5, and Figure 6 to more accurately show when the mode select inputs
(BMODE[0:1], L3VSEL, BVSEL) are sampled and AC timing requirements.
Figures 20 and 22: Updated/corrected dimensions in mechanical drawings.
Table 20. Document Revision History (continued)
Rev. No. Substantive Change(s)
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62 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Ordering Information
1.11 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in
Section 1.11.1, “Part Numbers Fully Addressed by This Document.” Note that the individual part numbers
corres pond t o a maximum proces sor c ore f reque ncy. For availa ble fr equenci es, c ontact your loca l Mo torol a
sales of f ice. In addi tion to the proce ssor fr equency, the part numberi ng scheme als o includ es an appli cati on
modifier which may speci fy special applica tion condi tion s. Each part number also contai ns a rev ision leve l
code which re fe rs t o the die mask revision numbe r. Secti on 1.11.2, “Par t Number s Not Full y Addressed by
This Document,” lists the part numbers which do not fully conform to the specifications of this document.
These special part numbers require an additional document called a part number specification.
1.11.1 Part Numbers Fully Addressed by This Document
Table 21 provides the Motorola part numbering nomenclature for the MPC7455.
1.11.2 Part Numbers Not Fully Addressed by This Document
Parts with application modifiers or revision levels not fully addressed in this specification document are
described in separate part number specifications which supplement and supersede this document; see
Table 22 through Ta ble 25.
Table 21. Part Numbering Nomenclature
xx 74x5xRX nnnn x x
Product
Code Part
Identifier Process
Descriptor Package Processor
Frequency 1Application
Modifier Revision Level
XC 27455
7445 A RX = CBGA 733
867
933
1000
L: 1.3 V ± 50 mV
0 to 105°CF: 3.3; PVR = 8001 0303
MC G: 3.4; PVR = 8001 0304
Notes:
1. Processor core frequencies supported by pa rts addressed by this specification only. Parts addressed by part
number specifications may support other maximum core frequencies.
2. The X prefix in a Motorola part number designates a “Pilot Production Prototype” as defined by Motorola SOP
3-13. These are from a limited production volume of prototypes manufactured, tested, and Q.A. inspected on a
qualified technology to simulate normal production. These parts have only preliminary reliability and
charac teri zation dat a . Befo re pi lot p rodu cti on prototyp es may be s hip ped, written authorizatio n from the cus tom er
must be on file in the applicable sales office acknowledging the qualification status and the fact that product
changes may still occur while shipping pilot production prot otypes.
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MOTOROLA MPC7455 RISC Microprocessor Hardware Specifications 63
Ordering Information
Table 22. Part Numbers Addressed by XPC74x5RXnnnLC Series Part Number Specification
(Document Order No. MPC7455RXLCPNS)
XPC 74x5RX nnn LC
Product
Code Part
Identifier Package Processor
Frequency Application Modifier Revision Level
XPC 7455
7445 RX = CBGA 600
733
800
867
933
L: 1.6 V ± 50 mV
0 to 105°CC: 2.1; PVR = 8001 0201
PPC 1000
Table 23. Part Numbers Addressed by XPC74x5RXnnnNx Series Part Number Specification
(Document Order No. MPC7455RXNXPNS)
XPC 74x5RX nnn NC
Product
Code Part
Identifier Package Processor
Frequency Application Modifier Revision Level
XPC 7455
7445 RX = CBGA 600
733
800
N: 1.3 V ± 50 mV
0 to 105°CC: 2.1; PVR = 8001 0201
Table 24. Part Numbers Addressed by XPC74x5RXnnnPx Series Part Number Specification
(Document Order No. MPC7455RXPXPNS)
XPC 7455 RX nnn PC
Product
Code Part
Identifier Package Processor
Frequency Application Modifier Revision Level
XPC 7455 RX = CBGA 933
1000 P: 1.85 V ± 50 mV
0 to 65°CC: 2.1; PVR = 8001 0201
Table 25. Part Numbers Addressed by XPC74x5RXnnnSx Series Part Number Specification
(Document Order No. MPC7455RXSXPNS)
XPC 7455 RX nnnn SC
Product
Code Part
Identifier Package Processor
Frequency Application Modifier Revision Level
XPC 7455 RX = CBGA 1000 S: 1.85 V ± 50 mV
0 to 75°CC: 2.1; PVR = 8001 0201
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64 MPC7455 RISC Microprocessor Hardware Specifications MOTOROLA
Ordering Information
1.11.3 Part Marking
Parts are marked as the example shown in Figure 29.
Figure 31. Part Marking for BGA Device
BGA
Notes:
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States
.
MMMM MM is the 6-digit mask number.
ATWLYYWWA is the traceability code.
MC7455A
RX1000LG
MMMMMM
ATWLYYWWA
7450
BGA
MC7445A
RX1000LG
MMMMMM
ATWLYYWWA
7440
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Ordering Information
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MPC7455EC
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