PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM 4Mb ZBTTM SRAM MT55L256L18P1, MT55L256V18P1, MT55L128L32P1, MT55L128V32P1, MT55L128L36P1, MT55L128V36P1 WITH SMART ZBT OPTION 3.3V VDD, 3.3V or 2.5V I/O FEATURES * SMART ZBTTM option to minimize potential bus contention * High frequency and 100 percent bus utilization * Fast cycle times: 6ns, 7.5ns and 10ns * Single +3.3V 5% power supply (VDD) * Separate +3.3V or +2.5V isolated output buffer supply (VDDQ) * Advanced control logic for minimum control signal interface * Individual BYTE WRITE controls may be tied LOW * Single R/W# (read/write) control pin * CKE# pin to enable clock and suspend operations * Three chip enables for simple depth expansion * Clock-controlled and registered addresses, data I/Os and control signals * Internally self-timed, fully coherent WRITE * Internally self-timed, registered outputs to eliminate the need to control OE# * SNOOZE MODE for reduced-power standby * Common data inputs and data outputs * Linear or interleaved burst modes * Burst feature (optional) * Pin/function compatibility with 2Mb, 8Mb and 16Mb ZBT SRAM family * Automatic power-down OPTIONS 100-Pin TQFP** 119-Pin BGA MARKING * Timing (Access/Cycle/MHz) 4ns/6ns/166 MHz 4.2ns/7.5ns/133 MHz 5ns/10ns/100 MHz * Configurations 3.3V I/O 256K x 18 128K x 32 128K x 36 2.5V I/O 256K x 18 128K x 32 128K x 36 * Package 100-pin TQFP 119-pin, 14mm x 22mm BGA -6 -7.5* -10* **JEDEC-standard MS-026 BHA (LQFP). MT55L256L18P1 MT55L128L32P1 MT55L128L36P1 GENERAL DESCRIPTION The Micron(R) Zero Bus TurnaroundTM (ZBTTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The SMART ZBT feature enhances the ability of the SRAM to run in systems with minimal transition time on the data bus, whether using multiple SRAMs or complementing ASIC designs. Micron's SMART ZBT feature allows the tKHQX1 (clock HIGH to output valid) to adapt to the system clock, thus reducing contention issues. The SMART ZBT will drive the bus turn-on later than the traditional ZBT. MT55L256V18P1 MT55L128V32P1 MT55L128V36P1 T B *SMART ZBT option available. Part Number Example: MT55L256L18P1T-10A 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM FUNCTIONAL BLOCK DIAGRAM 256K x 18 18 SA0, SA1, SA 18 SA1 SA1' D1 Q1 SA0 SA0' BURST D0 Q0 LOGIC MODE CLK CKE# 16 18 ADDRESS REGISTER 0 ADV/LD# K K 18 WRITE ADDRESS REGISTER 2 WRITE ADDRESS REGISTER 1 18 ADV/LD# 256K x 9 x 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BWa# WRITE DRIVERS BWb# MEMORY ARRAY R/W# S E N S E A M P S O U T P U T R E G I S T E R S E INPUT REGISTER 1 E OE# CE# CE2 CE2# D A T A S T E E R I N G O U T P U T B U F F E R S DQs E INPUT REGISTER 0 E READ LOGIC FUNCTIONAL BLOCK DIAGRAM 128K x 32/36 17 SA0, SA1, SA 17 SA1 SA1' D1 Q1 SA0 SA0' BURST D0 Q0 LOGIC MODE CLK CKE# 15 17 ADDRESS REGISTER 0 ADV/LD# K K WRITE ADDRESS REGISTER 1 17 WRITE ADDRESS REGISTER 2 17 ADV/LD# BWa# BWb# 128K x 8 x 4 (x32) WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS BWc# 128K x 9 x 4 (x36) MEMORY ARRAY BWd# R/W# S E N S E A M P S O U T P U T R E G I S T E R S E INPUT REGISTER 1 E OE# CE# CE2 CE2# D A T A S T E E R I N G O U T P U T B U F F E R S DQs E INPUT REGISTER 0 E READ LOGIC NOTE: Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions and timing diagrams for detailed information. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM GENERAL DESCRIPTION (continued) Micron's 4Mb ZBT SRAMs integrate a 256K x 18, 128K x 32, or 128K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization, eliminating any turnaround cycles when transitioning from READ to WRITE, or vice versa. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), cycle start input (ADV/LD#), synchronous clock enable (CKE#), byte write enables (BWa#, BWb#, BWc# and BWd#) and read/write (R/W#). Asynchronous inputs include the output enable (OE#, which may be tied LOW for control signal minimization), clock (CLK) and snooze enable (ZZ, which may be tied LOW if unused). There is also a burst mode pin (MODE) that selects between interleaved and linear burst modes. MODE may be tied HIGH, LOW or left unconnected if burst is unused. The data-out (Q), enabled by OE#, is registered by the rising edge of CLK. WRITE cycles can be from one to four bytes wide as controlled by the write control inputs. All READ, WRITE and DESELECT cycles are initiated by the ADV/LD# input. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV/LD#). Use of burst mode is optional. It 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 is allowable to give an address for each individual READ and WRITE cycle. BURST cycles wrap around after the fourth access from a base address. To allow for continuous, 100 percent use of the data bus, the pipelined ZBT SRAM uses a LATE LATE WRITE cycle. For example, if a WRITE cycle begins in clock cycle one, the address is present on rising edge one. BYTE WRITEs need to be asserted on the same cycle as the address. The data associated with the address is required two cycles later, or on the rising edge of clock cycle three. Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During a BYTE WRITE cycle, BWa# controls DQa pins; BWb# controls DQb pins; BWc# controls DQc pins; and BWd# controls DQd pins. Cycle types can only be defined when an address is loaded, i.e., when ADV/LD# is LOW. Parity/ECC bits are only available on the x18 and x36 versions. Micron's 4Mb ZBT SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are LVTTLcompatible. Users can choose either a 2.5V or 3.3V I/O version. The device is ideally suited for systems requiring high bandwidth and zero bus turnaround delays. Please refer to Micron's Web site (www.micron.com/ mti/msp/html/sramprod.html) for the latest data sheet. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM TQFP PIN ASSIGNMENT TABLE PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 x18 NC NC NC NC NC DQb DQb DQb DQb DQb DQb DQb DQb DQb NC x32 NC DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc MS# VDD VDD VSS DQd DQd VDDQ VSS DQd DQd DQd DQd x36 DQc DQc DQc DQc DQc DQc DQc DQc DQc DQd DQd DQd DQd DQd DQd PIN # x18 x32 x36 26 VSS 27 VDDQ 28 NC DQd DQd 29 NC DQd DQd 30 NC NC DQd 31 MODE (LBO#) 32 SA 33 SA 34 SA 35 SA 36 SA1 37 SA0 38 DNU 39 DNU 40 VSS 41 VDD 42 DNU 43 DNU 44 SA 45 SA 46 SA 47 SA 48 SA 49 SA 50 SA PIN # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 x18 NC NC NC NC NC DQa DQa DQa DQa DQa NC x32 NC DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa ZZ VDD VDD VSS DQb DQb VDDQ VSS DQb DQb DQb DQb x36 DQa DQa DQa DQa DQa DQb DQb DQb DQb DQb DQb PIN # x18 x32 x36 76 VSS 77 VDDQ 78 NC DQb DQb 79 NC DQb DQb 80 SA NC DQb 81 SA 82 SA 83 NF* 84 NF* 85 ADV/LD# 86 OE# (G#) 87 CKE# 88 R/W# 89 CLK 90 VSS 91 VDD 92 CE2# 93 BWa# 94 BWb# 95 NC BWc# BWc# 96 NC BWd# BWd# 97 CE2 98 CE# 99 SA 100 SA * Pins 83 and 84 are reserved for address expansion, 8Mb and 16Mb respectively. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM SA NC NC VDDQ VSS NC DQa DQa DQa VSS VDDQ DQa DQa VSS VDD VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC PIN ASSIGNMENT (TOP VIEW) 100-PIN TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x18 SA SA SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE (LBO#) NC/DQb* DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS VDD VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC/DQa* NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb MS# VDD VDD VSS DQb DQb VDDQ VSS DQb DQb DQb NC VSS VDDQ NC NC NC SA SA NF** NF** ADV/LD# OE# (G#) CKE# R/W# CLK VSS VDD CE2# BWa# BWb# NC NC CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x32/x36 SA SA SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE (LBO#) NC/DQc* DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc MS# VDD VDD VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC/DQd* SA SA NF** NF** ADV/LD# OE# (G#) CKE# R/W# CLK VSS VDD CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA *No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. **Pins 83 and 84 are reserved for address expansion, 8Mb and 16Mb respectively. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM TQFP PIN DESCRIPTIONS x18 37 36 32-35, 44-50, 80-82, 99, 100 x32/x36 37 36 32-35, 44-50, 81, 82, 99, 100 93 94 - - 93 94 95 96 BWa# BWb# BWc# BWd# Input 89 89 CLK Input 98 98 CE# Input 92 92 CE2# Input 97 97 CE2 Input 86 86 OE# (G#) Input 85 85 87 87 CKE# Input 64 64 ZZ Input 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 SYMBOL TYPE SA0 Input SA1 SA ADV/LD# Input DESCRIPTION Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Pins 83 and 84 are reserved as address bits for higher-density 8Mb and 16Mb ZBT SRAMs, respectively. SA0 and SA1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address. BWs are associated with addresses and apply to subsequent data. BWa# controls DQa pins; BWb# controls DQb pins; BWc# controls DQc pins; BWd# controls DQd pins. Clock: This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD# LOW). Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD# LOW). This input can be used for memory depth expansion. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD# LOW). This input can be used for memory depth expansion. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is the JEDECstandard term for OE#. Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new address at the CLK rising edge. Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the device. When CKE# is HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM TQFP PIN DESCRIPTIONS (continued) x18 88 x32/x36 88 14 14 MS# (a) 58, 59, 62, 63, 68, 69, 72-74 (b) 8, 9, 12, 13, 18, 19, 22-24 (a) 52, 53, 56-59, 62, 63 (b) 68, 69, 72-75, 78, 79 (c) 2, 3, 6-9, 12, 13 (d) 18, 19, 22-25, 28, 29 51 80 1 30 31 DQa N/A 31 SYMBOL TYPE R/W# Input DQb DESCRIPTION Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW. Input Smart Enable: A LOW on this pin selects the SMART ZBT function. A HIGH on this pin selects normal ZBT function. Do not alter input state while device is operating. Input/ SRAM Data I/Os: Byte "a" is DQa pins; Byte "b" is DQb Output pins; Byte "c" is DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold times around the rising edge of CLK. DQc DQd NC/DQa NC/ NC/DQb I/O NC/DQc NC/DQd MODE Input (LBO#) 1-3, 6, 7, 25, 28-30, 51-53, 56, 57, 75, 78, 79, 95, 96 N/A NC NC 83, 84 83, 84 NF - 38, 39, 42, 43 38, 39, 42, 43 DNU - 15, 16, 41, 65, 66, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 15, 16, 41, 65, 66, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VDD Supply VDDQ Supply VSS Supply 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 No Connect/Data Bits: On the x32 version, these pins are no connect (NC) and can be left floating or connected to GND to minimize thermal impedance. On the x36 version, these bits are DQs. Mode: This input selects the burst sequence. A LOW on this pin selects linear burst. NC or HIGH on this pin selects interleaved burst. Do not alter input state while device is operating. LBO# is the JEDEC-standard term for MODE. No Connect: These pins can be left floating or connected to GND to minimize thermal impedance. No Function: These are internally connected to the die and will have the capacitance of input pins. It is allowable to leave these pins unconnected or driven by signals. Reserved for address expansion, pin 83 becomes an SA at 8Mb density and pin 84 becomes an SA at 16Mb density. Do Not Use: These signals may either be unconnected or wired to GND to minimize thermal impedance. Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Ground: GND. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM PIN LAYOUT (TOP VIEW) 119-PIN BGA x18 x32/x36 1 2 3 4 5 6 7 VDDQ SA SA NF1 SA SA VDDQ A 1 2 3 4 5 6 7 VDDQ SA SA NF1 SA SA VDDQ NC CE2 SA ADV/LD# SA CE2# NC NC SA SA VDD SA SA NC DQc NC/DQPc2 VSS NC VSS NC/DQPb2 DQb DQc DQc VSS CE# VSS DQb DQb VDDQ DQc VSS OE# VSS DQb VDDQ DQc DQc BWc# NF1 BWb# DQb DQb DQc DQc VSS R/W# VSS DQb DQb VDDQ VDD VDD3 VDD VDD3 VDD VDDQ DQd DQd VSS CLK VSS DQa DQa DQd DQd BWd# NC BWa# DQa DQa VDDQ DQd VSS CKE# VSS DQa VDDQ DQd DQd VSS SA1 VSS DQa DQa DQd NC/DQPd2 VSS SA0 VSS NC/DQa2 DQa NC SA MODE VDD MS# SA NC NC NC SA SA SA NC ZZ VDDQ DNU DNU DNU DNU NC VDDQ A B B NC CE2 SA ADV/LD# SA CE2# NC C C NC SA SA SA VDD SA NC D D DQb NC VSS VSS NC DQPa NC E E NC DQb VSS VSS CE# NC DQa F F VDDQ NC VSS VSS OE# DQa VDDQ G G NC DQb BWb# NF1 VSS NC DQa H H DQb NC R/W# VSS VSS DQa NC J J VDDQ VDD VDD3 VDD3 VDD VDD VDDQ K K NC DQb VSS CLK VSS NC DQa L L DQb NC VSS NC BWa# DQa NC M M VDDQ DQb VSS CKE# VSS NC VDDQ N N DQb NC VSS SA1 VSS DQa NC P P NC DQPb VSS SA0 VSS NC DQa R R NC SA MODE VDD MS# SA NC T T NC SA SA NC SA SA ZZ U U VDDQ DNU DNU DNU DNU NC VDDQ TOP VIEW TOP VIEW NOTE: 1. Pins 4G and 4A are reserved for address expansion, 8Mb and 16Mb respectively. 2. No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 3. Pins 3J and 5J do not have to be connected directly to VDD if the input voltage is VIH. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM BGA PIN DESCRIPTIONS x18 x32/x36 SYMBOL 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T 4P 4N 2A, 2C, 2R, 3A, 3B, 3C, 3T, 4T, 5A, 5B, 5C, 5T, 6A, 6C, 6R SA0 SA1 SA 5L 3G - - 5L 5G 3G 3L BWa# BWb# BWc# BWd# Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa# controls DQa's and DQPa; BWb# controls DQb's and DQPb. For the x32 and x36 versions, BWa# controls DQa's and DQPa; BWb# controls DQb's and DQPb; BWc# controls DQc's and DQPc; BWd# controls DQd's and DQPd. Parity is only available on the x18 and x36 versions. 4M 4M CKE# Input Synchronous Clock Enable: This active LOW input permits CLK to propogate throughout the device. When CKE# is HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet the setup and hold times around the rising edge of CLK. 4H 4H R/W# Input Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations must meet the setup and hold times around the rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW. 4K 4K CLK Input Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. 4E 4E CE# Input Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. 6B 6B CE2# Input Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. 7T 7T ZZ 2B 2B CE2 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 TYPE DESCRIPTION Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Input Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. Input Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM BGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL TYPE 4F 4F OE# Input Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. 4B 4B ADV/LD# Input Synchronous Address Advance/Load: When HIGH. this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new address at the CLK rising edge. 3R 3R MODE Input Mode: This input selects the burst sequence. A LOW on this input selects "linear burst." NC or HIGH on this input selects "interleaved burst." Do not alter input state while device is operating. 5R 5R MS# Input Smart Enable: This input will select SMART ZBT mode when a LOW is present. A HIGH will select normal ZBT mode. Do not alter input state while device is operating. 4A, 4G 4A, 4G NF Input No Function: These pins are internally connected to the die and will have the capacitance of input pins. It is allowable to leave these pins unconnected or driven by signals. These pins are reserved for address expansion; 4G becomes an SA at 8Mb density and 4A becomes an SA at 16Mb density. (a) 6F, 6H, 6L, 6N, 7E, 7G, 7K, 7P (b) 1D, 1H, 1L, 1N, 2E, 2G, 2K, 2M (a) 6K, 6L, 6M, 6N, 7K, 7L, 7N, 7P (b) 6E, 6F, 6G, 6H, 7D, 7E, 7G, 7H (c) 1D, 1E, 1G, 1H, 2E, 2F, 2G, 2H (d) 1K, 1L, 1N, 1P, 2K, 2L, 2M, 2N DQa 6D 2P - - 6P 6D 2D 2P 2J, 3J, 4C, 4J, 2J, 3J, 4C, 4J, 4R, 5J, 6J 4R, 5J, 6J 1A, 1F, 1J, 1M, 1U, 7A, 7F, 7J, 7M, 7U 1A, 1F, 1J, 1M, 1U, 7A, 7F, 7J, 7M, 7U 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 DQb DESCRIPTION Input/ SRAM Data I/Os: For the x18 version, Byte "a" is DQa's; Byte "b" Output is DQb's. For the x32 and x36 versions, Byte "a" is DQa's; Byte "b" is DQb's; Byte "c" is DQc's; Byte "d" is DQd's. Input data must meet setup and hold times around the rising edge of CLK. DQc DQd NC/DQPa NC/DQPb NC/DQPc NC/DQPd VDD VDDQ NC/ I/O No Connect/Parity Data I/Os: On the x32 version, these are No Connect (NC). On the x18 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb. On the x36 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd. Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM BGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 3D, 3E, 3F, 3H, 3K, 3L, 3M, 3N, 3P, 5D, 5E, 5F, 5G, 5H, 5K, 5M, 5N, 5P 3D, 3E, 3F, 3H, 3K, 3M, 3N, 3P, 5D, 5E, 5F, 5H, 5K, 5M, 5N, 5P VSS 2U, 3U, 4U, 5U 2U, 3U, 4U, 5U DNU - Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. 1B, 1C, 1E, 1G, 1K, 1P, 1R, 1T, 2D, 2F, 2H, 2L, 2N, 4D, 4L, 4T, 6E, 6G, 6K, 6M, 6P, 6U, 7B, 7C, 7D, 7H, 7L, 7N, 7R 1B, 1C, 1R, 1T, 2T, 4D, 4L, 6T, 6U, 7B, 7C, 7R NC - No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 TYPE DESCRIPTION Supply Ground: GND. 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X00 X...X11 X...X10 X...X10 X...X11 X...X00 X...X01 X...X11 X...X10 X...X01 X...X00 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10 PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x18) FUNCTION R/W# BWa# BWb# READ H X X WRITE Byte "a" WRITE Byte "b" WRITE All Bytes WRITE ABORT/NOP L L L L L H L H H L L H NOTE: Using R/W# and BYTE WRITE(s), any one or more bytes may be written. PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x32/x36) FUNCTION READ R/W# H BWa# X BWb# X BWc# X BWd# X WRITE Byte "a" WRITE Byte "b" WRITE Byte "c" WRITE Byte "d" WRITE All Bytes L L L L L L H H H L H L H H L H H L H L H H H L L WRITE ABORT/NOP L H H H H NOTE: Using R/W# and BYTE WRITE(s), any one or more bytes may be written. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM STATE DIAGRAM FOR ZBT SRAM DS BURST DS DS DESELECT TE RI W AD RE READ S WRITE BEGIN READ READ D DS READ BURST BURST AD RE E RIT W BURST KEY: BURST READ COMMAND DS READ WRITE BURST BEGIN WRITE WRITE WRITE BURST WRITE BURST OPERATION DESELECT New READ New WRITE BURST READ, BURST WRITE or CONTINUE DESELECT NOTE: 1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the clock (CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock (CLK). 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM TRUTH TABLE (Notes 5-10) OPERATION DESELECT Cycle DESELECT Cycle DESELECT Cycle CONTINUE DESELECT Cycle READ Cycle (Begin Burst) READ Cycle (Continue Burst) NOP/DUMMY READ (Begin Burst) DUMMY READ (Continue Burst) WRITE Cycle (Begin Burst) WRITE Cycle (Continue Burst) NOP/WRITE ABORT (Begin Burst) WRITE ABORT (Continue Burst) IGNORE CLOCK EDGE (Stall) SNOOZE MODE ADDRESS USED CE# CE2# CE2 ZZ None H X X L None X H X L None X X L L None X X X L External L L H L ADV/ LD# R/W# BWx OE# CKE# CLK DQ NOTES L X X X L LH High-Z L X X X L LH High-Z L X X X L LH High-Z H X X X L LH High-Z 1 L H X L L LH Q Next X X X L H X X L L LH Q 1, 11 External L L H L L H X H L LH High-Z 2 Next X X X L H X X H L LH High-Z External L L H L L L L X L LH D 1, 2, 11 3 Next X X X L H X L X L LH D None L L H L L L H X L LH High-Z Next X X X L H X H X L LH High-Z Current X X X L X X X X H LH - None X X X H X X X X X X High-Z 1, 3, 11 2, 3 1, 2, 3, 11 4 NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle is executed first. 2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a WRITE command is given, but no operation is performed. 3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. Some users may use OE# when the bus turn-on and turn-off times do not meet their requirements. 4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE CLOCK EDGE cycle. 5. X means "Don't Care." H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#, BWc# and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW. 6. BWa# enables WRITEs to Byte "a" (DQa's); BWb# enables WRITEs to Byte "b" (DQb's); BWc# enables WRITEs to Byte "c" (DQc's); BWd# enables WRITEs to Byte "d" (DQd's). 7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 8. Wait states are inserted by setting CKE# HIGH. 9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up. 10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth burst cycle. 11. The address counter is incremented for all CONTINUE BURST cycles. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See Micron Technical Note TN-05-14 for more information. Voltage on VDD Supply Relative to VSS ................................ -0.5V to +4.6V Voltage on VDDQ Supply Relative to VSS ................................... -0.5V to VDD VIN ........................................... -0.5V to VDDQ + 0.5V Storage Temperature (plastic) ............ -55C to +150C Junction Temperature** ................................... +150C Short Circuit Output Current ........................... 100mA 3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0C TA +70C; VDD, VDDQ = 3.3V 0.165 unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage CONDITIONS SYMBOL VIH MIN 2.0 MAX VDD + 0.3 UNITS V NOTES 1, 2 Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current DQ pins VIH VIL ILI ILO 2.0 -0.3 -1.0 VDD + 0.3 0.8 1.0 V V A 1, 2 1, 2 3 -1.0 1.0 A VOH VOL 2.4 0.4 V V 1, 4 1, 4 VDD VDDQ 3.135 3.135 3.465 3.465 V V 1 1, 5 Output High Voltage Output Low Voltage 0V VIN VDD Output(s) disabled, 0V VIN VDD IOH = -4.0mA IOL = 8.0mA Supply Voltage Isolated Output Buffer Supply NOTE: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH +4.6V for t tKHKH/2 for I 20mA Undershoot: VIL -0.7V for t tKHKH/2 for I 20mA Power-up: VIH +3.465V and VDD 3.135V for t 200ms 3. MODE pin has an internal pull-up, and input leakage = 10A. 4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 5. VDDQ should never exceed VDD. VDD and VDDQ can be externally wired together to the same power supply for 3.3V I/O operation. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM 2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0C TA +70C; VDD = +3.3V 0.165V; VDDQ = +2.5V +0.4V/-0.125V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current CONDITIONS Data bus (DQx) Inputs SYMBOL VIHQ VIH MIN 1.7 1.7 MAX UNITS VDDQ + 0.3 V VDD + 0.3 V NOTES 1, 2 1, 2 VIL ILI ILO -0.3 -1.0 -1.0 0.7 1.0 1.0 V A A 1, 2 3 Output High Voltage 0V VIN VDD Output(s) disabled, 0V VIN VDDQ (DQx) IOH = -2.0mA VOH 1.7 - V 1 Output Low Voltage IOH = -1.0mA IOL = 2.0mA VOH VOL 2.0 - - 0.7 V V 1 1 IOL = 1.0mA VOL VDD VDDQ - 3.135 0.4 3.465 V V 1 1 2.375 2.9 V 1 CONDITIONS SYMBOL TYP MAX UNITS NOTES TA = 25C; f = 1 MHz VDD = 3.3V CI CO CA CCK 3 4 3 4 5 3.5 pF pF pF 4 4 4 3 3.5 pF 4 Supply Voltage Isolated Output Buffer Supply TQFP CAPACITANCE DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance BGA CAPACITANCE DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS NOTES TA = 25C; f = 1 MHz CI 4 7 pF 4 VDD = 3.3V CO 4.5 5.5 pF 4 Address Capacitance CA 4 7 pF 4 Clock Capacitance CCK 4.5 5.5 pF 4 Address/Control Input Capacitance Input/Output Capacitance (DQ) NOTE: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH +4.6V for t tKHKH/2 for I 20mA Undershoot: VIL -0.7V for t tKHKH/2 for I 20mA Power-up: VIH +3.465V and VDD 3.135V for t 200ms 3. MODE pin has an internal pull-up, and input leakage = 10A. 4. This parameter is sampled. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (Note 1) (0C TA +70C; VDD = +3.3V 0.165V unless otherwise noted) MAX DESCRIPTION CONDITIONS SYMBOL TYP -6 -7.5 -10 Power Supply Current: Operating Device selected; All inputs VIL or VIH; Cycle time tKC (MIN); VDD = MAX; Outputs open IDD 200 500 400 300 mA 2, 3, 4 Power Supply Current: Idle Device selected; VDD = MAX; CKE# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC (MIN) IDD1 10 25 25 20 mA 2, 3, 4 CMOS Standby Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDD - 0.2; All inputs static; CLK frequency = 0 ISB2 0.5 10 10 10 mA 3, 4 Device deselected; VDD = MAX; All inputs VIL or VIH; All inputs static; CLK frequency = 0 ISB3 6 25 25 25 mA 3, 4 Device deselected; VDD = MAX; ADV/LD# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC (MIN) ISB4 45 120 75 60 mA 3, 4 ZZ VIH ISB2Z 0.5 10 10 10 mA 4 TTL Standby Clock Running SNOOZE MODE UNITS NOTES TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Top of Case) CONDITIONS SYMBOL TYP UNITS NOTES Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. JA 46 C/W 5 JC 2.8 C/W 5 BGA THERMAL RESISTANCE DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) CONDITIONS SYMBOL TYP Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. JA 40 C/W 5 JC 9 C/W 5 JB 17 C/W 5 Junction to Pins (Bottom) UNITS NOTES NOTE: 1. VDDQ = +3.3V 0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O configuration. 2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 3. "Device deselected" means device is in a deselected cycle as defined in the truth table. "Device selected" means device is active (not in deselected mode). 4. Typical values are measured at 3.3V, 25C and 10ns cycle time. 5. This parameter is sampled. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM AC ELECTRICAL CHARACTERISTICS (Notes 6, 8, 9) (0C TA +70C; VDD = +3.3V 0.165V; original ZBT mode, MS# = HIGH) -6 DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE# to output valid OE# to output in Low-Z OE# to output in High-Z Setup Times Address Clock enable (CKE#) Control signals Data-in Hold Times Address Clock enable (CKE#) Control signals Data-in SYMBOL MIN tKHKH 6.0 fKF tKHKL tKLKH tKHQX1 tKHQZ 0 tGHQZ tAVKH tEVKH tCVKH tDVKH tKHAX tKHEX tKHCX tKHDX 100 3.2 3.2 4.2 1.5 1.5 1.5 3.5 4.2 0 3.5 MAX 10 2.0 2.0 3.5 3.5 MIN 133 3.5 1.5 1.5 1.5 -10 MAX 7.5 1.7 1.7 tGLQV tGLQX MIN 166 tKHQV tKHQX -7.5 MAX 5.0 1.5 1.5 1.5 3.5 5.0 0 4.2 5.0 UNITS NOTES ns MHz ns ns 1 1 ns ns ns ns ns ns ns 2 2, 3, 4, 5 2, 3, 4, 5 6 2, 3, 4, 5 2, 3, 4, 5 1.5 1.5 1.5 1.5 1.7 1.7 1.7 1.7 2.0 2.0 2.0 2.0 ns ns ns ns 7 7 7 7 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns 7 7 7 7 NOTE: 1. 2. 3. 4. 5. 6. Measured as HIGH above VIH and LOW below VIL. Refer to Technical Note TN-55-01, "Designing with ZBT SRAMs," for a more thorough discussion on these parameters. This parameter is sampled. This parameter is measured with output loading as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O. Transition is measured 200mV from steady state voltage. OE# can be considered a "Don't Care" during WRITEs; however, controlling OE# can help fine-tune a system for turnaround timing. 7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when they are being registered into the device. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when ADV/LD# is LOW to remain enabled. 8. Test conditions as specified with output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V 0.165V) and Figure 3 for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V). 9. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM AC ELECTRICAL CHARACTERISTICS (Notes 6, 8, 9) (0C TA +70C; VDD = +3.3V 0.165V; SMART ZBT mode, MS# = LOW) -6 DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid -7.5 -10 SYMBOL MIN MAX MIN MAX MIN tKHKH 6.0 15 166 7.5 15 133 10 fKF tKHKL tKLKH 1.7 1.7 tKHQV tKHQX tKHKH tKHKH 3 Clock to output in Low-Z tKHQX1 tKHKH TBD 3 Clock to output in High-Z OE# to output valid OE# to output in Low-Z OE# to output in High-Z Setup Times Address Clock enable (CKE#) Control signals Data-in Hold Times Address Clock enable (CKE#) Control signals Data-in NOTE: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. tKHQZ 1.5 tGLQV tGLQX tEVKH tCVKH tDVKH tKHAX tKHEX tKHCX tKHDX 1.5 0 tGHQZ tAVKH 3.5 3.5 ns MHz ns ns 1 1 ns 10 - 0.2 ns 2, 10 - 0.2 ns 2, 3, 4, 5, 10 ns ns ns ns 2, 3, 4, 5 6 2, 3, 4, 5 2, 3, 4, 5 tKHKH + 1.9 3 - 0.2 tKHKH - 0.2 tKHKH 3 3 3.5 4.2 0 3.5 NOTES 3.2 3.2 TBD TBD UNITS 100 2.0 2.0 3 Clock to output invalid MAX 1.5 + 1.9 3.5 5.0 0 4.2 5.0 1.5 1.5 1.5 1.5 1.7 1.7 1.7 1.7 2.0 2.0 2.0 2.0 ns ns ns ns 7 7 7 7 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns 7 7 7 7 Measured as HIGH above VIH and LOW below VIL. Refer to Technical Note TN-55-01, "Designing with ZBT SRAMs," for a more thorough discussion on these parameters. This parameter is sampled. This parameter is measured with output loading as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O. Transition is measured 200mV from steady state voltage. OE# can be considered a "Don't Care" during WRITEs; however, controlling OE# can help fine-tune a system for turnaround timing. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when they are being registered into the device. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when ADV/LD# is LOW to remain enabled. Test conditions as specified with output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V 0.165V) and Figure 3 for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V). A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times. TBD indicates value is to be determined. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM 3.3V I/O AC TEST CONDITIONS 2.5V I/O AC TEST CONDITIONS Input pulse levels ................................... VSS to 3.3V Input pulse levels ................................... VSS to 2.5V Input rise and fall times .................................... 1ns Input rise and fall times .................................... 1ns Input timing reference levels .......................... 1.5V Input timing reference levels ........................ 1.25V Output reference levels ................................... 1.5V Output reference levels ................................. 1.25V Output load ............................. See Figures 1 and 2 Output load ............................. See Figures 3 and 4 3.3V I/O Output Load Equivalents 2.5V I/O Output Load Equivalents Q Q Z O= 50 Z O= 50 50 50 VT = 1.25V VT = 1.5V Figure 1 Figure 3 +3.3V +2.5V 317 1,667 Q Q 5pF 351 5pF 1,538 Figure 2 Figure 4 LOAD DERATING CURVES The Micron 256K x 18, 128K x 32, and 128K x 36 ZBT SRAM timing is dependent upon the capacitive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM SNOOZE MODE SNOOZE MODE is a low-current, "power-down" mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time the ZZ pin is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become disabled and all outputs go to High-Z. The ZZ pin is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic HIGH, ISB2Z is guaranteed after the time tZZI is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tRZZ, only a DESELECT or READ cycle should be given. SNOOZE MODE ELECTRICAL CHARACTERISTICS DESCRIPTION CONDITIONS SYMBOL MAX UNITS Current during SNOOZE MODE ZZ VIH ISB2Z 10 mA Current during SNOOZE MODE (P Version) ZZ VIH ISB2ZP 1 mA 0 2(tKHKH) ns 1 0 2(tKHKH) ns 1 2(tKHKH) ns 1 ns 1 tZZ ZZ active to input ignored ZZ inactive to input sampled tRZZ ZZ active to snooze current tZZI tRZZI ZZ inactive to exit snooze current MIN 0 NOTES NOTE: 1. This parameter is sampled. SNOOZE MODE WAVEFORM CLK t ZZ ZZ I t RZZ t ZZI SUPPLY I ISB2Z t RZZI ALL INPUTS (except ZZ) DESELECT or READ Only Outputs (Q) High-Z DON'T CARE 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM READ/WRITE TIMING (ORIGINAL ZBT MODE, MS# = HIGH) 1 2 3 t KHKH 4 5 6 A3 A4 7 8 9 10 A5 A6 A7 CLK tEVKH tKHEX tKHKL tKLKH CKE# tCVKH tKHCX CE# ADV/LD# R/W# BWx# A1 ADDRESS A2 tKHQV tDVKH tAVKH tKHAX DQ tKHDX D(A1) tKHQX tKHQX1 D(A2) Q(A3) D(A2+1) tGLQV tKHQZ Q(A4+1) Q(A4) D(A5) Q(A6) tGHQZ tKHQX tGLQX OE# COMMAND WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DON'T CARE DESELECT UNDEFINED READ/WRITE TIMING PARAMETERS ORIGINAL ZBT MODE, MS# = HIGH -6 SYM tKHKH fKF MIN 6.0 tKHKL 1.7 1.7 tKLKH tKHQX1 tKHQZ 1.5 tGLQV NOTE: 1. 2. 3. 4. 0 -10 MAX 100 4.2 1.5 0 -6 MAX 3.2 3.2 1.5 1.5 3.5 3.5 MIN 10 133 2.0 2.0 3.5 1.5 1.5 tGLQX MIN 7.5 166 tKHQV tKHQX -7.5 MAX 5.0 1.5 1.5 3.5 4.2 1.5 0 3.5 5.0 -7.5 MAX 4.2 -10 UNITS ns MHz SYM tGHQZ tAVKH MIN 1.5 1.7 2.0 UNITS ns ns ns ns tEVKH 1.5 1.5 1.7 1.7 2.0 2.0 ns ns ns ns ns tDVKH 1.5 0.5 0.5 1.7 0.5 0.5 2.0 0.5 0.5 ns ns ns ns ns tKHCX 0.5 0.5 0.5 0.5 0.5 0.5 ns ns tCVKH tKHAX tKHEX tKHDX MAX 3.5 MIN MIN MAX 5.0 ns For this waveform, ZZ is tied LOW. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM READ/WRITE TIMING (SMART ZBT MODE, MS# = LOW) 1 2 t KHKH 3 4 5 6 A3 A4 7 8 9 10 A5 A6 A7 CLK tEVKH tKHEX tKHKL tKLKH CKE# tCVKH tKHCX CE# ADV/LD# R/W# BWx# A1 ADDRESS A2 tKHQV tDVKH tAVKH tKHAX DQ tKHDX D(A1) tKHQX tKHQX1 D(A2) tGLQV Q(A3) D(A2+1) tKHQZ Q(A4+1) Q(A4) D(A5) Q(A6) tGHQZ tKHQX tGLQX OE# COMMAND WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DON'T CARE DESELECT UNDEFINED READ/WRITE TIMING PARAMETERS SMART ZBT MODE, MS# = LOW -6 SYM tKHKH -7.5 MIN MAX 6.0 -10 MIN MAX MIN 7.5 15 133 10 UNITS 100 SYM tGLQV tGLQX tGHQZ tKHKL 1.7 2.0 3.2 ns MHz ns tKLKH 1.7 2.0 3.2 ns tAVKH ns tEVKH fKF tKHQV 15 166 MAX tKHKH TBD 3 tKHQX TBD tKHKH tKHQX1 TBD tKHKH 3 3 tKHQZ 1.5 NOTE: 1. 2. 3. 4. 3.5 tKHKH + 1.9 3 - 0.2 tKHKH - 0.2 tKHKH 1.5 3 3 3.5 + 1.9 ns - 0.2 ns 3.5 0 MIN MAX 5.0 0 4.2 5.0 UNITS ns ns ns 2.0 2.0 ns ns 1.5 1.5 0.5 1.7 1.7 0.5 2.0 2.0 0.5 ns ns ns tKHCX 0.5 0.5 0.5 0.5 0.5 0.5 ns ns tKHDX 0.5 0.5 0.5 ns tDVKH tKHEX ns -10 MAX 4.2 1.7 1.7 tKHAX 1.5 -7.5 MIN 1.5 1.5 tCVKH - 0.2 -6 MIN MAX 3.5 0 3.5 For this waveform, ZZ is tied LOW. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM NOP, STALL AND DESELECT CYCLES 1 2 3 A1 A2 4 5 A3 A4 6 7 8 9 10 CLK CKE# CE# ADV/LD# R/W# BWx# ADDRESS A5 tKHQZ D(A1) DQ Q(A2) Q(A3) D(A4) Q(A5) tKHQX COMMAND WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) STALL NOP READ Q(A5) DESELECT DON'T CARE NOP, STALL AND DESELECT TIMING PARAMETERS (for original ZBT) -6 SYM tKHQX tKHQZ MIN 1.5 1.5 MAX 3.5 MIN 1.5 1.5 -7.5 MAX 3.5 MAX 3.5 UNDEFINED NOP, STALL AND DESELECT TIMING PARAMETERS (for SMART ZBT) -10 MIN 1.5 1.5 CONTINUE DESELECT UNITS ns ns -6 MIN MAX SYM tKHQX -7.5 MIN tKHKH TBD 3 tKHQZ 1.5 3.5 -10 MAX tKHKH - 0.2 1.5 MIN 3 3.5 MAX ns - 0.2 1.5 UNITS 3.5 ns NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a "pause." A WRITE is not performed during this cycle. 2. For this waveform, ZZ and OE# are tied LOW. 3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) PIN #1 INDEX 0.32 22.10 +0.10 -0.15 +0.06 -0.10 0.65 20.10 0.10 DETAIL A 1.50 0.10 0.10 14.00 0.10 16.00 +0.20 -0.05 0.25 GAGE PLANE 1.40 0.05 0.60 0.15 DETAIL A NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM 119-PIN BGA 22.00 0.20 19.94 0.10 Substrate material: BT resin laminate 0.60 0.10 14.00 0.10 0.90 0.10 0.15 11.94 0.10 SEATING PLANE 2.40 MAX A1 CORNER O 0.75 0.15 (dimension applies to a noncollapsed solder ball) A1 CORNER 1.27 (TYP) 7.62 1.27 (TYP) 20.32 NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. Solder ball land pad is 0.6mm. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc., and Motorola Inc. SMART ZBT and SMART Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc. 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1.p65 - Rev. 3/00 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.