FEATURES FUNCTIONAL BLOCK DIAGRAM ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard) Military temperature range: -55C to +125C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request APPLICATIONS INTERNAL CLOCK GENERATOR AD2S1210-EP TYPE II TRACKING LOOP FAULT DETECTION FAULT DETECTION OUTPUTS ADC POSITION REGISTER ENCODER EMULATION OUTPUTS VELOCITY REGISTER CONFIGURATION REGISTER DATA I/O MULTIPLEXER DATA BUS OUTPUT DATA I/O RESET Figure 1. PRODUCT HIGHLIGHTS GENERAL DESCRIPTION The AD2S1210-EP is a complete 10-bit to 16-bit resolution tracking resolver-to-digital converter, integrating an on-board programmable sinusoidal oscillator that provides sine wave excitation for resolvers. 3. The converter accepts 3.15 V p-p 27% input signals, in the range of 2 kHz to 20 kHz on the sine and cosine inputs. A Type II servo loop is employed to track the inputs and convert the input sine and cosine information into a digital representation of the input angle and velocity. The maximum tracking rate is 3125 rps. 5. Rev. A VOLTAGE REFERENCE ADC INPUTS FROM RESOLVER 2. Full details about this enhanced product, including theory of operation, registers details, and applications information, are available in the AD2S1210 data sheet, which should be concluded in conjunction with this data sheet. CRYSTAL SYNTHETIC REFERENCE 1. DC and ac servo motor control Encoder emulation Electric power steering Electric vehicles Integrated starter generators/alternators Automotive motion sensing and control REFERENCE OSCILLATOR (DAC) EXCITATION OUTPUTS REFERENCE PINS 09154-001 Complete monolithic resolver-to-digital converter 3125 rps maximum tracking rate (10-bit resolution) 2.5 arc minutes of accuracy 10-/12-/14-/16-bit resolution, set by user Parallel and serial 10-bit to 16-bit data ports Absolute position and velocity outputs System fault detection Programmable fault detection thresholds Differential inputs Incremental encoder emulation Programmable sinusoidal oscillator on board Compatible with DSP and SPI interface standards 5 V supply with 2.3 V to 5 V logic interface ENCODER EMULATION Data Sheet Variable Resolution, 10-Bit to 16-Bit R/D Converter with Reference Oscillator AD2S1210-EP 4. 6. Ratiometric tracking conversion. The Type II tracking loop provides continuous output position data without conversion delay. It also provides noise immunity and tolerance of harmonic distortion on the reference and input signals. System fault detection. A fault detection circuit can sense loss of resolver signals, out-of-range input signals, input signal mismatch, or loss of position tracking. The fault detection threshold levels can be individually programmed by the user for optimization within a particular application. signal range. The sine and cosine inputs can accept differential input voltages of 3.15 V p-p 27%. Programmable excitation frequency. Excitation frequency is easily programmable to a number of standard frequencies between 2 kHz and 20 kHz. Triple format position data. Absolute 10-bit to 16-bit angular position data is accessed via either a 16-bit parallel port or a 4-wire serial interface. Incremental encoder emulation is in standard A-quad-B format with direction output available. Digital velocity output. 10-bit to 16-bit signed digital velocity accessed via either a 16-bit parallel port or a 4-wire serial interface. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2010-2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD2S1210-EP Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Timing Specifications ...................................................................5 Enhanced Product Features ............................................................ 1 Absolute Maximum Ratings ............................................................7 Applications ....................................................................................... 1 ESD Caution...................................................................................7 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................8 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 10 Product Highlights ........................................................................... 1 Outline Dimensions ....................................................................... 14 Revision History ............................................................................... 2 Ordering Guide .......................................................................... 14 Specifications..................................................................................... 3 REVISION HISTORY 5/2018--Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Added Enhanced Product Features Section.................................. 1 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 6/2010--Revision 0: Initial Version Rev. A | Page 2 of 16 Data Sheet AD2S1210-EP SPECIFICATIONS AVDD = DVDD = 5.0 V 5%, CLKIN = 8.192 MHz 25%, EXC, EXC frequency = 10 kHz to 20 kHz (10-bit); 6 kHz to 20 kHz (12-bit); 3 kHz to 12 kHz (14-bit); 2 kHz to 10 kHz (16-bit); TA = TMIN to TMAX; unless otherwise noted.1 Table 1. Parameter SINE, COSINE INPUTS2 Voltage Amplitude Input Bias Current Input Impedance Phase Lock Range Common-Mode Rejection ANGULAR ACCURACY3 Angular Accuracy Resolution Linearity INL 10-Bit 12-Bit 14-Bit 16-Bit Linearity DNL Repeatability VELOCITY OUTPUT Velocity Accuracy4 10-Bit 12-Bit 14-Bit 16-Bit Resolution5 DYNAMNIC PERFORMANCE Bandwidth 10-Bit 12-Bit 14-Bit 16-Bit Min Typ Max Unit Conditions/Comments 2.3 3.15 4.0 V p-p 8.25 A k Degrees arc sec/V Sinusoidal waveforms, differential SIN to SINLO, COS to COSLO VIN = 4.0 V p-p, CLKIN = 8.192 MHz VIN = 4.0 V p-p, CLKIN = 8.192 MHz Sine/cosine vs. EXC output, Control Register D3 = 0 10 Hz to 1 MHz, Control Register D4 = 0 arc min Bits No missing codes 485 -44 +44 20 2.5 + 1 LSB 10, 12, 14, 16 1 2 4 16 0.9 LSB LSB LSB LSB LSB LSB 2 2 4 16 LSB LSB LSB LSB Bits 6600 5400 2800 2200 1500 1200 350 275 Hz Hz Hz Hz Hz Hz Hz Hz 3125 2500 1250 1000 625 500 156.25 125 rps 1 9, 11, 13, 15 2000 2900 900 1200 400 600 100 125 Tracking Rate 10-Bit 12-Bit 14-Bit 16-Bit Acceleration Error 10-Bit 12-Bit 14-Bit 16-Bit 7 + 1 LSB 30 30 30 30 rps rps rps arc min arc min arc min arc min Rev. A | Page 3 of 16 Zero acceleration Zero acceleration Zero acceleration Zero acceleration CLKIN = 8.192 MHz CLKIN = 8.192 MHz CLKIN = 8.192 MHz CLKIN = 8.192 MHz CLKIN = 10.24 MHz CLKIN = 8.192 MHz CLKIN = 10.24 MHz CLKIN = 8.192 MHz CLKIN = 10.24 MHz CLKIN = 8.192 MHz CLKIN = 10.24 MHz CLKIN = 8.192 MHz At 50,000 rps2, CLKIN = 8.192 MHz At 10,000 rps2, CLKIN = 8.192 MHz At 2500 rps2, CLKIN = 8.192 MHz At 125 rps2, CLKIN = 8.192 MHz AD2S1210-EP Data Sheet Parameter Settling Time 10 Step Input 10-Bit 12-Bit 14-Bit 16-Bit Settling Time 179 Step Input 10-Bit 12-Bit 14-Bit 16-Bit EXC, EXC OUTPUTS Voltage Min Center Voltage Frequency EXC/EXC DC Mismatch EXC/EXC AC Mismatch THD VOLTAGE REFERENCE REFOUT Drift PSRR CLKIN, XTALOUT6 VIL Voltage Input Low VIH Voltage Input High LOGIC INPUTS VIL Voltage Input Low VIH Voltage Input High Typ Max Unit Conditions/Comments 0.6 2.2 6.5 27.5 0.9 3.3 9.8 48 ms ms ms ms To settle to within 2 LSB, CLKIN = 8.192 MHz To settle to within 2 LSB, CLKIN = 8.192 MHz To settle to within 2 LSB, CLKIN = 8.192 MHz To settle to within 2 LSB, CLKIN = 8.192 MHz 1.5 4.75 10.5 45 2.4 6.1 15.2 68 ms ms ms ms To settle to within 2 LSB, CLKIN = 8.192 MHz To settle to within 2 LSB, CLKIN = 8.192 MHz To settle to within 2 LSB, CLKIN = 8.192 MHz To settle to within 2 LSB, CLKIN = 8.192 MHz 3.2 3.6 4.0 V p-p Load 100 A, typical differential output (EXC to EXC) = 7.2 V p-p 2.40 2 2.47 2.53 20 30 132 V kHz mV mV dB -58 2.40 IOZH High Level Three-State Leakage IOZL Low Level Three-State Leakage POWER REQUIREMENTS AVDD DVDD VDRIVE POWER SUPPLY IAVDD IDVDD IOVDD 2.53 V ppm/C dB 0.8 V V 0.8 0.7 VDRIVE = 2.7 V to 5.25 V VDRIVE = 2.3 V to 2.7 V VDRIVE = 2.7 V to 5.25 V VDRIVE = 2.3 V to 2.7 V 10 V V V V A 80 A RES0, RES1, RD, WR/FSYNC, A0, A1, and RESET pins 2.0 2.0 1.7 IIL Low Level Input Current (NonPull-Up) IIL Low Level Input Current (Pull-Up) IIH High Level Input Current LOGIC OUTPUTS VOL Voltage Output Low VOH Voltage Output High 2.47 100 -60 -10 IOUT = 100 A A 0.4 10 V V V A A 5.25 5.25 5.25 V V V 12 35 2 mA mA mA 2.4 2.0 -10 4.75 4.75 2.3 First five harmonics 1 VDRIVE = 2.3 V to 5.25 V VDRIVE = 2.7 V to 5.25 V VDRIVE = 2.3 V to 2.7 V Temperature range is as follows: -55C to +125C. The voltages SIN, SINLO, COS, and COSLO, relative to AGND, must always be between 0.15 V and AVDD - 0.2 V. 3 All specifications within the angular accuracy parameter are tested at constant velocity, that is, zero acceleration. 4 The velocity accuracy specification includes velocity offset and dynamic ripple. 5 For example, when RES0 = 0 and RES1 = 1, the position output has a resolution of 12 bits. The velocity output has a resolution of 11 bits with the MSB indicating the direction of rotation. In this example, with a CLKIN frequency of 8.192 MHz, the velocity LSB is 0.488 rps, that is, 1000 rps/(211). 6 The clock frequency of the AD2S1210-EP can be supplied with a crystal, an oscillator, or directly from a DSP/microprocessor digital output. When using a single-ended clock signal directly from the DSP/microprocessor, the XTALOUT pin should remain open circuit and the logic levels outlined under the logic inputs parameter in Table 1 apply. 2 Rev. A | Page 4 of 16 Data Sheet AD2S1210-EP TIMING SPECIFICATIONS AVDD = DVDD = 5.0 V 5%, TA = TMIN to TMAX, unless otherwise noted.1 Table 2. Parameter fCLKIN Description Frequency of clock input tCK Clock period (tCK = 1/fCLKIN) t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 A0 and A1 setup time before RD/CS low Delay CS falling edge to WR/FSYNC rising edge Address/data setup time during a write cycle Address/data hold time during a write cycle Delay WR/FSYNC rising edge to CS rising edge Delay CS rising edge to CS falling edge Delay between writing address and writing data A0 and A1 hold time after WR/FSYNC rising edge Delay between successive write cycles Delay between rising edge of WR/FSYNC and falling edge of RD Delay CS falling edge to RD falling edge Enable delay RD low to data valid in configuration mode VDRIVE = 4.5 V to 5.25 V VDRIVE = 2.7 V to 3.6 V VDRIVE = 2.3 V to 2.7 V RD rising edge to CS rising edge Disable delay RD high to data high-Z Disable delay CS high to data high-Z Delay between rising edge of RD and falling edge of WR/FSYNC SAMPLE pulse width Delay from SAMPLE before RD/CS low Hold time RD before RD low Enable delay RD/CS low to data valid VDRIVE = 4.5 V to 5.25 V VDRIVE = 2.7 V to 3.6 V VDRIVE = 2.3 V to 2.7 V RD pulse width A0 and A1 set time to data valid when RD/CS low VDRIVE = 4.5 V to 5.25 V VDRIVE = 2.7 V to 3.6 V VDRIVE = 2.3 V to 2.7 V Delay WR/FSYNC falling edge to SCLK rising edge Delay WR/FSYNC falling edge to SDO release from high-Z VDRIVE = 4.5 V to 5.25 V VDRIVE = 2.7 V to 3.6 V VDRIVE = 2.3 V to 2.7 V Delay SCLK rising edge to DBx valid VDRIVE = 4.5 V to 5.25 V VDRIVE = 2.7 V to 3.6 V VDRIVE = 2.3 V to 2.7 V SCLK high time SCLK low time SDI setup time prior to SCLK falling edge SDI hold time after SCLK falling edge t13 t14A t14B t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 Rev. A | Page 5 of 16 Limit at TMIN, TMAX 6.144 10.24 98 163 2 22 3 2 2 10 2 x tCK + 20 2 6 x tCK + 20 2 2 Unit MHz min MHz max ns min ns max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min 37 25 30 2 16 16 2 2 x tCK + 20 6 x tCK + 20 2 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min 17 21 33 6 ns min ns min ns min ns min 36 37 29 3 ns min ns min ns min ns min 16 26 29 ns min ns min ns min 24 18 32 0.4 x tSCLK 0.4 x tSCLK 3 2 ns min ns min ns min ns min ns min ns min ns min AD2S1210-EP Parameter t29 t30 t31 t32 t33 t34 fSCLK 1 2 Data Sheet Description Delay WR/FSYNC rising edge to SDO high-Z Delay from SAMPLE before WR/FSYNC falling edge Delay CS falling edge to WR/FSYNC falling edge in normal mode A0 and A1 setup time before WR/FSYNC falling edge A0 and A1 hold time after WR/FSYNC falling edge2 In normal mode, A0 = 0, A1 = 0/1 In configuration mode, A0 = 1, A1 = 1 Delay WR/FSYNC rising edge to WR/FSYNC falling edge Frequency of SCLK input VDRIVE = 4.5 V to 5.25 V VDRIVE = 2.7 V to 3.6 V VDRIVE = 2.3 V to 2.7 V Limit at TMIN, TMAX 15 6 x tCK + 20 ns 2 2 Unit ns min ns min ns min ns min 24 x tCK + 5 ns 8 x tCK + 5 ns 10 ns min ns min ns min 20 25 15 MHz MHz MHz Temperature range is as follows: -55C to +125C. A0 and A1 should remain constant for the duration of the serial readback. This may require 24 clock periods to read back the 8-bit fault information in addition to the 16 bits of position/velocity data. If the fault information is not required, A0/A1 may be released after 16 clock cycles. Rev. A | Page 6 of 16 Data Sheet AD2S1210-EP ABSOLUTE MAXIMUM RATINGS Table 3. Parameter AVDD to AGND, DGND DVDD to AGND, DGND VDRIVE to AGND, DGND AVDD to DVDD AGND to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Analog Output Voltage Swing Input Current to Any Pin Except Supplies1 Operating Temperature Range (Ambient) EP Grade Storage Temperature Range JA Thermal Impedance2 JC Thermal Impedance2 RoHS-Compliant Temperature, Soldering Reflow ESD 1 2 Rating -0.3 V to +7.0 V -0.3 V to +7.0 V -0.3 V to AVDD -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to VDRIVE + 0.3 V -0.3 V to VDRIVE + 0.3 V -0.3 V to AVDD + 0.3 V 10 mA Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION -55C to +125C -65C to +150C 54C/W 15C/W 260(-5/+0)oC 2 kV HBM Transient currents of up to 100 mA do not cause latch-up. JEDEC 2S2P standard board. Rev. A | Page 7 of 16 AD2S1210-EP Data Sheet A0 EXC EXC AGND SIN SINLO COSLO AVDD COS REFBYP REFOUT RES0 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 RES1 1 36 A1 PIN 1 CS 2 35 DOS 34 LOT RD 3 WR/FSYNC 4 33 RESET DGND 5 32 DIR AD2S1210-EP DVDD 6 31 NM TOP VIEW (Not to Scale) CLKIN 7 30 B XTALOUT 8 29 A SOE 9 28 DB0 SAMPLE 10 27 DB1 DB15/SDO 11 26 DB2 DB14/SDI 12 25 DB3 09154-002 DB4 DB5 DB6 DB7 DB8 DGND VDRIVE DB9 DB10 DB11 DB12 DB13/SCLK 13 14 15 16 17 18 19 20 21 22 23 24 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic RES1 2 3 CS RD 4 WR/FSYNC 5, 19 DGND 6 DVDD 7 CLKIN 8 XTALOUT 9 SOE 10 SAMPLE 11 DB15/SDO 12 DB14/SDI Description Resolution Select 1. Logic input. RES1 in conjunction with RES0 allows the resolution of the AD2S1210-EP to be programmed. Chip Select. Active low logic input. The device is enabled when CS is held low. Edge-Triggered Logic Input. When the SOE pin is high, this pin acts as a frame synchronization signal and output enable for the parallel data outputs, DB15 to DB0. The output buffer is enabled when CS and RD are held low. When the SOE pin is low, the RD pin should be held high. Edge-Triggered Logic Input. When the SOE pin is high, this pin acts as a frame synchronization signal and input enable for the parallel data inputs, DB7 to DB0. The input buffer is enabled when CS and WR/FSYNC are held low. When the SOE pin is low, the WR/FSYNC pin acts as a frame synchronization signal and enable for the serial data bus. Digital Ground. These pins are ground reference points for digital circuitry on the AD2S1210-EP. Refer all digital input signals to this DGND voltage. Both of these pins can be connected to the AGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Digital Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD2S1210-EP. The AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Clock Input. A crystal or oscillator can be used at the CLKIN and XTALOUT pins to supply the required clock frequency of the AD2S1210-EP. Alternatively, a single-ended clock can be applied to the CLKIN pin. The input frequency of the AD2S1210-EP is specified from 6.144 MHz to 10.24 MHz. Crystal Output. When using a crystal or oscillator to supply the clock frequency to the AD2S1210-EP, apply the crystal across the CLKIN and XTALOUT pins. When using a single-ended clock source, the XTALOUT pin should be considered a no connect pin. Serial Output Enable. Logic input. This pin enables either the parallel or serial interface. The serial interface is selected by holding the SOE pin low, and the parallel interface is selected by holding the SOE pin high. Sample Result. Logic input. Data is transferred from the position and velocity integrators to the position and velocity registers after a high-to-low transition on the SAMPLE signal. The fault register is also updated after a high-to-low transition on the SAMPLE signal. Data Bit 15/Serial Data Output Bus. When the SOE pin is high, this pin acts as DB15, a three-state data output pin controlled by CS and RD. When the SOE pin is low, this pin acts as SDO, the serial data output bus controlled by CS and WR/FSYNC. The bits are clocked out on the rising edge of SCLK. Data Bit 14/Serial Data Input Bus. When the SOE pin is high, this pin acts as DB14, a three-state data output pin controlled by CS and RD. When the SOE pin is low, this pin acts as SDI, the serial data input bus controlled by CS and WR/FSYNC. The bits are clocked in on the falling edge of SCLK. Rev. A | Page 8 of 16 Data Sheet Pin No. 13 Mnemonic DB13/SCLK 14 to 17 18 DB12 to DB9 VDRIVE 20 21 to 28 29 DB8 DB7 to DB0 30 B 31 NM 32 DIR 33 RESET 34 35 LOT DOS 36 37 38 A1 A0 EXC 39 EXC 40 AGND 41 42 43 SIN SINLO AVDD 44 45 46 47 48 COSLO COS REFBYP REFOUT RES0 A AD2S1210-EP Description Data Bit 13/Serial Clock. In parallel mode, this pin acts as DB13, a three-state data output pin controlled by CS and RD. In serial mode, this pin acts as the serial clock input. Data Bit 12 to Data Bit 9. Three-state data output pins controlled by CS and RD. Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. Decouple this pin to DGND. The voltage range on this pin is 2.3 V to 5.25 V and may be different from the voltage range at AVDD and DVDD but should never exceed either by more than 0.3 V. Data Bit 8. Three-state data output pin controlled by CS and RD. Data Bit 7 to Data Bit 0. Three-state data input/output pins controlled by CS, RD, and WR/FSYNC. Incremental Encoder Emulation Output A. Logic output. This output is free running and is valid if the resolver format input signals applied to the converter are valid. Incremental Encoder Emulation Output B. Logic output. This output is free running and is valid if the resolver format input signals applied to the converter are valid. North Marker Incremental Encoder Emulation Output. Logic output. This output is free running and is valid if the resolver format input signals applied to the converter are valid. Direction. Logic output. This output is used in conjunction with the incremental encoder emulation outputs. The DIR output indicates the direction of the input rotation and is high for increasing angular rotation. Reset. Logic input. The AD2S1210-EP requires an external reset signal to hold the RESET input low until VDD is within the specified operating range of 4.75 V to 5.25 V. Loss of Tracking. Logic output. Loss of tracking (LOT) is indicated by a logic low on the LOT pin and is not latched. Degradation of Signal. Logic output. Degradation of signal (DOS) is detected when either resolver input (sine or cosine) exceeds the specified DOS sine/cosine threshold or when an amplitude mismatch occurs between the sine and cosine input voltages. DOS is indicated by a logic low on the DOS pin. Mode Select 1. Logic input. A1 in conjunction with A0 allows the mode of the AD2S1210-EP to be selected. Mode Select 0. Logic input. A0 in conjunction with A1 allows the mode of the AD2S1210-EP to be selected. Excitation Frequency. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the excitation frequency register. Excitation Frequency Complement. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the excitation frequency register. Analog Ground. This pin is the ground reference points for analog circuitry on the AD2S1210-EP. Refer all analog input signals and any external reference signal to this AGND voltage. Connect the AGND pin to the AGND plane of a system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Positive Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p. Negative Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p. Analog Supply Voltage, 4.75 V to 5.25 V. This pin is the supply voltage for all analog circuitry on the AD2S1210-EP. The AVDD and DVDD voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Negative Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p. Positive Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p. Reference Bypass. Connect reference decoupling capacitors at this pin. Typical recommended values are 10 F and 0.01 F. Voltage Reference Output. Resolution Select 0. Logic input. RES0 in conjunction with RES1 allows the resolution of the AD2S1210-EP to be programmed. Rev. A | Page 9 of 16 AD2S1210-EP Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, AVDD = DVDD = VDRIVE = 5 V, SIN/SINLO = 3.15 V p-p, COS/COSLO = 3.15 V p-p, CLKIN = 8.192 MHz, unless otherwise noted. 5000 9000 4500 8000 4000 7000 HITS PER CODE HITS PER CODE 3500 6000 5000 4000 3000 2500 2000 1500 3000 1000 2000 09154-003 8198 8199 8196 8197 8194 8195 8193 8192 8191 8190 8189 8188 8186 8187 8185 8184 8183 8182 8181 CODE CODE Figure 3. Typical 16-Bit Angular Accuracy Histogram Of Codes, 10,000 Samples 09154-006 0 1000 8178 8179 8180 8181 8182 8183 8184 8185 8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199 8200 8201 500 Figure 6. Typical 12-Bit Angular Accuracy Histogram of Codes, 10,000 Samples, Hysteresis Disabled 8000 12000 7000 10000 8000 HITS PER CODE HITS PER CODE 6000 5000 4000 3000 6000 4000 2000 CODE 0 510 09154-004 8199 8198 8197 8196 8195 8194 8193 8192 8191 8190 8189 8188 8187 8186 8185 8184 8183 8182 8181 0 Figure 4. Typical 14-Bit Angular Accuracy Histogram of Codes, 10,000 Samples, Hysteresis Disabled 511 512 CODES 513 514 09154-017 2000 1000 Figure 7. Typical 12-Bit Angular Accuracy Histogram of Codes, 10,000 Samples, Hysteresis Enabled 12000 1400 10000 1200 HITS PER CODE 6000 4000 800 600 400 2000 200 2047 2048 CODES 2049 2050 0 CODE Figure 5. Typical 14-Bit Angular Accuracy Histogram of Codes, 10,000 Samples, Hysteresis Enabled Figure 8. Typical 10-Bit Angular Accuracy Histogram of Codes, 10,000 Samples, Hysteresis Disabled Rev. A | Page 10 of 16 09154-018 2046 8176 8177 8178 8179 8180 8181 8182 8183 8184 8185 8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199 8200 0 09154-005 HITS PER CODE 1000 8000 Data Sheet AD2S1210-EP 20 12000 18 16 14 8000 ANGLE (Degrees) HITS PER CODE 10000 6000 4000 12 10 8 6 4 2000 128 CODES 129 130 0 0 20 18 18 16 16 14 14 ANGLE (Degrees) 20 12 10 8 4 2 2 8 12 16 20 24 TIME (ms) 28 32 36 40 0 225 16 200 14 175 ANGLE (Degrees) 18 12 10 8 50 2 25 0 5 6 TIME (ms) 7 8 0.75 1.00 1.25 1.50 TIME (ms) 1.75 2.00 2.25 2.50 100 75 4 0.50 125 4 3 0.25 150 6 9 10 0 09154-009 ANGLE (Degrees) 250 2 5.00 Figure 13. Typical 10-Bit 10 Step Response 20 1 4.50 0 Figure 10. Typical 16-Bit 10 Step Response 0 4.00 8 4 4 3.50 10 6 0 1.50 2.00 2.50 3.00 TIME (ms) 12 6 0 1.00 Figure 12. Typical 12-Bit 10 Step Response 09154-010 ANGLE (Degrees) Figure 9. Typical 10-Bit Angular Accuracy Histogram of Codes, 10,000 Samples, Hysteresis Enabled 0.50 09154-007 127 0 Figure 11. Typical 14-Bit 10 Step Response 8 16 24 32 40 48 TIME (ms) 56 64 Figure 14. Typical 16-Bit 179 Step Response Rev. A | Page 11 of 16 72 80 09154-014 126 09154-038 0 09154-008 2 AD2S1210-EP Data Sheet 5 0 16 -5 14 -10 MAGNITUDE (dB) 18 10 8 14-BIT -15 -25 -30 4 -35 2 -40 0 0.25 0.50 0.75 1.00 1.25 1.50 TIME (ms) 1.75 2.00 2.25 2.50 12-BIT -20 6 0 10-BIT 16-BIT -45 1 Figure 15. Typical 14-Bit 179 Step Response 10 100 1k FREQUENCY (Hz) 10k 100k 09154-015 12 09154-013 ANGLE (Degrees) 20 Figure 18. Typical System Magnitude Response 250 0 225 -20 -40 175 -60 150 -80 125 100 -120 -140 50 -160 25 -180 0 1 2 3 4 5 6 TIME (ms) 7 8 9 10 16-BIT -200 1 10 100 1k FREQUENCY (Hz) 10k 100k Figure 19. Typical System Phase Response Figure 16. Typical 12-Bit 179 Step Response 10 225 9 200 8 TRACKING ERROR (Degrees) 250 175 150 125 100 75 50 7 6 5 4 3 2 0 0 1 2 3 4 TIME (ms) 5 0 0 Figure 17. Typical 10-Bit 179 Step Response 500 1000 1500 ACCELERATION (rps2) 2000 2500 Figure 20. Typical 16-Bit Tracking Error vs. Acceleration Rev. A | Page 12 of 16 09154-022 1 25 09154-011 ANGLE (Degrees) 12-BIT -100 75 0 14-BIT 09154-016 PHASE (dB) 200 09154-012 ANGLE (Degrees) 10-BIT AD2S1210-EP 10 10 9 9 8 8 TRACKING ERROR (Degrees) 7 6 5 4 3 2 1 6 5 4 3 2 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 ACCELERATION (rps2) 09154-021 1 0 Figure 21. Typical 14-Bit Tracking Error vs. Acceleration 9 8 7 6 5 4 3 2 0 20000 60000 100000 ACCELERATION (rps2) 140000 180000 09154-020 1 0 0 0 200000 400000 600000 800000 ACCELERATION (rps2) 1000000 Figure 23. Typical 10-Bit Tracking Error vs. Acceleration 10 TRACKING ERROR (Degrees) 7 Figure 22. Typical 12-Bit Tracking Error vs. Acceleration Rev. A | Page 13 of 16 09154-019 TRACKING ERROR (Degrees) Data Sheet AD2S1210-EP Data Sheet OUTLINE DIMENSIONS 9.20 9.00 SQ 8.80 SIDE VIEW 1.60 MAX 0.75 0.60 0.45 TOP VIEW 48 37 1 1.00 REF 36 SEATING PLANE 7.20 7.00 SQ 6.80 0.20 0.15 0.09 0.15 0.10 0.05 7 0 0.08 MAX COPLANARITY 12 25 24 13 VIEW A 0.50 BSC VIEW A 0.27 0.22 0.17 PKG-005430 ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC 01-17-2018-A 1.45 1.40 1.35 Figure 24. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model1 AD2S1210SST-EP-RL7 AD2S1210SSTZ-EPRL7 1 Temperature Range -55C to +125C -55C to +125C Package Description 48-Lead LQFP 48-Lead LQFP Z = RoHS Compliant Part Rev. A | Page 14 of 16 Package Option ST-48 ST-48 Data Sheet AD2S1210-EP NOTES Rev. A | Page 15 of 16 AD2S1210-EP Data Sheet NOTES (c)2010-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09154-0-5/18(A) Rev. A | Page 16 of 16