Variable Resolution, 10-Bit to 16-Bit R/D
Converter with Reference Oscillator
Data Sheet AD2S1210-EP
Rev. A Document Feedback
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FEATURES
Complete monolithic resolver-to-digital converter
3125 rps maximum tracking rate (10-bit resolution)
±2.5 arc minutes of accuracy
10-/12-/14-/16-bit resolution, set by user
Parallel and serial 10-bit to 16-bit data ports
Absolute position and velocity outputs
System fault detection
Programmable fault detection thresholds
Differential inputs
Incremental encoder emulation
Programmable sinusoidal oscillator on board
Compatible with DSP and SPI interface standards
5 V supply with 2.3 V to 5 V logic interface
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC standard)
Military temperature range: −55°C to +125°C
Controlled manufacturing baseline
1 assembly/test site
1 fabrication site
Product change notification
Qualification data available on request
APPLICATIONS
DC and ac servo motor control
Encoder emulation
Electric power steering
Electric vehicles
Integrated starter generators/alternators
Automotive motion sensing and control
GENERAL DESCRIPTION
The AD2S1210-EP is a complete 10-bit to 16-bit resolution
tracking resolver-to-digital converter, integrating an on-board
programmable sinusoidal oscillator that provides sine wave
excitation for resolvers.
The converter accepts 3.15 V p-p ± 27% input signals, in the range
of 2 kHz to 20 kHz on the sine and cosine inputs. A Type II
servo loop is employed to track the inputs and convert the input
sine and cosine information into a digital representation of the
input angle and velocity. The maximum tracking rate is 3125 rps.
Full details about this enhanced product, including theory of
operation, registers details, and applications information, are
available in the AD2S1210 data sheet, which should be
concluded in conjunction with this data sheet.
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
OSCILLATOR
(DAC)
EXCITATION
OUTPUTS
AD2S1210-EP
ENCODER
EMULATION
SYNTHETIC
REFERENCE
RESET
DATA I/O
INPUTS
FROM
RESOLVER
ENCODER
EMULATION
OUTPUTS
VOLTAGE
REFERENCE
REFERENCE
PINS
INTERNAL
CLOCK
GENERATOR
CRYSTAL
TYPE II
TRACKING LOO P FAULT
DETECTION FAULT
DETECTION
OUTPUTS
POSITION
REGISTER
ADC
ADC
CONFIGURATION
REGISTER
MULTIPLEXER
DATA BUS OUTPUT
DATA I/O
VELOCITY
REGISTER
0
9154-001
Figure 1.
PRODUCT HIGHLIGHTS
1. Ratiometric tracking conversion. The Type II tracking loop
provides continuous output position data without
conversion delay. It also provides noise immunity and
tolerance of harmonic distortion on the reference and
input signals.
2. System fault detection. A fault detection circuit can sense
loss of resolver signals, out-of-range input signals, input
signal mismatch, or loss of position tracking. The fault
detection threshold levels can be individually programmed
by the user for optimization within a particular application.
3. signal range. The sine and cosine inputs can accept
differential input voltages of 3.15 V p-p ± 27%.
4. Programmable excitation frequency. Excitation frequency
is easily programmable to a number of standard frequencies
between 2 kHz and 20 kHz.
5. Triple format position data. Absolute 10-bit to 16-bit angular
position data is accessed via either a 16-bit parallel port or a
4-wire serial interface. Incremental encoder emulation is in
standard A-quad-B format with direction output available.
6. Digital velocity output. 10-bit to 16-bit signed digital
velocity accessed via either a 16-bit parallel port or a 4-wire
serial interface.
AD2S1210-EP Data Sheet
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Enhanced Product Features ............................................................ 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications ...................................................................5
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configuration and Function Descriptions ..............................8
Typical Performance Characteristics ........................................... 10
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
5/2018—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Added Enhanced Product Features Section .................................. 1
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
6/2010—Revision 0: Initial Version
Data Sheet AD2S1210-EP
Rev. A | Page 3 of 16
SPECIFICATIONS
AVDD = DVDD = 5.0 V ± 5%, CLKIN = 8.192 MHz ± 25%, EXC, EXC frequency = 10 kHz to 20 kHz (10-bit); 6 kHz to 20 kHz (12-bit);
3 kHz to 12 kHz (14-bit); 2 kHz to 10 kHz (16-bit); TA = TMIN to TMAX; unless otherwise noted.1
Table 1.
Parameter Min Typ Max Unit Conditions/Comments
SINE, COSINE INPUTS2
Voltage Amplitude 2.3 3.15 4.0 V p-p Sinusoidal waveforms, differential SIN to SINLO,
COS to COSLO
Input Bias Current 8.25 μA VIN = 4.0 V p-p, CLKIN = 8.192 MHz
Input Impedance 485 kΩ VIN = 4.0 V p-p, CLKIN = 8.192 MHz
Phase Lock Range −44 +44 Degrees Sine/cosine vs. EXC output, Control Register D3 = 0
Common-Mode Rejection ±20 arc sec/V 10 Hz to 1 MHz, Control Register D4 = 0
ANGULAR ACCURACY3
Angular Accuracy ±2.5 + 1 LSB ±7 + 1 LSB arc min
Resolution 10, 12, 14, 16 Bits No missing codes
Linearity INL
10-Bit ±1 LSB
12-Bit ±2 LSB
14-Bit ±4 LSB
16-Bit ±16 LSB
Linearity DNL ±0.9 LSB
Repeatability ±1 LSB
VELOCITY OUTPUT
Velocity Accuracy4
10-Bit ±2 LSB Zero acceleration
12-Bit ±2 LSB Zero acceleration
14-Bit ±4 LSB Zero acceleration
16-Bit ±16 LSB Zero acceleration
Resolution5 9, 11, 13, 15 Bits
DYNAMNIC PERFORMANCE
Bandwidth
10-Bit 2000 6600 Hz
2900 5400 Hz CLKIN = 8.192 MHz
12-Bit 900 2800 Hz
1200 2200 Hz CLKIN = 8.192 MHz
14-Bit 400 1500 Hz
600 1200 Hz CLKIN = 8.192 MHz
16-Bit 100 350 Hz
125 275 Hz CLKIN = 8.192 MHz
Tracking Rate
10-Bit 3125 rps CLKIN = 10.24 MHz
2500 CLKIN = 8.192 MHz
12-Bit 1250 rps CLKIN = 10.24 MHz
1000 CLKIN = 8.192 MHz
14-Bit 625 rps CLKIN = 10.24 MHz
500 CLKIN = 8.192 MHz
16-Bit 156.25 rps CLKIN = 10.24 MHz
125 CLKIN = 8.192 MHz
Acceleration Error
10-Bit 30 arc min At 50,000 rps2, CLKIN = 8.192 MHz
12-Bit 30 arc min At 10,000 rps2, CLKIN = 8.192 MHz
14-Bit 30 arc min At 2500 rps2, CLKIN = 8.192 MHz
16-Bit 30 arc min At 125 rps2, CLKIN = 8.192 MHz
AD2S1210-EP Data Sheet
Rev. A | Page 4 of 16
Parameter Min Typ Max Unit Conditions/Comments
Settling Time 10° Step Input
10-Bit 0.6 0.9 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz
12-Bit 2.2 3.3 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz
14-Bit 6.5 9.8 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz
16-Bit 27.5 48 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz
Settling Time 179° Step Input
10-Bit 1.5 2.4 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz
12-Bit 4.75 6.1 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz
14-Bit 10.5 15.2 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz
16-Bit 45 68 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz
EXC, EXC OUTPUTS
Voltage 3.2 3.6 4.0 V p-p Load ±100 μA, typical differential output
(EXC to EXC) = 7.2 V p-p
Center Voltage 2.40 2.47 2.53 V
Frequency 2 20 kHz
EXC/EXC DC Mismatch 30 mV
EXC/EXC AC Mismatch 132 mV
THD −58 dB First five harmonics
VOLTAGE REFERENCE
REFOUT 2.40 2.47 2.53 V ±IOUT = 100 μA
Drift 100 ppm/°C
PSRR −60 dB
CLKIN, XTALOUT6
VIL Voltage Input Low 0.8 V
VIH Voltage Input High 2.0 V
LOGIC INPUTS
VIL Voltage Input Low 0.8 V VDRIVE = 2.7 V to 5.25 V
0.7 V VDRIVE = 2.3 V to 2.7 V
VIH Voltage Input High 2.0 V VDRIVE = 2.7 V to 5.25 V
1.7 V VDRIVE = 2.3 V to 2.7 V
IIL Low Level Input Current (Non-
Pull-Up)
10 μA
IIL Low Level Input Current (Pull-Up) 80 μA RES0, RES1, RD, WR/FSYNC, A0, A1, and RESET pins
IIH High Level Input Current −10 μA
LOGIC OUTPUTS
VOL Voltage Output Low 0.4 V VDRIVE = 2.3 V to 5.25 V
VOH Voltage Output High 2.4 V VDRIVE = 2.7 V to 5.25 V
2.0 V VDRIVE = 2.3 V to 2.7 V
IOZH High Level Three-State Leakage −10 μA
IOZL Low Level Three-State Leakage 10 μA
POWER REQUIREMENTS
AVDD 4.75 5.25 V
DVDD 4.75 5.25 V
VDRIVE 2.3 5.25 V
POWER SUPPLY
IAVDD 12 mA
IDVDD 35 mA
IOVDD 2 mA
1 Temperature range is as follows: −55°C to +125°C.
2 The voltages SIN, SINLO, COS, and COSLO, relative to AGND, must always be between 0.15 V and AVDD − 0.2 V.
3 All specifications within the angular accuracy parameter are tested at constant velocity, that is, zero acceleration.
4 The velocity accuracy specification includes velocity offset and dynamic ripple.
5 For example, when RES0 = 0 and RES1 = 1, the position output has a resolution of 12 bits. The velocity output has a resolution of 11 bits with the MSB indicating the
direction of rotation. In this example, with a CLKIN frequency of 8.192 MHz, the velocity LSB is 0.488 rps, that is, 1000 rps/(211).
6 The clock frequency of the AD2S1210-EP can be supplied with a crystal, an oscillator, or directly from a DSP/microprocessor digital output. When using a single-ended
clock signal directly from the DSP/microprocessor, the XTALOUT pin should remain open circuit and the logic levels outlined under the logic inputs parameter in Table 1 apply.
Data Sheet AD2S1210-EP
Rev. A | Page 5 of 16
TIMING SPECIFICATIONS
AVDD = DVDD = 5.0 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter Description Limit at TMIN, TMAX Unit
fCLKIN Frequency of clock input 6.144 MHz min
10.24 MHz max
tCK Clock period (tCK = 1/fCLKIN) 98 ns min
163 ns max
t1 A0 and A1 setup time before RD/CS low 2 ns min
t2 Delay CS falling edge to WR/FSYNC rising edge 22 ns min
t3 Address/data setup time during a write cycle 3 ns min
t4 Address/data hold time during a write cycle 2 ns min
t5 Delay WR/FSYNC rising edge to CS rising edge 2 ns min
t6 Delay CS rising edge to CS falling edge 10 ns min
t7 Delay between writing address and writing data 2 × tCK + 20 ns min
t8 A0 and A1 hold time after WR/FSYNC rising edge 2 ns min
t9 Delay between successive write cycles 6 × tCK + 20 ns min
t10 Delay between rising edge of WR/FSYNC and falling edge of RD 2 ns min
t11 Delay CS falling edge to RD falling edge 2 ns min
t12 Enable delay RD low to data valid in configuration mode
V
DRIVE = 4.5 V to 5.25 V 37 ns min
V
DRIVE = 2.7 V to 3.6 V 25 ns min
V
DRIVE = 2.3 V to 2.7 V 30 ns min
t13 RD rising edge to CS rising edge 2 ns min
t14A Disable delay RD high to data high-Z 16 ns min
t14B Disable delay CS high to data high-Z 16 ns min
t15 Delay between rising edge of RD and falling edge of WR/FSYNC 2 ns min
t16 SAMPLE pulse width 2 × tCK + 20 ns min
t17 Delay from SAMPLE before RD/CS low 6 × tCK + 20 ns min
t18 Hold time RD before RD low 2 ns min
t19 Enable delay RD/CS low to data valid
V
DRIVE = 4.5 V to 5.25 V 17 ns min
V
DRIVE = 2.7 V to 3.6 V 21 ns min
V
DRIVE = 2.3 V to 2.7 V 33 ns min
t20 RD pulse width 6 ns min
t21 A0 and A1 set time to data valid when RD/CS low
V
DRIVE = 4.5 V to 5.25 V 36 ns min
V
DRIVE = 2.7 V to 3.6 V 37 ns min
V
DRIVE = 2.3 V to 2.7 V 29 ns min
t22 Delay WR/FSYNC falling edge to SCLK rising edge 3 ns min
t23 Delay WR/FSYNC falling edge to SDO release from high-Z
V
DRIVE = 4.5 V to 5.25 V 16 ns min
V
DRIVE = 2.7 V to 3.6 V 26 ns min
V
DRIVE = 2.3 V to 2.7 V 29 ns min
t24 Delay SCLK rising edge to DBx valid
V
DRIVE = 4.5 V to 5.25 V 24 ns min
V
DRIVE = 2.7 V to 3.6 V 18 ns min
V
DRIVE = 2.3 V to 2.7 V 32 ns min
t25 SCLK high time 0.4 × tSCLK ns min
t26 SCLK low time 0.4 × tSCLK ns min
t27 SDI setup time prior to SCLK falling edge 3 ns min
t28 SDI hold time after SCLK falling edge 2 ns min
AD2S1210-EP Data Sheet
Rev. A | Page 6 of 16
Parameter Description Limit at TMIN, TMAX Unit
t29 Delay WR/FSYNC rising edge to SDO high-Z 15 ns min
t30 Delay from SAMPLE before WR/FSYNC falling edge 6 × tCK + 20 ns ns min
t31 Delay CS falling edge to WR/FSYNC falling edge in normal mode 2 ns min
t32 A0 and A1 setup time before WR/FSYNC falling edge 2 ns min
t33 A0 and A1 hold time after WR/FSYNC falling edge2
In normal mode, A0 = 0, A1 = 0/1 24 × tCK + 5 ns ns min
In configuration mode, A0 = 1, A1 = 1 8 × tCK + 5 ns ns min
t34 Delay WR/FSYNC rising edge to WR/FSYNC falling edge 10 ns min
fSCLK Frequency of SCLK input
V
DRIVE = 4.5 V to 5.25 V 20 MHz
V
DRIVE = 2.7 V to 3.6 V 25 MHz
V
DRIVE = 2.3 V to 2.7 V 15 MHz
1 Temperature range is as follows: −55°C to +125°C.
2 A0 and A1 should remain constant for the duration of the serial readback. This may require 24 clock periods to read back the 8-bit fault information in addition to the
16 bits of position/velocity data. If the fault information is not required, A0/A1 may be released after 16 clock cycles.
Data Sheet AD2S1210-EP
Rev. A | Page 7 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
AVDD to AGND, DGND −0.3 V to +7.0 V
DVDD to AGND, DGND −0.3 V to +7.0 V
VDRIVE to AGND, DGND −0.3 V to AVDD
AVDD to DVDD −0.3 V to +0.3 V
AGND to DGND −0.3 V to +0.3 V
Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to VDRIVE + 0.3 V
Digital Output Voltage to DGND −0.3 V to VDRIVE + 0.3 V
Analog Output Voltage Swing −0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies1 ±10 mA
Operating Temperature Range (Ambient)
EP Grade −55°C to +125°C
Storage Temperature Range −65°C to +150°C
θJA Thermal Impedance2 54°C/W
θJC Thermal Impedance2 15°C/W
RoHS-Compliant Temperature, Soldering
Reflow
260(−5/+0)oC
ESD 2 kV HBM
1 Transient currents of up to 100 mA do not cause latch-up.
2 JEDEC 2S2P standard board.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
AD2S1210-EP Data Sheet
Rev. A | Page 8 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48
RES0
47
REFOU
T
46
REFBYP
45
COS
44
COSLO
43
AVDD
42
SINLO
41
SIN
40
AGND
39
EXC
38
EXC
37
A0
35 DOS
34 LOT
33 RESET
30 B
31 NM
32 DIR
36 A1
29 A
28 DB0
27 DB1
25 DB3
26 DB2
2
CS
3
RD
4
W
R/FSYNC
7
CLKIN
6
DVDD
5
DGND
1
RES1
8
XTALOUT
9
SOE
10
SAMPLE
12
DB14/SDI
11
DB15/SDO
13
DB13/SCLK
14
DB12
15
DB11
16
DB10
17
DB9
18
VDRIVE
19
DGND
20
DB8
21
DB7
22
DB6
23
DB5
24
DB4
PIN 1
AD2S1210-EP
TOP VIEW
(No t to Scale)
0
9154-002
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No. Mnemonic Description
1 RES1 Resolution Select 1. Logic input. RES1 in conjunction with RES0 allows the resolution of the AD2S1210-EP to be
programmed.
2 CS Chip Select. Active low logic input. The device is enabled when CS is held low.
3 RD Edge-Triggered Logic Input. When the SOE pin is high, this pin acts as a frame synchronization signal and output
enable for the parallel data outputs, DB15 to DB0. The output buffer is enabled when CS and RD are held low. When
the SOE pin is low, the RD pin should be held high.
4 WR/FSYNC Edge-Triggered Logic Input. When the SOE pin is high, this pin acts as a frame synchronization signal and input
enable for the parallel data inputs, DB7 to DB0. The input buffer is enabled when CS and WR/FSYNC are held low.
When the SOE pin is low, the WR/FSYNC pin acts as a frame synchronization signal and enable for the serial data bus.
5, 19 DGND Digital Ground. These pins are ground reference points for digital circuitry on the AD2S1210-EP. Refer all digital input
signals to this DGND voltage. Both of these pins can be connected to the AGND plane of a system. The DGND and
AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
6 DVDD Digital Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD2S1210-EP. The AVDD and
DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient
basis.
7 CLKIN Clock Input. A crystal or oscillator can be used at the CLKIN and XTALOUT pins to supply the required clock frequency of
the AD2S1210-EP. Alternatively, a single-ended clock can be applied to the CLKIN pin. The input frequency of the
AD2S1210-EP is specified from 6.144 MHz to 10.24 MHz.
8 XTALOUT Crystal Output. When using a crystal or oscillator to supply the clock frequency to the AD2S1210-EP, apply the crystal
across the CLKIN and XTALOUT pins. When using a single-ended clock source, the XTALOUT pin should be
considered a no connect pin.
9 SOE Serial Output Enable. Logic input. This pin enables either the parallel or serial interface. The serial interface is selected
by holding the SOE pin low, and the parallel interface is selected by holding the SOE pin high.
10 SAMPLE Sample Result. Logic input. Data is transferred from the position and velocity integrators to the position and velocity
registers after a high-to-low transition on the SAMPLE signal. The fault register is also updated after a high-to-low
transition on the SAMPLE signal.
11 DB15/SDO Data Bit 15/Serial Data Output Bus. When the SOE pin is high, this pin acts as DB15, a three-state data output pin
controlled by CS and RD. When the SOE pin is low, this pin acts as SDO, the serial data output bus controlled by CS and
WR/FSYNC. The bits are clocked out on the rising edge of SCLK.
12 DB14/SDI
Data Bit 14/Serial Data Input Bus. When the SOE pin is high, this pin acts as DB14, a three-state data output pin controlled
by CS and RD. When the SOE pin is low, this pin acts as SDI, the serial data input bus controlled by CS and WR/FSYNC. The
bits are clocked in on the falling edge of SCLK.
Data Sheet AD2S1210-EP
Rev. A | Page 9 of 16
Pin
No. Mnemonic Description
13 DB13/SCLK Data Bit 13/Serial Clock. In parallel mode, this pin acts as DB13, a three-state data output pin controlled by CS and RD. In
serial mode, this pin acts as the serial clock input.
14 to
17
DB12 to
DB9
Data Bit 12 to Data Bit 9. Three-state data output pins controlled by CS and RD.
18 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
Decouple this pin to DGND. The voltage range on this pin is 2.3 V to 5.25 V and may be different from the voltage
range at AVDD and DVDD but should never exceed either by more than 0.3 V.
20 DB8 Data Bit 8. Three-state data output pin controlled by CS and RD.
21 to
28
DB7 to DB0 Data Bit 7 to Data Bit 0. Three-state data input/output pins controlled by CS, RD, and WR/FSYNC.
29 A Incremental Encoder Emulation Output A. Logic output. This output is free running and is valid if the resolver format
input signals applied to the converter are valid.
30 B Incremental Encoder Emulation Output B. Logic output. This output is free running and is valid if the resolver format
input signals applied to the converter are valid.
31 NM North Marker Incremental Encoder Emulation Output. Logic output. This output is free running and is valid if the
resolver format input signals applied to the converter are valid.
32 DIR Direction. Logic output. This output is used in conjunction with the incremental encoder emulation outputs. The DIR
output indicates the direction of the input rotation and is high for increasing angular rotation.
33 RESET Reset. Logic input. The AD2S1210-EP requires an external reset signal to hold the RESET input low until VDD is within
the specified operating range of 4.75 V to 5.25 V.
34 LOT Loss of Tracking. Logic output. Loss of tracking (LOT) is indicated by a logic low on the LOT pin and is not latched.
35 DOS Degradation of Signal. Logic output. Degradation of signal (DOS) is detected when either resolver input (sine or cosine)
exceeds the specified DOS sine/cosine threshold or when an amplitude mismatch occurs between the sine and
cosine input voltages. DOS is indicated by a logic low on the DOS pin.
36 A1 Mode Select 1. Logic input. A1 in conjunction with A0 allows the mode of the AD2S1210-EP to be selected.
37 A0 Mode Select 0. Logic input. A0 in conjunction with A1 allows the mode of the AD2S1210-EP to be selected.
38 EXC Excitation Frequency. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its
complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the excitation
frequency register.
39 EXC Excitation Frequency Complement. Analog output. An on-board oscillator provides the sinusoidal excitation signal
(EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the
excitation frequency register.
40 AGND Analog Ground. This pin is the ground reference points for analog circuitry on the AD2S1210-EP. Refer all analog
input signals and any external reference signal to this AGND voltage. Connect the AGND pin to the AGND plane of a
system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V
apart, even on a transient basis.
41 SIN Positive Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
42 SINLO Negative Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
43 AVDD Analog Supply Voltage, 4.75 V to 5.25 V. This pin is the supply voltage for all analog circuitry on the AD2S1210-EP. The
AVDD and DVDD voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
44 COSLO Negative Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
45 COS Positive Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
46 REFBYP Reference Bypass. Connect reference decoupling capacitors at this pin. Typical recommended values are 10 μF and 0.01 μF.
47 REFOUT Voltage Reference Output.
48 RES0 Resolution Select 0. Logic input. RES0 in conjunction with RES1 allows the resolution of the AD2S1210-EP to be
programmed.
AD2S1210-EP Data Sheet
Rev. A | Page 10 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, AVDD = DVDD = VDRIVE = 5 V, SIN/SINLO = 3.15 V p-p, COS/COSLO = 3.15 V p-p, CLKIN = 8.192 MHz, unless otherwise noted.
8181
8182
8183
8184
8185
8186
8187
8188
8189
8190
8191
8192
8193
8194
8195
8196
8197
8198
8199
1000
2000
3000
4000
5000
6000
7000
8000
9000
HIT S P E R CODE
CODE
09154-003
Figure 3. Typical 16-Bit Angular Accuracy Histogram Of Codes,
10,000 Samples
8000
7000
6000
5000
4000
3000
2000
1000
0
8181
8182
8183
8184
8185
8186
8187
8188
8189
8190
8191
8192
8193
8194
8195
8196
8197
8198
8199
HIT S P E R CODE
CODE
09154-004
Figure 4. Typical 14-Bit Angular Accuracy Histogram of Codes,
10,000 Samples, Hysteresis Disabled
12000
10000
8000
6000
4000
2000
02046 2047 2048 2049 2050
CODES
HIT S P E R CODE
09154-005
Figure 5. Typical 14-Bit Angular Accuracy Histogram of Codes,
10,000 Samples, Hysteresis Enabled
8178
8179
8180
8181
8182
8183
8184
8185
8186
8187
8188
8189
8190
8191
8192
8193
8194
8195
8196
8197
8198
8199
8200
8201
HIT S P E R CODE
CODE
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
09154-006
Figure 6. Typical 12-Bit Angular Accuracy Histogram of Codes,
10,000 Samples, Hysteresis Disabled
12000
10000
8000
6000
4000
2000
0510 511 512 513 514
CODES
HIT S P E R CODE
09154-017
Figure 7. Typical 12-Bit Angular Accuracy Histogram of Codes,
10,000 Samples, Hysteresis Enabled
Figure 8. Typical 10-Bit Angular Accuracy Histogram of Codes,
10,000 Samples, Hysteresis Disabled
Data Sheet AD2S1210-EP
Rev. A | Page 11 of 16
12000
10000
8000
6000
4000
2000
0126 127 128 129 130
CODES
HIT S P E R CODE
09154-038
Figure 9. Typical 10-Bit Angular Accuracy Histogram of Codes,
10,000 Samples, Hysteresis Enabled
20
18
16
14
12
10
8
6
4
2
00 4 8 12 16 20 24 28 32 36 40
TIME (ms)
ANGL E ( Degrees)
09154-010
Figure 10. Typical 16-Bit 10° Step Response
20
18
16
14
12
10
8
6
4
2
00 1 2 3 4 5 6 7 8 9 10
TIME (ms)
ANGL E ( Degrees)
09154-009
Figure 11. Typical 14-Bit 10° Step Response
20
18
16
14
12
10
8
6
4
2
000.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
TIME (ms)
ANGL E ( Degrees)
09154-008
Figure 12. Typical 12-Bit 10° Step Response
20
18
16
14
12
10
8
6
4
2
000.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
TIME (ms)
ANGL E ( Degrees)
09154-007
Figure 13. Typical 10-Bit 10° Step Response
250
225
200
175
150
125
100
75
50
25
00 8 16 24 32 40 48 56 64 72 80
TIME (ms)
ANGL E ( Degrees)
09154-014
Figure 14. Typical 16-Bit 179° Step Response
AD2S1210-EP Data Sheet
Rev. A | Page 12 of 16
20
18
16
14
12
10
8
6
4
2
00 0.25 0.50 0.75 1.001.25 1.501.75 2.00 2.25 2.50
TIME (ms)
ANGL E ( Degrees)
09154-013
Figure 15. Typical 14-Bit 179° Step Response
250
225
200
175
150
125
100
75
50
25
00 1 2 3 4 5 6 7 8 9 10
TIME (ms)
ANGL E ( Degrees)
09154-012
Figure 16. Typical 12-Bit 179° Step Response
Figure 17. Typical 10-Bit 179° Step Response
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45110 100 1k 10k 100k
FREQUENCY ( Hz )
MAG NI TUDE ( dB)
16-BIT
14-BIT 12-BIT
10-BIT
09154-015
Figure 18. Typical System Magnitude Response
0
–40
–20
–60
–80
–100
–120
–140
–160
–180
–200110 100 1k 10k 100k
FREQUENCY ( Hz )
PHASE (dB)
16-BIT
14-BIT 12-BIT
10-BIT
09154-016
Figure 19. Typical System Phase Response
10
8
9
7
6
5
4
3
2
1
00500 1000 1500 2000 2500
ACCELE RATI ON (rps
2
)
TRACKI NG ERROR (Degrees)
09154-022
Figure 20. Typical 16-Bit Tracking Error vs. Acceleration
Data Sheet AD2S1210-EP
Rev. A | Page 13 of 16
10
8
9
7
6
5
4
3
2
1
005000 10000 15000 20000 25000 30000 35000 40000 45000
ACCELE RATI ON (rps2)
TRACKI NG ERROR (Degrees)
09154-021
Figure 21. Typical 14-Bit Tracking Error vs. Acceleration
10
8
9
7
6
5
4
3
2
1
0020000 60000 100000 140000 180000
ACCELE RATI ON (rps2)
TRACKI NG ERROR (Degrees)
09154-020
Figure 22. Typical 12-Bit Tracking Error vs. Acceleration
10
8
9
7
6
5
4
3
2
1
00200000 400000 600000 800000 1000000
ACCELE RATI ON (rps
2
)
TRACKI NG ERROR (Degrees)
09154-019
Figure 23. Typical 10-Bit Tracking Error vs. Acceleration
AD2S1210-EP Data Sheet
Rev. A | Page 14 of 16
OUTLINE DIMENSIONS
1
12 13 25
24
36
37
48
COMPLIANT TO JEDE C S TANDARDS MS-026-BBC
01-17-2018-A
VIEW A
1.60
MAX
0.75
0.60
0.45
1.00 REF
0.27
0.22
0.17
PKG-005430
9.20
9.00 SQ
8.80
7.20
7.00 SQ
6.80
TOP VIEW
SIDE VIEW
0.08 M AX
COPLANARITY
7°
0°
VIEW A
ROT ATED 9 0 ° CCW
1.45
1.40
1.35
0.15
0.10
0.05
0.20
0.15
0.09
SEATING
PLANE
0.50
BSC
Figure 24. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD2S1210SST-EP-RL7 −55°C to +125°C 48-Lead LQFP ST-48
AD2S1210SSTZ-EPRL7 −55°C to +125°C 48-Lead LQFP ST-48
1 Z = RoHS Compliant Part
Data Sheet AD2S1210-EP
Rev. A | Page 15 of 16
NOTES
AD2S1210-EP Data Sheet
Rev. A | Page 16 of 16
NOTES
©2010–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09154-0-5/18(A)