THC63LVDM83D-B - CALIFORNIA EASTERN LABORATORIES

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7

PLL

TA +/-

TB +/-

TC +/-

TD +/-

TCLK +/-

R/F

/PDWN

TA0-6

TC0-6

TD0-6

TRANSMITTER

(8 to 160MHz)

CMOS/TTL

7

RS

7

TB0-6 7

INPUTS

CLOCK

(LVDS)

8-160MHz

DATA

(LVDS)

(56-1120Mbit/On Each

LVDS Channel)

CLKIN

THC63LVDM83D

CMOS/TTL PARALLEL

TO SERIAL

7

PLL

TA +/-

TB +/-

TC +/-

TD +/-

TCLK +/-

R/F

/PDWN

TA0-6

TC0-6

TD0-6

TRANSMITTER

(8 to 160MHz)

CMOS/TTL

7

RS

7

TB0-6 7

INPUTS

CLOCK

(LVDS)

8-160MHz

DATA

(LVDS)

(56-1120Mbit/On Each

LVDS Channel)

CLKIN

THC63LVDM83D

CMOS/TTL PARALLEL

TO SERIAL

THC63LVDM83D

24bit COLOR LVDS TRANSMITTER

General Description

The THC63LVDM83D transmitter is designed to support pixel

data transmission between Host and Flat Panel Display up to

1080p/WUXGA resolutions.

The THC63LVDM83D converts 28bits of LVCMOS data into

four OpenLDI(LVDS) data streams. The transmitter can be

programmed for rising edge or falling edge clock through a

dedicated pin. At a transmit clock frequency of 160MHz,

24bits of RGB data and 4bits of timing and control data

(HSYNC, VSYNC, DE, CONT1) are transmitted at an

effective rate of 1120Mbps per OpenLDI(LVDS) channel.

Application

･Medium and Small Size Panel

･Tablet PC / Notebook PC

･Security Camera / Industrial Camera

･Multi Function Printer

･Industrial Equipment

･Medical Equipment Monitor

Features

･Compatible with TIA/EIA-644 LVDS Standard

･7:1 OpenLDI(LVDS) Transmitter

･Operating Temperature Range : 0 to +70C

･No Special Start-up Sequence Required

･Spread Spectrum Clocking Tolerant up to 100kHz Frequency

Modulation and +/-2.5% Deviations.

･Wide Dot Clock Range: 8 to 160MHz Suited for

TV Signal : NTSC(12.27MHz) - 1080p(148.5MHz)

PC Signal : QVGA(8MHz) - WUXGA(154MHz)

･56pin TSSOP Package

･1.2V to 3.3V LVCMOS/ inputs are supported.

･LVDS swing is reducible as 200mV by RS-pin to reduce EMI

and power consumption.

･PLL requires no external components.

･Power Down Mode.

･Input clock triggering edge is selectable by R/F-pin

･EU RoHS Compliant.

Block Diagram

Figure 1. Block Diagram

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Pin Diagram

Figure 2. Pin Diagram

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Pin Description

Pin Name

Pin #

Direction

Type

Description

TA+, TA-

47, 48

Output

LVDS

LVDS Data Out

TB+, TB-

45, 46

TC+, TC-

41, 42

TD+, TD-

37, 38

TCLK+,

TCLK-

39, 40

LVDS Clock Out

TA0 ~ TA6

51, 52, 54, 55, 56, 3, 4

Input

LVCMOS

Pixel Data Input

TB0 ~ TB6

6, 7, 11, 12, 14, 15, 19

TC0 ~ TC6

20, 22, 23, 24, 27, 28,

30

TD0 ~ TD6

50, 2, 8, 10, 16, 18, 25

/PDWN

32

H : Normal Operation

L : Power Down (All outputs are Hi-Z)

RS

1

LVDS Swing Mode, VREF Select See Fig.7,

8

VREF : is Input Reference Voltage

R/F

17

Input Clock Triggering Edge Select

H : Rising Edge

L : Falling Edge

CLKIN

31

Input Clock

VCC

9, 26

Power

-

Power Supply Pins for LVCMOS inputs and

digital circuit.

GND

5, 13, 21, 29, 53

Ground Pins for LVCMOS Inputs and Digital

Circuitry.

LVDS VCC

44

Power Supply Pins for LVDS Outputs.

LVDS GND

36, 43 49

Ground Pins for LVDS Outputs.

PLL VCC

34

Power Supply Pin for PLL Circuitry.

PLL GND

33, 35

Ground Supply Pin for PLL Circuitry.

Table 1. Pin Description

RS Pin

LVDS

Swing

Small Swing

Input Support

VCC 350mV N/A

0.6 to 1.4V 350mV RS=VREF

GND 200mV N.A

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LVDS_OutP

LVDS_OutN

IN_N

IN_P

3.5mA

Absolute Maximum Ratings

Parameter

Min

Max

Unit

All Supply Voltage (VCC, LVDS VCC, PLL VCC)

-0.3

+4.0

V

LVCMOS Input Voltage

-0.3

VCC + 0.3

V

LVDS Output Pin

-0.3

VCC + 0.3

V

Output Current

-30

30

mA

Junction Temperature

-

+125

C

Storage Temperature

-55

+150

C

Reflow Peak Temperature

-

+260

C

Reflow Peak Temperature Time

-

10

sec

Maximum Power Dissipation @+25C

-

1.8

W

Table 2. Absolute Maximum Ratings

Recommended Operating Conditions

Symbol

Parameter

Min

Typ

Max

Unit

VCC, LVDS VCC

PLL VCC

All Supply Voltage

3.0

3.3

3.6

V

Ta

Operating Ambient Temperature

0

25

+70

C

-

Clock Frequency

8

-

160

MHz

Table 3. Recommended Operating Conditions

“Absolute Maximum Ratings” are those values beyond which the safety of the device can not be guaranteed.

They are not meant to imply that the device should be operated at these limits. The tables of “Electrical

Characteristics Table4, 5, 6, 7” specify conditions for device operation.

“Absolute Maximum Rating” value also includes behavior of overshooting and undershooting.

Equivalent LVDS Output Schematic Diagram

Figure 3. LVDS Output Schematic Diagram

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CLKIN

Tx0-6

Power Consumption

Over recommended operating supply and temperature range unless otherwise specified

Symbol

Parameter

Conditions

Typ*

Max

Unit

ITCCW

LVDS Transmitter

Operating Current

Worst Case Pattern

(Fig.4)

RL=100, CL=5pF, f=85MHz, RS=VCC

61

67

mA

RL=100, CL=5pF, f=135MHz,

RS=VCC

77

83

mA

RL=100, CL=5pF, f=160MHz,

RS=VCC

84

92

mA

RL=100, CL=5pF, f=85MHz, RS=GND

50

56

mA

RL=100, CL=5pF, f=135MHz,

RS=GND

65

71

mA

RL=100, CL=5pF, f=160MHz,

RS=GND

73

80

mA

ITCCS

LVDS Transmitter

Power Down Current

/PDWN=L, All Inputs=L or H

-

10

µA

*Typ values are at the conditions of VCC=3.3V and Ta = +25ºC

Table 4. Power Consumption

Worst Case Pattern

x=A,B,C,D Figure 4. Worst Case Pattern

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Electrical Characteristics

LVCMOS DC Specifications

Over recommended operating supply and temperature range unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ*

Max

Unit

VIH

High Level Input Voltage

RS=VCC or GND

2.0

-

VCC

V

VIL

Low Level Input Voltage

RS=VCC or GND

GND

-

0.8

V

VDDQ1

Small Swing Voltage

1.2

-

2.8

V

VREF

Input Reference Voltage

Small Swing (RS=VDDQ/2)

-

VDDQ/2

-

VSH2

Small Swing High Level

Input Voltage

VREF= VDDQ/2

VDDQ/2

+100m

V

-

V

VSL2

Small Swing Low Level

Input Voltage

VREF= VDDQ/2

-

VDDQ/2

-100mV

V

IINC

Input Current

GND  VIN  VCC

-

10

A

*Typ values are at the conditions of VCC=3.3V and Ta = +25ºC

Notes : 1 VDDQ voltage defines the max voltage of small swing inputs at RS=VREF. It is not an actual input

voltage.

2 Small swing signals are applied to TA0-6, TB0-6, TC0-6, TD0-6 and CLKIN.

Table 5. LV-CMOS DC Specifications

LVDS Transmitter DC Specifications

Over recommended operating supply and temperature range unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ*

Max

Unit

VOD

Differential Output Voltage

RL=100Ω

Normal swing

RS=VCC

250

350

450

mV

Reduced

swing

RS=GND

100

200

300

mV

∆VOD

Change in VOD between

complementary output

states

RL=100Ω

-

35

mV

VOC

Common Mode Voltage

1.125

1.25

1.375

V

∆VOC

Change in VOC between

complementary output

states

-

35

mV

IOS

Output Short Circuit

Current

VOUT=GND, RL=100Ω

-

-24

mA

IOZ

Output TRI-STATE

Current

/PDWN=GND,

VOUT=GND to VCC

-

10

A

*Typ values are at the conditions of VCC=3.3V and Ta = +25ºC

Table 6. LVDS Transmitter DC Specifications

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CLK IN

90%

10%

90%

10%

tTCIT tTCIT

VOC

VOD

50Ω

5pF

Tn+

Tn-

0%

20%

80%

100%

0V

tLVT tLVT

VOD(H)

VOD(L)

LVCMOS & LVDS Transmitter AC Specifications

Over recommended operating supply and temperature range unless otherwise specified

Symbol

Parameter

Min

Typ

Max

Unit

tTCIT

CLK IN Transition Time

-

5.0

ns

tTCP

CLK IN Period

6.25

T

125

ns

tTCH

CLK IN High Time

0.35T

0.5T

0.65T

ns

tTCL

CLK IN Low Time

0.35T

0.5T

0.65T

ns

tTCD

CLK IN to TCLK+/- Delay

-

3T

-

ns

tTS

LVCMOS Data Setup to CLK IN

2.0

-

ns

tTH

LVCMOS Data Hold from CLK IN

0.0

-

ns

tLVT

LVDS Transition Time

-

0.6

1.5

ns

tTOP1

Output Data Position0 (T=6.25ns ~ 20ns)

-0.15

0.0

+0.15

ns

tTop0

Output Data Position1 (T=6.25ns ~ 20ns)

T/7-0.15

T/7

T/7+0.15

ns

tTop6

Output Data Position2 (T=6.25ns ~ 20ns)

2T/7-0.15

2T/7

2T/7+0.15

ns

tTop5

Output Data Position3 (T=6.25ns ~ 20ns)

3T/7-0.15

3T/7

3T/7+0.15

ns

tTop4

Output Data Position4 (T=6.25ns ~ 20ns)

4T/7-0.15

4T/7

4T/7+0.15

ns

tTop3

Output Data Position5 (T=6.25ns ~ 20ns)

5T/7-0.15

5T/7

5T/7+0.15

ns

tTop2

Output Data Position6 (T=6.25ns ~ 20ns)

6T/7-0.15

6T/7

6T/7+0.15

ns

tTPLL

Phase Lock Loop Set

-

10.0

ms

*Typ values are at the conditions of VCC=3.3V and Ta = +25ºC

Table 7. LVCMOS & LVDS Transmitter AC Specifications

LVCMOS Input

Figure 5. CLKIN Transmission Time

LVDS Output

LVDS Output Load

Figure 6. LVDS Output Load and Transmission Time

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RS

VOD

VCC

0.6 ~ 1.4V

GND 200mV

350mV

RS

VREF

VCC ---

0.6 ~ 1.4V

VDDQ/2

GND ---

AC Timing Diagrams

LVCMOS Inputs

Normal Swing Input

Note :

CLKIN : Solid line denotes the setting of R/F=GND

Dashed line denotes the setting of R/F = VCC

Figure 7. LVCOMS Inputs and LVDS Clock Output Timing 1

Small Swing Inputs

Note :

CLKIN : Solid line denotes the setting of R/F=GND

Dashed line denotes the setting of R/F = VCC

Figure 8. LVCMOS Inputs and LVDS Output Timing 2

tTCP

tTS tTH

tTCH

tTCL

CLKIN

Tx0-Tx6

tTCD

TCLK+

TCLK-

VCC

GND

VCC

VOC

VCC/2 VCC/2 VCC/2

VCC/2 VCC/2

tTCP

tTS tTH

tTCH

tTCL

CLKIN

Tx0-Tx6

tTCD

TCLK+

TCLK-

VDDQ

GND

VDDQ

VREF

VOC

VREF

VDDQ/2 VDDQ/2

VDDQ/2 VDDQ/2 VDDQ/2

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Vdiff = 0V Vdiff = 0V

TCLK+/-

tTOP1tTOP0

tTOP6

tTOP5

tTOP4

tTOP3

tTOP2

TD6 TD5 TD4 TD3 TD2 TD1 TD0

TD+/-

TC6 TC5 TC4 TC3 TC2 TC1 TC0TC+/-

TB6 TB5 TB4 TB3 TB2 TB1 TB0TB+/-

TA6 TA5 TA4 TA3 TA2 TA1 TA0TA+/-

(Differential)

Next Cycle

Previous Cycle

2.0V

CLKIN

/PDWN

TCLK+/-

3.0V

VCC tTPLL

Vdiff = 0V

LVDS Output Data Position

Figure 9. LVDS Output Data Position

Phase Lock Loop Set Time

Figure 10. PLL Lock Loop Set Time

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Spread Spectrum Clocking Tolerant

Figure 11. Spread Spectrum Clocking Tolerant

The graph indicates the range that the IC works normally under SS clock input operation.

The results are measured with a typical sample on condition of +25Cº and 3.3V, therefore these

values are for reference and do not guarantee the performance of a product under other

circumstance.

LVDS Data Timing Diagram

Figure 12. LVDS Data Timing Diagram

Vdiff=0V Vdiff=0V

TCLK+/-

(Differntial)

Tx+/-

X=A,B,C,D

Previous Pixel Data Pixel Data

Tx6 Tx5 Tx4 Tx3 Tx2 Tx1 Tx0

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For Display Application

THC63LVDM83D Pixel Data Mapping for JEIDA Format (6bit, 8bit Application)

Note : Use TA to TC channels and open TD channel for 6bit application.

Table 8. Data Mapping for JEIDA Format

6bit

8bit

TA0

R2

TA1

R3

TA2

R4

TA3

R5

TA4

R6

TA5

R7

TA6

G2

TB0

G3

TB1

G4

TB2

G5

TB3

G6

TB4

G7

TB5

B2

TB6

B3

TC0

B4

TC1

B5

TC2

B6

TC3

B7

TC4

Hsync

TC5

Vsync

TC6

DE

TD0

-

R0

TD1

-

R1

TD2

-

G0

TD3

-

G1

TD4

-

B0

TD5

-

B1

TD6

-

N/A

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THC63LVDM83D Pixel Data Mapping for VESA Format (6bit, 8bit Application)

Note : Use TA to TC channels and open TD channel for 6bit application.

Table 9. Data Mapping for VESA Format

6bit

8bit

TA0

R0

TA1

R1

TA2

R2

TA3

R3

TA4

R4

TA5

R5

TA6

G0

TB0

G1

TB1

G2

TB2

G3

TB3

G4

TB4

G5

TB5

B0

TB6

B1

TC0

B2

TC1

B3

TC2

B4

TC3

B5

TC4

Hsync

TC5

Vsync

TC6

DE

TD0

-

R6

TD1

-

R7

TD2

-

G6

TD3

-

G7

TD4

-

B6

TD5

-

B7

TD6

-

N/A

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Typical Connection

Figure 13. Typical Connection Diagram

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Notes

1) Cable Connection and Disconnection

Do not connect and disconnect the LVDS cable, when the power is supplied to the system.

2) GND Connection

Connect each GND of the PCB which THC63LVDM83D and LVDS-Rx on it. It is better for EMI

reduction to place GND cable as close to LVDS cable as possible.

3) Multi Drop Connection

Multi drop connection is not recommended.

Figure 14. Multi Drop Connection

4) Asynchronous use

Asynchronous using such as following systems is not recommended.

Figure 15. Asynchronous Use

LVDS-RX

THC63LVDM83D

LVDS-RX

TCLK+

TCLK-

IC

CLKOUT

DATA

LVDS-RX

IC

TCLK+

TCLK-

TCLK+

TCLK-

CLKOUT

DATA

THC63LVDM83D

IC

TCLK+

TCLK-

TCLK+

TCLK-

CLKOUT

DATA

IC

THC63LVDM83D

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1.00REF

0.60+/-0.15

0.25

GAUGE PLANE

0.5

0.17~0.27

14.00+/-0.10

S

0.10 S

6.10+/-0.1

8.10 NOM

0.05~0.15 1.20MAX

SEATING PLANE

UNIT:mm

Package

Figure 16. Package Diagram

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CY1=

HE=e=

E=

Ttyp.=

Gmin= b=

Zmax= Xmax=

Zmax/2

5. 50

9. 30

0.60

8.100

6.10

10.34

0.500

1. 90

0.200

0.470

Unit mm

Package

Land Pattern

Reference Land Pattern

Figure 17. Reference of Land Pattern

The recommendation mounting method of THine device is reflow soldering.

The reference pattern is using the calculation result on condition of reflow soldering.

Notes

This land pattern design is a calculated value based on JEITA ET-7501.

Please take into consideration in an actual substrate design about enough the ease of mounting, the intensity of

connection, the density of mounting, and the solder paste used, etc… The optimal land pattern size changes

with these parameters. Please use the value shown by the land pattern as reference data.

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Notices and Requests

1. The product specifications described in this material are subject to change without prior notice.

2. The circuit diagrams described in this material are examples of the application which may not always apply to

the customer's design. We are not responsible for possible errors and omissions in this material. Please note if

errors or omissions should be found in this material, we may not be able to correct them immediately.

3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties the

contents of this material without our prior permission is prohibited.

4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will

be exempted from the responsibility unless it directly relates to the production process or functions of the

product.

5. Product Application

5.1 Application of this product is intended for and limited to the following applications: audio-video device,

office automation device, communication device, consumer electronics, smartphone, feature phone, and

amusement machine device. This product must not be used for applications that require extremely

high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control

device, combustion chamber device, medical device related to critical care, or any kind of safety device.

5.2 This product is not intended to be used as an automotive part, unless the product is specified as a product

conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") in this data sheet.

THine Electronics, Inc. (“THine”) accepts no liability whatsoever for any product other than the Specified

Product for it not conforming to the aforementioned demands and specifications.

5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that the

user and THine have been previously and explicitly agreed to each other.

6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain

small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have

sufficiently redundant or error preventive design applied to the use of the product so as not to have our

product cause any social or public damage.

7. Please note that this product is not designed to be radiation-proof.

8. Testing and other quality control techniques are used to this product to the extent THine deems necessary to

support warranty for performance of this product. Except where mandated by applicable law or deemed

necessary by THine based on the user’s request, testing of all functions and performance of the product is not

necessarily performed.

9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic

goods under the Foreign Exchange and Foreign Trade Control Law.

10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or

malfunction, if pins of the product are shorted by such as foreign substance. The damages may cause a

smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection

devices, such as fuses.

THine Electronics, Inc.

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