DATA SH EET
Product specification
Supersedes data of April 1991 1996 Aug 01
DISCRETE SEMICONDUCTORS
BF998; BF998R
Silicon N-channel dual-gate
MOS-FETs
1996 Aug 01 2
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
FEATURES
Short channel trans i stor with high forward transfer
admittance to input capacitance ratio
Low noise gain controlled amplifier up to 1 GHz.
APPLICATIONS
VHF and UHF applications with 12 V supply voltage,
such as television tuners and professional
communications equipm ent.
DESCRIPTION
Depletion type field effect transistor in a plastic
microminiatur e SOT1 43 B or SOT1 43 R pa ckage with
source and substrate interconn ected. The transis t ors are
protected against exces sive input voltage surges by
integrated back-to-back diodes betw een gates and
source.
PINNING
CAUTION
The device is supplie d in an antistatic package. The
gate-source inpu t must be protected against static
discharge during transport or handling.
PIN SYMBOL DESCRIPTION
1s, bsource
2 d drain
3g
2gate 2
4g
1gate 1
Fig.1 Simplified outline (SOT143B)
and symbol; BF998.
Marking code: MOp.
handbook, halfpage
s,b
d
g1
g2
43
21
Top view MAM039
handbook, halfpage
s,b
d
g1
g2
MAM040
34
12
Top view
Fig.2 Simplified outline (SOT143R)
and symbol; BF998R.
Marking code: MOp.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
VDS drain-source voltage 12 V
IDdrain current 30 mA
Ptot total power dissipation 200 mW
yfsforward transfer admittance 24 mS
Cig1-s input capacitance at gate 1 2.1 pF
Crs reverse transfe r capacitance f = 1 MHz 25 fF
F noise figure f = 800 MHz 1 dB
Tjoperating junction temperature 150 C
1996 Aug 01 3
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
LIMITING VALUES
In accordance with the Absolute Maximum Rating S ystem (IEC 134).
Notes
1. Device mounted o n a c eramic substrate, 8 mm 10 mm 0.7 mm.
2. Device mounted on a pr inted-circuit board.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS drain-source voltage 12 V
IDdrain current 30 mA
IG1 gate 1 current 10 mA
IG2 gate 2 current 10 mA
Ptot total power dissipation; BF998 up to Tamb =60C; see Fig.3; not e 1 200 mW
up to Tamb =50C; see Fig.3; not e 2 200 mW
Ptot total power dissipation; BF998R up to Tamb =50C; see Fig.4; note 1 200 mW
Tstg storage temperature 65 +150 C
Tjoperating junction temperature 150 C
Fig.3 Power derating curves; BF998.
handbook, halfpage
0
100
0 200100
200
(mW)
Ptot max (1)(2)
MLA198
Tamb ( C)
o
(1) Ceramic substrate.
(2) Printed-circuit boa rd.
Fig.4 Power derating c urv e; BF998R.
handbook, halfpage
0
100
0 200100
200
(mW)
Ptot max
MGA002
Tamb (°C)
1996 Aug 01 4
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
THERMAL CHARACTE RISTI CS
Notes
1. Device mounted o n a c eramic substrate, 8 mm 10 mm 0.7 mm.
2. Device mounted on a pr inted-circuit board.
STATIC CHARACTERISTICS
Tj=25C; unless otherwise specified.
Note
1. Measured under pulse condition.
DYNAMIC CHARACTERISTICS
Common source; Tamb =25C; VDS =8V; V
G2-S =4V; I
D=10mA.
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth j-a thermal resistance from junction to ambient in free air; BF998 note 1 460 K/W
note 2 500 K/W
Rth j-a thermal resistance from junction to ambient in free air; BF998R note 1 500 K/W
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V(BR)G1-SS gate 1-source breakdown voltage VG2-S =V
DS =0; I
G1-SS =10 mA 6 20 V
V(BR)G2-SS gate 2-source breakdown voltage VG1-S =V
DS =0; I
G2-SS =10 mA 6 20 V
V(P)G1-S gate 1-source cut-off voltage VG2-S =4V; V
DS =8V; I
D=20A2.0 V
V(P)G2-S gate 2-source cut-off voltage VG1-S =0; V
DS =8V; I
D=20A1.5 V
IDSS drain-source current VG2-S =4V; V
DS =8V; V
G1-S =0; note1 2 18 mA
IG1-SS gate 1 cut-off current VG2-S =V
DS =0; V
G1-S =5V 50 nA
IG2-SS gate 2 cut-off current VG1-S =V
DS =0; V
G2-S =5V 50 nA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
yfsforward transfer admittance f = 1 kHz 21 24 mS
Cig1-s input capacitance at gate 1 f = 1 MHz 2.1 2.5 pF
Cig2-s input capacitance at gate 2 f = 1 MH z 1.2 pF
Cos output capacitance f = 1 MHz 1.05 pF
Crs reverse transfer capacitance f = 1 MH z 25 fF
F noise figure f = 200 MHz; GS=2mS; B
S=B
Sopt 0.6 dB
f=800MHz; G
S= 3.3 mS; BS=B
Sopt 1.0 dB
1996 Aug 01 5
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
Fig.5 Output characteristics; typical values.
handbook, halfpage
010
24
0
8
16
4
12
20
MGE813
2468
VDS (V)
ID
(mA) 0.4 V
0.3 V
0.2 V
0.1 V
0 V
−0.5 V
−0.4 V
−0.3 V
−0.2 V
−0.1 V
VG1-S =
VG2-S =4V; T
amb =25C.
Fig.6 Transfer characterist ics ; typical values.
handbook, halfpage
−11
24
0
8
16
4
12
20
MGE815
0
3 V 2 V
1 V
0 V
VG2-S = 4 V
VG1 (V)
ID
(mA)
VDS =8V; T
amb =25C.
Fig.7 Drain current as a func tion of gate 1
voltage; typical values.
handbook, halfpage
−1600 −400−800−1200 400
24
0
8
16
4
12
20
MGE814
0
max typ
min
VG1 (mV)
ID
(mA)
VDS =8V; V
G2-S =4V; T
amb =25C.
Fig.8 Forward transfer admittance as a function of
drain current; typical values.
handbook, halfpage
020
30
0
6
12
18
24
MGE811
161284 ID (mA)
0.5 V
4 V
1 V
2 V
3 V
VG2-S = 0 V
|yfs|
(mS)
VDS =8V; T
amb =25C.
1996 Aug 01 6
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
Fig.9 Forward transfer admittance as a function of
gate 1 voltage; typical values.
VDS =8V; T
amb =25C.
handbook, halfpage
−11
30
0
6
12
18
24
MGE812
0VG1 (V)
0 V
1 V
2 V
3 V
VG2-S = 4 V
|yfs|
(mS)
Fig.10 Ou tput capacitance as a function of
drain-source voltage; typical values.
handbook, halfpage
414
1.5
1.0
1.1
1.2
1.3
1.4
MGE810
Cos
(pF)
6 8 10 12
VDS (V)
12 mA
10 mA
8 mA
VG2-S =4V; f=1MHz; T
amb =25C.
Fig.11 G ate 1 input capacitance as a function of
gate 1-source voltage; typical values.
handbook, halfpage
−2.4 −1.6 −0.8 0.8
MGE809
0
2.1
1.9
1.7
2.3
1.5
1.3
Cis
(pF)
VG1-S (V)
VDS =8V; V
G2-S = 4 V; f = 1 MHz; Tamb =25C.
Fig.12 Gate 1 input capac itance as a f uncti on of
gate 2-source voltage; typical values.
handbook, halfpage
642
Cis
(pF)
−2
2.4
2.3
2.1
2.0
2.2
MBH479
0VG2−S (V)
VDS =8V; V
G1-S = 0 V; f = 1 MHz; Tamb =25C.
1996 Aug 01 7
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
Fig.13 Input admittance as a function of the
frequency; typical values.
VDS =8V; V
G2-S =4V; I
D=10mA; T
amb =25C.
103
MGC466
102
10
10 2
1
10
10 1
yis
(mS)
f (MHz)
bis
gis
Fig.14 Reverse transfer admittance and phase as a
function of frequenc y; typical values.
VDS =8V; V
G2-S =4V; I
D=10mA; T
amb =25C.
103
MGC467
102
10
103
102
10
1
yrs
103
10
10
1
2
(μS)
f (MHz)
rs
yrs
(deg)
rs
ϕ
ϕ
Fig.15 Forward transfer admittance and phase as a
function of frequenc y; typical values.
VDS =8V; V
G2-S =4V; I
D=10mA; T
amb =25C.
Fig.16 Output admittance as a function of the
frequency; typical values.
VDS =8V; V
G2-S =4V; I
D=10mA; T
amb =25C.
10
3
MGC469
10
2
10
10
1
10
1
10
2
yos
(mS)
f (MHz)
bos
gos
1996 Aug 01 8
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
handbook, full pagewidth
MGE802
330 kΩ
1.8 kΩ
360 Ω
100 kΩ
140 kΩ
1 nF
1 nF
47 μF
20 μH
1 nF
10 pF
D2
BB405
330 kΩ
1 nF
1 nF
Vtun
output
50 Ω
output
C1
5.5 pF
50 Ω
input
VDD
VDD
Vagc
47 kΩ
1 nF
1 nF
1 nF
L2
L1
1 nF
15 pF
D1
BB405
Vtun
input
VDD =12V; G
S=2mS; G
L= 0.5 mS.
L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm.
L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm.
Tapped at approximately half a turn from the cold side, to adjust GL= 0.5 mS. C1 adjusted for GS=2mS.
Fig.17 Gain control test circuit at f = 200 MHz.
1996 Aug 01 9
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
Fig.18 Gain control test circuit at f = 800 MHz.
VDD =12V; G
S= 3.3 mS; GL=1mS.
L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm.
L2 = 2 cm, silvered 0.8 mm copper wire, 4 mm above ground plane.
L3 = 2 cm, silvered 0.5 mm copper wire, 4 mm above ground plane.
handbook, full pagewidth
MGE801
1.8 kΩ360 Ω
100 kΩ
1 nF
1 nF
1 nF
50 Ω
output
1 nF
50 Ω
input
VDD
VDD
VDD Vagc
270 kΩ
140 kΩ
1 nF
1 nF
L4
L1
L2
1 nF
C1
2 to 18 pF C2
0.5 to 3.5 pF
C3
0.5 to
3.5 pF
C4
4 to 40 pF
L3
1996 Aug 01 10
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
handbook, halfpage
010
0
−50
−40
−30
−20
−10
MGE808
ΔGtr
(dB)
2468
Vagc (V)
IDSS =
max
typ
min
Fig.19 Automatic gain control characteristics
measured in circui t of Fig.17.
VDD =12V; f=200MHz; T
amb =25C.
handbook, halfpage
010
0
−50
−40
−30
−20
−10
MGE807
ΔGtr
(dB)
2468
Vagc (V)
IDSS =
max
typ
min
Fig.20 Automatic gain control characteristics
measured in circuit of Fig.18.
VDD =12V; f=800MHz; T
amb =25C.
1996 Aug 01 11
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
PACKAGE OUTLINES
UNIT A
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.1
0.9
A1
max
0.1
b1
0.88
0.78
c
0.15
0.09
D
3.0
2.8
E
1.4
1.2
HEywvQ
2.5
2.1 0.45
0.15 0.55
0.45
e
1.9
e1
1.7
Lp
0.1 0.10.2
bp
0.48
0.38
DIMENSIONS (mm are the original dimensions)
SOT143B 04-11-16
06-03-16
0 1 2 mm
scale
Plastic surface-mounted package; 4 leads SOT143B
D
HE
EA
B
vMA
X
A
A1
Lp
Q
detail X
c
y
wM
e1
e
B
21
34
b1
bp
1996 Aug 01 12
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
UNIT A
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.1
0.9
A1
max
0.1
b1
0.88
0.78
c
0.15
0.09
D
3.0
2.8
E
1.4
1.2
HEywvQ
2.5
2.1 0.55
0.25 0.45
0.25
e
1.9
e1
1.7
Lp
0.1 0.10.2
bp
0.48
0.38
DIMENSIONS (mm are the original dimensions)
SOT143R SC-61AA 04-11-16
06-03-16
0 1 2 mm
scale
Plastic surface-mounted package; reverse pinning; 4 leads SOT143R
D
HE
EA
B
vMA
X
A
A1
Lp
Q
detail X
c
y
wM
e1
e
B
12
43
b1
bp
1996 Aug 01 13
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
DATA SHEET STATUS
Notes
1. Please consult the most rec ently issued document befor e initiating or completing a design.
2. The product s tatus of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DOCUMENT
STATUS(1) PRODUCT
STATUS(2) DEFINITION
Objective data sheet Develo pment This document contains data from the objective specification for product
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Productio n This document contains the pr oduct specification.
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provided in a Product data she et shall define the
specification of the product as agre ed between NXP
Semiconductors and its custo m er, unless NXP
Semiconductors and cus to mer have explicitly agreed
otherwise in writing. In no event however, shall an
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product is deemed to offer functions and qualities beyond
those described in the Product data sheet.
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Limited warranty and liability Information in this
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However, NXP Semiconduc tors does not give any
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reserves the right to make changes to information
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accepts no liability for inclusion and/or use of NXP
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Applications Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of
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Semiconductors products, and NXP Semiconductors
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Semiconductors pro du ct is su itable and fit for the
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party customer(s). Customers should provide appropriate
design and opera ting safeguards to minimize the risks
associated with their ap plications and produ cts.
1996 Aug 01 14
NXP Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
NXP Semiconductors does not accept any liability related
to any default, damage, cost s or problem which is based
on any weakness or default in the customer’s applications
or products, or the applic ation or use by customer’s th ird
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semic on ductors products in order to
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the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this
respect.
Limiting values Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operat ion of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
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Semiconductors products are sold subje ct to the general
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Quick refer ence data The Quick reference data is an
extract of th e product data given in the Li miting values and
Characteristics sections of this document, and as su ch is
not complete, exhaus tive or legally binding.
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In the event that customer uses the product for design-in
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© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in th is do cum en t d oes not form part o f an y q uot ation or co nt ract, is believed to be a ccur ate a nd re liable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
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Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimer s. No cha ng es were made to the technical content, except for package outline
drawings which were updated to the latest version.
Printed in The Netherlands R77/02/pp15 Date of re le ase:1996 Aug 01