2x, 31.76 W, Digital Input, Filterless Stereo Class-D Audio Amplifier SSM3582 Data Sheet FEATURES Supported sample rates from 8 kHz to 192 kHz; 24-bit resolution Multiple PCM audio serial data formats TDM slave with support for up to 16 devices on a single bus I2S or left justified slave Adjustable full-scale output tailored for many PVDD sources 2- and 3-cell Li-Ion batteries Digital volume control with selectable smooth ramp Automatic power-down function Supply monitoring automatic gain control (AGC) function reduces system brownout Standalone operational mode without I2C Temperature sensor with 1C step readout via I2C Short-circuit, undervoltage, and thermal protection Thermal early warning Power-on reset PVDD sensing ADC 40-lead, 6 mm x 6 mm LFCSP with thermal pad Digital input stereo, high efficiency Class-D amplifier Operates from a single 4.5 V to 16 V supply State-of-the-art, proprietary, filterless - modulation 106.5 dB signal-to-noise ratio 0.004% total harmonic distortion plus noise (THD + N) at 5 W into 8 38.5 V rms A weighted output noise Pop/clickless on/off sequence 2x 14.67 W output at 12 V supply to 4 loads at <1% THD + N 2x 14.4 W output at 16 V supply to 8 loads at <1% THD + N Mono mode for increased maximum output power 1x 49.69 W output at 16 V supply to 2 loads at <1% THD + N Support for low impedance loads As low as 3 /5 H in stereo mode As low as 2 /5 H in mono mode High power efficiency 93.8% efficiency into an 8 load 90.6% efficiency into a 4 load 12.34 mA quiescent current with single 12 V PVDD supply Single supply operation with internal LDOs or option to use an external 5 V and 1.8 V supply for lowest power consumption I2C control and hardware modes with up to 16 pin-selectable slots/addresses APPLICATIONS Mobile computing All in one computers Portable electronics Wireless speakers Televisions FUNCTIONAL BLOCK DIAGRAM DVDD SDA SCL ADDR0 ADDR1 I2C CONTROL DVDD_EN AVDD AVDD_EN DVDD AVDD 1.8V LDO 5V LDO PVDD PVDD ADC TEMPERATURE SENSOR OUTL+ DAC BLCK FSYNC SDATA I2S TDM INTERFACE THREE-LEVEL - MODULATOR FULL BRIDGE POWER STAGE BSTL+ BSTL- OUTL- VOLUME BATTERY AGC OUTR+ DAC THREE-LEVEL - MODULATOR FULL BRIDGE POWER STAGE BSTR+ BSTR- PGND AGND 13399-001 OUTR- SSM3582 Figure 1. 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Technical Support www.analog.com SSM3582 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Standalone Operation ................................................................ 30 Applications ....................................................................................... 1 Mono Mode ................................................................................. 31 Functional Block Diagram .............................................................. 1 Analog and Digital Gain ........................................................... 31 Revision History ............................................................................... 2 Pop and Click Suppression........................................................ 31 General Description ......................................................................... 3 Temperature Sensor ................................................................... 31 Specifications..................................................................................... 4 Faults and Limiter Status Reporting ........................................ 32 Digital Input/Output Specifications........................................... 8 VBAT (PVDD) Sensing................................................................ 32 Digital Timing Specifications ..................................................... 8 Limiter and Battery Tracking Threshold Control .................. 32 Digital Input Timing Specifications ........................................... 8 High Frequency Clipper ............................................................ 35 Absolute Maximum Ratings.......................................................... 11 EMI Noise.................................................................................... 35 Thermal Resistance .................................................................... 11 Output Modulation Description .............................................. 35 ESD Caution ................................................................................ 11 Bootstrap Capacitors.................................................................. 36 Pin Configuration and Function Descriptions ........................... 12 Power Supply Decoupling ......................................................... 36 Typical Performance Characteristics ........................................... 14 Output EMI Filtering ................................................................. 36 Theory of Operation ...................................................................... 25 PCB Placement ........................................................................... 36 Overview...................................................................................... 25 Layout .......................................................................................... 37 Power Supplies ............................................................................ 25 Register Summary .......................................................................... 38 Power-Up Sequence ................................................................... 26 Register Details ............................................................................... 39 Power-Down Operation ............................................................ 26 Typical Application Circuit ........................................................... 57 Clocking ....................................................................................... 26 Outline Dimensions ....................................................................... 59 Digital Audio Serial Interface ................................................... 26 Ordering Guide .......................................................................... 59 REVISION HISTORY 5/2019--Rev. 0 to Rev. A Changes to Address: 0x04, Reset: 0xA1, Name: POWER_CTRL Section and Table 28....................................................................... 40 4/2016--Revision 0: Initial Version Rev. A| Page 2 of 59 Data Sheet SSM3582 GENERAL DESCRIPTION The SSM3582 is a fully integrated, high efficiency, digital input stereo Class-D audio amplifier. It can operate from a single supply, and requires only a few external components, significantly reducing the circuit bill of materials. The pulse code modulation (PCM) audio serial port supports most common protocols, such as I2S, left justified, and time division multiplexing (TDM), and can address up to 16 devices on a single interface, for up to 32 audio playback channels. A proprietary, spread spectrum - modulation scheme enables direct connection to the speaker, and ensures state-of-the-art analog performance while lowering radiated emissions compared to other Class-D architectures. An optional ultralow electromagnetic interference (EMI) mode significantly reduces radiated emissions above 100 MHz, enabling longer speaker cable lengths. Audio is transmitted digitally to the amplifier, minimizing the possibility of signal corruption in digital environments. The amplifier provides outstanding analog performance, with an over 106 dB signal-to-noise ratio and a vanishingly low 0.004% THD + N. IC operation is controlled through a dedicated I2C interface. The two ADDRx pins (2x, 5-level) define up to 16 individual addresses in I2C and standalone modes, and automatically set the default TDM slots attribution. The SSM3582 operates from a single 4.5 V to 16 V supply, and is capable of delivering 2 x 15 W rms continuously into 8 and 4 loads at <1% total harmonic distortion (THD). The efficient modulation scheme maintains excellent power efficiency over a wide range of impedances: 93% into an 8 load and 90% into a 4 load. Optimization of the output pulse maintains performance at impedances as low as 3 /5 H, enabling its use with extended bandwidth tweeters. A micropower shutdown mode is triggered by removing the digital audio interface clock, with a typical current of <1 A. A software power-down mode is also available. An automatic power-down feature shuts down the amplifier and the digital-to-analog converter (DAC) when no signal is present at the input, minimizing power consumption during digital silence. The device restarts when nonzero data is present at the input. Mute and unmute transitions are pop/click free. The SSM3582 is specified over the commercial temperature range of -40C to +85C. The device has built-in thermal shutdown and output short-circuit protection, as well as an early thermal warning with programmable gain limiting to maintain operation. The SSM3582 is available in a 40-lead, 6 mm x 6 mm lead frame chip scale package (LFCSP), with a thermal pad to improve heat dissipation. Rev. A| Page 3 of 59 SSM3582 Data Sheet SPECIFICATIONS PVDD = 12 V, AVDD = 5 V (external), DVDD = 1.8 V (external), RL = 8 + 33 H, BCLK = 3.072 MHz, FSYNC = 48 kHz, TA = -40C to +85C, unless otherwise noted. The measurements are taken with a 20 kHz AES17 low-pass filter. The other load impedances used are 4 + 15 H and 3 + 10 H. Measurements are taken with a 20 kHz AES17 low-pass filter, unless otherwise noted. Table 1. Parameter DEVICE CHARACTERISTICS Output Power Per Channel Stereo Mode Symbol Min Typ Max Unit PO f = 1 kHz, both channels driven RL = 8 , THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 16 V RL = 8 , THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V RL = 8 , THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V RL = 8 , THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 5 V RL = 8 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 16 V RL = 8 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V RL = 8 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V RL = 8 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 5 V RL = 4 , THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 16 V RL = 4 , THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V RL = 4 , THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V RL = 4 , THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 5 V RL = 4 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 16 V RL = 4 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V RL = 4 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V RL = 4 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 5 V f = 1 kHz RL = 3 , THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 16 V RL = 3 , THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V RL = 3 , THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V RL = 3 , THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 5 V RL = 3 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 16 V RL = 3 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V RL = 3 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V RL = 3 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 5 V RL = 2 , THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 16 V RL = 2 , THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V RL = 2 , THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V RL = 2 , THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 5 V RL = 2 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 16 V RL = 2 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V RL = 2 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V RL = 2 , THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 5 V Speaker inductance Mono Mode Minimal Load Inductance Efficiency Stereo Mode Test Conditions/Comments 14.4 8.1 2.76 1.41 18 10 3.43 1.75 25.6 14.67 5.06 2.6 31.76 18.31 6.3 3.21 W W W W W W W W W W W W W W W W 36.11 20.46 7 3.58 44.96 25.49 8.7 4.43 49.69 28.55 9.85 5 62.4 35.5 12.22 6.22 W W W W W W W W W W W W W W W W H Both channels driven PO = 10 W, RL = 8 , PVDD = 12 V PO = 10 W, RL = 8 , PVDD = 12 V (low EMI mode) PO = 18 W, RL = 4 , PVDD = 12 V PO = 15 W, RL = 4 , PVDD = 12 V (low EMI mode) 94 93.8 90.6 89.5 % % % % PO = 25 W, RL = 3 , PVDD = 12 V PO = 25 W, RL = 3 , PVDD = 12 V (low EMI mode) PO = 35 W, RL = 2 , PVDD = 12 V PO = 35 W, RL = 2 , PVDD = 12 V (low EMI mode) 92.3 92.1 89.9 89.7 % % % % 5 Mono Mode Rev. A| Page 4 of 59 Data Sheet Parameter Total Harmonic Distortion + Noise Output Stage On Resistance Overcurrent Protection Trip Point Average Switching Frequency Differential Output Offset Voltage Crosstalk between Left and Right POWER SUPPLIES Supply Voltage Range Power Supply Rejection Ratio AC ANALOG GAIN Gain = 00 Gain = 01 Gain = 10 Gain = 11 SHUTDOWN CONTROL 1 Turn On Time, Volume Ramp Disabled fS = 12 kHz fS = 24 kHz fS = 48 kHz fS = 96 kHz fS = 192 kHz Turn On Time, Volume Ramp Enabled fS = 12 kHz fS = 24 kHz fS = 48 kHz fS = 96 kHz fS = 192 kHz Turn Off Time, Volume Ramp Disabled Turn Off Time, Volume Ramp Enabled fS = 12 kHz fS = 24 kHz fS = 48 kHz fS = 96 kHz fS = 192 kHz Output Impedance SSM3582 Symbol THD + N Test Conditions/Comments PO = 5 W into 8 , f = 1 kHz, PVDD = 12 V Min Typ 0.004 Max Unit % RON IOC 100 6 m A peak fSW 300 kHz AV = 19 dB 1 mV Measured at 1 kHz with regards to full-scale output 100 dB VOOS PVDD AVDD DVDD PSRR PSRRAC AV tWU tWUR tSD tSDR 4.5 4.5 1.62 VRIPPLE =100 mV rms at 1 kHz VRIPPLE =1 V rms at 1 kHz Measured with 0 dBFS input at 1 kHz PVDD 6.3 V PVDD 9 V PVDD 12.6 V PVDD = 16 V 5.0 1.8 16 5.5 1.98 V V V 86 88 dB dB 6.2 8.75 12.5 15.5 V peak V peak V peak V peak Time from SPWDN = 0 to output switching, DAC_HV = 1 or DAC_MUTE_x = 1, tWU = 4 FSYNC cycles to 7 FSYNC cycles + 7.68 ms Time from SPWDN = 0 to full volume output switching, DAC_HV = 0 and DAC_MUTE_x = 0, VOL_x = 0x40 tWUR = tWU + 15.83 ms tWUR = tWU + 15.83 ms tWUR = tWU + 15.83 ms tWUR = tWU + 7.92 ms tWUR = tWU + 0.99 ms Time from SPWDN = 1 to full power-down, DAC_HV = 1 or DAC_MUTE_x = 1 Time from SPWDN = 1 to full power-down, DAC_HV = 0 and DAC_MUTE_x = 0, VOL_x = 0x40 tSDR = tSD + 15.83 ms tSDR = tSD + 15.83 ms tSDR = tSD + 15.83 ms tSDR = tSD + 7.92 ms tSDR = tSD + 0.99 ms ZOUT 8.01 7.84 7.76 7.72 7.70 8.27 7.98 7.83 7.76 7.72 ms ms ms ms ms 23.84 23.67 23.59 15.64 8.69 24.10 23.81 23.66 15.68 8.71 ms ms ms ms ms s 100 15.932 15.932 15.932 8.016 1.09 100 Rev. A| Page 5 of 59 ms ms ms ms ms k SSM3582 Data Sheet Parameter NOISE PERFORMANCE 2 Output Voltage Noise Signal-to-Noise Ratio PVDD ADC PERFORMANCE PVDD Sense Full-Scale Range PVDD Sense Absolute Accuracy Resolution Temperature Sense ADC Temperature Sense Range Temperature Sense Accuracy DIE TEMPERATURE Overtemperature Warning Overtemperature Protection UNDERVOLTAGE FAULT AVDD PVDD 1 2 Symbol en SNR Test Conditions/Comments Stereo mode f = 20 Hz to 20 kHz, A weighted, PVDD = 12 V, 8 f = 20 Hz to 20 kHz, A weighted, PVDD = 16 V, 8 f = 20 Hz to 20 kHz, A weighted, PVDD = 12 V, 4 f = 20 Hz to 20 kHz, A weighted, PVDD = 16 V, 4 PO = 8.1 W, RL = 8 , AV = 19 dB, PVDD = 12 V, A weighted PO = 14.4 W, RL = 8 , AV = 21 dB, PVDD = 16 V, A weighted PO = 14.67 W, RL = 4 , AV = 19 dB, PVDD = 12 V, A weighted PO = 25.58 W, RL = 4 , AV = 21 dB, PVDD = 16 V, A weighted Min Typ Max PVDD with full-scale ADC output 3.8 16.2 V PVDD = 15 V -8 +8 LSB PVDD = 5 V Unsigned 8-bit output with 3.8 V offset -6 +6 LSB Bits +160 5 C C 117 145 C C 3.6 3.6 V V 37.8 38.5 36.8 36.3 106.5 108.9 106.3 108.9 V rms V rms V rms V rms dB dB dB dB 8 -60 Unit Guaranteed by design. Noise performance is based on the bench data for TA = -40C to +85C. Software master power-down indicates that the clocks are turned off. Automatic power-down indicates that there is no dither or zero input signal with clocks on; the device enters soft power-down after 2048 cycles of zero input values. Quiescent indicates triangular dither with zero input signal. All specifications are typical, with a 48 kHz sample rate, in stereo mode, unless otherwise noted. Table 2. Power Supply Current Consumption, No Load 1 Edge Rate Control Mode Normal Internal Regulator Disabled Enabled Low EMI Disabled Enabled 1 IPVDD Test Conditions Software master power-down Automatic power-down Quiescent Software master power-down Automatic power-down Quiescent Software master power-down Automatic power-down Quiescent Software master power-down Automatic power-down Quiescent PVDD = 5 V 0.065 0.065 2.54 0.065 209 9.78 0.065 0.065 2.56 0.065 209 9.69 PVDD = 12 V 0.065 0.065 4.94 0.065 286 12.38 0.065 0.065 5.01 0.065 286 12.09 N/A means not applicable. Rev. A| Page 6 of 59 PVDD = 16 V 0.065 0.065 6.25 0.065 329 14.05 0.065 0.065 6.31 0.065 329 13.74 IDVDD IAVDD PVDD = 1.8 V 2.68 43.72 0.945 N/A N/A N/A 2.68 43.72 0.945 N/A N/A N/A PVDD = 5 V 7.542 7.542 6.335 N/A N/A N/A 7.542 7.542 6.171 N/A N/A N/A Unit A A mA A A mA A A mA A A mA Data Sheet SSM3582 Table 3. Power Supply Current Consumption, 4 + 15 H 1 Edge Rate Control Mode Normal Internal Regulator Disabled Enabled Low EMI Disabled Enabled 1 IPVDD Test Conditions Software master power-down Automatic power-down Quiescent Software master power-down Automatic power-down Quiescent Software master power-down Automatic power-down Quiescent Software master power-down Automatic power-down Quiescent PVDD = 5 V 0.065 0.065 2.6 0.065 209 9.83 0.065 0.065 2.51 0.065 209 9.64 PVDD = 12 V 0.065 0.065 4.93 0.065 286 12.34 0.065 0.065 4.62 0.065 286 11.86 PVDD = 16 V 0.065 0.065 6.25 0.065 329 13.58 0.065 0.065 5.6 0.065 329 12.87 IDVDD IAVDD PVDD = 1.8 V 2.68 43.72 0.945 N/A N/A N/A 2.68 43.72 0.945 N/A N/A N/A PVDD = 5 V 7.542 7.542 6.477 N/A N/A N/A 7.542 7.542 6.182 N/A N/A N/A IDVDD IAVDD PVDD = 1.8 V 2.68 43.72 0.942 N/A N/A N/A 2.68 43.72 0.942 N/A N/A N/A PVDD = 5 V 7.542 7.542 6.432 N/A N/A N/A 7.542 7.542 6.232 N/A N/A N/A Unit A A mA A A mA A A mA A A mA N/A means not applicable. Table 4. Power Supply Current Consumption, 8 + 33 H 1 Edge Rate Control Mode Normal Internal Regulator Disabled Enabled Low EMI Disabled Enabled 1 IPVDD Test Conditions Software master power-down Automatic power-down Quiescent Software master power-down Automatic power-down Quiescent Software master power-down Automatic power-down Quiescent Software master power-down Automatic power-down Quiescent PVDD = 5 V 0.065 0.065 2.59 0.065 209 9.82 0.065 0.065 2.57 0.065 209 9.65 PVDD = 12 V 0.065 0.065 5.02 0.065 286 12.39 0.065 0.065 4.86 0.065 286 12.02 PVDD = 16 V 0.065 0.065 6.31 0.065 329 13.73 0.065 0.065 6.02 0.065 329 13.18 Unit A A mA A A mA A A mA A A mA N/A means not applicable. Table 5. Power-Down Current Parameter POWER-DOWN CURRENT Symbol IPVDD IAVDD IDVDD Test Conditions/Comments External AVDD = 5 V and DVDD = 1.8 V, software master power-down, no BCLK/FSYNC PVDD = 5 V PVDD = 12 V PVDD = 16 V AVDD = 5 V external DVDD = 1.8 V external Rev. A| Page 7 of 59 Min Typ 65 65 65 7.542 2.7 Max Unit nA nA nA A A SSM3582 Data Sheet DIGITAL INPUT/OUTPUT SPECIFICATIONS Table 6. Parameter INPUT VOLTAGE 1 BCLK, FSYNC, SDATA, SCL, and SDA Pins High (VIH) Low (VIL) INPUT LEAKAGE BCLK, FSYNC, SDATA, ADDRx, SCL, and SDA Pins High (IIH) Low (IIL) INPUT CAPACITANCE OUTPUT DRIVE STRENGTH1 SDA SAMPLE RATE (FSYNC FREQUENCY) 1 Min Typ 0.7 x DVDD -0.3 3 8 Max Unit 5.5 +0.3 x DVDD V V 1 1 5 A A pF 5 192 mA kHz Test Conditions/Comments The pull-up resistor for SCL and SDA must be scaled according to the external pull-up voltage in the system. The typical value for a pull-up resistor for 1.8 V is 2.2 k. DIGITAL TIMING SPECIFICATIONS All timing specifications are given for the default setting (I2S mode) of the serial input port. Table 7. Parameter I2C PORT fSCL tSCLH tSCLL tSCS tSCH tDS tDH tSCR tSCF tSDR tSDF tBFT Min Limit Max 400 0.26 0.5 0.26 0.26 50 0.14 120 120 120 120 0.5 Unit Description kHz s s s s ns s ns ns ns ns s SCL frequency SCL high SCL low Setup time; relevant for repeated start condition Hold time; after this period, the first clock is generated Data setup time Data hold time SCL rise time SCL fall time SDA rise time SDA fall time Bus free time (time between stop and start) Unit Description ns ns ns ns ns ns ns BCLK low pulse width BCLK high pulse width SDATA setup; time to BCLK rising SDATA hold; time from BCLK rising FSYNC setup time to BCLK rising FSYNC hold time to BCLK rising Minimum BCLK period DIGITAL INPUT TIMING SPECIFICATIONS Table 8. Parameter SERIAL PORT tBIL tBIH tSIS tSIH tLIS tLIH tBP TMIN 10 10 4 4 5 5 20 Limit TMAX Rev. A| Page 8 of 59 Data Sheet SSM3582 Digital Timing Diagrams tSDR tDS tSCH tSCH SDA tDH tSCR tSDF tSCLH tSCS tSCLL START CONDITION tSCF tBFT STOP CONDITION 13399-002 SCL Figure 2. I2C Port Timing tBIH tBP BCLK tBIL tLIH tLIS FSYNC SDATA LEFT-JUSTIFIED MODE tSIS MSB MSB - 1 tSIH SDATA I2C-JUSTIFIED MODE tSIS MSB tSIH tSIS MSB LSB tSIH tSIH Figure 3. Serial Input Port Timing PVDD tWU PVDD/2 OUTPUT I2C POWER-UP COMMAND Figure 4. Turn On Time, Hard Volume Rev. A| Page 9 of 59 13399-104 0V 13399-003 tSIS SDATA RIGHT-JUSTIFIED MODE SSM3582 Data Sheet tSD PVDD OUTPUT I2C POWER-DOWN COMMAND Figure 5. Turn Off Time, Hard Volume Rev. A| Page 10 of 59 13399-105 0V Data Sheet SSM3582 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25C, unless otherwise noted. THERMAL RESISTANCE Table 9. JA (junction to air) is specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. JA and JB are determined according to JESD51-9 on a 4-layer (2s2p) printed circuit board (PCB) with natural convection cooling. Parameter PVDD Supply Voltage DVDD Supply Voltage AVDD Supply Voltage PGND and AGND Differential Digital Input Pins FSYNC, BCLK, SDATA, SCL, SDA Analog Input Pins ADDRx AVDD_EN DVDD_EN ESD Susceptibility Human Body Model Charged Device Model Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) Rating -0.3 V to +17 V -0.3 V to +1.98 V -0.3 V to +5.5 V 0.3 V -0.3 V to +5.5 V -0.3 V to +1.98 V -0.3 V to +17 V -0.3 V to +5.5 V Table 10. Thermal Resistance Package Type 40-Lead, 6 mm x 6 mm LFCSP ESD CAUTION 2 kV 1 kV -65C to +150C -40C to +85C -65C to +150C 300C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A| Page 11 of 59 JA 27 JC 1.1 Unit C/W SSM3582 Data Sheet 40 39 38 37 36 35 34 33 32 31 BSTL+ OUTL+ OUTL+ PVDD PVDD PVDD PVDD OUTL- OUTL- BSTL- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SSM3582 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 PGND PGND DVDD ADDR1 ADDR0 AGND AVDD DVDD_EN PGND PGND NOTES 1. USE MULTIPLE VIAS TO CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON THE PCB. 13399-004 BSTR+ OUTR+ OUTR+ PVDD PVDD PVDD PVDD OUTR- OUTR- BSTR- 11 12 13 14 15 16 17 18 19 20 PGND 1 PGND 2 AVDD_EN 3 SCL 4 SDA 5 FSYNC 6 SDATA 7 BCLK 8 PGND 9 PGND 10 Figure 6. Pin Configuration Table 11. Pin Function Descriptions Pin No. 1 2 3 Mnemonic PGND PGND AVDD_EN Type1 PWR PWR AIN 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCL SDA FSYNC SDATA BCLK PGND PGND BSTR+ OUTR+ OUTR+ PVDD PVDD PVDD PVDD OUTR- OUTR- BSTR- PGND PGND DVDD_EN DIN DIO DIN DIN DIN PWR PWR AIN AOUT AOUT PWR PWR PWR PWR AOUT AOUT AIN PWR PWR AIN 24 25 26 27 28 29 30 31 AVDD AGND ADDR0 ADDR1 DVDD PGND PGND BSTL- PWR PWR AIN AIN PWR PWR PWR AIN Description Left Channel Power Stage Ground. Left Channel Power Stage Ground. 5 V AVDD Regulator Enable. Connect this pin to PVDD to enable the AVDD regulator or connect to AGND to disable the regulator. When this pin is connected to PVDD, the regulator is enabled. When this pin is connected to AGND, the regulator is disabled. I2C Clock Input. I2C Data. I2S/TDM Frame Sync (FSYNC) Input. I2S/TDM Serial Data (SDATA) Input. I2S/TDM Bit Clock (BCLK) Input. Right Channel Power Stage Ground. Right Channel Power Stage Ground. Bootstrap Input, Right Channel Noninverting. Right Channel Noninverting Output. Right Channel Noninverting Output. Right Channel Power Stage Supply. Right Channel Power Stage Supply. Right Channel Power Stage Supply. Right Channel Power Stage Supply. Right Channel Inverting Output. Right Channel Inverting Output. Bootstrap Input, Right Channel Inverting. Right Channel Power Stage Ground. Right Channel Power Stage Ground. 1.8 V DVDD Regulator Enable. Connect this pin to AVDD to enable the DVDD regulator or connect to AGND to disable the regulator. When this pin is connected to AVDD, the regulator is enabled. When this pin is connected to AGND, the regulator is disabled. Analog Supply 5 V Regulator Output/External 5 V Input. Analog Ground. Address Select 0 (See Table 14). Address Select 1 (See Table 14). Digital Supply 1.8 V Regulator Output/External 1.8 V Input. Left Channel Power Stage Ground. Left Channel Power Stage Ground. Bootstrap Input, Left Channel Inverting. Rev. A| Page 12 of 59 Data Sheet Pin No. 32 33 34 35 36 37 38 39 40 1 Mnemonic OUTL- OUTL- PVDD PVDD PVDD PVDD OUTL+ OUTL+ BSTL+ EPAD SSM3582 Type 1 AOUT AOUT PWR PWR PWR PWR AOUT AOUT AIN Description Left Channel Inverting Output. Left Channel Inverting Output. Left Channel Power Stage Supply. Left Channel Power Stage Supply. Left Channel Power Stage Supply. Left Channel Power Stage Supply. Left Channel Noninverting Output. Left Channel Noninverting Output. Bootstrap Input, Left Channel Noninverting. Exposed Pad. Use multiple vias to connect the exposed pad to the ground plane on the PCB. PWR is power supply or ground pin, AIN is analog input, DIN is digital input, DIO is digital input/output, and AOUT is analog output. Rev. A| Page 13 of 59 SSM3582 Data Sheet FREQUENCY (Hz) 20k 10k 5k 2k 3k 13399-009 20k 10k 5k 3k 2k 1k FREQUENCY (Hz) 20k 10k 5k 3k 2k 1k 500 300 200 100 13399-010 NO SIGNAL ANALOG GAIN = 8.9V peak RL = 4 (LOW EMI) 20 30 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 50 AMPLITUDE (dBV) 13399-007 20k 10k 5k 3k 2k 1k 500 300 200 100 50 500 FREQUENCY (Hz) Figure 11. Amplitude vs. Frequency, No Signal, Analog Gain = 6.3 V peak 60dBFS INPUT ANALOG GAIN = 12.6V peak RL = 4 (LOW EMI) 20 30 300 200 100 20 30 FREQUENCY (Hz) AMPLITUDE (dBV) 1k NO SIGNAL ANALOG GAIN = 6.3V peak RL = 4 (LOW EMI) 50 AMPLITUDE (dBV) 13399-006 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20k 10k 5k 3k 2k 1k 500 300 200 100 50 30 20 AMPLITUDE (dBV) Figure 10. Amplitude vs. Frequency, 60 dBFS Input, Analog Gain = 16 V peak 60dBFS INPUT ANALOG GAIN = 8.9V peak RL = 4 (LOW EMI) Figure 8. Amplitude vs. Frequency, 60 dBFS Input, Analog Gain = 8.9 V peak 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 500 FREQUENCY (Hz) Figure 7. Amplitude vs. Frequency, 60 dBFS Input, Analog Gain = 6.3 V peak 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 300 200 100 13399-008 60dBFS INPUT ANALOG GAIN = 16V peak RL = 4 (LOW EMI) 20 30 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20k 10k 5k 3k 2k 1k 500 300 200 100 50 13399-005 AMPLITUDE (dBV) 60dBFS INPUT ANALOG GAIN = 6.3V peak RL = 4 (LOW EMI) 50 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 30 AMPLITUDE (dBV) TYPICAL PERFORMANCE CHARACTERISTICS FREQUENCY (Hz) Figure 9. Amplitude vs. Frequency, 60 dBFS Input, Analog Gain = 12.6 V peak Figure 12. Amplitude vs. Frequency, No Signal, Analog Gain = 8.9 V peak Rev. A| Page 14 of 59 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 SSM3582 1.000 NO SIGNAL ANALOG GAIN = 12.6V peak RL = 4 (LOW EMI) RL = 4 PVDD = 12V 0.500 0.200 0.050 0.020 100mW 0.010 1W 5W 0.002 0.001 20 20k 10k 5k 3k 2k 1k 500 300 200 100 50 13399-011 0.005 13399-014 THD + N (%) 0.100 20 30 AMPLITUDE (dBV) Data Sheet 50 100 200 500 2k 1k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 16. THD + N vs. Frequency, RL = 4 , PVDD = 12 V 1.000 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 NO SIGNAL ANALOG GAIN = 16V peak RL = 4 (LOW EMI) 0.500 RL = 4 PVDD = 16V 0.200 THD + N (%) 0.100 0.050 0.020 100mW 0.010 1W 13399-015 10W 0.002 0.001 20 20k 10k 5k 3k 2k 1k 500 300 200 100 50 13399-012 0.005 20 30 AMPLITUDE (dBV) Figure 13. Amplitude vs. Frequency, No Signal, Analog Gain = 12.6 V peak 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 17. THD + N vs. Frequency, RL = 4 , PVDD = 16 V Figure 14. Amplitude vs. Frequency, No Signal, Analog Gain = 16 V peak 1.000 1.000 0.500 0.200 0.100 0.100 THD + N (%) 0.200 0.050 0.020 0.010 RL = 8 PVDD = 4.5V 0.050 0.020 0.010 100mW 100mW 0.005 0.005 500mW 0.002 0.001 20 50 100 200 500 1k 2k 5k 10k 13399-016 1W 13399-013 THD + N (%) 0.500 RL = 4 PVDD = 4.5V peak 0.002 0.001 20 20k 50 100 200 500 1k 2k 5k 10k FREQUENCY (Hz) FREQUENCY (Hz) Figure 18. THD + N vs. Frequency, RL = 8 , PVDD = 4.5 V Figure 15. THD + N vs. Frequency, RL = 4 , PVDD = 4.5 V peak Rev. A| Page 15 of 59 20k SSM3582 Data Sheet 1.000 10 RL = 8 PVDD = 12V 0.500 RL = 4 ANALOG GAIN = 8.9V peak 5 0.100 0.500 THD + N (%) 1.000 0.050 0.020 0.010 100mW 4.5V 12.0V 16.0V (3dB GAIN ADDED) 0.200 0.100 0.050 0.020 0.010 1W 10k 0.001 20k 50 5k 5 10 20 2k 500m 1 2 1k 50m 500 FREQUENCY (Hz) 100m 200m 200 5m 10m 20m 100 500 1m 2m 50 10 20 0.002 50 100 200 0.001 13399-020 0.005 5W 0.002 20 0.005 13399-017 THD + N (%) 2 0.200 POWER (W) Figure 22. THD + N vs. Power, RL = 4 , Analog Gain = 8.9 V peak Figure 19. THD + N vs. Frequency, RL = 8 , PVDD = 12 V 10 1.000 RL = 8 PVDD = 16V 0.500 RL = 4 ANALOG GAIN = 12.6V peak 5 0.200 1.000 0.100 0.500 THD + N (%) THD + N (%) 2 0.050 0.020 0.010 100mW 0.005 1W 0.002 5W 4.5V 12.0V 16.0V 0.200 0.100 0.050 0.020 0.010 0.002 0.001 20k FREQUENCY (Hz) 50 10k 5 10 20 5k 500m 1 2 2k 50m 1k 100m 200m 500 5m 10m 20m 200 500 1m 2m 100 50 100 200 50 10 20 20 0.001 13399-021 13399-018 0.005 POWER (W) Figure 23. THD + N vs. Power, RL = 4 , Analog Gain = 12.6 V peak Figure 20. THD + N vs. Frequency, RL = 8 , PVDD = 16 V 10 2 2 1.000 1.000 0.500 0.100 0.010 0.005 0.005 0.002 50 5 10 20 0.001 500m 1 2 50 5 10 20 500m 1 2 50m 100m 200m 5m 10m 20m 500 1m 2m 50 100 200 20 0.001 5m 10m 20m 0.002 10 13399-019 0.020 0.010 13399-022 0.050 0.020 500 1m 2m 0.050 50 100 200 0.100 4.5V 12.0V 16.0V 0.200 20 0.200 THD + N (%) 4.5V 7.0V 16.0V 10 THD + N (%) 0.500 RL = 4 ANALOG GAIN = 16V peak 5 50m RL = 4 ANALOG GAIN = 6.3V peak 5 100m 200m 10 POWER (W) POWER (W) Figure 24. THD + N vs. Power, RL = 4 , Analog Gain = 16 V peak Figure 21. THD + N vs. Power, RL = 4 , Analog Gain = 6.3 V peak Rev. A| Page 16 of 59 Data Sheet SSM3582 10 10 RL = 8 ANALOG GAIN = 6.3V peak 2 2 1.000 1.000 0.500 0.100 0.020 0.010 0.010 0.005 0.005 0.002 50 5 10 20 POWER (W) Figure 25. THD + N vs. Power, RL = 8 , Analog Gain = 6.3 V peak Figure 28. THD + N vs. Power, RL = 8 , Analog Gain = 16 V peak 7 10 RL = 8 ANALOG GAIN = 8.9V peak 5 ANALOG GAIN = 6.3V peak RL = 4 POUT = 10% 6 2 POUT = 1% 1.000 5 0.500 4.5V 12.0V 16.0V 0.200 POWER (W) THD + N (%) 500m 1 2 10u POWER (W) 50m 0.001 50 5 10 20 500m 1 2 50m 100m 200m 5m 10m 20m 500 1m 2m 50 100 200 20 10 0.001 100m 200m 0.002 13399-026 0.050 0.020 5m 10m 20m 0.050 500u 1m 2m 0.100 4.5V 12.0V 16.0V 0.200 50u 100u 200u 0.200 THD + N (%) 4.5V 7.0V 16.0V 13399-023 THD + N (%) 0.500 RL = 8 ANALOG GAIN = 16V peak 5 20u 5 0.100 0.050 4 3 0.020 2 0.010 0.005 0 50 5 10 20 500m 1 2 50m 100m 200m 5m 10m 20m 500 1m 2m 50 100 200 20 10 0.001 13399-028 1 13399-024 0.002 5 6 7 8 9 10 11 12 PVDD (V) POWER (W) Figure 29. Power vs. PVDD, RL = 4 , Analog Gain = 6.3 V peak Figure 26. THD + N vs. Power, RL = 8 , Analog Gain = 8.9 V peak 14 10 ANALOG GAIN = 8.9V peak RL = 4 RL = 8 ANALOG GAIN = 12.6V peak 5 POUT = 10% 12 2 POUT = 1% 1.000 10 POWER (W) 4.5V 12.0V 16.0V 0.200 0.100 0.050 8 6 0.020 4 0.010 0.002 0 50 5 10 20 500m 1 2 50m 100m 200m 5m 10m 20m 500 1m 2m 50 100 200 20 0.001 2 13399-027 13399-025 0.005 10 THD + N (%) 0.500 7 8 9 10 11 12 PVDD (V) POWER (W) Figure 27. THD + N vs. Power, RL = 8 , Analog Gain = 12. 6 V peak Figure 30. Power vs. PVDD, RL = 4 , Analog Gain = 8.9 V peak Rev. A| Page 17 of 59 SSM3582 Data Sheet 100 30 ANALOG GAIN = 12.6V peak RL = 4 90 POUT = 10% 25 80 POUT = 1% 70 EFFICIENCY (%) 15 10 60 NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 8.9V peak RL = 4 PVDD = 7V 50 40 30 20 13399-029 5 7 9 11 13 13399-032 POWER (W) 20 0 NORMAL EMI LOW EMI 10 0 15 0 1 2 3 4 5 6 7 POUT (W) PVDD (V) Figure 31. Power vs. PVDD, RL = 4 , Analog Gain = 12.6 V peak Figure 34. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 8.9 V peak, RL = 4 , PVDD = 7 V 100 35 ANALOG GAIN = 16V peak RL = 4 90 30 80 NORMAL EMI LOW EMI 70 EFFICIENCY (%) POWER (W) 25 POUT = 10% 20 POUT = 1% 15 NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 12.6V peak RL = 4 PVDD = 12V 60 50 40 30 10 13399-030 0 7 9 11 13 13399-033 20 5 10 0 15 0 2.5 5.0 PVDD (V) 12.5 15.0 17.5 20.0 Figure 35. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 12.6 V peak, RL = 4 , PVDD = 12 V 100 100 90 90 80 NORMAL EMI LOW EMI 70 NORMAL EMI LOW EMI NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 6.3V peak RL = 4 PVDD = 5V 50 40 50 40 30 30 20 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 16V peak RL = 4 PVDD = 16V 60 13399-034 EFFICIENCY (%) 70 60 13399-031 EFFICIENCY (%) 10.0 POUT (W) Figure 32. Power vs. PVDD, RL = 4 , Analog Gain = 16 V peak 80 7.5 10 0 3.5 0 POUT (W) 5 10 15 20 25 30 35 POUT (W) Figure 33. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 6.3 V peak, RL = 4 , PVDD = 5 V Figure 36. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 16 V peak, RL = 4 , PVDD = 16 V Rev. A| Page 18 of 59 Data Sheet SSM3582 100 100 90 90 80 80 NORMAL EMI LOW EMI NORMAL EMI LOW EMI FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 6.3V peak RL = 4 PVDD = 5V 50 40 50 40 30 30 20 20 10 0 0 1.0 0.5 1.5 2.0 2.5 3.0 FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 16V peak RL = 4 PVDD = 16V 60 13399-038 60 EFFICIENCY (%) 70 13399-035 EFFICIENCY (%) 70 10 0 3.5 0 5 10 15 POUT (W) 20 25 30 35 POUT (W) Figure 37. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 6.3 V peak, RL = 4 , PVDD = 5 V Figure 40. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 16 V peak, RL = 4 , PVDD = 16 V 100 0.010 NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 12.6V peak RL = 4 90 80 0.008 NORMAL EMI LOW EMI 60 FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 8.9V peak RL = 4 PVDD = 7V 50 IPVDD (A) EFFICIENCY (%) 70 40 0.006 NORMAL EMI LOW EMI 0.004 30 20 0 0 1 2 3 4 5 6 13399-039 13399-036 0.002 10 0 5 7 7 9 POUT (W) Figure 38. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 8.9 V peak, RL = 4 , PVDD = 7 V 15 Figure 41. IPVDD vs. PVDD, No Ferrite Bead, Analog Gain = 12.6 V peak, RL = 4 100 0.010 NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 12.6V peak RL = 4 90 80 0.008 NORMAL EMI LOW EMI NORMAL EMI 70 FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 12V peak RL = 4 PVDD = 12V 60 50 IPVDD (A) EFFICIENCY (%) 13 11 PVDD (V) 40 LOW EMI 0.006 0.004 30 20 0 0 5 10 15 13399-040 13399-037 0.002 10 0 20 5 POUT (W) 7 9 11 13 15 PVDD (V) Figure 39. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 12 V peak, RL = 4 , PVDD = 12 V Rev. A| Page 19 of 59 Figure 42. IPVDD vs. PVDD, No Ferrite Bead, Analog Gain = 12.6 V peak, RL = 4 SSM3582 Data Sheet 20 3.5 ANALOG GAIN = 6.3V peak RL = 8 POUT = 10% ANALOG GAIN = 16V peak RL = 8 18 3.0 16 POUT = 1% 14 POWER (W) POWER (W) 2.5 2.0 1.5 POUT = 10% 12 10 POUT = 1% 8 6 1.0 13399-041 0 5 6 7 8 9 10 11 13399-044 4 0.5 2 0 12 7 8 9 11 10 12 13 14 15 16 PVDD (V) PVDD (V) Figure 46. Power vs. PVDD, Analog Gain = 16 V peak, RL = 8 Figure 43. Power vs. PVDD, Analog Gain = 6.3 V peak, RL = 8 100 7 ANALOG GAIN = 8.9V peak RL = 8 POUT = 10% 90 6 80 POUT = 1% NORMAL EMI LOW EMI 70 EFFICIENCY (%) POWER (W) 5 4 3 60 NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 6.3V peak RL = 8 PVDD = 5V 50 40 30 2 13399-042 0 7 8 9 10 10 0 12 11 13399-045 20 1 0 0.5 1.0 1.5 2.0 POUT (W) PVDD (V) Figure 47. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 6.3 V peak, RL = 8 , PVDD = 5 V Figure 44. Power vs. PVDD, Analog Gain = 8.9 V peak, RL = 8 14 100 ANALOG GAIN = 12.6V peak RL = 8 POUT = 10% 90 12 80 POUT = 1% NORMAL EMI LOW EMI EFFICIENCY (%) 70 8 6 60 NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 8.9V peak RL = 8 PVDD = 7V 50 40 30 4 0 7 8 9 10 11 12 13 14 15 10 0 16 PVDD (V) Figure 45. Power vs. PVDD, Analog Gain = 12.6 V peak, RL = 8 13399-046 20 2 13399-043 POWER (W) 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 POUT (W) Figure 48. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 8.9 V peak, RL = 8 , PVDD = 7 V Rev. A| Page 20 of 59 Data Sheet SSM3582 100 100 90 90 80 80 NORMAL EMI LOW EMI NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 12.6V peak RL = 8 PVDD = 12V 50 40 60 50 40 30 30 20 20 10 0 2 4 6 10 8 FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 8.9V peak RL = 8 PVDD = 7V 13399-050 EFFICIENCY (%) 60 0 NORMAL EMI LOW EMI 70 13399-047 EFFICIENCY (%) 70 10 0 12 0 0.5 1.0 1.5 POUT (W) Figure 49. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 12.6 V peak, RL = 8 , PVDD = 12 V 100 90 90 80 NORMAL EMI LOW EMI 50 40 4.0 NORMAL EMI LOW EMI 60 40 30 20 20 0 5 10 10 0 20 15 FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 12.6V peak RL = 8 PVDD = 12V 50 30 10 0 2.5 5.0 POUT (W) 7.5 10.0 12.5 POUT (W) Figure 50. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 16 V peak, RL = 8 , PVDD = 16 V Figure 53. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 12.6 V peak, RL = 8 , PVDD = 12 V 100 100 90 90 80 80 NORMAL EMI LOW EMI 70 NORMAL EMI LOW EMI 70 EFFICIENCY (%) FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 6.3V peak RL = 8 PVDD = 5V 60 50 40 30 FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 16V peak RL = 8 PVDD = 16V 60 50 40 30 20 13399-049 20 10 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 13399-052 EFFICIENCY (%) 3.5 13399-051 EFFICIENCY (%) NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 16V peak RL = 8 PVDD = 16V 60 0 3.0 70 13399-048 EFFICIENCY (%) 70 0 2.5 Figure 52. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 8.9 V peak, RL = 8 , PVDD = 7 V 100 80 2.0 POUT (W) 10 0 2.00 POUT (W) 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 POUT (W) Figure 51. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 6.3 V peak, RL = 8 , PVDD = 5 V Figure 54. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 16 V peak, RL = 8 , PVDD = 16 V Rev. A| Page 21 of 59 SSM3582 Data Sheet 100 100 90 90 80 80 NORMAL EMI LOW EMI 50 40 60 40 30 30 20 20 10 0 0 1 2 3 6 5 4 NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 16V peak (MONO) RL = 2 PVDD = 16V 50 13399-056 EFFICIENCY (%) NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 6.3V peak (MONO) RL = 2 PVDD = 5V 60 13399-053 EFFICIENCY (%) NORMAL EMI LOW EMI 70 70 10 0 7 0 10 20 30 POUT (W) Figure 55. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 6.3 V peak, RL = 2 , PVDD = 5 V 100 90 90 80 NORMAL EMI LOW EMI NORMAL EMI LOW EMI NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 8.9V peak (MONO) RL = 2 PVDD = 7V 60 50 40 50 40 30 30 20 20 10 0 0 2 4 6 8 10 12 NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 6.3V peak (MONO) RL = 3 PVDD = 5V 60 13399-057 EFFICIENCY (%) 70 13399-054 EFFICIENCY (%) 70 10 0 14 0 0.5 1.0 1.5 2.0 POUT (W) 100 90 90 80 NORMAL EMI LOW EMI 70 3.5 4.0 4.5 5.0 NORMAL EMI LOW EMI NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 12.6V peak (MONO) RL = 2 PVDD = 12.6V 60 50 40 50 40 30 30 20 20 10 0 5 10 15 20 25 30 35 NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 8.9V peak (MONO) RL = 3 PVDD = 7V 60 13399-058 EFFICIENCY (%) 70 13399-055 EFFICIENCY (%) 3.0 Figure 59. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 6.3 V peak, RL = 3 , PVDD = 5 V 100 80 2.5 POUT (W) Figure 56. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 8.9 V peak, RL = 2 , PVDD = 7 V 0 70 60 50 Figure 58. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 16 V peak, RL = 2 , PVDD = 16 V 100 80 40 POUT (W) 10 0 40 0 1 2 3 4 5 6 7 8 9 10 POUT (W) POUT (W) Figure 57. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 12.6 V peak, RL = 2 , PVDD = 12.6 V Figure 60. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 8.9 V peak, RL = 3 , PVDD = 7 V Rev. A| Page 22 of 59 Data Sheet SSM3582 30 100 ANALOG GAIN = 8.9V peak (MONO) RL = 2 90 80 25 NORMAL EMI LOW EMI POUT = 10% 20 NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 12.6V peak (MONO) RL = 3 PVDD = 12V 60 50 POWER (W) 40 15 10 30 20 13399-059 5 10 0 POUT = 1% 0 5 10 15 20 25 0 30 13399-062 EFFICIENCY (%) 70 7 8 9 Figure 61. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 12.6 V peak, RL = 3 , PVDD = 12 V 12 60 ANALOG GAIN = 12.6V peak (MONO) RL = 2 90 80 50 NORMAL EMI LOW EMI POUT = 10% 70 40 NO FERRITE BEAD, 220pF CAPACITOR ANALOG GAIN = 16V peak (MONO) RL = 3 PVDD = 16V 60 50 POWER (W) 40 POUT = 1% 30 20 30 20 13399-060 10 10 0 5 10 15 20 25 30 35 40 45 0 50 13399-063 EFFICIENCY (%) 11 Figure 64. Power vs. PVDD, Analog Gain = 8.9 V peak, RL = 2 100 0 10 PVDD (V) POUT (W) 7 8 9 10 11 12 13 14 15 16 PVDD (V) POUT (W) Figure 62. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 16 V peak, RL = 3 , PVDD = 16 V Figure 65. Power vs. PVDD, Analog Gain = 12.6 V peak, RL = 2 70 14 ANALOG GAIN = 16V peak MONO) RL = 2 ANALOG GAIN = 8.9V peak (MONO) RL = 4 60 12 POUT = 10% 10 50 POUT = 10% 6 40 POUT = 1% 30 4 20 2 10 0 5 6 7 8 9 10 11 0 12 13399-064 POWER (W) 8 13399-061 POWER (W) POUT = 1% 7 8 9 10 11 12 13 14 15 16 PVDD (V) PVDD (V) Figure 63. Power vs. PVDD, Analog Gain = 8.9 V p-p, RL = 4 Figure 66. Power vs. PVDD, Analog Gain = 16 V peak, RL = 2 Rev. A| Page 23 of 59 SSM3582 Data Sheet 9 35 ANALOG GAIN = 6.3V peak (MONO) RL = 4 8 ANALOG GAIN = 12.6V peak (MONO) RL = 3 POUT = 10% 30 7 POUT = 1% 25 POUT = 10% POWER (W) POWER (W) 6 5 4 POUT = 1% 20 15 3 10 2 0 5 6 7 8 9 10 11 0 12 13399-067 5 13399-065 1 7 8 9 10 PVDD (V) 12 13 14 15 16 PVDD (V) Figure 67. Power vs. PVDD, Analog Gain = 6.3 V peak, RL = 4 Figure 69. Power vs. PVDD, Analog Gain = 12.6 V peak, RL = 3 50 18 ANALOG GAIN = 8.9V peak (MONO) RL = 3 16 14 ANALOG GAIN = 16V peak (MONO) RL = 3 POUT = 10% 45 40 POUT = 1% 35 POWER (W) 12 10 8 6 POUT = 10% 30 25 POUT = 1% 20 15 4 0 7 8 9 10 11 13399-068 10 2 13399-066 POWER (W) 11 5 0 12 PVDD (V) 7 8 9 10 11 12 13 14 15 16 PVDD (V) Figure 68. Power vs. PVDD, Analog Gain = 8.9 V peak RL = 3 Figure 70. Power vs. PVDD, Analog Gain = 16 V peak, RL = 3 Rev. A| Page 24 of 59 Data Sheet SSM3582 THEORY OF OPERATION OVERVIEW POWER SUPPLIES The SSM3582 is a stereo, Class-D audio amplifier with a filterless modulation scheme that greatly reduces external component count, conserving board space and reducing system cost. The SSM3582 does not require an output filter; it relies on the inherent inductance of the speaker coil and the natural filtering of the speaker and human ear to recover the audio component of the square wave output. Most Class-D amplifiers use some variation of pulsewidth modulation (PWM) to generate the output switching pattern, whereas the SSM3582 uses - modulation, resulting in important benefits. - modulators do not produce a sharp peak with many harmonics in the AM broadcast band, as pulsewidth modulators often do. - modulation reduces the amplitude of spectral components at high frequencies, reducing EMI emission that may otherwise radiate from speakers and long cable traces. Due to the inherent spread spectrum nature of - modulation, the need for oscillator synchronization is eliminated for designs incorporating multiple SSM3582 amplifiers. The SSM3582 uses less power in quiescent conditions, which helps conserve the power drawn from the battery or power supply. PVDD PVDD supplies the output power stages, as well as the low dropout (LDO) regulator for AVDD and DVDD. AVDD AVDD is the analog supply used for the modulator, power stage driver, and other analog blocks. When the AVDD_EN pin = PVDD, the internal regulator generates 5 V and the AVDD pin is used for decoupling only. When the AVDD_EN pin = AGND, 5 V must be provided to the AVDD pin from an external system source, minimizing power losses. DVDD DVDD supplies the digital circuitry. The current in this node is very low, below 1 mA. When the DVDD_EN pin = AVDD, the internal regulator generates 1.8 V and the DVDD pin is used for decoupling only. When the DVDD_EN pin = AGND, 1.8 V must be provided to the DVDD pin from an external system source, minimizing power losses. The SSM3582 integrates overcurrent and temperature protection and a thermal warning with optional programmable automatic gain reduction. Table 12 summarizes the power dissipation in various supply configurations, operating modes, and load characteristics. Table 12. Typical Power Supply Current Consumption for fS = 48 kHz 1 5 AVDD_ EN Pin Low Load No load PVDD No load Low 8 + 33 H PVDD 8 + 33 H 1 Test Conditions SPWDN = 1 Automatic power-down Dither input SPWDN = 1 Automatic power-down Dither input SPWDN = 1 Automatic power-down Dither input SPWDN = 1 Automatic power-down Dither input PVDD (V) 12 Total Power (mW) IPVDD (mA) 0.000065 0.043314 0.000065 0.117186 IPVDD (mA) 0.000065 0.000065 Total Power (mW) 0.043574 0.117446 16 AVDD Pin External External IAVDD (mA) 0.007542 0.007542 IDVDD (mA) 0.00268 0.04372 IPVDD (mA) 0.000065 0.000065 Total Power (mW) 0.042859 0.116731 External Internal Internal 6.335 N/A N/A 0.945 N/A N/A 2.54 0.000065 0.209 46.076 0.000325 1.045 4.94 0.000065 0.286 92.656 0.00078 3.432 6.25 0.000065 0.329 133.376 0.00104 5.264 Internal External External N/A 0.007542 0.007542 N/A 0.00268 0.04372 9.78 0.000065 0.000065 48.9 0.042859 0.116731 12.38 0.000065 0.000065 148.56 0.043314 0.117186 14.05 0.000065 0.000065 224.8 0.043574 0.117446 External Internal Internal 6.432 N/A N/A 0.942 N/A N/A 2.59 0.000065 0.209 46.8056 0.000325 1.045 5.02 0.000065 0.286 94.0956 0.00078 3.432 6.31 0.000065 0.329 134.8156 0.00104 5.264 Internal N/A N/A 9.82 49.1 12.39 148.68 13.73 219.68 N/A means not applicable. Rev. A| Page 25 of 59 SSM3582 Data Sheet POWER-UP SEQUENCE CLOCKING Using Only PVDD as a Source A BCLK signal must be provided to the SSM3582 for proper operation. The BCLK signal must have a minimum frequency of 2.048 MHz. The BCLK rate is autodetected, but the sampling frequency must be indicated. The BCLK rates supported at 32 kHz to 48 kHz are 50, 64, 100, 128, 192, 200, 256, 384, 400, 512, 768, 800, and 1024 times the sample rate. When SSM3582 is used in single-supply mode, all internal rails are generated from PVDD. The internal AVDD (5 V) and DVDD (1.8 V) regulators can be enabled by pulling the AVDD_EN and DVDD_EN pins high. AVDD_EN is pulled to PVDD, and DVDD_EN is pulled to AVDD. The amplifier is operational and responds to I2C writes 10 ms after applying PVDD 5 V. Using PVDD and External AVDD Take care when an external 5 V is supplied to AVDD. The internal 5 V LDO must be disabled by pulling the AVDD_EN pin low. In this case, DVDD (1.8 V) is generated from PVDD. It is important to maintain PVDD > AVDD to prevent the back powering of PVDD. Using PVDD and External AVDD and DVDD DIGITAL AUDIO SERIAL INTERFACE The SSM3582 includes a standard serial audio interface that is slave only. The interface is capable of receiving I2S, left justified, PCM, or TDM formatted data. The serial interfaces have three main operating modes. The stereo modes, typically I2S or left justified, are used when there is a single chip on the interface bus. TDM mode is more flexible and offers the ability to have multiple chips on the bus. Stereo Operating Modes--I2S, Left Justified If using an external AVDD and DVDD source, both the AVDD_EN and DVDD_EN pins must be pulled low. It is important to maintain PVDD > AVDD/DVDD to prevent back powering PVDD. Stereo modes use both edges of FSYNC to determine the placement of data. Stereo mode is enabled when SAI_MODE = 0, and the I2S or left justified format is determined by the SDATA_ FMT register setting. DVDD must be present for the device to respond to I2C commands. The device becomes operational ~10 ms after DVDD is present. PVDD must be at least 5 V for the output stage to turn on, and must be 6 V for optimal performance. The I2S or left justified interface formats supports various BCLK/ FSYNC ratios (see Table 13). Sample rates from 8 kHz to 192 kHz are accepted. POWER-DOWN OPERATION TDM Operating Mode The SSM3582 offers several power-down options via the I2C. Register 0x04 provides multiple options for setting the various power-down modes. The TDM operating mode allows multiple chips to connect to a single serial interface. When set to 1, the SPWDN bit fully powers down the device. In this case, only the I2C and 1.8 V regulator blocks, if enabled via the DVDD_EN pin, are kept active. The SSM3582 monitors both the BCLK and FSYNC pins for clock presence. When no BCLK is present, the device automatically powers down all internal circuitry to its lowest power state. When BCLK returns, the device automatically powers up following its usual power sequence. To guarantee click/pop free shutdown, power down the device via the SPDWN control before clock removal. If enabled, the APWDN_EN bit activates a low power state after 2048 consecutive zero input samples are received. Only the I2C and digital audio input blocks are kept active. Individual channels can be powered down using Bits[3:2] in Register 0x04. The temperature sense ADC can be powered down using Bit 5 in Register 0x04. The FSYNC signal operates at the desired sample rate. A rising edge of the FSYNC signal indicates the start of a new frame. For proper operation, this signal must be one BCLK cycle wide, transitioning on a falling BCLK edge. The MSB of data is present on the SDATA signal one BCLK cycle later. The SDATA signal is latched on a rising edge of BCLK. Each chip on the TDM bus can occupy 16, 24, 32, 48, or 64 BCLK cycles, set via the TDM_BCLKS control bits. The maximum number of devices connected to a single TDM bus depends on the sample rate and number of bits per channel. The supported combinations of sample rates and bit depths are described in Table 13. The maximum bit clock frequency is 49.152 MHz. Using the TDM16 format, up to eight devices (16 channels) can be connected to a single TDM interface, and can operate at up to a 96k sample rate and at 32 bits per channel. See Table 13 for the supported options at the 48 kHz, 96 kHz, and 192 kHz sample rates. Note that the interface is slave only, with the bit clock, frame sync, and data provided to the device. ADDRx pin settings dictate the default TDM slots for each device, and can be modified using the TDM_SLOT control register. Rev. A| Page 26 of 59 Data Sheet SSM3582 Table 13. Supported BCLK Rates in MHz 1 Sample Rate (kHz) 8 to 12 16 to 24 32 to 48 64 to 96 128 to 192 1 2 50 64 100 128 192 200 N/A N/A Yes Yes Yes N/A N/A Yes Yes Yes N/A Yes Yes Yes Yes N/A Yes Yes Yes Yes N/A Yes Yes Yes Yes Yes Yes Yes Yes Yes BCLK/FSYNC Ratio 256 384 BCLK (MHz) 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes N/A 512 768 800 1024 2048 4096 Yes Yes Yes Yes N/A Yes Yes Yes N/A N/A Yes Yes Yes N/A N/A Yes Yes Yes N/A N/A Yes Yes N/A N/A N/A Yes N/A N/A N/A N/A Yes means that the specified rate is supported and N/A means not applicable. BCLK = (BCLK/FSYNC ratio) x sample rate. I2C Control The SSM3582 supports an I C-compatible, 2-wire serial bus, shared across multiple peripherals. Two signals, serial data (SDA) and serial clock (SCL), carry information between the SSM3582 and the system I2C master controller. The SSM3582 is always a slave on the bus, and cannot initiate a data transfer. Each slave device is identified by a unique address. The address byte format is shown in Table 14. The address resides in the first seven bits of the I2C write. The LSB of this byte sets either a read or write operation. Logic Level 1 corresponds to a read operation and Logic Level 0 corresponds to a write operation. For device address settings, see Table 16. 2 Table 14. I2C Device Address Byte Format Bit 7 0 Bit 6 0 Bit 5 1 Bit 4 Bit 3 Bit3 Bit 2 Bit 2 ADDR0 Bit 1 ADDR1 Bit 0 R/W Both SDA and SCL are open drain, and require pull-up resistors to the input/output voltage. The SSM3582 operates within the I2C voltage range of 1.6 V to 3.6 V. Addressing Initially, each device on the I2C bus is in an idle state, monitoring the SDA and SCL lines for a start condition and the proper address. The I2C master initiates a data transfer by establishing a start condition, defined by a high to low transition on SDA while SCL remains high. This start condition indicates that an address/ data stream follows. All devices on the bus respond to the start condition and shift the next eight bits (the 7-bit address plus the R/W bit), MSB first. The device that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This ninth bit is known as an acknowledge bit. All other devices withdraw from the bus at this point and return to the idle condition. The device address for the SSM3582 is determined by the state of the ADDRx pins. See the Device Address Setting section for more details. The R/W bit determines the direction of the data. A Logic 0 on the LSB of the first byte means the master writes information to the peripheral, whereas a Logic 1 means the master reads information from the peripheral after writing the subaddress and repeating the start address. A data transfer takes place until a stop condition is encountered. A stop condition occurs when SDA transitions from low to high while SCL is held high. The timing for the I2C port is shown in Figure 71. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, the SSM3582 immediately jumps to the idle condition. During a given SCL high period, issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued, the SSM3582 does not issue an acknowledge and returns to the idle condition. If the user exceeds the highest subaddress while in automatic-increment mode, one of two actions is taken. In read mode, the SSM3582 outputs the highest subaddress register contents until the master device issues a no acknowledge, indicating the end of a read. A no acknowledge condition is a condition in which the SDA line is not pulled low on the ninth clock pulse on SCL. If the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the SSM3582, and the device returns to the idle condition. Device Address Setting The device can be set at 16 different I2C addresses using the ADDR1 and ADDR0 pins, as well as 16 hardware modes. ADDR1 and ADDR0 are sampled during the start-up procedure. These pins set the appropriate operating mode, the I2C address, and the default TDM slots. The ADDRx pins can be set to five different voltage levels, as defined in Table 15. The ADDRx pins are referenced to the DVDD rail of the device; connect pull-up resistors to the internally generated DVDD rail if the regulator is used. Table 15. ADDRx Pin Input Level Mapping ADDRx State Connected to Ground Connected to Ground Using a 47 k Resistor Left Floating Connected to DVDD Using a 47 k Resistor Connected to DVDD Rev. A| Page 27 of 59 Level (V) 0 0.45 0.9 1.35 1.8 SSM3582 Data Sheet Table 16. ADDRx Pins to I2C Device Address and TDM Slot Mapping ADDR0 0 0 1 1 0 0 1 1 Pull-down Pull-down Pull-up Pull-up Pull-down Pull-down Pull-up Pull-up 1 ADDRx Pin State 1 ADDR1 0 1 0 1 Pull-down Pull-up Pull-down Pull-up 0 1 0 1 Pull-down Pull-up Pull-down Pull-up MONO = 0 1, 2 3, 4 5, 6 7, 8 9, 10 11, 12 13, 15 15, 16 17, 18 19, 20 21, 22 23, 24 25, 26 27, 28 29, 30 31, 32 Device Address 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Default TDM Slot MONO = 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 = connect to ground, 1 = connect to DVDD. In the case of a pull-down state, connect to ground via a 47 k resistor. In the case of a pull-up state, connect to DVDD via a 47 k resistor. I2C Read and Write Operations Figure 72 shows the timing of a single-word write operation. Every ninth clock, the SSM3582 issues an acknowledge by pulling SDA low. Figure 73 shows the timing of a burst mode write sequence. This figure shows an example where the target destination registers are two bytes. The SSM3582 knows to increment its subaddress register every byte because the requested subaddress corresponds to a register or memory area with a byte word length. The timing of a single-word read operation is shown in Figure 74. Note that the first R/W bit is 0, indicating a write operation, because the subaddress must still be written to set up the internal address. After the SSM3582 acknowledges the receipt of the subaddress, the master must issue a repeated start command, followed by the chip address byte with the R/W set to 1 (read). This repeated command causes the SSM3582 SDA to reverse and to begin driving data back to the master. The master then responds every ninth pulse with an acknowledge pulse to the SSM3582. Refer to Table 17 for a list of abbreviations in Figure 72 through Figure 75. Table 17. Abbreviations for Figure 72 Through Figure 75 Symbol S P AM AS Rev. A| Page 28 of 59 Meaning Start bit Stop bit Acknowledge (ACK used in Figure 72 through Figure 75) by master Acknowledge (ACK used in Figure 72 through Figure 75) by slave Data Sheet SSM3582 SCL SDA START BY MASTER ACK ACK R/W FRAME 2 SUBADDRESS BYTE FRAME1 CHIP ADDRESS BYTE SCL (CONTINUED) ACK ACK FRAME 3 DATA BYTE 1 STOP BY MASTER FRAME 4 DATA BYTE 2 START BIT IC ADDRESS (7 BITS) R/W =0 ACK BY SLAVE SUBADDRESS (8 BITS) ACK BY SLAVE DATA BYTE 1 (8 BITS) STOP BIT 13399-070 Figure 71. I2C Read/Write Timing S CHIP ADDRESS, R/W = 0 AS SUBADDRESS AS DATAWORD 1 AS DATAWORD 2 AS ... P 13399-071 Figure 72. Single-Word I2C Write Format S CHIP ADDRESS, R/W = 0 AS SUBADDRESS AS S CHIP AS ADDRESS, R/W = 1 DATA BYTE 1 AM DATA BYTE N P 13399-072 Figure 73. Burst Mode I2C Write Format S CHIP AS ADDRESS, R/W = 0 SUBADDRESS AS S CHIP AS ADDRESS, R/W = 1 Figure 75. Burst Mode I2C Read Format Rev. A| Page 29 of 59 DATAWORD 1 AM ... P 13399-073 Figure 74. Single-Word I2C Read Format 13399-069 SDA (CONTINUED) SSM3582 Data Sheet STANDALONE OPERATION The SSM3582 can be operated in a standalone hardware control mode without any I2C control. The same ADDRx pins used to set the I2C device address are used to set the functionality of the device. In standalone mode, the I2C pins (SCL and SDA) are inputs and are shorted to DVDD or AGND to set the TDM slot/sample rate of the device (see Table 18). In this case, the ANA_GAIN bits are set to 11 and SPWDN is set to 0 by default. In standalone mode, TDM slot selection, mono mode operation, and sample rate are selected via different pin settings. The device looks at the FSYNC signal and, if it is a 50% duty cycle, uses I2S settings. If the FYSNC signal is a pulse, the device uses TDM settings. Table 18. Standalone Mode Pin Settings and Functionality Sample Rate 32 kHz to 48 kHz 8 kHz to 12 kHz 32 kHz to 48 kHz 8 kHz to 12 kHz 64 kHz to 96 kHz 16 kHz to 24 kHz 64 kHz to 96 kHz 128 kHz to 192 kHz ADDR0 0 1 Pull-down Pull-up Open Open Open Open Open 0 1 Pull-down Pull-up Open Open Open Open Open 0 1 Pull-down Pull-up Open Open Open Open Open 0 1 Pull-down Pull-up Open Open Open Open Open Pin States ADDR1 Open Open Open Open 0 1 Pull-down Pull-up Open Open Open Open Open 0 1 Pull-down Pull-up Open Open Open Open Open 0 1 Pull-down Pull-up Open Open Open Open Open 0 1 Pull-down Pull-up Open SDA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rev. A| Page 30 of 59 SCL 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 TDM Slot(s) 1, 2 3, 4 5, 6 7, 8 9, 10 11, 12 13, 14 15, 16 1, 2 1 2 3 4 5 6 7 8 1, 2 1, 2 3, 4 5, 6 7, 8 9, 10 11, 12 13, 14 15, 16 1, 2 1 2 3 4 5 6 7 8 1, 2 MONO 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Data Sheet SSM3582 MONO MODE Table 19. Analog Gain Settings and Drive Characteristics The SSM3582 can be operated in mono mode for driving low impedance loads. In mono mode, the left and right power stages can be connected in parallel, as shown in Figure 87. Use caution when setting up mono mode. For proper operation, any hardware changes are required along with setting the register. For mono mode operation, set MONO (Register 0x04, Bit 4) to 1. By default, this bit is set to 0 for stereo mode. After the bit is set for mono mode, only the left channel modulator is active and it feeds both the left and right channel power stages. The OUTL+ and OUTR+ pins are in phase. The OUTL- and OUTR- pins are also in phase. For mono mode, OUTL+ must be shorted to OUTR+; similarly, OUTL- must be shorted to OUTR-. ANA_GAIN[1:0] 1 0 In standalone mode, the ADDR0, ADDR1, SCL, and SDA pins determine the TDM slot. See the Table 18 for the possible TDM slot configurations in mono mode. ANALOG AND DIGITAL GAIN Four different gain settings are available to optimize the dynamic range of the amplifier in relation to the PVDD supply voltage. In software mode, the initial 19 dB gain setting can be updated through the control interface. In standalone mode, the I2C interface pins set the gain of the device. Table 19 summarizes the gain settings and load drive characteristics of the amplifier. The amplifier analog gain is set prior to enabling the device outputs and must not be changed during operation; a proper mute/unmute sequence is required to prevent audible transients between gain settings. Finer level control is available in the digital domain, with a very flexible -70 dB to +24 dB, 0.375 dB/step ramp volume control and selectable nonaliasing clipping point. The digital volume control also includes a playback level limiter that can be set in tandem with the battery voltage monitor to prevent the amplifier from browning out the system when battery level is critically low. 0 0 1 1 0 1 0 1 VOUT Gain, 1 V rms (dB) 13 16 19 21 RMS (V rms) 4.47 6.31 8.91 11.20 Peak-to-Peak (V) 6.32 8.92 12.60 15.87 POP AND CLICK SUPPRESSION Pops and clicks are undesirable audible transients generated by the amplifier system that do not come from the system input signal. Voltage transients as small as 10 mV can be heard as an audible pop in the speaker. Voltage transients at the output of audio amplifiers often occur when shutdown is activated or deactivated. The SSM3582 has a pop and click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation. Set either mute or power-down before BCLK is removed to ensure a pop free experience. TEMPERATURE SENSOR The SSM3582 contains an 8-bit ADC that measures the die temperature of the device and is enabled via the TEMP_PWDN bit in Register 0x04. After the sensor is enabled, the temperature can be read via the I2C in the TEMP register, Register 0x1B. The temperature information is stored in Register 0x1B in an 8-bit, unsigned format. The ADC input range is fixed internally from -60C to +195C. To convert the hexadecimal value to the temperature (Celsius) value, use the following steps: 1. 2. Convert the hexadecimal value to decimal and then subtract 60. For example, if the hexadecimal value is 0x54, the decimal value is 84. Calculate the temperature using the following equation: Temperature = Decimal Value - 60 With a decimal value of 84, Temperature = 84 - 60 = 24C Rev. A| Page 31 of 59 SSM3582 Data Sheet Table 20. Fault Reporting Registers Fault Type PVDD Undervoltage (UV) 5 V Regulator UV Limiter/Gain Reduction Engage Clipping, Left Channel Clipping, Right Channel Output Overcurrent (OC) Die Overtemperature (OT) Die Overtemperature Warning (OTW) Battery Voltage > VBAT_INF_x Flag Set Condition PVDD below <3.6 V 5 V regulator voltage at AVDD < 3.6 V Left channel limiter engaged Right channel limiter engaged Left channel DAC clipping Right channel DAC clipping Left channel output current > 6 A peak Right channel output current > 6 A peak Die temperature > 145C Die temperature > 117C Battery voltage PVDD > VBAT_INF_L Battery voltage PVDD > VBAT_INF_R FAULTS AND LIMITER STATUS REPORTING The SSM3582 offers comprehensive protections against the faults at the outputs and reporting to help with system design. The faults listed in Table 20 are reported using the status registers. The faults listed in Table 20 are reported in Register 0x18 and Register 0x19 and can be read via I2C by the microcontroller in the system. In the event of a fault occurrence, use Register 0x0B to control how the device reacts to the faults. Table 21. Register 0x16, Register 0x17, Fault Recovery Fault Type OTW Manual Recovery Autorecovery Attempts UV Die OT OC Flag Set Condition The amount of gain reduction applied if there is an OTW for left channel The amount of gain reduction applied if there is an OTW for the right channel Use to attempt manual recovery in case of a fault event When autorecovery from faults is used, set the number of attempts using this bit Recovery can be automatic or manual Recovery can be automatic or manual Recovery can be automatic or manual Status Reported Register Register 0x16, Bits[1:0], OTW_ GAIN_L Register 0x16, Bits[5:4], OTW_ GAIN_R Register 0x17, Bit 7, MRCV Register 0x17, Bits[5:4], MAX_AR Register 0x17, Bit 2, ARCV_UV Register 0x17, Bit 1, ARCV_OT Register 0x17, Bit 0, ARCV_OC When the automatic recovery mode is set, the device attempts to recover itself after the fault event and, in case the fault persists, then the device sets the fault again. This process repeats until the fault is resolved. Status Reported Register Register 0x18, Bit 7, UVLO_PVDD Register 0x18, Bit 6, UVLO_VREG Register 0x19, Bit 3, LIM_EG_L Register 0x19, Bit 7, LIM_EG_R Register 0x19, Bit 2, CLIP_L Register 0x19, Bit 6, CLIP_R Register 0x19, Bit 1, AMP_OC_L Register 0x19, Bit 5, AMP_OC_R Register 0x18, Bit 1, OTF Register 0x18, Bit 0, OTW Register 0x19, Bit 0, BAT_WARN_L Register 0x19, Bit 4, BAT_WARN_R When the manual recovery mode is used, the device shuts down and the recovery must be attempted using the system microcontroller. VBAT (PVDD) SENSING The SSM3582 contains an 8-bit ADC that measures the voltage of the battery voltage (VBAT/PVDD) supply. The battery voltage information is stored in Register 0x1A as an 8-bit unsigned format. The ADC input range is fixed internally at 3.8 V to 16.2 V. To convert the hexadecimal value to the voltage value, use the following steps: Convert the hexadecimal value to decimal. For example, if the hexadecimal value is 0xA9, the decimal value is 169. Calculate the voltage using the following equation: Voltage = 3.8 V + 12.4 V x Decimal Value/255 With a decimal value of 169, Voltage = 3.8 V + 12.4 V x 169/255 = 12.02 V LIMITER AND BATTERY TRACKING THRESHOLD CONTROL The SSM3582 contains an output limiter that can be used to limit the peak output voltage of the amplifier. The limiter works on the rms and peak value of the signal. The limiter threshold, slope, attack rate, and release rate are programmable using Register 0x0E, Register 0x0F, and Register 0x10 for the left channel and Register 0x11, Register 0x12, Register 0x13 for the right channel. The limiter can be enabled or disabled using LIM_EN_L, Bits[1:0] in Register 0x0E, Bits[1:0] for the left channel and the LIM_EN_R bits, Bits[1:0] in Register 0x11, for the right channel. The threshold at which the output is limited is determined by the LIM_THRES_L bits setting, Bits[7:3] in Register 0x0F for the left channel, and the LIM_THRES_R bits setting, Bits[7:3] in Register 0x12 for the right channel. When the ouput signal level exceeds the set threshold level, the limiter activates and limits the signal level to the set limit. Below the set threshold, the output level is not affected. Rev. A| Page 32 of 59 Data Sheet SSM3582 When set to a variable threshold, the SSM3582 monitors the VBAT supply and automatically adjusts the limiter threshold based on the VBAT supply voltage. The VBAT supply voltage at which the limiter begins to decrease the output level is determined by the VBAT inflection point (the VBAT_INF _L bits (Register 0x10, Bits[7:0]) for the left channel and VBAT_INF_R bits (Register 0x13, Bits[7:0]) for the right channel). When LIM_EN_x = 01, the limiter is enabled. When LIM_EN_x = 10, the limiter mutes the output if VBAT falls below VBAT_INF_x. When LIM_EN_x = 11, the limiter engages only when the battery voltage is lower than VBAT_INF_x. When VBAT is greater than VBAT_INF_x, no limiting occurs. Note that there is hysteresis on VBAT_INF_x for the limiter disengaging. The limiter, when active, reduces the gain of the amplifier. The rate of gain reduction or attack rate is determined by the LIM_ATR_ x bits (Register 0x0E and Register 0x11, Bits[5:4]). Similarly, when the signal level drops below the limiter threshold, the gain is restored. The gain release rate is determined by the LIM_RRT bits (Register 0x0E and Register 0x11, Bits[7:6]). LIM_EN_x = 00 VBAT_TRACK_x = 0 AMPLIFIER CLIPPING LEVEL The VBAT_INF_x point is defined as the battery voltage at which the limiter either activates or deactivates depending on the LIM_EN_x mode (see Table 22). When the battery voltage is greater than VBAT_INF_x, the limiter is not active. When the battery voltage is less than VBAT_INF_X, the limiter is activated. The VBAT_INF_x bits can be set from 3.8 V to 16.2 V. The 8-bit value for the voltage can be calculated using the following equation: INPUT LEVEL Voltage = 3.8 + 12.4 x Decimal Value/255 13399-076 The limiter threshold can be set as fixed or to vary with the battery voltage via the VBAT_TRACK_L bit (Register 0x0E, Bit 2) for the left channel and VBAT_TRACK_R bit (Register 0x11, Bit 2) for right channel. When set to fixed, the limiter threshold is fixed and does not vary with battery voltage. The threshold can be set from 2 V peak to 16 V peak using the LIM_THRES_x bit (see Figure 77). The limiter offers various active modes that can be set using the LIM_EN_x bits (Register 0x0E and Register 0x11, Bits[1:0]) and the VBAT_TRACK_x bit, as shown in Table 22. PEAK OUTPUT LEVEL The limiter threshold can be set above the maximum output voltage of the amplifier. In this case, the limiter allows maximum peak output; in other words, the output may clip depending on the power supply voltage and not the limiter. Figure 76. Limiter Example (LIM_EN_x = 0b0, VBAT_TRACK_x = 0bX) Convert the decimal value to an 8-bit hexadecimal value and use it to set the VBAT_INF_x bits. The slope bits (Register 0x0F and Register 0x12, Bits[1:0]) determine the rate at which the limiter threshold is lowered relative to the amount of change in VBAT below the VBAT_INF_x point. LIMITER THRESHOLD FIXED AT SET VALUE AND DOES NOT TRACK VBAT LIMITER THRESHOLD LIM_THRES_x The slope is the ratio of the limiter threshold reduction to the VBAT voltage reduction. The slope ratio can be set from 1:1 to 4:1. This function is useful to prevent early shutdown under low battery conditions. As the VBAT voltage falls, the limiter threshold is lowered. This lower threshold results in the lower output level and therefore helps to reduce the current drawn from the battery and in turn helps prevent early shutdown due to low VBAT. VBAT Figure 77. Limiter Fixed (LIM_EN_x = 0b01, VBAT_TRACK_x = 0b0) Table 22. Limiter Modes LIM_EN_x 00 01 01 10 11 11 VBAT_TRACK_x 0 or 1 0 1 0 or 1 0 1 Limiter No Fixed Variable Fixed Fixed Variable VBAT < VBAT_INF_x Not applicable Use the set threshold Lowers the threshold Mutes the output Use the set threshold Lowers the threshold VBAT > VBAT_INF_x Not applicable Use the set threshold Use the set threshold Use the set threshold No limiting No limiting Rev. A| Page 33 of 59 Comments See Figure 76 See Figure 77 See Figure 78 and Figure 79 Not shown See Figure 80 and Figure 81 See Figure 82 and Figure 83 13399-077 Slope = Limiter Threshold/VBAT SSM3582 Data Sheet LIM_EN_x = 01 VBAT_TRACK_x = 1 LIMITER THRESHOLD CHANGE FOR VBAT < VBAT_INF_x 13399-078 CHANGE IN LIM THRESHOLD = N x (VBAT_INF_x - VBAT) WHERE N = 1 TO 4, SET USING SLOPE BITS IN REG 0x0F, REG 0x12 INPUT LEVEL VBAT Figure 81. Limiter Fixed (LIM_EN_x = 0b11, VBAT_TRACK_x = 0b0) Figure 78. Limiter Fixed (LIM_EN_x = 0b01, VBAT_TRACK_x = 0b1) LIM_EN_x = 11 VBAT_TRACK_x = 1 LIMITER THRESHOLD STAYS AT THE SET VALUE FOR VBAT > VBAT_INF_x VBAT > VBAT_INF_x LIMITER IS NOT ACTIVE AMPLIFIER CLIPPING LEVEL VBAT_INF_x PEAK OUTPUT LEVEL LIMITER THRESHOLD CHANGE FOR VBAT < VBAT_INF CHANGE IN LIM THRESHOLD = N x (VBAT_INF_x - VBAT) WHERE N = 1 TO 4, SET USING SLOPE BIT IN REG 0x0F, REG 0x12 VBAT Figure 79. Output Level vs. VBAT in Limiter Tracking Mode (LIM_EN_x = 0b01, VBAT_TRACK_x = 0b1) INPUT LEVEL Figure 82. Limiter Example (LIM_EN_x = 0b11, VBAT_TRACK_x = 0b1) LIMITER THRESHOLD INACTIVE FOR VBAT > VBAT_INF_x SET LIM_THRES_x LIMITER THRESHOLD AMPLIFIER CLIPPING LEVEL LIMITER THRESHOLD SETTING NO CHANGE IN LIM THRESHOLD PER VBAT VBAT_INF_x SLOPE LIMITER THRESHOLD LOWERS FOR VBAT < VBAT_INF_x INPUT LEVEL 13399-080 VBAT 13399-083 LIM_EN_x = 11 VBAT_TRACK_x = 0 PEAK OUTPUT LEVEL 13399-082 LIMITER THRESHOLD LOWERS FOR VBAT < VBAT_INF_x LIMITER THRESHOLD SETTING 13399-079 LIMITER THRESHOLD LIM_THRES_x SLOPE 13399-081 LIMITER THRESHOLD VBAT > VBAT_INF_x LIMITER LIMITER THRESHOLD SETTING PEAK OUTPUT LEVEL LIMITER THRESHOLD FIXED AT SET VALUE AND DOES NOT TRACK VBAT LIM_THRES_x Figure 83. Output Level vs. VBAT in Limiter Tracking Mode (LIM_EN_x = 0b11, VBAT_TRACK_x = 0b1) Figure 80. Limiter Example (LIM_EN_x = 0b11, VBAT_TRACK_x = 0) Rev. A| Page 34 of 59 Data Sheet SSM3582 HIGH FREQUENCY CLIPPER OUTPUT MODULATION DESCRIPTION The high frequency clipper can be controlled via the DAC_CLIP_L bits (Register 0x14, Bits[7:0]) and the DACL_CLIP_R bits (Register 0x15, Bits[7:0]). The SSM3582 uses three level, - output modulation. Each output can swing from ground to PVDD, and vice versa. Ideally, when no input signal is present, the output differential voltage is 0 V because there is no need to generate a pulse. In a real-world situation, noise sources are always present. These bits determine the clipper threshold, relative to full scale. When enabled, the clipper digitally clips the signal after the DAC interpolation. EMI NOISE The SSM3582 uses a proprietary modulation and spread spectrum technology to minimize EMI emissions from the device. The SSM3582 passes FCC Class-B emissions testing with an unshielded 20 inch cable using ferrite bead-based filtering. For applications that have difficulty passing FCC Class-B emission tests, the SSM3582 includes an ultralow EMI emissions mode that significantly reduces the radiated emissions at the Class-D outputs, particularly above 100 MHz. Note that reducing the supply voltage greatly reduces radiated emissions. Due to this constant presence of noise, a differential pulse is occasionally generated in response to this stimulus. A small amount of current flows into the inductive load when the differential pulse is generated. However, typically, the output differential voltage is 0 V. This feature ensures that the current flowing through the inductive load is small. When the user sends an input signal, an output pulse is generated to follow the input voltage. The differential pulse density is increased by raising the input signal level. Figure 84 depicts three-level, - output modulation with and without input stimulus. OUTPUT = 0V +5V OUTx+ 0V +5V OUTx- 0V +5V VOUT 0V -5V OUTPUT > 0V +5V OUTx+ 0V +5V OUTx- 0V +5V VOUT 0V OUTPUT < 0V +5V OUTx+ 0V +5V OUTx- 0V VOUT -5V 13399-074 0V Figure 84. Three-Level, - Output Modulation With and Without Input Stimulus Rev. A| Page 35 of 59 SSM3582 Data Sheet BOOTSTRAP CAPACITORS OUTPUT EMI FILTERING The output stage of the SSM3582 uses a high-side NMOS driver, rather than a PMOS driver. To generate the gate drive voltage for the high-side NMOS, a bootstrap capacitor for each output terminal acts as a floating power supply for the switching cycle. Use 0.22 F capacitors to connect the appropriate output pin (OUTx) to the bootstrap pin (BSTx). For example, connect a 0.22 F capacitor between OUTL+ (a left channel, noninverting output) and BSTL+ for bootstrapping the left channel. Similarly, connect another 0.22 F capacitor between the OUTL- and BSTL- pins for the left channel inverting output. Additional EMI filtering may be required when the speaker traces and cables are long and present a significant capacitive load that can create additional draw from the amplifier. Typical power ferrites present a significant magnetic hysteresis cycle that affects THD performance and are not recommended for high performance designs. The NFZ filter series from Murata, designed in close collaboration with Analog Devices, Inc., provides a closed hysteresis loop similar to an air coil with minimum impact on performance. Products are available at upwards of 4 A rms, well suited to this application. A small capacitor can be added between the output of the filter and ground to further attenuate very high frequencies. Take care to ensure the capacitor is properly sized so as not to affect idle power consumption or efficiency. POWER SUPPLY DECOUPLING To ensure high efficiency, low THD, and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short duration voltage spikes. These spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input must be decoupled with a good quality, low ESL, low ESR bulk capacitor larger than 220 F. This capacitor bypasses low frequency noise to the ground plane. For high frequency decoupling, place 1 F capacitors as close as possible to the PVDD pins of the device. BSTL+ 0.22F CAPACITOR PCB PLACEMENT Component selection and placement have great influence on system performance, both measured and subjective. Proper PVDD layout and decoupling is necessary to reach the specified level of performance, particularly at the highest power levels. The placement shown in Figure 85 ensures proper output stage decoupling for each channel, for minimum supply noise and maximum separation between channels. Additional bulk decoupling is necessary to reduce current ripple at low frequencies, and can be shared between several amplifiers in a multichannel solution. PVDD DECOUPLING 0.1F CAPACITOR BSTL- 0.22F CAPACITOR DVDD DECOUPLING 0.1F CAPACITOR BSTR+ 0.22F CAPACITOR BSTR- 0.22F CAPACITOR PVDD DECOUPLING 0.1F CAPACITOR Figure 85. Recommended Component Placement Rev. A| Page 36 of 59 13399-075 AVDD DECOUPLING 0.1F CAPACITOR Data Sheet SSM3582 LAYOUT As output power increases, care must be taken to lay out PCB traces and wires properly among the amplifier, load, and power supply; a poor layout increases voltage drops, consequently decreasing efficiency. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. For the lowest dc resistance (DCR) and minimum inductance, ensure that track widths for the outputs are at least 200 mil for every inch of length and use 1 oz. or 2 oz. copper. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load and supply pins must be as wide as possible; this also maintains the minimum trace resistances. In addition, good PCB layout isolates critical analog paths from sources of high interference. Separate high frequency circuits (analog and digital) from low frequency circuits. Properly designed multilayer PCBs can reduce EMI emission and increase immunity to the RF field by a factor of 10 or more, compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted by signal crossover. If the system has separate analog and digital ground and power planes, the analog ground plane must be directly beneath the analog power plane, and, similarly, the digital ground plane must be directly beneath the digital power plane. There must be no overlap between the analog and digital ground planes or between the analog and digital power planes. PVDD and PGND carry most of the device current, and must be properly decoupled with multiple capacitors at the device pins. To minimize ground bounce, use independent large traces to carry PVDD and PGND to the power supply, thus reducing the amount of noise the amplifier bridges inject in the circuit, particularly if common ground impedance is significant. Proper grounding guidelines help improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. Rev. A| Page 37 of 59 SSM3582 Data Sheet REGISTER SUMMARY Table 23. Register Summary Reg 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C Name VENDOR_ID DEVICE_ID1 DEVICE_ID2 REVISION POWER_CTRL AMP_DAC_CTRL DAC_CTRL VOL_LEFT_CTRL VOL_RIGHT_CTRL SAI_CTRL1 SAI_CTRL2 SLOT_LEFT_CTRL SLOT_RIGHT_CTRL LIM_LEFT_CTRL1 LIM_LEFT_CTRL2 LIM_LEFT_CTRL3 LIM_RIGHT_CTRL1 LIM_RIGHT_CTRL2 LIM_RIGHT_CTRL3 CLIP_LEFT_CTRL CLIP_RIGHT_CTRL FAULT_CTRL1 FAULT_CTRL2 STATUS1 STATUS2 VBAT TEMP SOFT_RESET Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit 7 Bit 6 Bit 5 Bit 4 APWDN_EN DAC_LPM DAC_HV RESERVED RESERVED DAC_MUTE_R TEMP_PWDN DAC_POL_R DAC_MUTE_L RESERVED SDATA_EDGE Bit 3 VENDOR DEVICE1 DEVICE2 REV MONO R_PWDN DAC_POL_L EDGE DAC_HPF RESERVED VOL_L VOL_R TDM_BCLKS DATA_WIDTH VOL_ZC_ONLY BCLK_POL RESERVED RESERVED RESERVED LIM_RRT_L LIM_ATR_L LIM_THRES_L LIM_RRT_R LIM_ATR_R LIM_THRES_R RESERVED VBAT_INF_L LIM_LINK Bit 2 Bit 1 L_PWDN RESERVED RESERVED SPWDN ANA_GAIN DAC_FS FSYNC_MODE CLIP_LINK TDM_SLOT_L TDM_SLOT_R VBAT_TRACK_L RESERVED SDATA_FMT VOL_LINK VBAT_TRACK_R RESERVED Bit 0 SAI_MODE AUTO_SLOT LIM_EN_L SLOPE_L LIM_EN_R SLOPE_R VBAT_INF_R DAC_CLIP_L DAC_CLIP_R RESERVED MRCV RESERVED UVLO_PVDD UVLO_VREG LIM_EG_R CLIP_R OTW_GAIN_R MAX_AR AMP_OC_R RESERVED RESERVED BAT_WARN_R LIM_EG_L VBAT TEMP RESERVED Rev. A| Page 38 of 59 RESERVED ARCV_UV CLIP_L OTW_GAIN_L ARCV_OT ARCV_OC OTF OTW AMP_OC_L BAT_WARN_L S_RST Reset 0x41 0x35 0x82 0x01 0xA1 0x8A 0x02 0x40 0x40 0x11 0x07 0x00 0x01 0xA0 0x51 0x22 0xA8 0x51 0x22 0xFF 0xFF 0x00 0x30 0x00 0x00 0x00 0x00 0x00 RW R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W Data Sheet SSM3582 REGISTER DETAILS Address: 0x00, Reset: 0x41, Name: VENDOR_ID 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 1 [7:0] VENDOR (R) Vendor ID Table 24. Bit Descriptions for VENDOR_ID Bits Bit Name [7:0] VENDOR Settings Description Reset Access Vendor ID 0x41 R Description Reset Access Device ID 1 0x35 R Description Reset Access Device ID 2 0x82 R Description Reset Access Revision Code 0x1 R Address: 0x01, Reset: 0x35, Name: DEVICE_ID1 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 [7:0] DEVICE1 (R) Device ID 1 Table 25. Bit Descriptions for DEVICE_ID1 Bits Bit Name [7:0] DEVICE1 Settings Address: 0x02, Reset: 0x82, Name: DEVICE_ID2 7 6 5 4 3 2 1 0 1 0 0 0 0 0 1 0 [7:0] DEVICE2 (R) Device ID 2 Table 26. Bit Descriptions for DEVICE_ID2 Bits Bit Name [7:0] DEVICE2 Settings Address: 0x03, Reset: 0x01, Name: REVISION 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [7:0] REV (R) Revision Code Table 27. Bit Descriptions for REVISION Bits Bit Name [7:0] REV Settings Rev. A| Page 39 of 59 SSM3582 Data Sheet Address: 0x04, Reset: 0xA1, Name: POWER_CTRL 7 6 5 4 3 2 1 0 1 0 1 0 0 0 0 1 [7] APWDN_EN (R/W) Auto Power-Down Enable 0: Auto Power-Down Feature Disabled. 1: Auto Power-Down Feature Enabled. [0] SPWDN (R/W) Software Master Power-Down 0: Norm al Operation. 1: Software Master Power-Down. [6] RESERVED [1] RESERVED [5] TEMP_PWDN (R/W) Tem perature Sensor Power-down 0: Tem perature Sensor On. 1: Tem perature Sensor Powered Down. [2] L_PWDN (R/W) Left Channel Power-Down 0: Left Channel Powered on. 1: Left Channel Powered Down. [4] MONO (R/W) Mono Mode Selection 0: Stereo Mode Enabled. 1: Mono Mode Enabled. [3] R_PWDN (R/W) Right Channel Power-Down 0: Right Channel Powered On. 1: Right Channel Powered Down. Table 28. Bit Descriptions for POWER_CTRL Bits 7 Bit Name APWDN_EN Settings 0 1 6 5 RESERVED TEMP_PWDN 0 1 4 MONO 0 1 3 R_PWDN 0 1 2 L_PWDN 0 1 1 0 RESERVED SPWDN 0 1 Description Automatic Power-Down Enable. Automatic power-down feature disabled. Automatic power-down feature enabled. Reserved. Temperature Sensor Power-Down. Temperature sensor on. Temperature sensor powered down. Mono Mode Selection. Stereo mode enabled. Mono mode enabled. Left Channel Power-Down. Right channel powered on. Right channel powered down. Left Channel Power-Down. Left channel powered on. Left channel powered down. Reserved. Software Master Power-Down Normal operation. Software master power-down. Rev. A| Page 40 of 59 Reset 0x1 Access R/W 0x0 0x1 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x1 R R/W Data Sheet SSM3582 Address: 0x05, Reset: 0x8A, Name: AMP_DAC_CTRL 7 6 5 4 3 2 1 0 1 0 0 0 1 0 1 0 [7] DAC_LPM (R/W) DAC low power m ode 0: DAC Low Power Mode Disabled. 1: DAC Low Power Mode Enabled. [6] RESERVED [5] DAC_POL_R (R/W) Right Channel DAC output polarity control 0: Norm al behavior. 1: Invert the DAC output. [1:0] ANA_GAIN (R/W) Am plifier analog gain select 0: +13dB (6.3 V peak) 1: +16 dB (8.9 V peak) 10: +19 dB (12.6 V peak) 11: +21 dB (16 V peak) [2] RESERVED [3] EDGE (R/W) Edge rate control 0: Norm al operation. 1: Low EMI m ode operation. [4] DAC_POL_L (R/W) Left Channel DAC output polarity control 0: Norm al behavior. 1: Invert the DAC output. Table 29. Bit Descriptions for AMP_DAC_CTRL Bits Bit Name 7 DAC_LPM Settings Description Reset Access DAC Low Power Mode. 0x1 R/W 0 DAC low power mode disabled. 1 DAC low power mode enabled. 6 RESERVED Reserved. 0x0 R 5 DAC_POL_R Right Channel DAC Output Polarity Control. 0x0 R/W 0x0 R/W 0x1 R/W 4 3 0 Normal behavior. 1 Invert the DAC output. DAC_POL_L Left Channel DAC Output Polarity Control. 0 Normal behavior. 1 Invert the DAC output. EDGE Edge Rate Control. 0 Normal operation. 1 Low EMI mode operation. 2 RESERVED Reserved. 0x0 R [1:0] ANA_GAIN Amplifier Analog Gain Select. 0x2 R/W 0 +13 dB (6.3 V peak). 1 +16 dB (8.9 V peak). 10 +19 dB (12.6 V peak). 11 +21 dB (16 V peak). Rev. A| Page 41 of 59 SSM3582 Data Sheet Address: 0x06, Reset: 0x02, Name: DAC_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 [7] DAC_HV (R/W) Hard volum e control 0: Soft volum e ram ping. 1: No volum e ram ping. [2:0] DAC_FS (R/W) DAC sam ple rate select 0: 8kHz to 12 kHz. 1: 16kHz to 24 kHz. 10: 32kHz to 48 kHz. 11: 64kHz to 96 kHz. 100: 128kHz to 192 kHz. 101: 48kHz to 72 kHz. [6] DAC_MUTE_R (R/W) DAC right channel m ute 0: Right channel unm uted. 1: Right channel m uted. [3] RESERVED [5] DAC_MUTE_L (R/W) DAC left channel m ute 0: Left channel unm uted. 1: Left channel m uted. [4] DAC_HPF (R/W) DAC high pass filter 0: DAC high pass filter disabled. 1: DAC high pass filter enabled. Table 30. Bit Descriptions for DAC_CTRL Bits Bit Name 7 DAC_HV 6 5 4 Settings Description Reset Access Hard Volume Control. 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0 Soft Volume Ramping. 1 No Volume Ramping. DAC_MUTE_R DAC Right Channel Mute. 0 Right Channel Unmuted. 1 Right Channel Muted. DAC_MUTE_L DAC Left Channel Mute. 0 Left Channel Unmuted. 1 Left Channel Muted. DAC_HPF DAC High-Pass Filter. 0 DAC High-Pass Filter Disabled. 1 DAC High-Pass Filter Enabled. 3 RESERVED Reserved. 0x0 R [2:0] DAC_FS DAC Sample Rate Select. 0x2 R/W 0 8 kHz to 12 kHz. 1 16 kHz to 24 kHz. 10 32 kHz to 48 kHz. 11 64 kHz to 96 kHz. 100 128 kHz to 192 kHz. 101 48 kHz to 72 kHz. Rev. A| Page 42 of 59 Data Sheet SSM3582 Address: 0x07, Reset: 0x40, Name: VOL_LEFT_CTRL 7 6 5 4 3 2 0 1 0 1 0 0 0 0 0 0 [7:0] VOL_L (R/W) Left channel volum e 0x00: +24 dB. 0x01: +23.625 dB. 0x02: ... ... 0xFD: -70.875 dB. 0xFE: -71.25 dB. 0xFF: Mute. Table 31. Bit Descriptions for VOL_LEFT_CTRL Bits Bit Name [7:0] VOL_L Settings Description Reset Access Left Channel Volume 0x40 R/W Description Reset Access Right Channel Volume 0x40 R/W 0x00 +24 dB 0x01 +23.625 dB 0x02 ... 0x3F +0.375 dB 0x40 0 dB 0x41 -0.375 dB 0x42 ... 0xFD -70.875 dB 0xFE -71.25 dB 0xFF Mute Address: 0x08, Reset: 0x40, Name: VOL_RIGHT_CTRL 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] VOL_R (R/W) Right channel volum e 0x00: +24 dB. 0x01: +23.625 dB. 0x02: ... ... 0xFD: -70.875 dB. 0xFE: -71.25 dB. 0xFF: Mute. Table 32. Bit Descriptions for VOL_RIGHT_CTRL Bits Bit Name [7:0] VOL_R Settings 0x00 +24 dB 0x01 +23.625 dB 0x02 ... 0x3F +0.375 dB 0x40 0 dB 0x41 -0.375 dB 0x42 ... 0xFD -70.875 dB 0xFE -71.25 dB 0xFF Mute Rev. A| Page 43 of 59 SSM3582 Data Sheet Address: 0x09, Reset: 0x11, Name: SAI_CTRL1 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 1 [7] RESERVED [0] SAI_MODE (R/W) Serial interface m ode select 0: Stereo m odes. 1: TDM m odes. [6] BCLK_POL (R/W) BCLK polarity control 0: Use rising edge to capture SDATA. 1: Use falling edge to capture SDATA. [1] SDATA_FMT (R/W) Serial data form at 0: I2S (delay by 1) Form at. 1: Left Justified Form at. [5:3] TDM_BCLKS (R/W) TDM slot width select 0: 16 bits. 1: 24 bits. 10: 32 bits. 11: 48 bits. 100: 64 bits. [2] FSYNC_MODE (R/W) FSYNC m ode 0: Stereo: low FSYNC is left channel; TDM: Fram e start on falling edge. 1: Stereo: high FSYNC is left channel; TDM: Fram e start on rising edge. Table 33. Bit Descriptions for SAI_CTRL1 Bits Bit Name 7 6 [5:3] 2 1 0 Settings Description Reset Access RESERVED Reserved. 0x0 R BCLK_POL BCLK Polarity Control 0x0 R/W 0x2 R/W 0x0 R/W 0x0 R/W 0x1 R/W 0 Use Rising Edge to Capture SDATA 1 Use Falling Edge to Capture SDATA TDM_BCLKS TDM Slot Width Select 0 16 Bits 1 24 Bits 10 32 Bits 11 48 Bits 100 64 Bits FSYNC_MODE FSYNC Mode 0 Stereo: Low FSYNC is Left Channel; TDM: Frame Start on Falling Edge 1 Stereo: High FSYNC is Left Channel; TDM: Frame Start on Rising Edge SDATA_FMT Serial Data Format 0 I2S (Delay by 1) Format 1 Left Justified Format SAI_MODE Serial Interface Mode Select 0 Stereo Modes 1 TDM Modes Rev. A| Page 44 of 59 Data Sheet SSM3582 Address: 0x0A, Reset: 0x07, Name: SAI_CTRL2 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 [7] SDATA_EDGE (R/W) SDATA edge delay m ode 0: Norm al operation. 1: Half cycle delay of SDATA. [0] AUTO_SLOT (R/W) Autom atic TDM slot selection 0: Set TDM slots using TDM_SLOTx Bits. 1: Set TDM slots autom atically using ADDRx pin settings. [6:5] RESERVED [4] DATA_WIDTH (R/W) Audio input data width 0: 24 bits. 1: 16 bits. [3] VOL_ZC_ONLY (R/W) Volum e control zero-crossing detection 0: Allow volum e to change at all tim es. 1: Only change volum e when zero-crossing is detected (m ay be different per-channel) [1] VOL_LINK (R/W) Channel volum e link 0: Use independent VOL_L and VOL_R controls. 1: Link both channels to VOL_L control. [2] CLIP_LINK (R/W) High frequency clipper link 0: Use Independent Left and Right DAC_CLIP_x Bits. 1: Link Both Channels to DAC_CLIP_L Bits. Table 34. Bit Descriptions for SAI_CTRL2 Bits Bit Name 7 SDATA_EDGE Settings Description Reset Access SDATA Edge Delay Mode 0x0 R/W 0 Normal Operation 1 Half Cycle Delay of SDATA [6:5] RESERVED Reserved 0x0 R 4 DATA_WIDTH Audio Input Data Width 0x0 R/W 0x0 R/W 0x1 R/W 0x1 R/W 0x1 R/W 3 2 1 0 0 24 Bits 1 16 Bits VOL_ZC_ONLY Volume Control Zero-Crossing Detection 0 Allow Volume to Change at All Times 1 Only Change Volume When Zero-Crossing is Detected (May Be Different Per Channel) CLIP_LINK High Frequency Clipper Link 0 Use Independent Left and Right DAC_CLIP_x Bits 1 Link Both Channels to DAC_CLIP_L Bits VOL_LINK Channel Volume Link 0 Use Independent VOL_L and VOL_R Controls 1 Link Both Channels to VOL_L Control AUTO_SLOT Automatic TDM Slot Selection 0 Set TDM Slots Using TDM_SLOT_x Bits 1 Set TDM Slots Automatically Using the ADDRx Pin Settings Rev. A| Page 45 of 59 SSM3582 Data Sheet Address: 0x0B, Reset: 0x00, Name: SLOT_LEFT_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4:0] TDM_SLOT_L (R/W) Left channel s lot s election Table 35. Bit Descriptions for SLOT_LEFT_CTRL Bits Bit Name [7:5] [4:0] Settings Description Reset Access RESERVED Reserved 0x0 R TDM_SLOT_L Left Channel Slot Selection 0x0 R/W Description Reset Access Address: 0x0C, Reset: 0x01, Name: SLOT_RIGHT_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [7:5] RESERVED [4:0] TDM_SLOT_R (R/W) Right channel s lot s election Table 36. Bit Descriptions for SLOT_RIGHT_CTRL Bits Bit Name Settings [7:5] RESERVED Reserved 0x0 R [4:0] TDM_SLOT_R Right Channel Slot Selection 0x1 R/W Address: 0x0E, Reset: 0xA0, Name: LIM_LEFT_CTRL1 7 6 5 4 3 2 1 0 1 0 1 0 0 0 0 0 [7:6] LIM_RRT_L (R/W) Left lim iter release rate 0: 3200 m s/dB. 1: 1600 m s/dB. 10: 1200 m s/dB. 11: 800 m s/dB. [1:0] LIM_EN_L (R/W) Left lim iter m ode 0: Lim iter off. 1: Lim iter on. 10: Mute output if VBAT<VBAT_INF_L. 11: Lim iter on only if VBAT<VBAT_INF_L. [5:4] LIM_ATR_L (R/W) Left lim iter attack rate 0: 120 us/dB. 1: 60 us/dB. 10: 30 us/dB. 11: 20 us/dB. [2] VBAT_TRACK_L (R/W) Left threshold battery tracking 0: Fixed Lim iter Threshold Set by LIM_THRES_L Bits in Register0x0F. 1: Ram p Down Lim iter Threshold when VBAT<VBAT_INF_L using SLOPE_x bits in Register 0x0F. [3] RESERVED Table 37. Bit Descriptions for LIM_LEFT_CTRL1 Bits Bit Name [7:6] LIM_RRT_L [5:4] 3 Settings Reset Access Left Limiter Release Rate 0x2 R/W 0x2 R/W 0x0 R 0 3200 ms/dB 1 1600 ms/dB 10 1200 ms/dB 11 800 ms/dB LIM_ATR_L RESERVED Description Left Limiter Attack Rate 0 120 s/dB 1 60 s/dB 10 30 s/dB 11 20 s/dB Reserved Rev. A| Page 46 of 59 Data Sheet Bits Bit Name 2 VBAT_TRACK_L [1:0] SSM3582 Settings Description Reset Access Left Threshold Battery Tracking 0x0 R/W 0x0 R/W 0 Fixed Limiter Threshold Set by LIM_THRES Bits in Register 0x0F 1 Ramp Down Limiter Threshold when VBAT < VBAT_INF_L using SLOPE_x bits in Register 0x0F. LIM_EN_L Left Limiter Mode 0 Limiter Off 1 Limiter On 10 Mute output if VBAT < VBAT_INF_L. 11 Limiter on only if VBAT < VBAT_INF_L. Address: 0x0F, Reset: 0x51, Name: LIM_LEFT_CTRL2 7 6 5 4 3 2 1 0 0 1 0 1 0 0 0 1 [7:3] LIM_THRES_L (R/W) Left Lim iter Threshold 0: 16 V peak. 1: 15.5 V peak. 2: 15 V peak. ... 29: 3 V peak. 30: 2.5 V peak. 31: 2 V peak. [1:0] SLOPE_L (R/W) Left Lim iter Threshold Reduction Slope 0: 1:1 Threshold:VBAT reduction. 1: 2:1 Threshold:VBAT reduction. 10: 3:1 Threshold:VBAT reduction. 11: 4:1 Threshold:VBAT reduction. [2] RESERVED Table 38. Bit Descriptions for LIM_LEFT_CTRL2 Bits Bit Name [7:3] LIM_THRES_L Settings Description Reset Access Left Limiter Threshold 0xA R/W 0 16 V peak 1 15.5 V peak 2 15 V peak 3 14.5 V peak 4 14 V peak 5 13.5 V peak 6 13 V peak 7 12.5 V peak 8 12 V peak 9 11.5 V peak 10 11 V peak 11 10.5 V peak 12 10 V peak 13 9.5 V peak 14 9.25 V peak 15 9 V peak 16 8.75 V peak 17 8.5 V peak 18 8.25 V peak 19 8 V peak 20 7.5 V peak Rev. A| Page 47 of 59 SSM3582 Bits Bit Name 2 RESERVED [1:0] SLOPE_L Data Sheet Settings Description Reset Access Reserved 0x0 R Left Limiter Threshold Reduction Slope 0x1 R/W Description Reset Access Left Limiter Battery Voltage Inflection Point 0x22 R/W 21 7 V peak 22 6.5 V peak 23 6 V peak 24 5.5 V peak 25 5 V peak 26 4.5 V peak 27 4 V peak 28 3.5 V peak 29 3 V peak 30 2.5 V peak 31 2 V peak 0 1:1 Threshold: VBAT Reduction 1 2:1 Threshold: VBAT Reduction 10 3:1 Threshold: VBAT Reduction 11 4:1 Threshold: VBAT Reduction Address: 0x10, Reset: 0x22, Name: LIM_LEFT_CTRL3 7 6 5 4 3 2 1 0 0 0 1 0 0 0 1 0 [7:0] VBAT_INF_L (R/W) Left lim iter battery voltage inflection point Table 39. Bit Descriptions for LIM_LEFT_CTRL3 Bits Bit Name [7:0] VBAT_INF_L Settings Rev. A| Page 48 of 59 Data Sheet SSM3582 Address: 0x11, Reset: 0xA8, Name: LIM_RIGHT_CTRL1 7 6 5 4 3 2 1 0 1 0 1 0 1 0 0 0 [7:6] LIM_RRT_R (R/W) Right lim iter release rate 0: 3200 m s/dB. 1: 1600 m s/dB. 10: 1200 m s/dB. 11: 800 m s/dB. [1:0] LIM_EN_R (R/W) Right lim iter m ode 0: Lim iter off. 1: Lim iter on. 10: Mute output if VBAT<VBAT_INF_R. 11: Lim iter on only if VBAT<VBAT_INF_R. [5:4] LIM_ATR_R (R/W) Right lim iter attack rate 0: 120 us/dB. 1: 60 us/dB. 10: 30 us/dB. 11: 20 us/dB. [2] VBAT_TRACK_R (R/W) Right threshold battery tracking 0: Fixed Lim iter Threshold set by LIM_THRES_R Bits in Register 0x12. 1: Ram p down lim iter threshold when VBAT<VBAT_INF_R using SLOPE_R Bits in Register 0x12. [3] LIM_LINK (R/W) Channel lim iter link 0: Use independent left and right channel lim iters. 1: Link both channels to one lim iter (use left lim iter controls) Table 40. Bit Descriptions for LIM_RIGHT_CTRL1 Bits Bit Name [7:6] LIM_RRT_R Settings 3 2 [1:0] Reset Access Right Limiter Release Rate 0x2 R/W 0x2 R/W 0x1 R/W 0x0 R/W 0x0 R/W 0 3200 ms/dB 1 1600 ms/dB 10 1200 ms/dB 11 [5:4] Description LIM_ATR_R 800 ms/dB Right Limiter Attack Rate 0 120 s/dB 1 60 s/dB 10 30 s/dB 11 20 s/dB LIM_LINK Channel Limiter Link 0 Use Independent Left and Right Channel Limiters 1 Link Both Channels to one Limiter (Use Left Limiter Controls) VBAT_TRACK_R Right Threshold Battery Tracking 0 Fixed Limiter Threshold set by LIM_THRES_R Bits in Register 0x12 1 Ramp down limiter threshold when VBAT < VBAT_INF_R using SLOPE_R Bits in Register 0x12. LIM_EN_R Right Limiter Mode 0 Limiter Off 1 Limiter On 10 Mute output if VBAT < VBAT_INF_R. 11 Limiter on only if VBAT < VBAT_INF_R. Rev. A| Page 49 of 59 SSM3582 Data Sheet Address: 0x12, Reset: 0x51, Name: LIM_RIGHT_CTRL2 7 6 5 4 3 2 1 0 0 1 0 1 0 0 0 1 [7:3] LIM_THRES_R (R/W) Right lim iter threshold 0: 16 Vp. 1: 15.5 Vp. 2: 15 Vp. ... 29: 3 Vp. 30: 2.5 Vp. 31: 2 Vp. [1:0] SLOPE_R (R/W) Right lim iter threshold reduction slope 0: 1:1 Threshold:VBAT reduction. 1: 2:1 Threshold:VBAT reduction. 10: 3:1 Threshold:VBAT reduction. 11: 4:1 Threshold:VBAT reduction. [2] RESERVED Table 41. Bit Descriptions for LIM_RIGHT_CTRL2 Bits Bit Name [7:3] LIM_THRES_R Settings Description Reset Access Right Limiter Threshold 0xA R/W 0 16 V p-p 1 15.5 V p-p 2 15 V p-p 3 14.5 V p-p 4 14 V p-p 5 13.5 V p-p 6 13 V p-p 7 12.5 V p-p 8 12 V p-p 9 11.5 V p-p 10 11 V p-p 11 10.5 V p-p 12 10 V p-p 13 9.5 V p-p 14 9.25 V p-p 15 9 V p-p 16 8.75 V p-p 17 8.5 V p-p 18 8.25 V p-p 19 8 V p-p 20 7.5 V p-p 21 7 V p-p 22 6.5 V p-p 23 6 V p-p 24 5.5 V p-p 25 5 V p-p 26 4.5 V p-p 27 4 V p-p 28 3.5 V p-p 29 3 V p-p 30 2.5 V p-p 31 2 V p-p Rev. A| Page 50 of 59 Data Sheet Bits Bit Name 2 RESERVED [1:0] SLOPE_R SSM3582 Settings Description Reset Access Reserved 0x0 R Right Limiter Threshold Reduction Slope 0x1 R/W Description Reset Access Right Limiter Battery Voltage Inflection Point 0x22 R/W Description Reset Access Left DAC High Frequency Clip Value 0xFF R/W 0 1:1 Threshold: VBAT Reduction 1 2:1 Threshold: VBAT Reduction 10 3:1 Threshold: VBAT Reduction 11 4:1 Threshold: VBAT Reduction Address: 0x13, Reset: 0x22, Name: LIM_RIGHT_CTRL3 7 6 5 4 3 2 1 0 0 0 1 0 0 0 1 0 [7:0] VBAT_INF_R (R/W) Right lim iter battery voltage inflection point Table 42. Bit Descriptions for LIM_RIGHT_CTRL3 Bits Bit Name [7:0] VBAT_INF_R Settings Address: 0x14, Reset: 0xFF, Name: CLIP_LEFT_CTRL 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 [7:0] DAC_CLIP_L (R/W) Left DAC high frequency clip value 0xFF: Clip to 0 dB. 0xFE: Clip to 255/256. 0xFD: Clip to 254/256. 0xFC: ... 0x00: Clip to 1/256. Table 43. Bit Descriptions for CLIP_LEFT_CTRL Bits Bit Name [7:0] DAC_CLIP_L Settings 0xFF Clip to 0 dB 0xFE Clip to 255/256 0xFD Clip to 254/256 0xFC ... 0x00 Clip to 1/256 Rev. A| Page 51 of 59 SSM3582 Data Sheet Address: 0x15, Reset: 0xFF, Name: CLIP_RIGHT_CTRL 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 [7:0] DAC_CLIP_R (R/W) Right DAC high frequency clip value 0xFF: Clip to 0 dB. 0xFE: Clip to 255/256. 0xFD: Clip to 254/256. 0xFC: ... 0x00: Clip to 1/256. Table 44. Bit Descriptions for CLIP_RIGHT_CTRL Bits Bit Name [7:0] DAC_CLIP_R Settings Description Reset Access Right DAC High Frequency Clip Value 0xFF R/W Description Reset Access 0xFF Clip to 0 dB 0xFE Clip to 255/256 0xFD Clip to 254/256 0xFC ... 0x00 Clip to 1/256 Address: 0x16, Reset: 0x00, Name: FAULT_CTRL1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:4] OTW_GAIN_R (R/W) Right channel over tem perature warning gain reduction 0: No gain reduction. 1: 1.5 dB gain reduction. 10: 3 dB gain reduction. 11: 5.625 dB gain reduction. [1:0] OTW_GAIN_L (R/W) Left channel over tem perature warning gain reduction 0: No gain reduction. 1: 1.5 dB gain reduction. 10: 3 dB gain reduction. 11: 5.625 dB gain reduction. [3:2] RESERVED Table 45. Bit Descriptions for FAULT_CTRL1 Bits Bit Name Settings [7:6] RESERVED Reserved 0x0 R [5:4] OTW_GAIN_R Right Channel Over Temperature Warning Gain Reduction 0x0 R/W 0 1 No Gain Reduction 1.5 dB Gain Reduction 10 3 dB Gain Reduction 11 5.625 dB Gain Reduction [3:2] RESERVED Reserved 0x0 R [1:0] OTW_GAIN_L Left Channel Over Temperature Warning Gain Reduction 0x0 R/W 0 No Gain Reduction 1 1.5 dB Gain Reduction 10 3 dB Gain Reduction 11 5.625 dB Gain Reduction Rev. A| Page 52 of 59 Data Sheet SSM3582 Address: 0x17, Reset: 0x30, Name: FAULT_CTRL2 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 0 [7] MRCV (W) Engage m anual fault recovery attem pt 0: No m anual recovery attem pt. 1: One m anual recovery attem pt. [0] ARCV_OC (R/W) Overcurrent fault auto recovery control 0: Auto Recovery Enabled. 1: Manual recovery using MRCV Bit. [6] RESERVED [1] ARCV_OT (R/W) Over tem perature fault auto recovery control 0: Auto Recovery Enabled. 1: Manual recovery using MRCV Bit. [5:4] MAX_AR (R/W) Maxim um Autom atic Recovery Attem pts 0: 1 attem pt. 1: 3 attem pts. 10: 7 attem pts. 11: Unlim ited attem pts. [2] ARCV_UV (R/W) Undervoltage Fault Auto Recovery Control 0: Auto Recovery Enabled. 1: Manual recovery using MRCV Bit. [3] RESERVED Table 46. Bit Descriptions for FAULT_CTRL2 Bits Bit Name Description Reset Access 7 MRCV Settings Engage Manual Fault Recovery Attempt 0x0 W 6 RESERVED Reserved 0x0 R [5:4] MAX_AR Maximum Automatic Recovery Attempts 0x3 R/W 0 1 Attempt 1 3 Attempts 10 7 Attempts 11 Unlimited Attempts 3 RESERVED Reserved 0x0 R 2 ARCV_UV Undervoltage Fault Automatic Recovery Control 0x0 R/W 0x0 R/W 0x0 R/W 0 1 1 0 ARCV_OT Automatic Recovery Enabled Manual Recovery Using MRCV Register Over Temperature Fault Automatic Recovery Control 0 Automatic Recovery Enabled 1 Manual Recovery Using MRCV Bit ARCV_OC Over Current Fault Automatic Recovery Control 0 Automatic Recovery Enabled 1 Manual Recovery Using MRCV Bit Rev. A| Page 53 of 59 SSM3582 Data Sheet Address: 0x18, Reset: 0x00, Name: STATUS1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] UVLO_PVDD (R) PVDD under-voltage fault condition 0: PVDD OK. 1: PVDD undervoltage fault condition. [0] OTW (R) Over tem perature warning condition 0: No over tem perature warning. 1: Over tem perature warning. [6] UVLO_VREG (R) Regulator under-voltage fault condition 0: No undervoltage fault for AVDD regulator. 1: Undervoltage fault for AVDD regulator. [1] OTF (R) Over tem perature fault condition 0: No over tem perature fault. 1: Over tem perature fault. [5:2] RESERVED Table 47. Bit Descriptions for STATUS1 Bits Bit Name 7 UVLO_PVDD Settings 0 1 6 UVLO_VREG [5:2] RESERVED 1 OTF 0 Description Reset Access PVDD Undervoltage Fault Condition 0x0 R 0x0 R Reserved 0x0 R Over Temperature Fault Condition 0x0 R 0x0 R Description Reset Access Right limiter gain reduction engaged 0x0 R PVDD OK PVDD undervoltage fault condition Regulator Undervoltage Fault Condition 0 No undervoltage fault for AVDD regulator 1 Undervoltage fault for AVDD regulator 0 No overtemperature fault 1 Overtemperature fault OTW Over Temperature Warning Condition 0 No overtemperature warning 1 Overtemperature warning Address: 0x19, Reset: 0x00, Name: STATUS2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] LIM_EG_R (R) Right lim iter gain reduction engaged 0: Lim iter Gain Reduction Right Off. 1: Lim iter Gain Reduction Right On. [0] BAT_WARN_L (R) Battery voltage warning for left channel (VBAT<VBAT_INF_x) 0: VBAT > VBAT_INF_L left channel. 1: VBAT < VBAT_INF_L left channel. [6] CLIP_R (R) Right channel DAC clipping detected 0: No clipping right channel. 1: Clipping right channel. [1] AMP_OC_L (R) Left channel am plifier overcurrent condition 0: No over current left channel. 1: Over current left channel. [5] AMP_OC_R (R) Right channel am plifier overcurrent condition 0: No over current right channel. 1: Over current right channel. [4] BAT_WARN_R (R) Battery voltage warning for right channel (VBAT<VBAT_INF_x) 0: VBAT > VBAT_INF_R right channel. 1: VBAT < VBAT_INF_R right channel. [2] CLIP_L (R) Left channel DAC clipping detected 0: No clipping left channel. 1: Clipping left channel. [3] LIM_EG_L (R) Left lim iter gain reduction engaged 0: Lim iter Gain Reduction Left Off. 1: Lim iter Gain Reduction Left On. Table 48. Bit Descriptions for STATUS2 Bits Bit Name 7 LIM_EG_R Settings 0 Limiter Gain Reduction Right Off. 1 Limiter Gain Reduction Right On. Rev. A| Page 54 of 59 Data Sheet Bits Bit Name 6 CLIP_R 5 4 3 2 1 0 SSM3582 Settings Description Reset Access Right channel DAC clipping detected 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Description Reset Access Battery Voltage Readback 0x0 R 0 No clipping right channel. 1 Clipping right channel. AMP_OC_R Right channel amplifier overcurrent condition 0 No overcurrent right channel. 1 Overcurrent right channel. BAT_WARN_R Battery voltage warning for right channel (VBAT < VBAT_INF_x) 0 VBAT > VBAT_INF_R right channel. 1 VBAT < VBAT_INF_R right channel. LIM_EG_L Left limiter gain reduction engaged 0 Limiter Gain Reduction Left Off. 1 Limiter Gain Reduction Left On. CLIP_L Left channel DAC clipping detected 0 No clipping left channel. 1 Clipping left channel. AMP_OC_L Left channel amplifier overcurrent condition 0 No over current left channel. 1 Over current left channel. BAT_WARN_L Battery voltage warning for left channel (VBAT < VBAT_INF_x) 0 VBAT > VBAT_INF_L left channel. 1 VBAT < VBAT_INF_L left channel. Address: 0x1A, Reset: 0x00, Name: VBAT 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] VBAT (R) Battery voltage readback Table 49. Bit Descriptions for VBAT Bits Bit Name [7:0] VBAT Settings Address: 0x1B, Reset: 0x00, Name: TEMP 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] TEMP (R) Tem perature Sens or Readout Table 50. Bit Descriptions for TEMP Bits Bit Name [7:0] TEMP Settings Description Reset Access Temperature Sensor Readout. The actual temperature in degrees Celsius is TEMP - 60 decimal. 0x0 R Rev. A| Page 55 of 59 SSM3582 Data Sheet Address: 0x1C, Reset: 0x00, Name: SOFT_RESET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:1] RESERVED [0] S_RST (W) Full software reset 0: Normal operation. 1: Perform full software reset. Table 51. Bit Descriptions for SOFT_RESET Bits Bit Name [7:1] 0 Settings Description Reset Access RESERVED Reserved 0x0 R S_RST Full Software Reset 0x0 W 0 Normal Operation 1 Perform Full Software Reset Rev. A| Page 56 of 59 Data Sheet SSM3582 TYPICAL APPLICATION CIRCUIT Figure 86 shows a typical application circuit for a stereo output. Figure 87 shows a typical application circuit for a mono output. +1.8V (DVDD) AVDD_EN C3 10F AVDD DVDD_EN C2 10F C4 0.1F C5 10F C9 470F C7 C8 10F 470F PVDD SCL SDA REG AVDD REG DVDD I2C PVDD BSTL+ BCLK I2S/TDM C6 0.1F FSYNC SDATA TDM I2S INPUT VOLUME - CLASS-D MODULATOR DAC FULL BRIDGE POWER STAGE C10 0.22F OUTL+ C11 0.22F PVDD - CLASS-D MODULATOR DAC FULL BRIDGE POWER STAGE AGND OPEN ADDRx GND ADDRx DVDD 47k TO GND 47k TO DVDD 47k DVDD 47k ADDRx OUTR- OPTIONAL FB3 C13 0.22F C16 220pF 4/8 C17 220pF FB3/FB3: MURATA FERRITE BEAD NFZ2MSM181 DVDD_EN PIN SETUP OPTIONS DVDD_EN AVDD DVDD_EN AVDD_EN PIN SETUP OPTIONS AVDD_EN ADDRx ADDRx C15 220pF FB4 PGND ADDRx PIN SETUP OPTIONS DVDD C12 0.22F OUTR+ BSTR- SSM3582 C14 220pF FB1/FB2: MURATA FERRITE BEAD NFZ2MSM181 BSTR+ VOLUME 4/8 FB2 OUTL- BSTL- OPTIONAL FB1 PVDD AVDD_EN Figure 86. Typical Application Circuit for Stereo Output Rev. A| Page 57 of 59 13399-084 I2C R2 2.2k C1 0.1uF PVDD +4.5V TO +16V DVDD R1 2.2k ADDR1 +1.8V ADDR0 SEE DEVICE ADDRESS SETTING SECTION SSM3582 Data Sheet +1.8V (DVDD) AVDD_EN C3 10F AVDD DVDD_EN C2 10F DVDD C1 0.1uF C5 10F C4 0.1F C9 470F C7 C8 10F 470F PVDD SCL SDA REG AVDD REG DVDD I2C PVDD BSTL+ BCLK I2S/TDM C6 0.1F FSYNC SDATA TDM I2S INPUT VOLUME - CLASS-D MODULATOR DAC FULL BRIDGE POWER STAGE C10 0.22F OUTL+ C11 0.22F PVDD - CLASS-D MODULATOR DAC FULL BRIDGE POWER STAGE AGND OPEN ADDRx GND ADDRx DVDD 47k TO GND 47k TO DVDD 47k DVDD 47k C15 220pF C12 0.22F OUTR- C13 0.22F PGND ADDRx PIN SETUP OPTIONS DVDD C14 220pF OUTR+ BSTR- SSM3582 2/3 FB1/FB2: MURATA FERRITE BEAD NFZ2MSM181 BSTR+ VOLUME FB1 FB2 OUTL- BSTL- OPTIONAL ADDRx DVDD_EN PIN SETUP OPTIONS DVDD_EN AVDD AVDD_EN PIN SETUP OPTIONS AVDD_EN ADDRx ADDRx DVDD_EN PVDD AVDD_EN Figure 87. Typical Application Circuit for Mono Output Rev. A| Page 58 of 59 13399-085 I2C R2 2.2k ADDR1 R1 2.2k ADDR0 +1.8V PVDD +4.5V TO +16V SEE DEVICE ADDRESS SETTING SECTION Data Sheet SSM3582 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.18 31 40 1 30 0.50 BSC 4.70 4.60 SQ 4.50 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 END VIEW PKG-005131 SEATING PLANE 0.45 0.40 0.35 21 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 10 11 20 P IN 1 IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) BOTTOM VIEW 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5 10-08-2018-A PIN 1 INDICATOR AREA 6.10 6.00 SQ 5.90 Figure 88. 40-Lead Lead Free Chip Scale Package [LFCSP] 6 mm x 6 mm Body and 0.75 mm Package Height (CP-40-7) Dimensions shown in millimeters ORDERING GUIDE Model1 SSM3582BCPZ SSM3582BCPZRL SSM3582BCPZR7 EVAL-SSM3582Z 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Description 40-Lead Lead Free Chip Scale Package [LFCSP] 40-Lead Lead Free Chip Scale Package [LFCSP] 40-Lead Lead Free Chip Scale Package [LFCSP] Evaluation Board Z = RoHs Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2016-2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13399-0-5/19(A) Rev. A| Page 59 of 59 Package Option CP-40-7 CP-40-7 CP-40-7