1
MX98715AEC-D
1. FEATURES
• A single chip solution integrates 100/10 Base-T fast
Ethernet MAC, PHY and PMD
• Microsoft PC97, 98, 99 and Novell 4.11/5.0 certified.
• Support DMI 2.0 management.
• Support Intel PXE remote boot device.
• Fully comply to IEEE 802.3u specification
• Operates over 100 meters of STP and cat 5 UTP cable
• Fully comply to PCI spec. 2.1 up to 33MHz
• Fully comply to Advanced Configuration and Power
Interface (ACPI) Rev 1.1
• Fully comply to PCI Bus Power Management Inter-
face spec. Rev 1.1
• Support full and half duplex operations in both 100
Base-TX and 10 Base-T mode
• Supports 3 kinds of wake up events defined in Net-
work Device Class Power Management Spec 1.0.
Including:
- Magic Packet
- Link Change (link-on)
- Wake Up Frames
• Supports IEEE802.3x Frame Based Flow Control
scheme in full duplex mode.
• Supports early interrupt on both transmit and receive
operations. • 100/10 Base-T NWAY auto-negotiation
function
• Large on-chip FIFOs for both transmit and receive
operations without external local memory
• Bus master architecture with linked host buffers deliv-
ers the most optimized performance
• 32-bit bus master DMA channel provides ultra low
CPU utilization suitable for server and windows appli-
cations.
• Proprietary Adaptive Network Throughput Control
(ANTC) technology to optimize data integrity and
throughput
• Support up to 64K bytes boot ROM interface
• Three levels of loopback diagnositic capability
• Support a variety of flexible address filtering modes
with 16 CAM addresses and 128 bits hash
• MicroWire interface to EEPROM for customer's IDs
and configuration data
• Single +5V power supply, CMOS technology, 128-pin
PQFP package.
( Magic packet technology is a trademark of advanced Micro De-
vice Corp. )
2. GENERAL DESCRIPTIONS
The MX98715AEC-D controller is an IEEE802.3u com-
pliant single chip 32-bit full duplex, 10/100Mbps highly
integrated Fast Ethernet combo solution, designed to
address high performance local area networking (LAN)
system application requirements.
MX98715AEC-D's PCI bus master architecture delivers
the optimized performance for future high speed and pow-
erful processor technologies. In other words, the
MX98715AEC-D not only keeps CPU utilization low while
maximizing data throughput, but it also optimizes the
PCI bandwidth providing the highest PCI bandwidth uti-
lization. To further reduce maintenance costs the
MX98715AEC-D uses drivers that are backward com-
patible with the original MXIC MX98715 series control-
lers.
The MX98715AEC-D contains a PCI local bus glueless
interface, a Direct Memory Access (DMA) buffer man-
agement unit, an IEEE802.3u-compliant Media Access
Controller (MAC), large T ransmit and Receive FIFOs, and
an on-chip 10 Base-T and 100 Base-TX transceiver sim-
plifying system design and improving high speed signal
quality. Full-duple x oper ation are supported in both 10
Base-T and 100 Base-TX modes that increases the
controller's operating bandwidth up to 200Mbps.
Equipped with intelligent IEEE802.3u-compliant auto-
negotiation, the MX98715AEC-D-based adapter allows
a single RJ-45 connector to link with the other
IEEE802.3u-compliant device without re-configuration.
P/N:PM0719 REV. 0.1 ,FEB. 05, 2001
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
ADVANCED INFORMATION
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MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
In MX98715AEC-D, an innovative and propr ietary de-
sign "Adaptive Netw ork Throughput Control" (ANTC) is
built-in to configure itself automatically by MXIC's driver
based on the PCI burst throughput of diff erent PCs. With
this proprietary design, MX98715AEC-D can always
optimize its operating bandwidth, network data integrity
and throughput for different PCs.
The MX98715AEC-D features Remote-Power-On and Re-
mote-W ake-Up capability and is compliant with the Ad-
vanced Configuration and Power Interface version 1.0
(A CPI). This support enab les a wide range of wak e-up
capabilities, including the ability to customize the con-
tent of specified packet which PC should respond to,
even when it is in a low-power state. PCs and worksta-
tions could take advantage of these capabilities of be-
ing waked up and served simultaneiously over the net-
work by remote server or workstation. It helps organiza-
tions reduce their maintenance cost of PC network.
The 32-bit multiplexed bus interface unit of
MX98715AEC-D provides a direct interface to a PCI lo-
cal bus, simplifing the design of an Ethernet adapter in a
PC system. With its on-chip support for both little and
big endian byte alignment, MX98715AEC-D can also ad-
dress non-PC applications.
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MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
3. PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
BPA4
BPA3
BPA2
BPA1(EEDI)
BPA0(EECK)
EECS
BPD0(EED0)
BPD1
BPD2
BPD3
BPD4
BPD5
BPD6
BPD7
GND
VDD
AD0
AD1
GND
AD2
AD3
VDD
AD4
AD5
GND
AD6
RTX
VDD
GND
VDD
GND
VDD
GND
LANWAKE
INTAB
RSTB
PCICLK
GNTB
REQB
AD31
AD30
GND
AD29
AD28
VDD
AD27
GND
AD26
AD25
GND
AD24
CBEB3
IDSEL
GND
AD23
AD22
GND
AD21
AD20
VDD
AD19
AD18
GND
AD17
AD16
CBEB2
FRAMEB
GND
IRDYB
TRDYB
DEVSELSB
STOPB
VDD
PERRB
SERRB
PAR
CBEB1
AD15
GND
AD14
AD13
VDD
AD12
AD11
AD10
GND
AD9
AD8
CBEB0
AD7
RTX2EQ
EQTEST2
GND
TXOP
TXON
VDD
GND
GND
VDD
RXIP
RXIN
VDD
GND
VDD
GND
GND
CKREF
VDD
RDA
GND
VDD
LED3
LED2
LED1
BPA15(LED0)
BPA14
BPA13
GND
VDD
BPA12
BPA11
BPA10
BPA9
BOEB
BPA8
BPA7
BPA6
BPA5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
MX98715AEC-D
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MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
4. PIN DESCRIPTION ( 128 PIN PQFP )
( T/S : tri-state, S/T/S : sustended tri-state, I : input, O : output, O/D : open dr ain )
Pin Name Type Pin No 128 Pin Function and Driver
AD[31:0] T/S 116, 117 PCI address/data bus: shared PCI address/data bus lines. Little or big endian
119,120, byte ordering are supported.
122,124,
125,127,
3,4,6,7,9,
10,12,13,
26,28,29,
31-33,35,
36,38,39,
41,42,44,
45,47,48
CBE[3:0] T/S 128,14 PCI command and byte enab le bus: shared PCI command b yte enable b us,
25,37 during the address phase of the transaction, these four bits pro vide the b us
command. During the data phase, these f our bits provide the b yte enable .
FRAMEB S/T/S 15 PCI FRAMEB signal: shared PCI cycle start signal, asserted to indicate the
beginning of a bus tr ansaction. As long as FRAMEB is asserted, data
transf ers continue.
TRDYB S/T/S 18 PCI Target ready: issued by the target agent, a data phase is completed on
the rising edge of PCICLK when both IRDYB and TRDYB are asserted.
IRDYB S/T/S 17 PCI Master ready: indicates the bus master's ability to complete the current
data phase of the transaction. A data phase is completed on any rising edge
of PCICLK when both IRDYB and TRDYB are asserted.
DEVSELB S/T/S 19 PCI slav e device select: asserted b y the target of the current b us access .
When 98715ALEC is the initiator of current bus access, the target must as
sert DEVSELB within 5 bus cycles, otherwise cycle is aborted.
IDS E L I 1 PCI initialization device select: target specific device select signal for
configuration cycles issued by host.
PCICLK I 113 PCI bus cloc k input: PCI bus cloc k range from 16MHz to 33MHz.
RSTB I 112 PCI b us reset: host system hardware reset.
LANWAKE O 110 LAN wak e up signal:asserts high to indicate a magic pac k et has been de-
tected in P ac ket enab le mode .
INTA B O/D 111 PCI bus interrupt request signal: wired to INTAB line.
SERRB O/D 23 PCI bus system error signal: If an address parity error is detected and CFCS
bit 8 is enabled, SERRB and CFCS's bit 30 will be asserted.
PERRB S/T/S 22 PCI b us data error signal: As a bus master , when a data parity error is
detected and CFCS bit 8 is enabled, CFCS bit 24 and CSR5 bit 13 will be
asserted. As a bus target, a data parity error will cause PERRB to be
asserted.
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MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
Pin Name Type Pin No 128 Pin Function and Driver
PAR T/S 24 PCI bus parity bit: shared PCI bus even parity bit for 32 bits AD bus and CBE
bus.
STOPB S/T/S 20 PCI Target requested transfer stop signal: as bus master, assertion of STOPB
cause MX98715AEC-D either to retry , disconnect, or abort.
REQB T/S 115 PCI bus request signal: to initiate a bus master cycle request
GNTB I 114 PCI bus g rant acknowledge signal: host asserts to inform MX98715AEC-D
that access to the bus is granted
BPA1 O 61 Boot PROM address bit 1(EECS=0): together with BPA[15:0] to access
(EEDI) e xternal boot PROM up to 256KB .
EEPROM data in(EECS=1): EEPROM serial data input pin.
BPA0 O 60 Boot PR OM address bit 0(EECS=0): together with BPA[15:0] to access
(EECK) e xternal boot PROM up to 256KB.
EEPROM clock(EECS=1): EEPROM clock input pin
BPA[14:0] O 77-76,
73-70, Boot PROM address line .
68-60
BPA1 5 O 7 8 Boot PROM address line 15.
/LED0 Programmable LED pin 0:
CSR9.28=1 Set the LED as Link Speed (10/100)LED.
CSR9.28=0 Set the LED as Activity LED.
Default is activity LED after reset.
<Note>:This pin acts as LED0 normally. It automatically switch to Boot
PROM address 15 function while accessing Boot PROM.
BPD0 T/S 58 Boot PROM data line 0(EECS=0): boot PROM or flash data line 0.
(EEDO) EEPROM data out(EECS=1): EEPROM serial data outpin(during reset
initialization).
BPD[7:0] T/S 51-58 Boot PROM data lines: boot PROM or flash data lines 7-0.
EECS O 59 EEPROM Chip Select pin.
BOEB O 69 Boot PROM Output Enable .
R D A O 8 4 Connecting an external resistor to ground, Resistor value=510 ohms
RTX O 103 Connecting an external resistor to ground, Resistor value=510 ohms
RTX2EQ O 102 Connecting an external resistor to ground, Resistor value=1.5K ohms.
EQTEST2 I 101 Not connected.
RXIP I 9 3 Twisted pair receive differential input: Support both 10 Base-T and 100
Base-TX receive differential input.
RXIN I 92 Twisted pair receive differential input: Support both 10 Base-T and 100
Base-TX receive differential input.
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MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
Pin Name Type Pin No 128 Pin Function and Driver
TXOP O 9 9 Twisted pair transmit differential output: Support both 10 Base-T and 100
Base-TX transmit differential output
TXON O 97 Twisted pair transmit differential output: Support both 10 Base-T and 100
Base-TX transmit differential output
CKREF I 86 Reference clock: 25MHz oscillator clock input
LED 1 O 79 Programmable LED pin 1:
CSR9.29=1 Set the LED as Link/Activity LED.
CSR9.29=0 Set the LED as Good Link LED.
Default is Good Link LED after reset.
LED 2 O 8 0 Programmable LED pin 2:
CSR9.30=1 Set the LED as Colision LED.
CSR9.30=0 Set the LED as Link Speed (10/100) LED .
Default is Link Speed LED after reset.
LED 3 O 8 1 Programmable LED pin 3:
CSR9.31=1 Set the LED as Full/Half duplex LED.
CSR9.31=0 Set the LED as Receive LED.
Default is Receive LED after reset.
VDD I 8,21,30,43, Power pins.
49,74,81,84,
89,91,94,97,
104,106,108,
121
GND I 2,5,11,16,27 Ground pins.
34,40,46,50
75,83,87,88
90,95,96,100
105,107,109
118,123,126
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MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
5. PROGRAMMING INTERFACE
5.1 PCI CONFIGURATION REGISTERS:
5.1.1 PCI ID REGISTER ( PFID ) ( Offset 03h-00h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Device ID (bit 31:16)
Vendor ID (bit 15:0)
5.1.2 PCI COMMAND AND STATUS REGISTER ( PFCS ) ( Offset 07h-04h )
The bit content will be reset to 0 when a 1 is written to the corresponding bit location.
bit 0 : IO Space Access, set to 1 enable IO access
bit 1 : Memory Space Access, set to 1 to enable memory access
bit 2 : Master Operation, set to 1 to support bus master mode
bit 5-3 : not used
bit 6 : Parity Error Response, set to 1 to enab le assertion of CSR<13> bit if parity error detected.
bit 7 : not used
bit 8 : System Error Enab le, set to 1 to enab le SERR# when parity error is detected on address lines and CBE[3:0].
bit 20 : New capability. Set to support PCI po wer management.
bit 22-bit19 : not used
bit 23 : Fast Back-to back, alw a ys set to accept fast back-to-back tr ansactions that are not sent to the same bus
device.
This register can be loaded from exter nal serial EEPROM or use a MXIC preset value of "10D9" and "0531" for
vendor ID and device ID respectively. Word location 3Eh and 3Dh in serial EEPROM are used to configure customer's
vendor ID and device ID respectively. If location 3Eh contains"FFFF" value then MXIC'svendor ID and device ID will
be set in this register, otherwise both 3Eh and 3Dh will be loaded into this register from serial EEPR OM.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Detect Party Error
Signal System Error
Data Parity Report
New Capability
Receive Master Abort
Receive Target Abort
Device Select Timing
Fast Back-to-back
System Error Enable
Parity Error Response
Master Operation
Memory Space Access
IO Space Access
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MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
5.1.3 PCI REVISION REGISTER ( PFRV ) ( Offset 0Bh-08h )
bit 3 - 0 : Step Number, range from 0 to Fh.
bit 7 - 4 : Re vision Number , fix ed to 2h f or MX98715AEC-D
bit 15 - 8 : not used
bit 23 - 16 : Subclass, fix ed to 0h.
bit 31 - 24 : Base Class, fix ed to 2h.
5.1.4 PCI LATENCY TIMER REGISTER ( PFLT ) (Offset 0Fh-0Ch)
bit 0 - bit 7 : System cache line size in units of 32 bit word, device driver should use this value to program CSR0<15:14>.
bit 8 - bit 15 : Configuration Latency Timer, when MX98715AEC-D assert FRAME#, it enables its latency timer to
count.
If MX98715AEC-D desserts FRAME# prior to timer expiration, then timer is ignored. Otherwise, after timer expires ,
MX98715AEC-D initiates transaction termination as soon as its GNT# is deserted.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Base Class
Step Number
Subclass
Revision Number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Configuration Latency Timer
System cache line size
PFLT Register (0Fh-0Ch)
bit 24:Data parity Report, is set to 1 only if PERR# active and PFCS<6> is also set.
bit 26-25:De vice Select Timing of DEVSELB pin.
bit 27:not used
bit 28:Receive Target Abort, is set to indicate a transaction is terminated by a target abort.
bit 29:Receive Master Abort, is set to indicate a master transaction with Master abort.
bit 30:Signal System Error, is set to indicate assertion of SERR#.
bit 31:Detected P arity Error, is set whene v er a parity error detected regardless of PFCS<6>.
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MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
5.1.5 PCI B ASE IO ADDRESS REGISTER ( PBIO ) ( Offset 13h-10h )
bit 0 : IO/Memory Space Indicator, fixed to 1 in this field will map into the IO space . This is a read only field.
bit 7 - 1 : not used, all 0 when read
bit 31 - 8 : Defines the address assignment mapping of MX98715AEC-D CSR registers.
5.1.6 PCI Base Memory Address Register ( PBMA ) ( Offset 17h-14h )
bit 0 : Memory Space Indicator , fix ed to 0 in this field will map into the memory space. This is a read only field.
bit 6 - 1 : not used, all 0 when read
bit 31 - 7 : Defines the address assignment mapping of MX98715AEC-D CSR registers.
5.1.7 PCI SUBSYSTEM ID REGISTER ( PSID ) ( Offset 2Ch-2Fh )
This register is used to uniquely identify the add-on board or subsystem where the NIC controller resides. V alues in
this register are loaded directly from e xternal serial EEPROM after system reset automatically. Word location 36h of
EEPROM is subsystem vendor ID and location 35h is subsystem ID.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Configuration Base Memory Address
Memory Spec Indicator
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Subsystem ID (31:16)
Subsystem Vendor ID (bit 15:0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Configuration Base IO Address
IO/Memory Spec Indicator
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MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
5.1.8 PCI B ASE EXPANSION R OM ADDRESS REGISTER ( PBER ) ( Offset 33h-30h )
bit 0 : Address Decode Enable, decoding will be enabled if only both enable bit in PFCS<1> and this expansion ROM
register are 1.
bit 10 - 1 : not use
bit 31 - 11 : Defines the upper 21 bits of expansion R OM base address .
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Expansion ROM Base Address (upper 21 bit)
Address Decode Enable
0 0 0 0 0 0 0
5.1.10 INTERRUPT REGISTER ( PFIT ) ( Offset 3Fh-3Ch )
bit 7 - 0 : Interrupt Line, system BIOS will writes the routing information into this field, driver can use this information
to determine priority and interrupt vector .
bit 15 - 8 : Interrupt Pin, fix ed to 01h which use INTA#.
bit 31 - 24 : Max_Lat which is a maximum period for a access to PCI b us .
bit 23 - 16 : Min_Gnt which is the maximum period that MX98715AEC-D needs to finish a burst PCI cycle.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Min-Gnt
Interrupt Pin
Max_Lat
0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0
Interrupt Line
5.1.9 PCI CAPABILITY POINTER REGISTER ( PFCP ) ( Offset 37h-34h )
bit 7- 0 : Capability pointer (Cap_Ptr) is set to 44h if PMEB is connected to PCI bus, otherwise 00.
bit 31- 8 : reserve d
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Capability Pointer (Set to 44h)
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MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
5.1.11 PCI DRIVER AREA REGISTER ( PFDA ) ( 43h-40h )
bit 29 : board type
bit 15 - 8 : driver is free to read and write this field for any purpose.
bit 7 - 0 : not used.
5.1.12 PCI POWER MANAGEMENT CAPABILITY REGISTER ( PPMC ) ( 47h-44h )
bit 31- 27 : PME_Support, read only indicates the po wer states in which the function may assert LANWAKE pin.
bit 31 ---- PME_D3cold (value=1)
bit 30 ---- PME_D3warm (value=1)
bit 29 ---- PME_D2 (v alue=1)
bit 28 ---- PME_D1 (v alue=1)
bit 27 ---- PME_D0 (v alue=1)
bit 26 : D2 mode support, read only, set to 1.
bit 25 : D1 mode support, read only, set to 1.
bit 24-22 : AUX_I bits. A uxiliary current field, set to 100.
bit 21 : DSI, read only, set to 0.
bit 20 : Auxiliary po wer source , set to 1. This bit only valid when bit 15 is a '1'.
bit 19 : PME Clock, read only, set to 0.
bit 18-16 : PCI power management version, set to 001, read only.
bit 15-8 : Ne xt Pointer , all bits set to 0.
bit 7-0 : Capability ID, read only, a 1 indicates that the data structure currently being pointed to is the PCI po wer
management data structure.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D2_Support
D1_Support
PME_Support
0 0 0 0 0 0 0 0
AUX_I
DSI
Auxiliary Power Source
PME Clock
Version
Next Pointer
Capability ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Board Type
Driver Special Use
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MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
5.1.13 PCI POWER MANAGEMENT COMMAND AND STATUS REGISTER ( PPMCSR ) ( 4Bh-48h )
bit 1-0 : Po wer_State , read/write , D0 mode is 00, D1 mode is 01, D2 mode is 10, D3 hot mode is 11.
bit7-2 : all 0. Reserv ed.
bit8 : PME_EN, set 1 to enable LANWAKE. Set 0 to disable LANWAKE assertion.
bit 12-9 : Data_Select f or report in the Data register located at bit 31:24.
bit 14-13 : Data_Scale , read only.
bit 15 : PME_Status independent of the state of PME_EN.
When set, indicates a assertion of LANWAKE pin. (support D3 cold).
Write 1 to clear the LANW AKE signal. Write 0, no eff ect.
bit 21-16 : Reserved.
bit 22 : B2_B3#, B2_B3 support for D3 hot, meaningful only if BPCC_EN = 1, read only.
bit 23 : BPCC_EN, Bus Power/Cloc k Control Enable , read only.
bit 31-24 : Data, read only.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bridge Extension Support
PME_Status
Data
Data_Scale
Data_Select
PME_EN
Reserved
Power State
0 0 0 0 0 0
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MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
5.2 HOST INTERF A CE REGISTERS
MX98715AEC-D CSRs are located in the host I/O or memory address space. The CSRs are double word aligned and
32 bits long. Definitions and address for all CSRs are as follows :
CSR Mapping
Register Meaning Offset from CSR Base
Address ( PBIO and PBMA )
CSR0 Bus mode 00
CSR1 Transmit poll demand 08h
CSR2 Receive poll demand 10h
CSR3 Receive list demand 18h
CSR4 Transmit list base address 20h
CSR5 Interrupt status 28h
CSR6 Operation mode 30h
CSR7 Interrupt enable 38h
CSR8 Missed frame counter 40h
CSR9 Serial ROM and MII management 48h
CSR10 Reserved 50h
CSR11 General Purpose timer 58h
CSR12 10 Base-T status port 60h
CSR13 SIA Reset Register 68h
CSR14 10 Base-T control port 70h
CSR15 Watchdog timer 78h
CSR20 Auto compensation A0h
CSR21 Flow control Register A8h
CSR22 MAC ID Byte 3-0 B0h
CSR23 Magic ID 5, 4 / MAC ID Byte 5, 4 B8h
CSR24 Magic ID Byte 3-0 C0h
CSR25 Filter 0 Byte Mask C8h
CSR26 Filter 1 Byte Mask D0h
CSR27 Filter 2 Byte Mask D8h
CSR28 Filter 3 Byte mask E0h
CRS29 Filter Offset E8h
CSR30 Filter 1&0 CRC-16 F 0h
CSR31 Filter 3&2 CRC-16 F 8h
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MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
5. 2.1 BUS MODE REGISTER ( CSR0 )
Field Name Description
0 S WR Software Reset, when set, MX98715AEC-D resets all internal hardware with the exception
of the configuration area and port selection.
1 BAR0 Internal bus arbitration scheme between receive and transmit processes.
The receive channel usually has higher priority over transmit channel when receive FIFO
is partially full to a threshold. This threshold can be selected b y programming this bit. Set
for lower threshold, reset for normal threshold.
6:2 D SL Descriptor Skip Length, specifies the number of longwords to skip between two descrip-
tors.
7 BLE Big/Little Ending, set for big endian byte ordering mode, reset for little endian byte ordering
mode, this option only applies to data buffers
13:8 PBL Programmable Burst Length, specifies the maximum number of longwords to be trans-
ferred in one DMA transaction. default is 0 which means unlimited burst length, possible
values can be 1,2,4,8,16,32 and unlimited .
15:14 CAL Cache Alignment, programmable address boundaries of data burst stop, MX98715AEC-D
can handle non-cache- aligned fragment as well as cache-aligned fragment efficiently.
18:17 TAP Transmit Auto-Polling time interval, defines the time inter val for MX98715AEC-D to per-
forms transmit poll command automatically at transmit suspended state.
21 RME PCI Memory Read Multiple command enable, indicates bus master may intend to fetch
more than one cache lines disconnecting.
23 R LE PCI Memory Read Line command enable, indicating bus master intends to fetch a com-
plete cache line.
2 4 WLE PCI Memory Write and Invalidate command enable, guarantees a minimum transfer of one
complete cache.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAP-Transmit Automatic Polling
WIE-Write and Invalidate Enable
RLE-Read Line Enable
RME-Read Multiple Enable
ZERO-Must be zero
DSL-Descriptor Skip Length
SWR-Software Reset
CAL-Cache Alignment
PBL-Programmable Burst Length
BLE-Big/Little Endian
BAR0-Bus Arbitration bit 0
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5.2.2 TRANSMIT POLL COMMAND ( CSR1 )
Field Name Description
31:0 TPC Write only , when written with any v alue, MX98715AEC-D read transmit descriptor list in
host memory pointed by CSR4 and processes the list.
5.2.3 RECEIVE POLL COMMAND ( CSR2 )
Field Name Description
31:0 RPC Write only , when written with any value, MX98715AEC-D read receive descriptor list in host
memory pointed by CSR3 and processes the list.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Transmit Poll command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Receive Poll command
TABLE 5.2.0 TRANSMIT AUTO POLLING BITS
CSR<18:17> Time Interv al
00 No transmit auto-polling, a write to CSR1 is required to poll
01 auto-poll e v ery 200 us
10 auto-poll e v ery 800 us
11 auto-poll e v ery 1.6 ms
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5.2.4 DESCRIPT OR LIST ADDRESS ( CSR3, CSR4 )
CSR3 Receive List Base Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start of Receive List Address
CSR4 Transmit List Base Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start of Transmit List Address
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5.2.5 STATUS REGISTER ( CSR5 )
Field Name Description
2 8 WKUPI W ake Up event interrupt. Set if wake-up e vent occurs in powerdo wn mode.
27 LC 100 Base-TX link status has changed either from pass to fail or fail to pass .
Read CSR12<1> f or 100 Base-TX link status.
25:23 EB Error Bits, read only, indicating the type of error that caused f atal bus error.
22:20 TS Transmit Process State , read only bits indicating the state of transmit process.
19:17 RS Receive Process State , read only bits indicating the state of receive process.
16 NIS Normal Interrupt Summary, is the logical OR of CSR5<0>, CSR5<2> and CSR5<6> and
CSR5<28>.
15 AI S Abnormal Interrupt Summary, is the logical OR of CSR5<1>, CSR5<3>, CSR5<5>,
CSR5<7>, CSR5<8>, CSR5<9>, CAR5<10>, CSR5<11> and CSR5<13>, CSR5<27>.
14 ERI Early receive interrupt, indicating the first buff er has been filled in ring mode, or 64 b ytes
has been received in chain mode .
1 3 FBE F atal Bus Error , indicating a system error occurred, MX98715AEC-D will disable all b us
access.
12 L F Link Fail, indicates a link fail state in 10 Base-T port. This bit is valid only when
CSR6<18>=0, CSR14<8>=1, and CSR13<3>=0.
1 1 GTE General Purpose Timer Expired, indicating CSR11 counter has expired.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RS-Receive Process State
NIS-Normal Interrupt Summary
LF-Link Fail
ETI-Early Transmit Interrupt
AIS-Abnormal Interrupt Summary
ERI-Early Receive Interrupt
FBE-Fatal Bus Error
GTE-General Purpose Timer Expired
WKUPI-Wake Up event Interrupt
LC-Link Change
RPS-Receive Process Stopped
RI-Receive Interrupt
EB-Error Bits
TS-Transmit Process State
RWT-Receiv e W atchdog Timeout
RU-Receive Buffer Unavailable
LPANCI-Link Pass/Autonegotiation
Completed Interrupt
UNF-Transmit Underflow
TJT-Transmit Jabber Timeout
TU-Transmit Buffer Unavailable
TPS-Transmit Process Stopped
TI-Transmit Interrupt
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Field Name Description
10 ETI Early Transmit Interrupt, indicating the pack et to be transmitted w as fully transf erred to
internal TX FIFO. CSR5<0> will automatically clears this bit.
9 R WT Receive Watchdog Time-out, reflects the network line status where receive w atchdog
timer has e xpired while the other node is still activ e on the netw ork.
8 RPS Write only, when written with any v alue, MX98715AEC-D reads receive descriptor list in
host memory pointed by CSR4 and processes the list.
7 RU Receive Buffer Unavailable, the receive process is suspended due to the next
descriptor in the receive list is owned by host. If no receive poll command is issued, the
reception process resumes when the ne xt recogniz ed incoming frame is receiv ed.
6 RI Receive Interrupt, indicating the completion of a frame reception.
5 UNF Transmit Underflow, indicating transmit FIFO has run empty before the completion of a
pack et transmission.
4 LPANCI When autonegotiation is not enabled ( CSR14<7>=0 ), this bit indicates that the 10
Base-T link integrity test has completed successfully, after the link was down. This bit is
also set as as a result of writing 0 to CSR14<12> ( Link Test Enable ).
When Autonegotiation is enabled ( CSR14<7> =1 ) , this bit indicates that the autonegotiation
has completed ( CSR12<14:12>=5 ). CSR12 should then be read for a link status report.
This bit is only v alid when CSR6<18>=0, i.e. 10 Base-T port is selected Link F ail interrupt
( CSR5<12> ) will automatically clears this bit.
3 TJT Transmit Ja bber Timeout, indicating the MX98715 has been excessiv ely activ e . The
transmit process is aborted and placed in the stopped state. TDES0<1> is also set.
2 TU Tr ansmit Buff er Unavailable , transmit process is suspended due to the ne xt descriptor in
the transmit list is o wned b y host.
1 TPS Transmit Process Stopped.
0 TI Transmit Interrupt. indicating a frame transmission was completed.
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TABLE 5.2.1 FATAL BUS ERROR BITS
CSR5<25:23> Process State
000 parity error for either SERR# or PERR#, cleared by softw are reset.
00 1 master abort
010 target abort
011 reserved
1XX reserved
TABLE 5.2.2 TRANSMIT PROCESS STATE
CSR5<22:20> Process State
000 Stopped- reset or transmit jabber e xpired.
001 Fetching tr ansmit descriptor
010 W aiting f or end of transmission
011 filling transmit FIFO
100 reserved
101 Setup pack et
110 Suspended, either FIFO underflow or una vailab le tr ansmit descriptor
111 closing transmit descriptor
TABLE 5.2.3 RECEIVE PROCESS STATE
CSR5<19:17> Process State
000 Stopped- reset or stop receive command. Fetching receiv e descriptor
010 checking f or end of receiv e pac k et
011 W aiting f or receive pac k et
100 Suspended, receive b uff er unav ailable
101 closing receive descriptor
110 Purging the current frame from the receive FIFO due to una vailable receiv e b uff er
111 queuing the receive fr ame from the receiv e FIFO into host receiv e b uffer
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5.2.6 OPERATION MODE REGISTER ( CSR6 )
Field Name Description
24 SCR Scramb ler Mode, def ault is set to enab le scr ambler function. Not affected by softw are
reset.
23 PC S Default is set to enable PCS functions . CSR6<18> must be set in order to operate in
symbol mode.
22 TTM Transmit Threshold Mode, set f or 10 Base-T and reset f or 100 Base-TX.
21 SF Store and Forward, when set, transmission starts only if a full pac k et is in tr ansmit FIFO.
the threshold values defined in CSR6<15:14> are ignored
19 HBD Heartbeat Disable , set to disable SQE function in 10 Base-T mode.
18 PS Port Select, default is 0 which is 10 Base-T mode, set for 100 Base-TX mode.
A software reset does not affect this bit.
17 COE Collision Offset Enable, set to enab le a modified bac koff algorithm during low collision
situation, reset f or normal backoff algorithm.
15:14 TR Threshold Control Bits, these bits controls the selected threshold level for MX98715AEC-
D's transmit FIFO, transmission starts when frame size within the tr ansmit FIFO is larger
than the selected threshold. Full frames with a length less than the threshold are also
transmitted.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COE-Collision Offset Enable
FC-Force collision mode
LOM-Loopback Operation Mode
TR-Threshold Control Bits
ST-Start/Stop Transmission Command
TTM-Transmit Threshold Mode
SF-Store and Forward
PR-Promiscuous Mode
HBD-Hearbeat Disable
PS-Port Select
FD-Full Duplex Mode
PM-Pass All Multicast
SB-Start/Stop Backoff Counter
IF-Inverse Filtering
PB-Pass Bad Frame
HO-Hash-Only Filtering Mode
SR-Start/Stop Receive
HP-Hash/Perfect Receive Filtering Mode
PCS-PCS function
SCR-Scrambler Mode
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Field Name Description
13 ST Start/Stop Transmission Command, set to place transmission process in running state
and will try to transmit current descriptor in transmit list. When reset, tr ansmit process is
placed in stop state.
12 FC F orce Collision Mode , used in collision logic test in internal loopback mode, set to force
collision during next tr ansmission attempt. This can result in e xcessiv e collision reported
in TDES0<8> if 16 or more collision.
11:10 LOM Loopback Operation Mode , see tab le 5.2.6.
9 FD Full-Duple x Mode , set f or simultaneous tr ansmit and receive oper ation, heart beat chec k
is disabled, TDES0<7> should be ignored, and internal loopback is not allowed. This bit
controls the v alue of bit 6 of link code w ord .
7 PM P ass All Multicast, set to accept all incoming fr ames with a multicast destination address
are received. Incoming frames with physical address are filtered according to the CSR6<0>
bit.
6 PR Promiscuous Mode, an y incoming v alid fr ames are accepted, def ault is reset and not
aff ected by softw are reset.
5 SB Start/Stop Back off Counter, when reset, the back off timer is not aff ected b y the network
carrier activity. Otherwise , timer will start counting when carrier drops.
4 IF In v erse Filtering, read only bit, set to operate in inv erse filtering mode, only valid during
perf ect filtering mode.
3 PB P ass Bad Frames, set to pass bad frame mode , all incoming frames passed the address
filtering are accepted including runt frames , collided fragments, truncated frames caused
b y FIFO ov erflo w.
2 HO Hash-Only Filtering Mode , read only bit, set to operate in imperfect filtering mode for both
ph ysical and multicast addresses .
1 SR Start/Stop Receive, set to place receiv e process in running state where descriptor
acquisition is attempted from current position in the receive list. Reset to place the
receive process in stop state .
0 HP Hash/Perfect Receiv e Filtering Mode, read only bit, set to use hash table to filter multicast
incoming frames . If CSR6<2> is also set, then the physical addresses are
imperf ect address filtered too . If CSR6<2> is reset, then physical addresses are perf ect
address filtered, according to a single ph ysical address as specified in setup fr ame.
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TABLE 5.2.4 TRANSMIT THRESHOLD
CSR6<21> CSR6<15:14> CSR6<22>=0 CSR6<22>=1 (Threshold bytes)
(for 100 Base-TX) (for 10 Base-T)
0 00 128 72
0 01 256 96
0 10 512 128
0 11 1024 160
1 XX ( Store and Forw ard )
TABLE 5.2.5 DATA PORT SELECTION
CSR14<7> CSR6<18> CSR6<22> CSR6<23> CSR6<24> Port
1 0 X X 1 Nway Auto-negotiation
0 0 1 X 0 10 Base-T
0 1 0 1 X 100 Base-TX
TABLE 5.2.6 LOOPBACK OPERATION MODE
CSR6<11:10> Operation Mode
00 Normal
01 Internal loopback at FIFO port
11 Internal loopback at the PHY level
10 External loopback at the PMD le v el
TABLE 5.2.7 FILTERING MODE
CSR6<7> CSR6<6> CSR6<4> CSR6<2> CSR6<0> Filtering Mode
0 0 0 0 0 16 perf ect filtering
0 0 0 0 1 512-bit hash + 1 perf ect filtering
0 0 0 1 1 512-bit hash f or multicast and
ph ysical addresses
0 0 1 0 0 Inverse filtering
X 1 0 0 X Promiscuous
0 1 0 1 1 Promiscuous
1 0 0 0 X Pass All Multicast
1 0 0 1 1 Pass All Multicast
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5.2.7 INTERRUPT MASK REGISTER ( CSR7 )
Field Name Description
28 WKUPIE Wak e Up Event Interrupt Enab le, enab les CSR5<28>.
27 LCE Link Changed Enab le, enab les CSR5<27>.
16 NIE Normal Interrupt Summary Enable, set to enab le CSR5<0>, CSR5<2>, CSR5<6>.
1 5 AIE Abnormal Interrupt Summary enable, set to enable CSR5<1>, CSR5<3>, CSR5<5>,
CSR5<7>, CSR5<8>, CSR5<9>, CSR5<11> and CSR5<13>.
14 ERIE Early Receive Interrupt Enable
13 FBE Fatal Bus Error Enable, set together with with CSR7<15> enab les CSR5<13>.
12 LFE Link F ail Interrupt Enable , enables CSR5<12>
11 GPTE General Purpose Timer Enab le, set together with CSr7<15> enab les CSR5<11>.
10 ETIE Early Transmit Interrupt Enab le, enab les CSR5<10>
9 RWE Receiv e W atchdog Timeout Enable, set together with CSR7<15> enab les CSR5<9>.
8 RSE Receive Stopped Enable , set together with CSR7<15> enables CSR5<8>.
7 R UE Receive Buff er Una v ailable Enable , set together with CSR7<15> enables CSR5<7>.
6 RIE Receiv e Interrupt Enable, set together with CSR7<16> enab les CSR5<6>.
5 UNE Underflo w Interrupt Enable , set together with CSR7<15> enables CSR5<5>.
4 LPANCIE Link P ass/Autonegotiation Completed Interrupt Enab le
3 TJE Transmit Ja bber Timeout Enab le, set together with CSR7<15> enab les CSR5<3>.
2 TUE Transmit Buff er Unav ailable Enab le , set together with CSR7<16> enables CSR5<2>.
1 TSE Transmit Stop Enab le, set together with CSR7<15> enables CSR5<1>.
0 TIE Tr ansmit Interrupt Enab le , set together with CSR7<16> enables CSR5<0>.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NIE-Normal interrupt Summary Enable
FBE-Fatal Bus Error Enable
LFE-Link Fail Enable
AIE-Abnormal Interrupt Summary Enable
ERIE-Early Receive Interrupt Enable
ETIE-Early Transmit Interrupt Enable
RIE-Receive Interrupt Enable
RWE-Receiv e W atchdog Enable
RSE-Receive Stopped Enable
GPTE-General-Purpose Timer Enable
RUE-Receive Buffer Unavailable Enable
UNE-Underflow Interrupt Enable
LPANCIE-Link Pass
/Nway Complete Interrupt Enable
TJE-Transmit Jabber Timeout Enable
TUE-Transmit Buffer Unavailable Enable
TSE-Transmit Stopped Enable
TIE-Transmit Interrupt Enable
LCE-Link Changed Enable
WKUPIE-Wake Up event interrupt Enable
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5.2.8 MISSED FRAME COUNTER ( CSR8 )
Field Name Description
16 MFO Missed Frame Overflow, set when missed frame counter overflo ws , reset when CSR8
is read.
15:0 MFC Missed F rame Counter, indicates the number of frames discarded because no host
receive descriptors w ere av ailab le.
5.2.9 NON-VOLATILE MEMOR Y CONTR OL REGISTER ( CSR9 )
Field Name Description
31 LED3SEL 0:Default v alue . Set LED3 as RX LED.
1:Set LED3 as F/H duple x LED.
30 LED2SEL 0: Default value . Set LED2 as SPEED LED.
1: Set LED2 as Collision LED
29 LED1SEL 0:Default v alue. Set LED1 as Good Link LED .
1: Set LED1 as Link/Activity LED.
28 LED0SEL 0:Default value. Set LED0 as Activity LED.
1: Set LED0 as Link Speed (10/100) LED .
2 4 *LED4SEL 0: Default value. Set LED4 as Collison LED .
1: Set LED4 as PMEB LED. (LED4 is ont bonded to pin)
1 4 R D Boot ROM read operation when boot ROM is selected.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Missed Frame Overflow
Missed Frame Counter
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR-Boot ROM Select
Data-Boot ROM data
or Serial ROM control
LED1SEL
LED4SEL
LED2SEL
LED3SEL
LED0SEL
WKFCAT
RD-Read Operation
Reload
SR-Serial ROM Select
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5.2.10 GENERAL PURPOSE TIMER ( CSR11 )
Field Name Description
1 6 CO N When set, the general purpose timer is in continuous operating mode. When reset, the
timer is in one-shot mode.
15:0 Timer Value contains the timer value in a cycle time of 204.8us .
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CON-Continuous Mode
Timer V alue
26:25 WKF ACT W ake up frame catenation option bits.
CRS21<4> CSR<26> CSR<25> Wake up event
0 X X CH0+CH1+CH2+CH3
1 0 0 (CH0*CH1)+(CH2*CH3)
1 0 1 (CH0*CH1)+CH2+CH3
1 1 0 (CH0*CH1*CH2)+CH3
1 1 1 CH0*CH1*CH2*CH3
13 Reload EEPROM reload operation select bit.
Operation definition:
RD Reload Operation
1 0 Boot ROM/EEPROM Read
1 1 EEPROM reload operation (SR=1)
12 B R Boot ROM Select, set to select boot ROM only if CSR9<11>=0.
1 1 S R Serial ROM Select, set to select serial ROM for either read or write operation.
Field Name Description
7:0 Data If boot ROM is selected ( CSR9<12> is set ), this field contains the data to be read from
and written to the boot ROM. If serial ROM is selected , CSR9<3:0> are defined as
follows :
3 S DO Serial ROM data out from serial ROM into MX98715AEC-D .
2 SDI Serial ROM data input to serial ROM from MX98715AEC-D .
1 SCLK Serial clock output to serial ROM.
0 S CS Chip select output to serial ROM.
W arning : CSR9<11> and CSR9<12> should be mutually exclusive for correct operations.
01
LED0SEL ACT SPEED
LED1SEL LINK LINK/ACT
LED2SEL SPEED COL
LED3SEL RX FULL/HALF
LED4SEL* COL PMEB
<Note> LED4SEL is only valid in MX98715B
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5.2.11 10 B ASE-T STATUS Port ( CSR12 )
Field Name Description
31:16 LPC Link P artner's Link Code W ord, where bit 16 is S0 ( selector field bit 0 ) and bit31 is NP
( Next Page ). Eff ectiv e only when CSR12<15> is read as a logical 1.
15 LPN Link P artner Negotiable , set when link partner support NW AY algorithm and CSR14<7>
is set.
14:12 ANS Autonegotiation Arbitration State , arbitration states are defined
000 = A utonegotiation disable
001 = Transmit disable
010 = ability detect
011 = Ackno wledge detect
100 = Complete ackno wledge detect
101 = FLP link good; autonegotiation complete
110 = Link check
When autonegotiation is completed, an ANC interrupt ( CSR5<4>) is generated, write
001 into this field can restart the autonegotiation sequence if CSR14<7> is set.
Otherwise, these bits should be 0.
11 TRF Transmit Remote F ault
3 APS Autopolarity State, set when polarity is positiv e. When reset, the 10Base-T polarity is
negative . The receiv ed bit stream is in v erted b y the receiv er.
2 LS10B Set when link status of 10 Base-T port link test fail. Reset when 10 Base-T link test is in
pass state.
1 LS100B Link state of 100 Base-TX, this bit reflects the state of SD pin, eff ectiv e only when
CSR6<23>= 1 ( PCS is set ). Set to indicate a f ail condition .i.e. SD=0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPC-Link Partner's Link Code Word
LPN-Link Partner Negotiable
ANS-Autonegotiation Arbitration State
TRF-Transmit Remote Fault
APS-Autopolarity State
LS10B-Link Status of 10 Base-T
LS100B-Link Status of 100 Base-TX
*Software reset has no effect on this register
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5.2.12 SIA Reset Register (CSR13)
Field Name Description
0 Nwa y Reset While writing 0 to this bit, resets the CSR12 & CSR14.
1 100Base-TX Reset Write a 1 will reset the internal 100 Base-TX PHY module
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
100 TX Reset-
100 Base-TX PHY level reset
Nway Reset-
Nway and 10 Base-T PHY level reset
5.2.13 10 Base-T Control PORT (CSR14)
Field Name Description
19 PAUSE Bit 10 of link code word f or 100 Base-TX pause mode .
18 T4 Bit 9 of link code word for T4 mode .
17 TXF Bit 8 of link code word f or 100 Base-TX full duplex mode.
16 TXH Bit 7 of link code word for 100 Base-TX half duplex mode. Meaningful only when CSR14<7>
( ANE ) is set.
12 LTE Link Test Enable , when set the 10 Base-T port link test function is enab led.
8 RSQ Receive Squelch Enable for 10 Base-T port. Set to enable .
7 ANE Autonegotiation Enable, .
6 HDE Half-Duple x Enable, this is the bit 5 of link code w ord, only meaningful when CSR14<7> is
set.
2 PWD10B Reset to power down 10 Base-T module , this will f orce both TX and RX port into tri-state
and pre v ent AC current path. Set for normal 10 Base T operation.
1 LBK Loop bac k enable f or 10 Base-T MCC .
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T4-100 Base-T4 (link code word)
PAUSE-Pause (link code word)
TXF-100 Base-TX full duplex
(link code word)
TXH-100 Base-TX half duplex
(link code word)
LTE-Link Test Enable
RSO-Receive Squelch Enable
ANE-Autonegotiation Enable
HDE-Half Duplex Enable)
PWD10B-Power down 10 Base-T
LBK-Loopback (MCC)
*The software reset bit (bit0 of CSR0) has no effect to this register.
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5.2.14 W ATCHDOG TIMER ( CSR15)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MBZ-Must Be Zero
RWR-Receiv e W atchdog Release
PWD-Receive W atchdog Disable
JCK-Jabber Clock
HUJ-Host Unjabber
JAB-Jabber Disable
Field Name Description
5 RW R Defines the time interval no carrier from receive watchdog e xpir ation until reenabling the
receive channel. When set, the receive watchdog is release 40-48 bit times from the last
carrier desertion. When reset, the receive w atchdog is released 16 to 24 bit times from
the last carrier desertion.
4 RW D When set, the receiv e w atchdog counter is disable. When reset, receiv e carriers longer
than 2560 bytes are guaranted to cause the watchdog counter to time out. Packets shorter
than 2048 bytes are guaranted to pass .
2 JCK When set, transmission is cut off after a range of 2048 b ytes to 2560 bytes is transmitted,
When reset, transmission f or the 10 Base-T port is cut off after a range of 26 ms to 33ms .
When reset, transmission for the 100 Base-TX port is cut off after a range of 2.6ms to
3.3ms.
1 HUJ Defines the time interv al between transmit jab ber e xpiration until reenabling of the
transmit channel. When set, the transmit channel is released immediately after the jabber
expiration.
When reset, the jabber is released 365ms to 420 ms after jab ber expiration f or 10 Base-T
port. When reset, the jabber is released 36.5ms to 42ms after the jabber e xploration for
100 Base-TX port.
0 JBD Ja bber Disab le, set to disab le tr ansmit jabber function.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DS130
DS120
5.2.15 Auto Compensation Register (CSR20)
Field Name Description
22 REOP Default = 1 for IC revision H, for all older revisions, this bit = 0 as default.
1 6 PENPRO It should be set to the same value as REOP bit.
14 DS130 When set, the auto-compensation circuit in transceiver is enable. Default=0
9 DS120 When set, the auto-compensation circuit in transceiver is enable. Default=0
<Note> DS120, DS130 must be set or reset together . Can be Loaded from EEPROM.
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5.2.16 Flow Control Register (CSR21)
Field Name Description
31:16 TMVAL Timer v alue in the flow control frame f or receiv e flo w control.
15 TEST Test the flow control timer .
14 RESTART Set the receive flow control into the restart mode, the RXFCEN should be asser ted.
The default v alue is 0.
13 RESTOP Set the receive flow control into the restop mode, the RXFCEN should be asser ted.
The default v alue is 0.
12 TXFCEN Transmit flo w control enab le . The default value is 1.
11 RXFCEN Receiv e flo w control enable . The def ault value is 0.
10 RUFCEN Send flow control frame control when the receive descriptor is unavailable, the RXFCEN
should be asserted. The default value is 0.
9 ST OPTX Indicate the tr ansmit status. If the receiv e flow control stop the tr ansmission, this bit is
set. After recovering transmission, this bit is clear.
8 REJECTFC Abort the receiv e flo w control fr ame when set. The default value is 0.
7 FCTH1 Receive flow control threshold 1.
6 FCTH0 Receive flow control threshold 0.
5 NFCEN Accept flow control from the auto-negotiation result.
4 WKFCATEN Enable the wake up frame catenation feature. See CSR9
3 LNKCHGDIS Set to disable link change detection in power down mode
2 MPHITDIS Set to disable magic packet address matching, loadable from EEPROM
Receive Flow Contr ol Threshold Table
FCTH1 1110
FCTH1 1000
Threshold V alue (Byte) 5 1 2 2 5 6 12 8 overflow
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMVAL-Flow Control timer Value
TEST-Test Flow Counter Timer
RESTART-Set Reset Mode
RESTOP-Set Restop Mode
TXFCEN-Transmit Flow Control Enable
RXFCEN-Receive Flow Control
STOPTX-Indicate the transmit is stoped
REJECTFC-Abort the Receive Flow Control Frame
FCTH1-Flow Control Thresold 1
FCTH0-Flow Control Thresold 0
RUFCEN-Receive Flow Control Enable
while Receive Descriptor is Unavailable
NFCEN-NWAY Flow Control
WKFCATEN-Wake up Frame Catenation Enable
LNKCHGDIS - Link change indication disable
MPHITDIS - magic packet hit disable
30
MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
5.2.17 MAC ID Byte 3-0 Register (CSR22)
5.2.18 Magic ID Byte 5,4/ MA C ID Byte 5,4 (CSR23)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAC ID byte 3
MAC ID byte 2
MAC ID byte 0
MAC ID byte 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Magic ID byte 5
Magic ID byte 4
MAC ID byte 4
MAC ID byte 5
5.2.19 Magic ID Byte 3-0 (CSR24)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Magic ID byte 3
Magic ID byte 2
Magic ID byte 0
Magic ID byte 1
5.2.20 Filter 0 Byte Mask Register 0 (CSR25)
Filter 1 Byte Mask Register 1 (CSR26)
Filter 2 Byte Mask Register 2 (CSR27)
Filter 3 Byte Mask Register 3 (CSR28)
CSR25 Filter N (N=0 to 3) Byte Mask Register N (N=0 to 3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Byte Mask
Field Name Description
31:0 Byte Mask If bit number j of the byte mask is set, byte n umber (offset+j) of the incoming frame is
checked.
31
MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
5.2.21 Filter Offset Register (CSR29)
Field Name Description
6:0 Pattern 0 Offset The offset defines the location of first byte that should be chec ked by filter 0 in the
frame. Offset is always g reater than 12.
7 Filter 0 Enable This bit is set to enab le the filter 0. If it is reset, filter 0 is disabled f or the wake-up
frame chec king.
14:8 Pattern 1 Offset The offset defines the location of first byte that should be checked by filter 1 in the
frame. Offset is always g reater than 12.
15 Filter 1 Enable This bit is set to enable the filter 1. If it is reset, filter 1 is disabled for the w ake-up
frame chec king.
22:16 Pattern 2 Offset The offset defines the location of first byte that should be checked by Filter 2 in
the frame . Offset is alwa ys greater than 12.
23 Filtre 2 Enable This bit is set to enable the filter 2. If it is reset, filter 2 is disabled for the w ake-up
frame chec king.
30:24 Pattern 3 Offset The offset defines the location of first byte that should be checked by Filter 3 in
the frame . Offset is alwa ys greater than 12.
31 Filter 3 Enab le This bit is set to enable the filtre 3. If it is reset, filter 3 is disabled for the w ake-up
frame chec king.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Filter 3 Offset
Filter 3 Enable
Filter 2 Enable
Filter 2 Offset
Filter 1 Enable
Filter 1 Offset
Filter 0 Enable
Filter 0 Offset
32
MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
Field Name Description
15:0 Filter 0 CRC-16 The 16-bit CRC value is programmed by the driver to be matched against the
current result from the CRC-16's remainder at the location specified by Filter 0
offset and Filter 0 Byte Mask register . if matched, the incoming frame is a wakeup
frame.
31:0 Filter 1 CRC-16 Same description as Filter 0 CRC-16.
5.2.22 Filter 1 and 0 CRC-16 Register (CSR30)
5.2.23 Filter 3 and 2 CRC-16 Register (CSR31)
Field Name Description
15:0 Filter 2 CRC-16 Same description as Filter 0 CRC-16.
31:0 Filter 3 CRC-16 Same description as Filter 0 CRC-16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Filter 1 CRC-16
Filter 0 CRC-16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Filter 3 CRC-16
Filter 2 CRC-16
33
MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
5.3 A CPI Power Management Support
The Advanced Configuration and Power Interface (ACPI)
Specification defines a flexible and abstract hardware
interface for a wide variety of PC systems to implement
pow er and thernal management functions . This chip is
fully compliant with the OnNow Network Device Class
P ower Management spec. rec.1.0, the PCI power man-
agement interface spec. rev.1.0 and the ACPI spec.
rev.1.0.
F our po wer states defined f or a PCI function are:
* D0-Fully On.
The device is completely active and respon-
sive.
* D1-Light Sleep.
Save a little power than D0 state. The PCI
clock is running.
* D2-Deeper Sleep:
Save more power than D1 state. The PCI clock
can be stopped.
* D3hot-Deepest Sleep:
Save more power than D2 state. The PCI clock
is stopped.
* D3cold-P o wer Do wn:
In this state, the main system power is
removedfrom the chip but will preserve their
PME context when transitioning from the D3cold
to the D0 state. Such function requires an
auxiliar y power source other than main sys-
tem pow er plane.
This chip also supports the OnNow Network Device
Class Specification based on the ACPI specification
defines the power management requirements of a net-
work de vice . It defines the following wake-up e vents:
* Reception of a Magic P ac k et.
* Reception of a Network wake-up frame.
* Detection of change in the network link state.
To put MX98715/725 into the sleep mode and enable
the wak e-up e vents detection are done as follo wing:
1. Write 1 to PPMCSR[8] to enable power management
feature.
2. Write the v alue to PPMCSR[1:0] to determine which
pow er state to enter.
If D1, D2 or D3hot state is set, the PC is still turned on
and is commonly called entering the Remote Wake-up
mode. Otherwise if the main power on a PC is totally
shut off, we call that it is in the D3cold state or Remote
Power-On mode. To sustain the operation of the Lan
card, a 5V standby power is required. Once the PC is
turned on, MX98715/725 loads the Magic ID from
EEPROM and set it up automatically. No registers is
needed to be programmed. After then, simply turn of
PC to enter D3cold state. In either Remote Wake-up mode
or Remote Power-On mode. The transceiver and the
RX bloc k are still alive to monitor the network activity. If
one of the three wak e-up e vents occured, the f ollo wing
status is changed:
1. PPMCSR[15] (PME status) is set to 1.
2. CRS5[28] (WKUPI) is set to 1.
3. PCI interrupt pin INTA# is asserted low.
4. PMEB pin is asserted low.
5. In MX98725, EXTSTARTB and LANWAKE are also
asserted.
5.3.1 Magic P ac ket
The Magic Pack et(TM) technology, proposed by AMD, is
used to remotely wak e up a sleeping or powered off PC
on a network. This is accomplished by sending a spe-
cific pack et, called Magic Pack et, to a node on the net-
work. When a NIC capable of recognizing the specific
frame goes to sleep (entering D1, D2 ro D3 state), it
scans all incoming frames addressed to the node for a
specific data sequence, which indicates to the control-
ler that this is a Magic Packet frame. The specific se-
quence consists of 16 duplications of the IEEE address
of this node, with no breaks or interruptions. This se-
quence can be located anywhere within the pac ket, but
must be preceded by a synchronization stream. The
synchronization stream is defined as 6 bytes of FFh.
For example, if the IEEE address for a particular node
on the network was 11h 22h 33h 44h 55h 66h, then the
Magic Packet for this node would be:
D A SA MISC. FF FF FF FF FF FF 11 22 33 44 55 66 11
22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66
MISC . CRC.
34
MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
This chip can automatically loads the IEEE address into
the internal registers from EEPROM while booting up.
the magic packet detection scheme is not active while
chip is in normal running state (D0). After entering into
the sleep mode(D1, D2, D3) b y host, the chip begins to
scan the incoming pack et b ut does not load the pac ket
into RX FIFO . If a magic pack et is detected, the PMEB
is asserted to notify the host.
Magic packet event occurs when the following condi-
tions are approv ed:
* The destination address of the received packet
matches.
* The PMEN bit (PPMCSR[8]) is set to 1.
* Not in D0 state.
* The magic packet pattern matches, i.e., 6*FFh +
16* Destination ID .
<Note>: The CRC value is not checked during magic
pack et detection.
5.3.2 Wake-up Frames
A network wake-up frame is typically a frame that is
sent by existing network protocols, such as ARP re-
quests or IP frames addressed to the machine. Before
putting the network adapter into the wake-up state , the
system passes to the adapter's driver a list of sample
frames and corresponding byte masks. Each sample
frame is an e xample of a frame that should wake up the
system. Each byte mask defines which bytes of the
incoming frames should be compared with correspond-
ing sample frame in order to determine whether or not
to accept the incoming frame as a wake-up e v ent.
The on-chip Wake-up logic prevides four programmable
filters that allow support of many different receive packet
patterns. Specifically, these filters allow suppor t of IP
and IPX protocols which currently are the only proto-
cols targeted to be power manageable. Each filter re-
lates to 32 contiguous bytes in the incoming fr ame.
When a frame is received from the network, the chip
examines its content to determine whether the pattern
matches to a wake-up frame. To know which byte of the
frame should be checked, a programmable byte-mask
and a programmable patter n offset are used for each
one of the f our supported filters. The pattern offset de-
fines the location of the first byte in the frame that should
be check ed. Beginning with the pattern offset, if bit j in
the byte mask is set, byte offset+j in the frame is
checked.
The chip implements imperfect pattern matching by
calculating a CRC-16 on all bytes of the receiv ed frame
that where specified by the pattern's offset and the byte
mask and comparing to a programmable pre-calculated
CRC-16 remainder value. The CRC calculation uses
the f ollowing polynomial:
G(X)=X16 + X15 + X2 +1
The calculated CRC-16 value is compared with four
possible CRC-16 v alues stored in CSR30 and CSR31.
if the result matches any one and the enable bit of the
corresponding filter also set, then we call a Wakeup
frame receiv ed.
Table1 shows the wake-up frame register block. This
b lock is accessed through CSR registers mapping.
Filter 0 Byte Mask CSR25
Filter 1 Byte Mask CSR26
Filter 2 Byte Mask CSR27
Filter 3 Byte Mask CSR28
Filter 3 Filter 2 Filter 1 Filter 0 CSR29
Filter 1 CRC-16 Filter 0 CRC-16 CSR30
Filter 3 CRC-16 Filter 2 CRC-16 CSR31
The four filters can operate independently to match four
32-byte wake up frames. They also can be programmed
to catenate each other to support longer wake up frames,
ranging from 32 bytes up to 128 bytes. The following
table sho ws the possible combination.
CSR21.4 CSR9.26 CSR9.25 Wake up event
WKFCATEN WKFCAT1 WKFCAT0
0 X X CH0+CH1+CH2+CH3
1 0 0 (CH0*CH1)+(CH2*CH3)
1 0 1 (CH0*CH1)+CH2+CH3
1 1 0 (CH0*CH1*CH2)+CH3
1 1 1 CH0*CH1*CH2*CH3
If WAKCATEN (CSR21.4) is not set, the f our filters are
independent and simultaneous to match the incoming
frame. When WKFCATEN is set, the catenation options
are determined by WKFCAT<1:0> (CSR<26:25>). For
example, if WKFCAT<1:0>=00, wake up event is oc-
curred only if either both of channel 0 and channel 1
match or both of channel 2 and channel 3 match. If the
35
MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
* Not in D0 state.
* The destination address of the received wakeup
frame matches.
* No CRC-32 error is detected in the wakeup fr ame.
* The PMEN bit (PPMCSR[8]) is set to 1.
* The enable bit in the wakeup frame register block
must be set.
* The CRC value calculated from the bytes in the
pre-designated locations equals to the respectively
stored CRC-16 value .
* If catenation must be met. enable bit WKFCATEN
is set, the condition in table 2.
5.3.3 Link Change
Link change wakeup event occurs when the following
conditions are met:
* Not in D0 state.
* The PMEN bit (PMCSR[8]) is set to 1.
* The cable is re-connected.
The Remote Power-on (RPO) feature is a mechanism
can be used to remotely power up a sleeping station.
When the PC turned on, MX98715AEC-D loads the net-
work ID from serial ROM automatically. Once the PC is
turned off, MX98715AEC-D enters the RPO mode.
MX98715AEC-D monitors the network for receipt of a
wakeup packet. If a magic packet or wake up frame is
received, it asserts LANWAKE, signal to wake up the
system. After main power is on, LANWAKE is deserted
by PCI RSTB signal. After the desertion, MX98715AEC-
D can enter RPO mode again if the main power is
switched off.
driver sets filter 0 and filter 1 be contiguous and also
sets filter 2 and filter 3 be contiguous by adjusting the
offsets, then two 64-byte wake up frames are supported.
Another example is that if WKFCAT<1:0>=11 and the
driver sets filter 0,1,2,3 as contiguous, a 128-byte wake
up frame is supported.
Wakeup Frames event occurs when following conditions
are met:
36
MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
6. AC/DC CHARA CTERISTICS
6.1 BOOT ROM READ TIMING
TRC
BPA 15-0
TOES
TCE
BCEB
BOEB
(CE&OE is typical shorted)
TOH
BPD 7:0
TACC
TOOLZ
TCOLZ
TOH
6.2 A C CHARACTERISTICS
SYMBOL DESCRIPTION MINIMUM TYPICAL MAXIMUM UNITS
TRC Read Cycle 8 - - PCI Cycle
TCE Chip Enab le Access Time - - 7 PCI Cycle
TACC Address Access Time - - 7 PCI Cycle
T OES Output Enable Access Time - - 7 PCI Cycl
T OH Output Hold from Address, CEB , or OEB 0 - - ns
PCI cycle range:66ns (16MHz)~25ns (40MHz)
37
MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
6.3 ABSOLUTE OPERATION CONDITION
Supply Voltage (VCC) -0.5V to +7.0V
DC Input Voltage (Vin) 4.75V to 5.25V
DC Output Voltage (Vout) -0.5V to VCC + 0.5V
Storage Temperature Range (Tstg) -55°C to +150°C
Operating T emperature Range 0°C to 70°C
Operating Surf ace Temperarure(25°C) 49°C(TYP)
P o wer Dissipation (PD) 750mW (Typ.)
Lead Temp. (TL) (Soldering, 10 sec) 260°C
ESD Rating (Rzap = 1.5k, Czap = 100pF) 1.0kV
Clamp Diode Current 20mA
6.4 DC CHARACTERISTICS
Symbol Parameter Conditions Min Max Units
TTL/PCI Input/Output
Voh Minimum High Le vel Output Voltage Ioh = -3mA 2.4 V
Vol Maximum Low Le v el Output Voltage Iol = +6mA 0.4 V
Vih Minimum High Le v el Input Voltage 2.0 V
Vil Maximum Lo w Lev el Input Voltage 0.8 V
Iin Input Current Vi = VCC or GND - 1.0 + 1.0 uA
Ioz Minimum TRI-STATE Output Leakage Current Vout = VCC or GND -10 +10 u A
LED output Dr iver
Vlol LED turn on Output Voltage Iol = 16mA 0.4 V
Supply
Idd Average Supply Current CKREF =25MHz
PCICLK = 33MHz
D0 (100Mbps) 150 185 mA
D1 (100Mbps) 150 185
D2 (100Mbps) 150 180
D3 (100Mbps) 150 180
D0 (10Mbps) 170 20 0
D1 (10Mbps) 170 19 5
D2 (10Mbps) 170 19 5
D3 (10Mbps) 170 19 5
Vdd A verage Supply V oltage 4.75V 5.25V V
38
MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
7.0 PACKAGE INFORMATION
128-Pin Plastic Quad Flat P ac k
A
eL
A1
L1
E3 aE
38
1
64
65
102
103
128 39
IH
D3
D
ZD
b
c
d
ZE
ITEM MILLIMETERS INCHES
a 14.00±.05 5.512±.002
b .20 [T yp .] .08 [T yp .]
c 20.00±.05 7.87±.002
d 1.346 .530
e .50 [T yp .] .20 [T yp .]
L1 1.60±.1 .63±.04
L .80±.1 .31±.04
ZE .75 [T yp .] .30 [T yp .]
E3 12.50 [Typ .] 4.92 [Typ.]
E 17.20±.2 6.77±.08
ZD .75 [T yp .] .30 [T yp .]
D3 18.50 [T y p.] 7.28 [T yp .]
D 23.20±.2 9.13±.08
A1 .25±.1 min. .01±.04 min.
A 3.40±.1 max. 1.34±.04 max.
Note Short Lead Short Lead
NOTE: Each lead centerline is located within .25 mm[.01
inch] of its true position [TP] at maximum material condi-
tion.
39
MX98715AEC-D
P/N:PM0719 REV. 0.1, FEB. 05, 2001
REVISION HIST OR Y
Revision Destription Page Date
0.0 New Datasheet MA Y/12/2000
0.1 modify Pin Configurations (Pin 79,80) P.3 FEB/05/2001
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
40
MX98715AEC-D
MX98715AEC-D
C9930
TA777001
37DDX
TAIWAN
TOP SIDE MARKING
line 1 : MX98715A is MXIC parts No.
"E" : PQFP
"C" : commercial grade
"-D" : bonding option
line 2 : Assembly Date Code.
line 3 : W af er Lot No.
line 4 : "37D" : revision code,
"D" : bonding option
"X" : no used
line 5 : State
