PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com 24-BIT 192-kHz SAMPLING ENHANCED MULTI-LEVEL DELTA-SIGMA AUDIO DIGITAL-TO-ANALOG CONVERTER Check for Samples: PCM1754-Q1, PCM1753-Q1 FEATURES APPLICATIONS * * * * * * * * * * 1 2 * * * * * * Qualified for Automotive Applications 24-Bit Resolution Analog Performance (VCC = 5 V) - Dynamic Range: 106 dB - SNR: 106 dB, Typical - THD+N: 0.002%, Typical - Full-Scale Output: 4 VPP, Typical 4x/8x Oversampling Digital Filter - Stop-Band Attenuation: -50 dB - Pass-Band Ripple: 0.04 dB Sampling Frequency: 5 kHz to 200 kHz System Clock: 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS, 1152 fS with Auto Detect Hardware Control (PCM1754) - I2S and 16-Bit Word, Right-Justified - 44.1 kHz Digital De-Emphasis - Soft Mute - Zero Flag for L-, R-Channel Common Output Power Supply: 5-V Single Supply Small 16-Lead SSOP Package, Lead-Free A/V Receivers DVD Movie Players DVD Add-On Cards for High-End PCs DVD Audio Players HDTV Receivers Car Audio Systems Other Applications Requiring 24-Bit Audio DESCRIPTION The PCM175x is a CMOS, monolithic, integrated circuit, which includes stereo digital-to-analog converters and support circuitry in a small 16-lead SSOP package. The data converters use TI's enhanced multilevel delta-sigma architecture, which employs 4th-order noise shaping and 8-level amplitude quantization to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM175x accepts industry standard audio data formats with 16- to 24-bit data, providing easy interfacing to audio DSP and decoder chips. Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through a three-wire serial control port, which supports register write functions. The PCM1753 is pin-compatible with the PCM1748, PCM1742, and PCM1741, except for pin 5. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc.. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010-2011, Texas Instruments Incorporated PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PACKAGE (2) TA -40C to 105C (1) (2) SSOP - DBQ ORDERABLE PART NUMBER Reel of 2000 TOP-SIDE MARKING PCM1754TDBQRQ1 P1754Q PCM1753TDBQRQ1 P1753T For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Supply voltage: VCC -0.3 V to 6.5 V 0.1 V Ground voltage differences: AGND, DGND Input voltage -0.3 V to 6.5 V 10 mA Input current (any pins except supplies) Ambient temperature under bias -40C to 105C Storage temperature -55C to 150C Junction temperature 150C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS All specifications at TA = 25C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Resolution TYP MAX 24 UNIT Bits DATA FORMAT Audio-data interface format PCM1753 PCM1753 I2S, standard, left-justified PCM1754 I2S, standard PCM1753 16-, 18-, 20-, 24-bit, selectable PCM1754 16-24-bit (I2S), 16-bit (standard) Audio-data bit length Audio data format fS MSB first, 2s complement Sampling frequency 5 200 kHz 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS, 1152 fS System clock frequency DIGITAL INPUT/OUTPUT Logic family VIH TTL compatible Input logic level 2 VIL 0.8 IIH (1) VIN = VCC 10 IIL (1) VIN = 0 V -10 IIH (2) VIN = VCC IIL (2) VIN = 0 V (1) (2) 2 Input logic current 65 100 VDC A -10 Pins 16, 1, 2, 3: SCK, BCK, DATA, LRCK Pins 12-15: TEST, DEMP, MUTE, FMT Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless otherwise noted) PARAMETER VOH (3) TEST CONDITIONS Output logic level IOH = -1 mA VOL (3) MIN TYP MAX 2.4 IOL = 1 mA 0.4 UNIT VDC DYNAMIC PERFORMANCE (4) (5) THD+N at VOUT = 0 dB THD+N at VOUT = -60 dB fS = 44.1 kHz 0.00% fS = 96 kHz 0.00% fS = 192 kHz 0.00% fS = 44.1 kHz 0.65% fS = 96 kHz 0.80% fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Dynamic range 0.95% 100 104 A-weighted, fS = 192 kHz 102 100 A-weighted, fS = 96 kHz fS = 44.1 kHz 106 dB 102 97 fS = 96 kHz Level linearity error dB 104 A-weighted, fS = 192 kHz Channel separation 106 A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 44.1 kHz Signal-to-noise ratio 0.01% 103 101 fS = 192 kHz 100 VOUT = -90 dB 0.5 dB dB DC ACCURACY Gain error 1 Gain mismatch, channel-to-channel 1 Bipolar zero error 30 VOUT = 0.5 VCC at BPZ 6 % of FSR 3 % of FSR 60 mV ANALOG OUTPUT Output voltage Full scale (0 dB) Center voltage Load impedance AC-coupled load 80% of VCC VPP 50% of VCC VDC 5 k DIGITAL FILTER PERFORMANCE FILTER CHARACTERISTICS (SHARP ROLLOFF) 0.04 dB Pass band 0.454 fS 0.54 6 fs Stop band 0.04 Pass-band ripple Stop-band attenuation (3) (4) (5) Stop band = 0.546 fS -50 dB dB Pin 11: ZEROA Analog performance specifications are measured using the System TwoTM Cascade audio measurement system by Audio PrecisionTM in the averaging mode. Conditions in 192-kHz operation are system clock = 128 fS and oversampling rate = 64 fS of register 18. Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 Submit Documentation Feedback 3 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG FILTER PERFORMANCE Frequency response At 20 kHz -0.03 At 44 kHz -0.20 dB POWER SUPPLY REQUIREMENTS (6) VCC ICC Voltage range Supply current 5 5.5 fS = 44.1 kHz 4.5 16 21 fS = 96 kHz 25 fS = 192 kHz 30 fS = 44.1 kHz Power dissipation 80 fS = 96 kHz 125 fS = 192 kHz 150 VDC mA 105 mW TEMPERATURE RANGE Operation temperature JA (6) 4 Thermal resistance -40 16-pin SSOP 105 115 C C/W Conditions in 192-kHz operation are system clock = 128 fS and oversampling rate = 64 fS of register 18. Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com PCM1754 DBQ PACKAGE (TOP VIEW) PCM1753 DBQ PACKAGE (TOP VIEW) BCK 1 16 SCK BCK 1 16 SCK DATA 2 15 FMT DATA 2 15 ML LRCK 3 14 MUTE LRCK 3 14 MC DGND 4 13 DEMP DGND 4 13 MD NC 5 12 TEST NC 5 12 ZEROL/NA VCC 6 11 ZEROA VCC 6 11 ZEROR/ZEROA VOUTL 7 10 VCOM VOUTL 7 10 VCOM 9 AGND VOUTR 8 9 AGND VOUTR 8 FUNCTIONAL BLOCK DIAGRAM BCK FMT Serial Control Port 4x/8x Oversampling Digital Filter and Function Control VCOM Output Amp and Low-Pass Filter DAC DEMP TEST VOUTR System Clock System Clock Manager Zero Detect ZEROA SCK Enhanced Multilevel Delta-Sigma Modulator VOUTL Power Supply Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 AGND MUTE Output Amp and Low-Pass Filter DAC VCC DATA Audio Serial Port DGND LRCK Submit Documentation Feedback 5 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com TERMINAL FUNCTIONS NAME NO. I/O DESCRIPTION AGND 9 - Analog ground BCK 1 I Audio-data bit-clock input DATA 2 I Audio-data digital input DGND 4 I Digital ground LRCK 3 - L-channel and R-channel audio data latch enable input MC 14 I Mode control clock input PCM1753 (1) MD 13 I Mode control data input (1) ML 15 I Mode control latch input (1) NC 5 - No connection SCK 16 I System clock input VCC 6 I Analog power supply, 5 V VCOM 10 - Common voltage decoupling VOUTL 7 - Analog output for L-channel VOUTR 8 O Analog output for R-channe ZEROR/ZEROA 11 O Zero flag output for R-channel/Zero flag output for L-/R-channels (2) ZEROL/NA 12 O Zero flag output for L-channel/Not assigned AGND 9 - Analog ground BCK 1 I Audio-data bit-clock input DATA 2 I Audio-data digital input DEMP 13 I De-emphasis control (1) DGND 4 - Digital ground FMT 15 I Data format select (1) LRCK 3 I L-channel and R-channel audio data latch enable input MUTE 14 I Analog mixing control (1) NC 5 - No connection SCK 16 I System clock input TEST 12 I Test pin. Ground or open (1) VCC 6 - Analog power supply, 5 V VCOM 10 - Common voltage decoupling VOUTL 7 O Analog output for L-channel VOUTR 8 O Analog output for R-channel ZEROA 11 O Zero flag output for L/R channels (2) PCM1754 (1) (2) 6 Schmitt-trigger input with internal pulldown Open-drain output (PCM1755). Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com TYPICAL PERFORMANCE CURVES All specifications at TA = 25C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted) DIGITAL FILTER (DE-EMPHASIS OFF) AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0.05 0 0.04 -20 0.03 0.02 Amplitude - dB Amplitude - dB -40 -60 -80 0.01 0.00 -0.01 -0.02 -100 -0.03 -120 -0.04 -0.05 0.0 -140 0 1 2 3 4 0.1 0.2 0.3 0.4 0.5 Frequency [x fS] Frequency [x fS] Figure 1. Frequency Response, Sharp Rolloff Figure 2. Pass-Band Ripple, Sharp Rolloff AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 5 0 4 -20 3 2 Amplitude - dB Amplitude - dB -40 -60 -80 1 0 -1 -2 -100 -3 -120 -4 -140 0 1 2 3 4 -5 0.0 0.1 Figure 3. Frequency Response, Slow Rolloff 0.2 0.3 0.4 0.5 Frequency [x fS] Frequency [x fS] Figure 4. Transition Characteristics, Slow Rolloff Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 Submit Documentation Feedback 7 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted) DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 fS = 32 kHz -1 -2 0.3 De-emphasis Error - dB De-emphasis Level - dB fS = 32 kHz 0.4 -3 -4 -5 -6 -7 0.2 0.1 0.0 -0.1 -0.2 -8 -0.3 -9 -0.4 -10 -0.5 0 2 4 6 8 10 12 14 0 2 4 f - Frequency - kHz 6 8 10 f - Frequency - kHz Figure 5. DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 fS = 44.1 kHz -1 fS = 44.1 kHz 0.4 0.3 De-emphasis Error - dB -2 De-emphasis Level - dB 14 Figure 6. DE-EMPHASIS LEVEL vs FREQUENCY -3 -4 -5 -6 -7 0.2 0.1 0.0 -0.1 -0.2 -8 -0.3 -9 -0.4 -10 -0.5 0 2 4 6 8 10 12 14 16 18 20 0 2 4 f - Frequency - kHz Submit Documentation Feedback 6 8 10 12 14 16 18 20 f - Frequency - kHz Figure 7. 8 12 Figure 8. Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted) DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 fS = 48 kHz -1 0.3 De-emphasis Error - dB -2 De-emphasis Level - dB fS = 48 kHz 0.4 -3 -4 -5 -6 -7 0.2 0.1 0.0 -0.1 -0.2 -8 -0.3 -9 -0.4 -10 -0.5 0 2 4 6 8 10 12 14 16 18 20 22 0 2 4 f - Frequency - kHz Figure 9. 6 8 10 12 14 16 f - Frequency - kHz 18 20 22 Figure 10. Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 Submit Documentation Feedback 9 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted) ANALOG DYNAMIC PERFORMANCE (SUPPLY VOLTAGE CHARACTERISTICS) DYNAMIC RANGE vs SUPPLY VOLTAGE 110 10 192 kHz, 128 fS 96 kHz, 384 fS 1 108 44.1 kHz, 384 fS -60 dB Dynamic Range - dB THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE 44.1 kHz, 384 fS 0.1 96 kHz, 384 fS 192 kHz, 128 fS 0.01 0 dB 0.001 0.0001 4.0 44.1 kHz, 384 fS 4.5 5.0 5.5 106 96 kHz, 384 fS 104 192 kHz, 128 fS 102 100 98 96 4.0 6.0 VCC - Supply Voltage - V 4.5 5.0 5.5 VCC - Supply Voltage - V Figure 11. Figure 12. SIGNAL-to-NOISE RATIO vs SUPPLY VOLTAGE CHANNEL SEPARATION vs SUPPLY VOLTAGE 110 110 108 44.1 kHz, 384 fS Channel Separation - dB SNR - Signal-to-Noise Ratio - dB 108 106 96 kHz, 384 fS 104 192 kHz, 128 fS 102 100 98 96 4.0 106 104 44.1 kHz, 384 fS 102 96 kHz, 384 fS 100 192 kHz, 128 fS 98 4.5 5.0 5.5 VCC - Supply Voltage - V 6.0 96 4.0 4.5 5.0 5.5 VCC - Supply Voltage - V Figure 13. 10 6.0 Submit Documentation Feedback 6.0 Figure 14. Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted) ANALOG DYNAMIC PERFORMANCE (TEMPERATURE CHARACTERISTICS) DYNAMIC RANGE vs FREE-AIR TEMPERATURE TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE 110 192 kHz, 128 fS 96 kHz, 384 fS 108 -60 dB 1 44.1 kHz, 384 fS Dynamic Range - dB THD+N - Total Harmonic Distortion + Noise - % 10 44.1 kHz, 384 fS 0.1 192 kHz, 128 fS 96 kHz, 384 fS 0.01 0.001 0.0001 -50 0 dB 44.1 kHz, 384 fS -25 0 25 50 75 TA - Free-Air Temperature - C 106 96 kHz, 384 fS 104 102 192 kHz, 128 fS 100 98 96 -50 100 -25 0 25 50 75 TA - Free-Air Temperature - C Figure 15. Figure 16. SIGNAL-to-NOISE RATIO vs FREE-AIR TEMPERATURE CHANNEL SEPARATION vs FREE-AIR TEMPERATURE 110 110 108 108 44.1 kHz, 384 fS Channel Separation - dB SNR - Signal-to-Noise Ratio - dB 100 106 104 96 kHz, 384 fS 102 192 kHz, 128 fS 100 98 96 -50 106 104 96 kHz, 384 fS 44.1 kHz, 384 fS 102 192 kHz, 128 fS 100 98 -25 0 25 50 75 TA - Free-Air Temperature - C 100 96 -50 -25 0 25 50 75 TA - Free-Air Temperature - C Figure 17. 100 Figure 18. Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 Submit Documentation Feedback 11 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com SYSTEM CLOCK AND RESET FUNCTIONS System Clock Input The PCM175x requires a system clock for operating the digital interpolation filters and multilevel delta-sigma modulators. The system clock is applied at the SCK input (pin 16). Table 1 shows examples of system clock frequencies for common audio sampling rates. Figure 19 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase-jitter and noise. TI's PLL170x family of multiclock generators is an excellent choice for providing the PCM175x system clock. Table 1. System Clock Rates for Common Audio Sampling Frequencies SYSTEM CLOCK FREQUENCY (fSCLK) (MHz) SAMPLING FREQUENCY 128 fS 192 fS 256 fS 384 fS 512 fS 768 fS 1152 fS 8 kHz 1.024 1.536 2.048 3.072 4.096 6.144 9.216 16 kHz 2.048 3.072 4.096 6.144 8.192 12.288 18.432 32 kHz 4.096 6.144 8.192 12.288 16.384 24.576 36.864 44.1 kHz 5.6448 8.4672 11.2896 16.9344 22.5792 33.8688 (1) 48 kHz 6.144 9.216 12.288 18.432 24.576 36.864 (1) 88.2 kHz (1) 11.2896 16.9344 96 kHz 12.288 18.432 192 kHz 24.576 36.864 22.5792 24.576 33.8688 36.864 (1) 45.1584 (1) (1) 49.152 (1) (1) (1) (1) (1) (1) This system clock rate is not supported for the given sampling frequency. t(SCKH) H 2.0 V System Clock (SCK) 0.8 V L t(SCKL) t(SCY) Figure 19. System Clock Input Timing Table 2. System Clock Input Timing PARAMETER SYMBOL MIN System clock pulse duration, high t(SCKH) 7 System clock pulse duration, low t(SCKL) 7 System clock pulse cycle time t(SCY) (1) 12 TYP MAX UNIT ns ns (1) ns 1/128 fS, 1/256 fS, 1/384 fS, 1/512 fS, 1/768 fS, or 1/1152 fS Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com Power-On Reset Functions The PCM175x includes a power-on reset function. Figure 20 shows the operation of this function. With the system clock active and VCC > 3 V (typical, 2.2 V to 3.7 V), the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time VCC > 3 V (typical, 2.2 V to 3.7 V). During the reset period (1024 system clocks), the analog output is forced to the bipolar zero level, or VCC/2. After the reset period, an internal register is initialized in the next 1/fS period and if SCK, BCK, and LRCK are provided continuously, the PCM175x provides proper analog output with unit group delay against the input data. VCC 3.7 V (Max) 3.0 V (Typ) 2.2 V (Min) Reset Reset Removal Internal Reset Don't Care 1024 System Clocks System Clock Figure 20. Power-On Reset Timing AUDIO SERIAL INTERFACE The audio serial interface for the PCM175x consists of a 3-wire synchronous serial port. It includes LRCK (pin 3), BCK (pin 1), and DATA (pin 2). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the PCM175x on the rising edge of BCK. LRCK is the serial audio left/right word clock. It is used to latch serial data into the internal registers of the serial audio interface. Both LRCK and BCK should be synchronous to the system clock. Ideally, it is recommended that LRCK and BCK be derived from the system clock input, SCK. LRCK is operated at the sampling frequency, fS. BCK can be operated at 32, 48, or 64 times the sampling frequency for standard (right-justified) format, and 32 times the sampling frequency of BCK is limited to 16-bit right-justified format only. BCK can be operated at 48 or 64 times the sampling frequency for the I2S and left-justified formats. 48 times the sampling frequency of BCK is limited to 192/384/768 fS SCKI. Internal operation of the PCM175x is synchronized with LRCK. Accordingly, internal operation is held when the sampling rate clock of LRCK is changed or when SCK and/or BCK is interrupted for a 3-bit clock cycle or longer. If SCK, BCK, and LRCK are provided continuously after this held condition, the internal operation is re-synchronized automatically in a period of less than 3/fS. External resetting is not required. Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 Submit Documentation Feedback 13 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com Audio Data Formats and Timing The PCM1753 supports industry-standard audio data formats, including right-justified, I2S, and left-justified. The PCM1754 supports I2S and 16-bit-word right-justified audio data formats. The data formats are shown in Figure 22. Data formats are selected using the format bits, FMT[2:0], located in control register 20 of the PCM1753, and are selected using the FMT pin on the PCM1754. The default data format is 24-bit left-justified. All formats require binary 2s-complement MSB-first audio data. Figure 21 shows a detailed timing diagram for the serial audio interface. 1.4 V LRCK t(BCH) t(BCL) t(LB) 1.4 V BCK t(BCY) t(BL) 1.4 V DATA t(DS) t(DH) Figure 21. Audio Interface Timing Table 3. Audio Interface Timing PARAMETER SYMBOL MIN MAX UNIT BCK pulse cycle time t(BCY) 1/(32 fS), 1/(48 fS), 1/(64 fS) (1) BCK high-level time t(BCH) 35 ns BCK low-level time t(BCL) 35 ns BCK rising edge to LRCK edge t(BL) 10 ns LRCK falling edge to BCK rising edge t(LB) 10 ns DATA setup time t(DS) 10 ns DATA hold time t(DH) 10 ns (1) 14 fS is the sampling frequency (e.g., 44.1 kHz, 48 kHz, 96 kHz, etc.). Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com (1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS, or 64 fS) 16-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 141516 1 2 3 14 1516 MSB 1 LSB 2 3 14 1516 MSB LSB 16-Bit Right-Justified, BCK = 32 fS DATA 14 1516 1 2 3 14 1516 MSB 1 LSB 2 3 14 1516 MSB LSB 18-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 16 1718 1 2 3 16 1718 MSB 1 LSB 2 3 16 1718 MSB LSB 20-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 18 1920 1 2 3 18 1920 MSB 1 2 LSB 3 18 1920 MSB LSB 24-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 22 2324 1 2 3 22 2324 MSB 1 2 3 22 2324 MSB LSB LSB (2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH 1/fS LRCK L-Channel R-Channel BCK (= 48 fS or 64 fS) DATA 1 2 3 N-2 N-1 N 1 LSB MSB 2 3 N-2 N-1 MSB LSB N 12 (3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L-Channel R-Channel BCK (= 48 fS, or 64 fS) DATA 1 2 3 N-2 N-1 MSB LSB N 1 2 3 MSB N-2 N-1 N 1 2 LSB Figure 22. Audio Data Input Formats Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 Submit Documentation Feedback 15 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com ZERO FLAG (PCM1754) The PCM1754 has a ZERO flag pin, ZEROA (pin 11). ZEROA is the L-channel and R-channel common zero flag pin. If the data for L-channel and R-channel remains at a 0 level for 1024 sampling periods (or LRCK clock periods), ZEROA is set to a logic 1 state. ZERO FLAG (PCM1753) Zero-Detect Condition Zero detection for either output channel is independent from the other channel. If the data for a given channel remains at a 0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that channel. Zero Flag Outputs If a zero-detect condition exists for one or more channels, the zero flag pins for those channels are set to a logic 1 state. There are zero flag pins for each channel, ZEROL (pin 12) and ZEROR (pin 11). These pins can be used to operate external mute circuits, or used as status indicators for a microcontroller, audio signal processor, or other digitally controlled function. The active polarity of zero flag outputs can be inverted by setting the ZREV bit of control register 22 to 1. The reset default is active-high output, or ZREV = 0. The L-channel and R-channel common zero flag can be selected by setting the AZRO bit of control register 22 to 1. The reset default is independent zero flags for L-channel and R-channel, or AZRO = 0. HARDWARE CONTROL (PCM1754) The digital functions of the PCM1754 are capable of hardware control. Table 4 shows selectable formats, Table 5 shows de-emphasis control, and Table 6 shows mute control. Table 4. Data Format Select FMT (PIN 15) DATA FORMAT 2 LOW 16- to 24-bit, I S format HIGH 16-bit right-justified Table 5. De-Emphasis Control DEMP (PIN 13) DE-EMPHASIS FUNCTION LOW 44.1 kHz de-emphasis OFF HIGH 44.1 kHz de-emphasis ON Table 6. Mute Control MUTE (PIN 14) MUTE LOW Mute OFF HIGH Mute ON OVERSAMPLING RATE CONTROL(PCM1754) The PCM1754 automatically controls the oversampling rate of the delta-sigma D/A converters with the system clock rate. The oversampling rate is set to 64x oversampling with every system clock and sampling frequency. 16 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com SOFTWARE CONTROL (PCM1753/55) The PCM1753/55 has many programmable functions which can be controlled in the software control mode. The functions are controlled by programming the internal registers using ML, MC, and MD. The serial control interface is a 3-wire serial port, which operates asynchronously to the audio serial interface. The serial control interface is used to program the on-chip mode registers. The control interface includes MD (pin 13), MC (pin 14), and ML (pin 15). MD is the serial data input, used to program the mode registers. MC is the serial bit clock, used to shift data into the control port. ML is the control port latch clock. Register Write Operation All write operations for the serial control port use 16-bit data words. Figure 23 shows the control data word format. The most significant bit must be a 0. There are seven bits, labeled IDX[6:0], that set the register index (or address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0]. Figure 24 shows the functional timing diagram for writing to the serial control port. ML is held at a logic 1 state until a register needs to be written. To start the register write cycle, ML is set to logic 0. Sixteen clocks are then provided on MC, corresponding to the 16 bits of the control data word on MD. After the sixteenth clock cycle has completed, ML is set to logic 1 to latch the data into the indexed mode control register. Figure 23. Control Data Word Format for MD Figure 24. Register Write Operation Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 Submit Documentation Feedback 17 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com Control Interface Timing Requirements Figure 25 shows a detailed timing diagram for the serial control interface. These timing parameters are critical for proper control port operation. x Figure 25. Control Interface Timing 18 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com MODE CONTROL REGISTERS (PCM1753/55) User-Programmable Mode Controls The PCM1753/55 includes a number of user programmable functions, which are accessed via control registers. The registers are programmed using the serial control interface, which was previously discussed in this data sheet. Table 7 lists the available mode control functions, along with their reset default conditions and associated register index. Table 7. User-Programmable Mode Controls FUNCTION RESET DEFAULT REGISTER BIT(s) 0 dB, no attenuation 16 and 17 AT1[7:0], AT2[7:0] Mute disabled 18 MUT[2:0] 64 fS oversampling 18 OVER Reset disabled 18 SRST DAC1 and DAC2 enabled 19 DAC[2:1] De-emphasis disabled 19 DM12 Digital attenuation control, 0 dB to -63 dB in 0.5-dB steps Soft mute control Oversampling rate control (64 fS or 128 fS) Soft reset control DAC operation control De-emphasis function control De-emphasis sample rate selection 44.1 kHz 19 DMF[1:0] Audio data format control 24-bit left-justified 20 FMT[2:0] Digital filter rolloff control Sharp rolloff 20 FLT Zero flag function select L-, R-channel independent 22 AZRO Normal phase 22 DREV High 22 ZREV Output phase select Zero flag polarity select Register Map The mode control register map is shown in Table 8. Each register includes an index (or address) indicated by the IDX[6:0] bits. Table 8. Mode Control Register Map (1) IDX (B8-B 14) REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 10h Register 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 11h Register 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 12h Register 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SRST OVER RSV RSV RSV RSV MUT2 MUT1 13h Register 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV DMF1 DMF0 DM12 RSV RSV DAC2 DAC1 14h Register 20 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV FLT RSV RSV FMT2 FMT1 FMT0 16h Register 22 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV AZRO ZREV DREV (1) RSV: Reserved for test operation. It should be set to 0 for regular operation. Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 Submit Documentation Feedback 19 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com Register Definitions ATx[7:0]: Digital Attenuation Level Setting Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2). Default value: 1111 1111b Each DAC channel (VOUTL and VOUTR) includes a digital attenuation function. The attenuation level can be set from 0 dB to -63 dB in 0.5-dB steps. Changes in attenuator levels are made by incrementing or decrementing one step (0.5 dB) for every 8/fS time internal until the programmed attenuator setting is reached. Alternatively, the attenuation level can be set to infinite attenuation (or mute). The attenuation data for each channel can be set individually. The attenuation level is set using the following formula: Attenuation level (dB) = 0.5 x (ATx[7:0]DEC - 255) where ATx[7:0]DEC = 0 through 255. For ATx[7:0]DEC = 0 through 128, attenuation is set to infinite attenuation. The following table shows the attenuation levels for various settings: . . . . . . . . . . . . . . . . . . MUTx: Soft Mute Control where x = 1 or 2, corresponding to the DAC outputs VOUTL (x = 1) and VOUTR (x = 2). Default value: 0 The mute bits, MUT1 and MUT2, are used to enable or disable the soft mute function for the corresponding DAC outputs, VOUTL and VOUTR. The soft mute function is incorporated into the digital attenuators. When mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation, one attenuator step (0.5 dB) for every 8/fS seconds. This provides pop-free muting of the DAC output. 20 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com By setting MUTx = 0, the attenuator is increased one step for every 8/fS seconds to the previously programmed attenuation level. OVER: Oversampling Rate Control Default value: 0 System clock rate = 256 fS, 384 fS, 512 fS, 768 fS, or 1152 fS: System clock rate = 128 fS or 192 fS: The OVER bit is used to control the oversampling rate of the delta-sigma D/A converters. The OVER = 1 setting is recommended when the sampling rate is 192 kHz (system clock rate is 128 fS or 192 fS). SRST: Reset Default value: 0 The SRST bit is used to enable or disable the soft reset function. The operation is the same as power-on reset. All registers are initialized. DACx: DAC Operation Control Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) or VOUTR (x = 2). Default value: 0 The DAC operation controls are used to enable and disable the DAC outputs, VOUTL and VOUTR. When DACx = 0, the corresponding output generates the audio waveform dictated by the data present on the DATA pin. When DACx = 1, the corresponding output is set to the bipolar zero level, or 0.5 VCC. DM12: Digital De-Emphasis Function Control Default value: 0 The DM12 bit is used to enable or disable the digital de-emphasis function. See the plots shown in the Typical Performance Curves section of this data sheet. Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 Submit Documentation Feedback 21 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function Default value: 00 The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it is enabled. FMT[2:0]: Audio Interface Data Format Default value: 101 The FMT[2:0] bits are used to select the data format for the serial audio interface. The following table shows the available format options. FLT: Digital Filter Rolloff Control Default value: 0 The FLT bit allows the user to select the digital filter rolloff that is best suited to the application. Two filter rolloff selections are available, sharp and slow. The filter responses for these selections are shown in the Typical Performance Curves section of this data sheet. DREV: Output Phase Select Default value: 0 22 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com The DREV bit is the output analog signal phase control. ZREV: Zero Flag Polarity Select Default value: 01h The ZREV bit allows the user to select the polarity of zero flag pins. AZRO: Zero Flag Function Select Default value: 0 The AZRO bit allows the user to select the function of zero flag pins. ANALOG OUTPUTS The PCM1753 includes two independent output channels, VOUTL and VOUTR. These are unbalanced outputs, each capable of driving 4 VPP typical into a 5-k ac-coupled load. The internal output amplifiers for VOUTL and VOUTR are biased to the dc common-mode (or bipolar zero) voltage, equal to 0.5 VCC. The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy present at the DAC outputs due to the noise shaping characteristics of the PCM1754 delta-sigma D/A converters. The frequency response of this filter is shown in Figure 26. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for many applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Applications Information section of this data sheet. Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 Submit Documentation Feedback 23 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com LEVEL vs FREQUENCY 10 0 Level - dB -10 -20 -30 -40 -50 -60 0.1 1 100 10 f - Frequency - kHz 1k 10k Figure 26. Output Filter Frequency Response 24 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com VCOM Output One unbuffered common-mode voltage output pin, VCOM (pin 10) is brought out for decoupling purposes. This pin is nominally biased to a dc voltage level equal to 0.5 VCC. This pin can be used to bias external circuits. Figure 27 shows an example of using the VCOM pin for external biasing applications. AV = -1, where AV = - R2 R1 PCM1754 VCC R1 R3 2 VOUTX(1) 3 C2 10 F - 1/2 OPA2353 1 + C1 R2 + Filtered Output VCOM + (1) X 10 F = L or R (a) Using VCOM to Bias a Single-Supply Filter Stage VCC PCM1754 - OPA337 Buffered VCOM + VCOM + 10 F (b) Using a Voltage Follower to Buffer VCOM When Biasing Multiple Nodes Figure 27. Biasing External Circuits Using the VCOM Pin Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 Submit Documentation Feedback 25 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com APPLICATION INFORMATION CONNECTION DIAGRAMS A basic connection diagram is shown in Figure 28, with the necessary power supply bypassing and decoupling components. TI recommends using the component values shown in Figure 28 for all designs. The use of series resistors (22 to 100 ) is recommended for the SCK, LRCK, BCK, and DATA inputs. The series resistor combines with the stray PCB and device input capacitance to form a low-pass filter, which reduces high-frequency noise emissions and helps to dampen glitches and ringing present on clock and data lines. +5 V + DATA FMT 15 Format 3 LRCK MUTE 14 MUTE On/Off 4 DGND DEMP 13 DEMP On/Off 5 NC TEST 12 6 VCC ZEROA 11 7 VOUTL VCOM 10 8 VOUTR AGND 9 10 F 2 + 10 F System Clock BCK + 10 F 16 + PCM Audio Data PCM1754 SCK 1 Zero Mute Control 10 F Post LPF Post LPF L-Ch Out R-Ch Out Figure 28. Basic Connection Diagram POWER SUPPLIES AND GROUNDING The PCM1754 requires 5 V for VCC. Proper power supply bypassing is shown in Figure 28. The 10-F capacitors should be tantalum or aluminum electrolytic. D/A OUTPUT FILTER CIRCUITS Delta-sigma D/A converters use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR) performance at the expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2. The out-of-band noise must be low-pass filtered in order to provide the optimal converter performance. This is accomplished by a combination of on-chip and external low-pass filtering. Figure 27(a) and Figure 29 show the recommended external low-pass active filter circuits for single- and dual-supply applications. These circuits are 2nd-order Butterworth filters using the multiple feedback (MFB) circuit arrangement, which reduces sensitivity to passive component variations over frequency and temperature. For more information regarding MFB active filter design, see Burr-Brown applications bulletin (SBAA055), available from the TI Web site at http://www.ti.com. Because the overall system performance is defined by the quality of the D/A converters and their associated analog output circuitry, high-quality audio operational amplifiers are recommended for the active filters. TI's OPA2353 and OPA2134 dual operational amplifiers are shown in Figure 27(a) and Figure 29, and are recommended for use with the PCM1754. 26 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com R2 R1 C1 R3 VIN 2 R4 - 1 VOUT OPA2134 C2 AV = - 3 + R2 R1 Figure 29. Dual-Supply Filter Circuit PCB LAYOUT GUIDELINES A typical PCB floor plan for the PCM175x is shown in Figure 30. A ground plane is recommended, with the analog and digital sections being isolated from one another using a split or cut in the circuit board. The PCM175x should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections to the digital audio interface and control signals originating from the digital section of the board. Analog Power Digital Power +VD AGND +5VA DGND +VS -VS VCC Digital Logic and Audio Processor DGND PCM1754 Output Circuits Digital Ground AGND Digital Section Analog Section Analog Ground Return Path for Digital Signals Figure 30. Recommended PCB Layout Separate power supplies are recommended for the digital and analog sections of the board. This prevents the switching noise present on the digital supply from contaminating the analog power supply and degrading the dynamic performance of the PCM175x. In cases where a common 5-V supply must be used for the analog and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital 5-V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 31 shows the recommended approach for single-supply applications. Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 Submit Documentation Feedback 27 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com Power Supplies RF Choke or Ferrite Bead +5V AGND +VS -V S VCC VDD Output Circuits DGND PCM1754 AGND Digital Section Analog Section Common Ground Figure 31. Single-Supply PCB Layout THEORY OF OPERATION The delta-sigma section of the PCM175x is based on an 8-level amplitude quantizer and a 4th-order noise shaper. This section converts the oversampled input data to 8-level delta-sigma format. A block diagram of the 8-level delta-sigma modulator is shown in Figure 32. This 8-level delta-sigma modulator has the advantage of stability and clock jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the interpolation filter is 64 fS. The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown in Figure 33 and Figure 34. The enhanced multilevel delta-sigma architecture also has advantages for input clock jitter sensitivity due to the multilevel quantizer, with the simulated jitter sensitivity shown in Figure 35. KEY PERFORMANCE PARAMETERS AND MEASUREMENT This section provides information on how to measure key dynamic performance parameters for the PCM175x. In all cases, an Audio Precision System Two Cascade audio measurement system or equivalent is used to perform the testing. Total Harmonic Distortion + Noise Total harmonic distortion + noise (THD+N) is a significant figure of merit for audio D/A converters because it takes into account both harmonic distortion and all noise sources within a specified measurement bandwidth. The average value of the distortion and noise is referred to as THD+N. For the PCM175x, THD+N is measured with a full-scale, 1-kHz digital sine wave as the test stimulus at the input of the DAC (see Figure 36). The digital generator is set to 24-bit audio word length and a sampling frequency of 44.1 kHz or 96 kHz. The digital generator output is taken from the unbalanced S/PDIF connector of the measurement system. The S/PDIF data is transmitted via a coaxial cable to the digital audio receiver on the DEM-DAI1753 demonstration board. The receiver is then configured to output 24-bit data in either I2S or left-justified data format. The DAC audio interface format is programmed to match the receiver output format. The analog output is then taken from the DAC post filter and connected to the analog analyzer input of the measurement system. The analog input is band limited using filters resident in the analyzer. The resulting THD+N is measured by the analyzer and displayed by the measurement system. 28 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com + IN 8 fS + + + + Z-1 + + Z-1 + + + + + Z-1 Z-1 + 8-Level Quantizer OUT 64 fS Figure 32. Eight-Level Delta-Sigma Modulator AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 20 20 40 40 60 60 Amplitude - dB Amplitude - dB 0 80 100 120 80 100 120 140 140 160 160 180 180 0 1 2 3 4 5 6 7 8 0 1 Frequency [x fS] Figure 33. Quantization Noise Spectrum (x64 Oversampling) 2 3 4 5 6 7 8 Frequency [x fS] Figure 34. Quantization Noise Spectrum (x128 Oversampling) Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 Submit Documentation Feedback 29 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com DYNAMIC RANGE vs JITTER 125 Dynamic Range - dB 120 115 110 105 100 95 90 0 100 200 300 400 500 600 Jitter - psp-p Figure 35. Jitter Dependence (x64 Oversampling) Dynamic Range Dynamic range is specified as A-weighted THD+N measured with a -60-dB full-scale, 1-kHz digital sine wave stimulus at the input of the D/A converter. This measurement is designed to give a good indicator of how the DAC performs given a low-level input signal. The measurement setup for the dynamic range measurement is shown in Figure 37, and is similar to the THD+N test setup discussed previously. The differences include the band limit filter selection, the additional A-weighting filter, and the -60-dB full-scale input level. Evaluation Board DEM-DAI1753 S/PDIF Receiver 2nd-Order Low-Pass Filter PCM1754 f-3 dB = 54 kHz or 108 kHz Audio Precision System Two Analyzer and Display Digital Generator S/PDIF Output 0 dB FS (100% Full-Scale), 24-Bit, 1-kHz Sine Wave Averaging Mode AES17 Filter Band Limit HPF = 400 Hz LPF = 30 kHz f-3 dB = 20.9 kHz Figure 36. Test Setup for THD+N Measurement 30 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 PCM1754-Q1 PCM1753-Q1 SLES254B - APRIL 2010 - REVISED DECEMBER 2011 www.ti.com Idle Channel Signal-to-Noise Ratio (SNR) The SNR test provides a measure of the noise floor of the D/A converter. The input to the D/A is all-0s data, and the dither function of the digital generator must be disabled to ensure an all-0s data stream at the input of the D/A converter. The measurement setup for SNR is identical to that used for dynamic range, with the exception of the input signal level. (See the note provided in Figure 37). Evaluation Board DEM-DAI1753 S/PDIF Receiver PCM1754 2nd-Order Low-Pass Filter f-3 dB = 54 kHz or 108 kHz Audio Precision System Two S/PDIF Output Digital Generator 0% Full-Scale, Dither Off (SNR) or -60 dB FS, 1 kHz Sine Wave (Dynamic Range) (1) Results Analyzer and Display Averaging Mode A-Weighting Filter(1) AES17 Filter Band Limit HPF = 400 Hz LPF = 30 kHz f-3 dB = 20.9 kHz without A-Weighting are approximately 3 dB worse. Figure 37. Test Setup for Dynamic Range and SNR Measurement Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): PCM1754-Q1 PCM1753-Q1 Submit Documentation Feedback 31 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) PCM1753TDBQRQ1 ACTIVE SSOP DBQ 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR PCM1754TDBQRQ1 ACTIVE SSOP DBQ 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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OTHER QUALIFIED VERSIONS OF PCM1753-Q1, PCM1754-Q1 : * Catalog: PCM1753, PCM1754 NOTE: Qualified Version Definitions: Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 * Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCM1753TDBQRQ1 SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PCM1754TDBQRQ1 SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1753TDBQRQ1 SSOP DBQ 16 2000 367.0 367.0 35.0 PCM1754TDBQRQ1 SSOP DBQ 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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