Reprogrammable Asynchronous
CMOS Logic Device
PLDC20RA10
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-03012 Rev. ** Revised March 26, 1997
1PLDC20RA10
Features
• Advanced-user programmable macrocell
•CMOS EPROM technology for reprogrammability
•Up to 20 input terms
•10 programmable I/O macrocells
•Out put macrocell program mable as combinatorial or
asynchronous D-type registered output
•Product-term control of register clock, reset and set and
output enable
•Register preload and power-up reset
•Four data product terms per output macrocell
•Fast
—Commercial
tPD = 15 ns
tCO = 15 ns
tSU = 7 ns
—Military
tPD = 20 ns
tCO = 20 ns
tSU = 10 ns
•Low power
—ICC max - 80 mA (Commercial)
—ICC max = 85 mA (Military)
•High reliability
—Proven EPROM technology
—>2001V input protection
—100% programming and functional testing
•Windowed DIP, windowed LCC, DIP, LCC, PLCC avail-
able
Functional Description
The Cypress PLDC20RA10 is a high-performance, sec-
ond-generation programmable logic device employing a flexi-
ble macrocell structure that allows any individual output to be
configured independently as a combinatorial output or as a
fully asynchronous D-type registered output.
The Cypress PLDC20RA10 provides lower-power operation
with su per i or sp ee d p erf o rma nc e t h an f u nc t io nal l y eq ui v al en t
bipolar devices through the use of high-performance 0.8-mi-
cron CMOS manufacturing technology.
The PLDC20RA10 is packaged in a 24 pin 300-mil molded
DIP, a 300-mil windowed cerDIP, and a 28-lead square lead-
less chip carrier, providing up to 20 inputs and 10 outputs.
When the windowed device is exposed to UV light, the 20RA10
is erased and can then be reprogrammed.
Logic Block Diagram
4
987 654321
10
15 16 17 18 19 20 21 22 23 24
III IIIII
4444444
VCC
11
12
13 14
IVSS
OE
44
I
I/O9I/O8I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0
4 4 4 4 4 4 4 4 44
MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
9 8765 4 321 0
PL
RA10–1
PLDC20RA10
Document #: 38-03012 Rev. ** Page 2 of 14
Macrocell Architecture
Figure 1 illustrates the architecture of the 20RA10 macrocell.
The cell dedicates three product terms for fully asynchronous
control of the register set, reset, and clock functions, as well
as, one term for control of the output enable function.
The output enable pr oduct term output is ANDed with the input
from pin 13 to allow either product term or hardwired external
control of the output or a combination of control from both
sources . If produc t-term-on ly con trol is sel ected , it i s aut omat-
ically chosen for all outputs since, for this case, the external
output enable pin must be tied LOW. The active polarity of
each output ma y be pro gram m ed i nde pen de ntly fo r eac h o ut-
put cell and is subsequently fixed. Figure 2 illustrates the out-
put enable options available.
When an I/O cell is configured as an output, combinatorial-only
capability may be selected by forcing the set and reset pro duct
term outputs to be HIGH under all input conditions. This is
achiev ed by programming al l input term program ming cells for
these two produ ct terms. Figure 3 illu strates the a vaila ble o ut-
put configuration optio ns.
An additional four uncommitted product terms are provided in
each output macrocell as resources for creation of user-de-
fined logic functions.
Programmable I/O
Because any of the ten I/O pi ns may be select ed as an input,
the device input configuration programmed by the user may
vary from a total of nine programmable plus ten dedicated in-
puts (a total of nineteen inputs) and one output down to a
ten-input, ten-output configuration with all ten programmable
I/O cells configured as outputs. Each input pin available in a
given configuration is available as an input to the four control
product terms and four uncommitted product terms of each
programmable I/O macrocell that has been configured as an
output.
An I/ O ce ll is pro gra mm ed as an in pu t by tyi n g t h e out p ut en-
able pin (pin 13) HIGH or by programming the output enable
product term to provide a LOW, thereby disabling the output
buffer, for all possible input combinations.
When utilizing the I/O macrocell as an output, the input path
functions as a feedback path allowing the output signal to be
fed back as an input to the product term array . When the output
cell is configured as a registered output, this feedback path
may be used to feed back the current output state to the device
inputs to provide current state control of the next output state
as required for state machine implementation.
Preload and Power-Up Reset
Functional testability of programmed devices is enhanced by
inclusion of register preload capability, which allows the state
of each register to be set by loading each register from an
external s ourc e prio r to ex erc isin g th e d ev ic e. Testing of c om-
plex state machine designs is simplified by the ability to load
an arbitrary state without cycling through long test vector se-
quences to reach the desired state. Recovery from illegal
states can be verified by loading illegal states and observing
recovery. Preload of a particular register is accomplished by
impressing the desired state on the register output pin and
lowering the signal level on the preload control pin (pin1) to a
logic LOW level. If the specified prelo ad set-up, hold and pulse
width minimums have been observed, the desired state is
loaded in to the register . To insure predictable system initializa-
tion, all registers are preset to a logic LOW state upon pow-
er-up, thereby s etting th e active LOW out puts to a lo gic HIGH .
Note:
1. The CG7C324 is the PLDC20RA10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The
principal difference is in the location of the “no connect” (NC) pins
Selection Guide
Generic Part
Number tPD ns tSU ns tCO ns tCC ns
Com‘l Mil Com’lMil Com’lMil Com’lMil
20RA10-15 15 715 80
20RA10-20 20 20 10 10 20 20 80 85
20RA10-25 25 15 25 85
20RA10-35 35 20 35 85
Pin Configurations
LCC
Top View STD PLCC/HLCC JEDEC PLCC/HLCC
Top View Top View
5
6
7
8
9
10
11
4 3 2 282726
12131415161718
25
24
23
22
21
20
19
I/O
I/O
I/O
I/O
I/O
I/O
2
3
4
5
6
7
25
24
23
22
21
20
19
5
6
7
8
9
10
11 121314 1516 1718
4 3 2 2827 26
I/O
I/O
I/O
I/O
I/O
I/O
2
3
4
5
6
7
PLDC20RA10 PLDC20RA10
NC
9
I
V
I/O
I/O
8
I/O
I/O
V
I
I
SS
V
I/O
I/O
0
1
0
1
CC
CC
9
8
I/O
I/O
V
I
I
SS
11
PL
RA10–2RA10–3RA10–4
I0
1
I
I
I
I
I
I
2
3
4
5
6
7
8
9
OE
NC
NC NC 25
24
23
22
21
20
19
5
6
7
8
9
10
11 121314 1516 1718
4 3 2 2827 26
I/O
I/O
I/O
I/O
I/O
I/O
2
3
4
5
6
7
PLDC20RA10
I
I
V
I/O
I/O0
1
CC
9
8
I/O
I/O
V
SS
1
I3
I
I
4
5
NC
NC
I6
OE
I
9
8
7
NC
PL
I
I0
1
I2
I3
I
I
4
5
NC
I6
I7
I
I
9
8
NC
OE
NC
NC
I2
0
1
NC
PL
CG7C324
[1]
PLDC20RA10
Document #: 38-03012 Rev. ** Page 3 of 14
.
Figure 1. PLDC20RA10 Macrocell
PRELOAD
(FROM PIN 1) OUTPUT ENABLE
(FROM PIN 13)
C0
R
S
P
QD
PL
1SOTO I/O PIN
RA10–5
O
Figure 2. Four Possible Output Enable Alternatives for the PLDC20RA10
Programmable
OE
RA10–6RA10–7
RA10–8RA10–9
Output Always Enabled
External Pin Combination of
Programmable and Hardwired
PLDC20RA10
Document #: 38-03012 Rev. ** Page 4 of 14
Figure 3. Four Possible Macrocell Configurations for the PLDC20RA10
Registered/ActiveLOW Combinatorial/Active LOW
Registered/ActiveHIGH Combinatorial/Active HIGH
D
SQ
R
D
SQ
R
RA10–10 RA10–11
RA10–12 RA10–13
PLDC20RA10
Document #: 38-03012 Rev. ** Page 5 of 14
Maximum Ratings
(Above w hi ch the useful l ife may be im pai red. For us er g uid e-
lines, not tes ted .)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12)...........................................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State............................................... –0.5V to +7.0V
DC Input Voltage.........................................–3.0 V to + 7.0 V
Output Current into Outputs (LOW).............................16 mA
Static Discharge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
DC Program Voltage ....................................................13.0V
]
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +75°C 5V ± 10%
Military[2] –55°C to +125°C 5V ± 10%
Electrical Characteristics Ov er the Operating Ran ge[3]
Parameter Description Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min.,
VIN =VIH or VIL IOH = –3.2 mA Com’l2.4 V
IOH = –2 mA Mil
VOL Output LOW Voltage VCC = Min.,
VIN = VIH or VIL IOL = 8 mA 0.5 V
VIH Input HIGH Level Guarantee d Input Logical HIGH Voltage for All Inputs [4] 2.0 V
VIL Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs[4] 0.8 V
IIX Input Leakage Current VSS ≤ VIN ≤ VCC, VCC = Max –10 +10 µA
IOZ Output Leakage Current VCC = Max., VSS ≤ VOUT ≤ VCC –40 +40 µA
ISC Output Short Circuit Current[5] VCC = Max., VOUT = 0.5V[6] –30 –90 mA
ICC1 Standby Power Supply Current VCC= Max., VIN = GND Outputs Open Com’l75 mA
Mil 80 mA
ICC2 Power Supply Current at
Frequency[5] VCC = Max., Outputs Disabled (In High Z
State) Device Operating at fMAX Com’l80 mA
Mil 85 mA
Capacitance[5]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance VIN = 2.0 V @ f = 1 MHz 10 pF
COUT Output Capacitance VOUT = 2.0 V @ f = 1 MHz 10 pF
Notes:
2. TA is the “instant on” case temperature.
3. See the last page of thi s specifi cat io n for Gro up A subgro up testing informa ti on .
4. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
5. Tested initially and after any design or process changes that may affect these parameters.
6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5 V has been chosen to
avoid test problems caused by tester ground degradation.
PLDC20RA10
Document #: 38-03012 Rev. ** Page 6 of 14
AC Test Loads and Waveforms (Commercial)
RA10–14 RA10–15
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AN D
SCOPE
(a) (b)
<5ns <5ns
OUTPUT
R1 457Ω
(470ΩMIL)
R2
270Ω
(319ΩMil)
170Ω
Equivale nt to: THÉ VENINEQUIVALENT(Commercial)
1.86V=Vthc
R1 457Ω
(470ΩMIL)
R2
270Ω
(319ΩMil)
OUTPUT 190Ω
Equivalent to: THÉ VENIN EQUIVALENT(Military)
2.02V=Vthc
RA10–16 RA10–17
Parameter Vth Ou tput Waveform Measurement Level
tPXZ(–)1.5V VOH 0.5V VX
0.5V
tPXZ(+) 2.6V VOL VX
tPZX(+) Vthc
0.5V
tPZX(–)Vthc VOL
0.5V
VXVOH
RA10–18
RA10–19
RA10–20
RA10–21
VX
0.5V VXRA10–22
VOH
0.5V
VOL VX
0.5V
VXVOH
RA10–23
RA10–24
0.5V VOL RA10–25
VX
tER(–)
tER(+)
tEA(+)
tEA(–)
1.5V
2.6V
Vthc
Vthc
(c)
PLDC20RA10
Document #: 38-03012 Rev. ** Page 7 of 14
Switching Characteristics Over the Operating Range[3, 7, 8]
Parameter Description
Commercial Military
Unit
–15 –20 –20 –25 –35
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tPD Input or Feedback to
Non-Registered Output 15 20 20 25 35 ns
tEA Input to Output Enable 15 20 20 30 35 ns
tER Input to Output
Disable 15 20 20 30 35 ns
tPZX Pin 13 to Output
Enable 12 15 15 20 25 ns
tPXZ Pin 13 to Output
Disable 12 15 15 20 25 ns
tCO Clock to Output 15 20 20 25 35 ns
tSU Input or Feedback
Set-Up Time 710 10 15 20 ns
tHHold Time 35355ns
tPClock Period
(tSU + tCO) 22 30 30 40 55 ns
tWH Clock Wid th HIG H[5] 10 13 12 18 25 ns
tWL Clock Wid th LOW [5] 10 13 12 18 25 ns
fMAX Maximum Frequency
(1/tP)[5] 45.5 33.3 33.3 25.0 18.1 MHz
tSInput of Asynchronous
Set to Registered Output 15 20 20 25 40 ns
tRInput of Asynchronous
Reset to Registered
Output
15 20 20 25 40 ns
tARW Asynchronous Reset
Width[5] 15 20 20 25 25 ns
tASW Asynchronous S-Width[5] 15 20 20 25 25 ns
tAR Asynchronous Set/
Reset Recovery Time 10 12 12 15 20 ns
tWP Preload Pulse Width 15 15 15 15 15 ns
tSUP Preload Set-Up Time 15 15 15 15 15 ns
tHP Preload Hold Time 15 15 15 15 15 ns
Notes:
7. Part (a) of AC Test Loads was used for all parameters except tEA, tER, tPZX and tPXZ, which use part (b).
8. The parameters tER and tPXZ are measured as the delay from the input disable logic threshold transition to VOH - 0.5 V for an enabled HIGH output or VOL
+0.5V for an enabled LOW output. Please see part (c) of AC Test Loads and Waveforms for waveforms and measurement reference levels.
PLDC20RA10
Document #: 38-03012 Rev. ** Page 8 of 14
Switching Waveform
CP
RESET
ASYNCHRONOUS
ASYNCHRONOUS
OUTPUTS
(HIGHASSERTED)
SET
OUTPUT ENABLE
INPUTPIN
INPUTS,REGISTERED
FEEDBACK
tAR
tPD tCO
tWH tWL
tSU
tER tEA
tP
RA10–26
tH
Preload Switching Waveform
Asynchronous Reset
Asynchronous Set
tEA
tER
tHP
tSUP
tWP RA10–27
PIN13
OUTPUT
ENABLE
REGISTER
OUTPUTS
PIN1
PRELOAD
CLOCK
RA10–28
tR
tARW
ASYNCHRONOUS
RESET
OUTPUT
RA10–29
tS
tASW
ASYNCHRONOUS
SET
OUTPUT
PLDC20RA10
Document #: 38-03012 Rev. ** Page 9 of 14
Functional Logic Diagram
PLDC20RA10
Document #: 38-03012 Rev. ** Page 10 of 14
MILITARY SPECIFICATIONS
Group A Subgroup Testi ng
Ordering Information
ICC2 tPD
(ns) tSU
(ns) tCO
(ns) Ordering Code Package
Name Package Type Operating
Range
80 15 715 PLDC20RA10-15JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
PLDC20RA10-15PC P13 24-Lead (300-Mil) Molded DIP
CG7C324-A15JC J64 28-Lead Plastic Leaded Chip Carrier
20 10 20 PLDC20RA10-20PC P13 24-Lead (300-Mil) Molded DIP
CG7C324-A20JC J64 28-Lead Plastic Leaded Chip Carrier
85 20 10 20 PLDC20RA10-20DMB D14 24 -Le ad (300 -Mi l) CerDIP Military
PLDC20RA10-20WMB W14 24-Lead (300-Mil) Windowed CerDIP
25 15 25 PLDC20RA10-25DMB D14 24 -Le ad (300 -Mi l) CerDIP
PLDC20RA10-25WMB W14 24-Lead (300-Mil) Windowed CerDIP
35 20 35 PLDC20RA10-35DMB D14 24 -Le ad (300 -Mi l) CerDIP
PLDC20RA10-35WMB W14 24-Lead (300-Mil) Windowed CerDIP
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameter Subgroups
tPD 9, 10, 11
tPZX 9, 10, 11
tCO 9, 10, 11
tSU 9, 10, 11
tH9, 10, 11
DC Characteristics
Parameter Subgroups
PLDC20RA10
Document #: 38-03012 Rev. ** Page 11 of 14
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9Config.A 28-Lead Plastic Leaded Chip Carrier J64
28-Square LeadlessChipCarrierL64
MIL-STD-1835 C-4
28-Pin Windowed Leadless Chip Carrier Q64
MIL-STD-1835 C-4
PLDC20RA10
Document #: 38-03012 Rev. ** Page 12 of 14
Package Diagrams (continued)
28-Pin Windowed Leaded Chip Carrier H64
PLDC20RA10
Document #: 38-03012 Rev. ** Page 13 of 14
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
24-Lead (300-Mil) Molded DIP P13/P13A
24-Lead (300-Mil) Windowed CerDIP W14
MIL-STD-1835 D-9 Config.A
PLDC20RA10
Document #: 38-03012 Rev. ** Page 14 of 14
Document Title: PLDC20RA10 Reprogrammable Asynchronous CMOS Logic Device
Document Number: 38-03012
REV. ECN NO. Issue Date Orig. of Change Description of Change
** 106294 04/24/01 SZV Change from Spec number: 38-00073 to 38-03012
