PLDC20RA10
Document #: 38-03012 Rev. ** Page 2 of 14
Macrocell Architecture
Figure 1 illustrates the architecture of the 20RA10 macrocell.
The cell dedicates three product terms for fully asynchronous
control of the register set, reset, and clock functions, as well
as, one term for control of the output enable function.
The output enable pr oduct term output is ANDed with the input
from pin 13 to allow either product term or hardwired external
control of the output or a combination of control from both
sources . If produc t-term-on ly con trol is sel ected , it i s aut omat-
ically chosen for all outputs since, for this case, the external
output enable pin must be tied LOW. The active polarity of
each output ma y be pro gram m ed i nde pen de ntly fo r eac h o ut-
put cell and is subsequently fixed. Figure 2 illustrates the out-
put enable options available.
When an I/O cell is configured as an output, combinatorial-only
capability may be selected by forcing the set and reset pro duct
term outputs to be HIGH under all input conditions. This is
achiev ed by programming al l input term program ming cells for
these two produ ct terms. Figure 3 illu strates the a vaila ble o ut-
put configuration optio ns.
An additional four uncommitted product terms are provided in
each output macrocell as resources for creation of user-de-
fined logic functions.
Programmable I/O
Because any of the ten I/O pi ns may be select ed as an input,
the device input configuration programmed by the user may
vary from a total of nine programmable plus ten dedicated in-
puts (a total of nineteen inputs) and one output down to a
ten-input, ten-output configuration with all ten programmable
I/O cells configured as outputs. Each input pin available in a
given configuration is available as an input to the four control
product terms and four uncommitted product terms of each
programmable I/O macrocell that has been configured as an
output.
An I/ O ce ll is pro gra mm ed as an in pu t by tyi n g t h e out p ut en-
able pin (pin 13) HIGH or by programming the output enable
product term to provide a LOW, thereby disabling the output
buffer, for all possible input combinations.
When utilizing the I/O macrocell as an output, the input path
functions as a feedback path allowing the output signal to be
fed back as an input to the product term array . When the output
cell is configured as a registered output, this feedback path
may be used to feed back the current output state to the device
inputs to provide current state control of the next output state
as required for state machine implementation.
Preload and Power-Up Reset
Functional testability of programmed devices is enhanced by
inclusion of register preload capability, which allows the state
of each register to be set by loading each register from an
external s ourc e prio r to ex erc isin g th e d ev ic e. Testing of c om-
plex state machine designs is simplified by the ability to load
an arbitrary state without cycling through long test vector se-
quences to reach the desired state. Recovery from illegal
states can be verified by loading illegal states and observing
recovery. Preload of a particular register is accomplished by
impressing the desired state on the register output pin and
lowering the signal level on the preload control pin (pin1) to a
logic LOW level. If the specified prelo ad set-up, hold and pulse
width minimums have been observed, the desired state is
loaded in to the register . To insure predictable system initializa-
tion, all registers are preset to a logic LOW state upon pow-
er-up, thereby s etting th e active LOW out puts to a lo gic HIGH .
Note:
1. The CG7C324 is the PLDC20RA10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The
principal difference is in the location of the “no connect” (NC) pins
Selection Guide
Generic Part
Number tPD ns tSU ns tCO ns tCC ns
Com‘l Mil Com’lMil Com’lMil Com’lMil
20RA10-15 15 715 80
20RA10-20 20 20 10 10 20 20 80 85
20RA10-25 25 15 25 85
20RA10-35 35 20 35 85
Pin Configurations
LCC
Top View STD PLCC/HLCC JEDEC PLCC/HLCC
Top View Top View
5
6
7
8
9
10
11
4 3 2 282726
12131415161718
25
24
23
22
21
20
19
I/O
I/O
I/O
I/O
I/O
I/O
2
3
4
5
6
7
25
24
23
22
21
20
19
5
6
7
8
9
10
11 121314 1516 1718
4 3 2 2827 26
I/O
I/O
I/O
I/O
I/O
I/O
2
3
4
5
6
7
PLDC20RA10 PLDC20RA10
NC
9
I
V
I/O
I/O
8
I/O
I/O
V
I
I
SS
V
I/O
I/O
0
1
0
1
CC
CC
9
8
I/O
I/O
V
I
I
SS
11
PL
RA10–2RA10–3RA10–4
I0
1
I
I
I
I
I
I
2
3
4
5
6
7
8
9
OE
NC
NC NC 25
24
23
22
21
20
19
5
6
7
8
9
10
11 121314 1516 1718
4 3 2 2827 26
I/O
I/O
I/O
I/O
I/O
I/O
2
3
4
5
6
7
PLDC20RA10
I
I
V
I/O
I/O0
1
CC
9
8
I/O
I/O
V
SS
1
I3
I
I
4
5
NC
NC
I6
OE
I
9
8
7
NC
PL
I
I0
1
I2
I3
I
I
4
5
NC
I6
I7
I
I
9
8
NC
OE
NC
NC
I2
0
1
NC
PL
CG7C324
[1]