tm
74AC175, 74ACT175 Quad D-Type Flip-Flop
April 2007
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4
74AC175, 74ACT175
Quad D-Type Flip-Flop
Features
■
I
CC
reduced by 50%
■
Edge-triggered D-type inputs
■
Buffered positive edge-triggered clock
■
Asynchronous common reset
■
True and complement output
■
Outputs source/sink 24mA
■
ACT175 has TTL-compatible inputs
General Description
The AC/ACT175 is a high-speed quad D-type flip-flop.
The device is useful for general flip-flop requirements
where clock and clear inputs are common. The informa-
tion on the D-type inputs is stored during the LOW-to-
HIGH clock transition. Both true and complemented out-
puts of each flip-flop are provided. A Master Reset input
resets all flip-flops, independent of the Clock or D-type
inputs, when LOW.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram Pin Descriptions
Order
Number
Package
Number Package Description
74AC175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Body
74AC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Body
74ACT175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
D
0
–D
3
Data Inputs
CP Clock Pulse Input
MR Master Reset Input
Q
0
–Q
3
Tr ue Outputs
Q
0
–Q
3
Complement Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
74AC175, 74ACT175 Quad D-Type Flip-Flop
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4 2
Logic Symbol
IEEE/IEC
Functional Description
The AC/ACT175 consists of four edge-triggered D-type
flip-flops with individual D inputs and Q and Q outputs.
The Clock and Master Reset are common. The four flip-
flops will store the state of their individual D inputs on the
LOW-to-HIGH clock (CP) transition, causing individual Q
and Q outputs to follow. A LOW input on the Master
Reset (MR) will force all Q outputs LOW and Q outputs
HIGH independent of Clock or Data inputs. The AC/
ACT175 is useful for general logic applications where a
common Master Reset and Clock are acceptable.
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
t
n
=
Bit Time before Clock Pulse
t
n+1
=
Bit Time after Clock Pulse
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Figure 1.
Inputs @ t
n
, MR
=
H Outputs @ t
n+1
D
n
Q
n
Q
n
LLH
HHL
74AC175, 74ACT175 Quad D-Type Flip-Flop
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4 3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
V
CC
Supply Voltage –0.5V to +7.0V
I
IK
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5V
–20mA
+20mA
V
I
DC Input Voltage –0.5V to V
CC
+ 0.5V
I
OK
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
–20mA
+20mA
V
O
DC Output Voltage –0.5V to V
CC
+ 0.5V
I
O
DC Output Source or Sink Current ±50mA
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin ±50mA
T
STG
Storage Temperature –65°C to +150°C
T
J
Junction Temperature 140°C
Symbol Parameter Rating
V
CC
Supply Voltage
AC
ACT
2.0V to 6.0V
4.5V to 5.5V
V
I
Input Voltage 0V to V
CC
V
O
Output Voltage 0V to V
CC
T
A
Operating Temperature –40°C to +85°C
∆
V
/
∆
t Minimum Input Edge Rate, AC Devices:
V
IN
from 30% to 70% of V
CC
,
V
CC
@ 3.3V, 4.5V, 5.5V
125mV/ns
∆
V
/
∆
t Minimum Input Edge Rate, ACT Devices:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
125mV/ns
74AC175, 74ACT175 Quad D-Type Flip-Flop
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4 4
DC Electrical Characteristics for AC
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Symbol Parameter
V
CC
(V) Conditions
T
A
=
+25°C T
A
=
–40°C to +85°C
UnitsTyp. Guaranteed Limits
V
IH
Minimum HIGH Level
Input Voltage
3.0 V
OUT
=
0.1V
or V
CC
– 0.1V
1.5 2.1 2.1 V
4.5 2.25 3.15 3.15
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level
Input Voltage
3.0 V
OUT
=
0.1V
or V
CC
– 0.1V
1.5 0.9 0.9 V
4.5 2.25 1.35 1.35
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level
Output Voltage
3.0 I
OUT
=
–50µA 2.99 2.9 2.9 V
4.5 4.49 4.4 4.4
5.5 5.49 5.4 5.4
V
IN
=
V
IL
or V
IH
:
3.0 I
OH
=
–12mA 2.56 2.46
4.5 I
OH
=
–24mA 3.86 3.76
5.5 I
OH
=
–24mA
(1)
4.86 4.76
V
OL
Maximum LOW Level
Output Voltage
3.0 I
OUT
=
50µA 0.002 0.1 0.1 V
4.5 0.001 0.1 0.1
5.5 0.001 0.1 0.1
V
IN
=
V
IL
or V
IH
:
3.0 I
OL
=
12mA 0.36 0.44
4.5 IOL = 24mA 0.36 0.44
5.5 IOL = 24mA(1) 0.36 0.44
IIN(3) Maximum Input
Leakage Current
5.5 VI = VCC, GND ±0.1 ±1.0 µA
IOLD Minimum Dynamic
Output Current(2)
5.5 VOLD = 1.65V Max. 75 mA
IOHD 5.5 VOHD = 3.85V Min. –75 mA
ICC(3) Maximum Quiescent
Supply Current
5.5 VIN = VCC or GND 4.0 40.0 µA
74AC175, 74ACT175 Quad D-Type Flip-Flop
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4 5
DC Electrical Characteristics for ACT
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
Symbol Parameter
VCC
(V) Conditions
TA = +25°C TA = –40°C to +85°C
UnitsTyp. Guaranteed Limits
VIH Minimum HIGH Level
Input Voltage
4.5 VOUT = 0.1V or
VCC – 0.1V
1.5 2.0 2.0 V
5.5 1.5 2.0 2.0
VIL Maximum LOW Level
Input Voltage
4.5 VOUT = 0.1V or
VCC – 0.1V
1.5 0.8 0.8 V
5.5 1.5 0.8 0.8
VOH Minimum HIGH Level
Output Voltage
4.5 IOUT = –50µA 4.49 4.4 4.4 V
5.5 5.49 5.4 5.4
VIN = VIL or VIH:
4.5 IOH = –24mA 3.86 3.76
5.5 IOH = –24mA(4) 4.86 4.76
VOL Maximum LOW Level
Output Voltage
4.5 IOUT = 50µA 0.001 0.1 0.1 V
5.5 0.001 0.1 0.1
VIN = VIL or VIH:
4.5 IOL= 24mA 0.36 0.44
5.5 IOL= 24mA(4) 0.36 0.44
IIN Maximum Input
Leakage Current
5.5 VI = VCC, GND ±0.1 ±1.0 µA
ICCT Maximum ICC/Input 5.5 VI = VCC – 2.1V 0.6 1.5 mA
IOLD Minimum Dynamic
Output Current(5)
5.5 VOLD = 1.65V Max. 75 mA
IOHD 5.5 VOHD = 3.85V Min. –75 mA
ICC Maximum Quiescent
Supply Current
5.5 VIN = VCC or GND 4.0 40.0 µA
74AC175, 74ACT175 Quad D-Type Flip-Flop
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4 6
AC Electrical Characteristics for AC
Note:
6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements for AC
Note:
7. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
Symbol
Parameter VCC (V)(6)
TA = +25°C,
CL = 50pF
TA = –40°C to +85°C,
CL = 50pF
Units Min. Typ. Max. Min. Max.
fMAX Maximum Clock Frequency 3.3 149 214 139 MHz
5.0 187 244 187
tPLH Propagation Delay,
CP to Qn or Qn
3.3 2.0 9.5 12.0 2.0 13.5 ns
5.0 1.5 7.0 9.0 1.0 9.5
tPHL Propagation Delay,
CP to Qn or Qn
3.3 2.5 8.5 13.0 2.0 14.5 ns
5.0 1.5 6.0 9.5 1.5 10.5
tPLH Propagation Delay,
MR to Qn
3.3 3.0 7.5 12.5 2.5 13.5 ns
5.0 2.0 5.5 9.0 1.5 10.0
tPHL Propagation Delay,
MR to Qn
3.3 3.0 8.5 11.0 2.5 12.5 ns
5.0 2.0 6.0 8.5 1.5 9.0
Symbol
Parameter VCC (V)(7)
TA = +25°C,
CL = 50pF
TA = –40°C to +85°C,
CL = 50pF
Units Typ. Guaranteed Minimum
tSSetup Time, HIGH or LOW,
Dn to CP
3.3 2.0 4.5 4.5 ns
5.0 1.0 3.0 3.0
tHHold Time, HIGH or LOW,
Dn to CP
3.3 1.0 1.0 1.0 ns
5.0 1.0 1.0 1.0
tWCP Pulse Width,
HIGH or LOW
3.3 2.5 4.5 4.5 ns
5.0 2.0 3.5 3.5
tWMR Pulse Width, LOW 3.3 2.5 4.5 5.0 ns
5.0 2.0 3.5 3.5
tREC Recovery Time, MR to CP 3.3 –2.0 0 0 ns
5.0 –1.0 0 0
74AC175, 74ACT175 Quad D-Type Flip-Flop
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4 7
AC Electrical Characteristics for ACT
Note:
8. Voltage Range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements for ACT
Note:
9. Voltage Range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
Parameter VCC (V)(8)
TA = +25°C,
CL = 50pF
TA = –40°C to +85°C,
CL = 50pF
UnitsMin. Typ. Max. Min. Max.
fMAX Maximum Clock
Frequency
5.0 175 236 145 MHz
tPLH Propagation Delay,
CP to Qn or Qn
5.0 2.0 6.0 10.0 1.5 11.0 ns
tPHL Propagation Delay,
CP to Qn or Qn
5.0 2.0 7.0 11.0 1.5 12.0 ns
tPLH Propagation Delay,
MR to Qn
5.0 2.0 6.0 9.5 1.5 10.5 ns
tPHL Propagation Delay,
MR to Qn
5.0 2.0 5.5 9.5 1.5 10.5 ns
Symbol Parameter VCC (V)(9)
TA = +25°C, TA = –40°C to +85°C,
CL = 50pF
Units
CL = 50pF
Typ. Guaranteed Minimum
tS (H) Setup Time, Dn to CP 5.0 3.0 2.0 2.0 ns
tS (L) 3.0 2.5 2.5
tHHold Time, HIGH or LOW,
Dn to CP
5.0 0 1.0 1.0 ns
tWCP Pulse Width,HIGH or LOW 5.0 4.0 3.0 3.5 ns
tWMR Pulse Width, LOW 5.0 4.0 3.0 4.0 ns
trec Recovery Time, MR to CP 5.0 0 0 0 ns
Symbol Parameter Conditions Typ. Units
CIN Input Capacitance VCC = OPEN 4.5 pF
CPD Power Dissipation Capacitance VCC = 5.0V 45.0 pF
74AC175, 74ACT175 Quad D-Type Flip-Flop
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4 8
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 2. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
74AC175, 74ACT175 Quad D-Type Flip-Flop
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4 9
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 3. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
74AC175, 74ACT175 Quad D-Type Flip-Flop
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4 10
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 4. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
0.65
4.4±0.1
MTC16rev4
0.11
4.55
5.00
5.00±0.10
12°
7.354.45
1.45
5.90
74AC175, 74ACT175 Quad D-Type Flip-Flop
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4 11
Physical Dimensions (Continued)
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 5. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
74AC175, 74ACT175 Quad D-Type Flip-Flop
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4 12
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In Design This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary First Production This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete Not In Production This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I24
