Revision History
4M x 32bit -AS4C4M32SA - 86-pin TSOP II PACKAGE
Revision Details Date
Rev 1.0 Preliminary datasheet Sep. 2015
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Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
Overview
The 128Mb SDRAM is a high-speed CMOS
synchronous DRAM containing 134,217,728 Mbits. It
is internally configured as a quad 1M x 32 DRAM
with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CLK). Each of the 1M x 32 bit banks is organized as
4096 rows by 256 columns by 32 bits. Read and
write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
BankActivate command which is then followed by a
Read or Write command.
The SDRAM provides for programmable Read or
Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use. By having a programmable
mode register, the system can choose the most
suitable modes to maximize its performance. These
devices are well suited for applications requiring
high memory bandwidth.
Features
•Fast access time from clock: 5.4/5.4 ns
•Fast clock rate: 166/143 MHz
•Fully synchronous operation
•Internal pipelined architecture
•Four internal banks (1M x 32-bit x 4bank)
•Programmable Mode
- CAS Latency: 2 or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential & Interleaved
- Burst-Read-Single-Write
•Burst stop function
•Individua l b y te c o n tro lle d b y DQM0-3
•Auto Refresh and Self Refresh
•4096 refresh cycles/64ms
•Single 3.3V ±0.3V power supply
•Operating Temperature
- Commercial (0°C~+70°C)
- Industrial (-40°C~+85°C)
•Interface: L VTTL
•Package:
- 86-pin 400 mil plastic TSOP II package (Pb free and Halogen free)
Table 1. Ordering Information
Product part No Org Temperature Max Clock (MHz)
AS4C4M32SA-6TIN Industrial -40°C to +85°C
Package
86-pin TSOP II
AS4C4M32SA-6TCN Commercial 0°C to +70°C
AS4C4M32SA-7TCN Commercial 0°C to +70°C
86-pin TSOP II
86-pin TSOP II
143 MHz
166 MHz
166 MHz
4M x 32
4M x 32
4M x 32
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Figure 1. Pin Assignment (Top View)
1 86
VDD VSS
2 85
DQ0 DQ15
3 84
VDDQ VSSQ
4 83
DQ1 DQ14
5 82
DQ2 DQ13
6 81
VSSQ VDDQ
7 80
DQ3 DQ12
8 79
DQ4 DQ11
9 78
VDDQ VSSQ
10 77
DQ5 DQ10
11 76
DQ6 DQ9
12 75
VSSQ VDDQ
13 74
DQ7 DQ8
14 73
NC NC
15 72
VDD VSS
16 71
DQM0 DQM1
18 69
CAS# NC
19 68
RAS# CLK
20 67
CS# CKE
22 65
BA0 A8
23 64
BA1 A7
24 63
A10/AP A6
25 62
A0 A5
26 61
A1 A4
27 60
A2 A3
28 59
DQM2 DQM3
29 58
VDD VSS
17 70
WE# NC
21 66
A11 A9
31 56
DQ16 DQ31
32 55
VSSQ VDDQ
33 54
DQ17 DQ30
34 53
DQ18 DQ29
35 52
VDDQ VSSQ
36 51
DQ19 DQ28
37 50
DQ20 DQ27
38 49
VSSQ VDDQ
30 57
NC NC
39 48
DQ21 DQ26
40 47
DQ22 DQ25
41 46
VDDQ VSSQ
42 45
DQ23 DQ24
43 44
VDD VSS
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Figure 2. Block Diagram
CLK
CKE
CS#
RAS#
CAS#
WE#
CLOCK
BUFFER
COMMAND
DECODER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
ADDRESS
BUFFER
REFRESH
COUNTER
DQ Buffer
4096 x 256 x 32
CELL ARRAY
(BANK #0)
Row
Decoder
4096 x 256 x 32
CELL ARRAY
(BANK #1)
Row
Decoder
4096 x256 x 32
CELL ARRAY
(BANK #2)
Row
Decoder
4096 x 256 x 32
CELL ARRAY
(BANK #3)
Row
Decoder
Column Decoder
Column Decoder
Column Decoder
Column Decoder
MODE
REGISTER
A9
A11
BA0
BA1
~
A0
DQ31
DQ0
~
DQM0~3
A10/AP
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Pin Descriptions
Table 2. Pin Details
Symbol
Description
CLK
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on
the po s itiv e edge o f CLK. C L K also incre ments the internal bu rs t counter and
controls the output re giste rs .
CKE
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE
goes low synchronously with clock(set-up and hold time same as other inputs), the
internal clock is suspended from the next clock cycle and the state of output and
burst address is frozen as long as the CK E remains low. When all banks are in the
idle sta te, deactiva ting the clock controls the entry to the Power Down and Self
Refresh modes. CKE is synchronous except after the device enters Power Down
and Self Refresh modes, where CKE becomes asynchronous until exiting the same
mode. The input buffers, including CLK, are disabled during Power Down and Self
Refresh modes, providing low standby power.
BA0, BA1
Bank Activate: BA0 and BA1 defines to which ba n k the Ban k A c tiv a te , Read, Write,
or BankPrecharge command is being applied. The bank address BA0 and BA1 is
used latched in mode register set.
A0-A11
Address Inputs: A0-A11 are sam pled during the BankActivate comm and (row
address A0-A11) and Read /Write comman d (column a d d res s A0-A7 with A10
defining Auto Precharge) to select one location out of the 1M available in the
respective bank. During a Precharge comma n d, A10 is sample d to d ete rmine if all
banks are to be precharged (A10 = H IGH). The ad d r e s s inp u ts als o pro v id e the op-
code during a Mode Register Set or Special Mode Register Set command.
CS#
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All comm and s are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
RAS#
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH,"
either the BankActivate command or the Precharge command is selected by the
WE# signal. When the WE# is asserted "HIGH," the BankActivate command is
selected and the bank designated by BA is turned on to the active state. When the
WE# is asserted "LOW," the Precharge command is selected and the bank
designated by BA is switched to the idle state after the precharge operation.
CAS#
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CLK. W hen RAS# is held "HIGH" and CS# is asserted "LOW," the column access is
started by asserting CAS# "LOW." Then, the R ead or Write comm and is selected by
asserting WE# "LOW" or "HIGH."
WE#
Write Enable: The WE# signal defines the operation commands in conjunction w ith
the RA S# and C A S# signals and is latched at the positive edges of CL K . The WE#
input is u sed to select the BankActivate or Precharge command and Read or Write
command.
DQM0-
DQM3
Data Input/Output Mask: Data Input Mask: DQM0-DQM3 are byte specific. Input
data is m asked when DQM is sam pled HIGH during a write cycle. DQM3 masks
DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0
masks DQ7-DQ0.
DQ0-
DQ31
Data I/O: The D Q0-31 input and output data are synchronized with the positive
edges of CLK. The I/Os are byte-maskable during Reads and Writes.
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NC
No Connect: These pins should be left unconnected.
VDDQ
DQ Power: Provide isolated power to DQs for improved noise immunity.
VSSQ
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
VDD
Power Supply: 3.3V ±0.3V.
VSS
Ground
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Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 3 shows the truth table for the operation commands.
Table 3. Truth Table (Note (1), (2))
Command
State
CKEn-1
CKEn
DQM(6)
BA0,1
A10
A11, A9-0
CS#
RAS#
CAS#
WE#
BankActivate
Idle(3)
H
X
X
V
Row address
L
L
H
H
BankPrecharge
Any
H
X
X
V
L
X
L
L
H
L
PrechargeAll
Any
H
X
X
X
H
X
L
L
H
L
Write
Active(3)
H
X
V
V
L
Column
address
(A0 ~ A7)
L
H
L
L
Write and AutoPrecharge
Active(3)
H
X
V
V
H
L
H
L
L
Read
Active(3)
H
X
V
V
L
Column
address
(A0 ~ A7)
L
H
L
H
Read and Autoprecharge
Active(3)
H
X
V
V
H
L
H
L
H
Mode Register Set
Idle
H
X
X
OP code
L
L
L
L
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
Burst Stop
Active(4)
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
L
L
L
H
SelfRefresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
SelfRefresh Exit
Idle
L
H
X
X
X
X
H
X
X
X
(SelfRefresh)
L
H
H
H
Clock Suspend Mode Entry
Active
H
L
X
X
X
X
H
X
X
X
L
V
V
V
Power Down Mode Entry
Any(5)
H
L
X
X
X
X
H
X
X
X
L
H
H
H
Clock Suspend Mode Exit
Active
L
H
X
X
X
X
X
X
X
X
Power Down Mode Exit
Any
L
H
X
X
X
X
H
X
X
X
(PowerDown)
L
H
H
H
Data Write/Output Enable
Active
H
X
L
X
X
X
X
X
X
X
Data Mask/Output Disable
Active
H
X
H
X
X
X
X
X
X
X
Note: 1. V = Valid, X = Don't care, L = Logic low, H = Logic high
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. DQM0-3
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Commands
1 BankActivate
(RAS# = "L ", CA S # = "H ", WE# = "H", BA 0,1= Bank, A0-A11 = Row Address)
The BankActivate comm and activates the idle bank designated by the BA0,1 (Bank Activate)
signal. By latching the row address on A0 to A11 at the time of this command, the selected row
access is initiated. The read or write operation in the same bank can occur after a time delay of
tRCD(min.) from the tim e o f ban k activa tion . A su b se q u en t Ba n kA c tiva te co mmand to a different row
in the same bank can only be issued after the previous active row has been precharged (refer to the
following figure). The m in imum time interv a l between successiv e BankAc tiv a te comm a n d s to the
same bank is defined by tRC(min.). The S D R A M has four intern al b a n ks o n th e s a m e chip and shares
part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of
the two banks. tRRD(min.) specifies the minimum time required betw ee n activating differen t banks .
After this command is used, the Write command performs the no mask write ope r a tio n .
Figure 3. BankActivate Command Cycle (Burst Length = n)
CLK
COMMAND
T0 T1
ADDRESS
T2 T3 Tn+3 Tn+4 Tn+5 Tn+6
RAS# - CAS# delay(t
RCD
) RAS# - RAS# delay time(t
RRD
)
RAS# - Cycle time(t
RC
)
AutoPrecharge
Begin
Bank A
Row Addr. Bank A
Col Addr. Bank B
Row Addr. Bank A
Row Addr.
Bank A
Activate
NOP NOP
R/W A with
AutoPrecharge
Bank B
Activate
NOP NOP
Bank A
Activate
Don’t Care
2 BankPrecharge command
(RAS# = "L ", CA S # = "H ", WE# = "L", BA0, 1 = Bank, A10 = "L", A0-A9, A11 = Don't care)
The BankPrecharge command precharges the bank designated by BA0, 1 signal. The
precharged bank is switched from the active state to the idle state. This command can be asserted
anytime after tRAS(min.) is satisfied from th e BankA ctiva te comm a n d in th e desired bank. T he
maximum time any bank can be active is specified by tRAS(max.). Therefo re, the prech a rge function
must be performed in any active bank within tRAS(max.). At th e end of precharg e , the precha rge d
bank is still in the idle state and is ready to be activated again.
3 PrechargeAll command
(RAS# = "L ", CA S # = "H ", WE# = "L", BA0,1 = Don’t care, A10 = "H", A0-A9, A11 = Don't care)
The PrechargeAll command precharges all the four banks simultaneously and can be issued
even if all banks are not in the act iv e state. All ba n k s are then switched to th e idle state.
4 Read command
(RAS# = "H ", C A S # = "L", WE# = "H", BA0, 1 = Bank, A10 = "L", A0-A7 = Column Address)
The Read comm and is used to read a burst of data on consecutive clock cycles from an active
row in a n active ban k. The bank mus t be active for at least tRCD(min.) b efo re the Read com mand is
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS latency after the issue of the Read com mand. Each subsequent data-out
element will be valid by the next positive clock edge (refer to the following figure). The D Qs go into
high-impedance at the end of the burst unless other com m and is initiated. The burst length, burst
sequence, a nd CAS latency are determined by the m ode register which is already programmed. A
full-page burst will continue until terminated (at the end of the page it w ill wrap to column 0 and
continue).
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Figure 4. Burst Read Operation (Burst Length = 4, CAS# Latency = 2, 3)
CLK
T0 T1
COMMAND
T2 T3 T4 T5 T6 T7 T8
CAS# latency=2
tCK2, DQ
CAS# latency=3
tCK3, DQ
READ A NOP NOP NOP NOP NOP NOP
NOP
NOP
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e.
DQM latency is two clocks for output buffers). A read burst without the auto precharge function may
be interrupted by a subsequent R ead or Write com m and to the same bank or the other active bank
before the end of the burst length. It may be interrupted by a BankP recharge/ PrechargeAll
command to the same bank too. The interrupt co ming from the Read co mm and can occur on any
clock cycle following a previous Read command (refer to the following figure).
Figure 5. Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
CLK T0 T1
COMMAND
T2 T3 T4 T5 T6 T7 T8
CAS# latency=2
t
CK2,
DQ
CAS# latency=3
t
CK3,
DQ
READ A READ B NOP NOP NOP NOP NOP NOP NOP
DOUT A
0
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
DOUT A
0
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
The D QM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from
a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write
command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a
single cycle w ith high-impedance on the D Q pins must occur between the last read data and the
Write command (refer to the following figure). If the d ata output of the burst read oc cu rs at th e
second clock of the b urst write, the DQMs must be asserted (HIGH) at least one clock prior to the
Write command to avoid internal bus contention.
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Figure 6. Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 2)
CLK
COMMAND
T0 T1
DQM
T2 T3 T4 T5 T6 T7 T8
CAS# latency=2
t
CK2,
DQ
Must be Hi-Z before
the Write Command
NOP NOP BANKA
ACTIVATE NOP READ A WRITE
A
DIN A
0
DIN A
1
NOP NOP
DIN A
2
NOP
T9
DIN A
3
NOP
Figure 7. Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 2)
Don’t Care
CLK
COMMAND
T0 T1
DQM
T2 T3 T4 T5 T6 T7 T8
CAS# latency=2
tCK2, DQ
Must be Hi-Z before
the Write Command
NOPREAD ANOPNOP NOP
DIN B3
DIN B2
DIN B1
DIN B0
NOP
WRITE B
NOP NOP
Figure 8. Read to Write Interval (Burst Length
≧ 4, CAS# Latency = 3)
CLK
COMMAND
T0 T1 T2 T3 T4 T5 T6
NOP READ A NOP NOP NOP NOP WRITE B NOP
T7 T8
NOP
DQM
DOUT A
0
DIN B
0
DIN B
1
DIN B
2
CAS# Latency=3
t
CK3, DQ
Must be Hi-Z before
the Write Command Don’t Care
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS latency.
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Figure 9. Read to Precharge (CAS# Latency = 2, 3)
CLK
T0 T1
ADDRESS
T2 T3 T4 T5 T6 T7 T8
CAS# latency=2
t
CK2,
DQ
CAS# latency=3
t
CK3,
DQ
COMMAND
tRP
NOPNOP
Precharge
NOP
Bank(s)
NOPNOPREAD A
Bank,
Col A
DOUT A
0
DOUT A
1
DOUT A
3
DOUT A
2
DOUT A
2
DOUT A
1
DOUT A
0
DOUT A
3
Bank
Row
Activate NOP
Don’t Care
5 Read and AutoPrecharge command
(RAS# = "H ", C A S # = "L", WE# = "H", BA = Bank, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after the
read opera tion . On c e this co m mand is given, any su b se q ue n t co m mand cannot occ ur w ithin a tim e
delay of {tRP(min.) + burst leng th}. At full-page burst, only the read operation is performed in this
command and the auto precharge function is ignored.
6 Write command
(RAS# = "H ", C A S # = "L", WE# = "L", BA = Ban k , A1 0 = "L ", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The ban k mu st be active for at least tRCD(min.) before the W rite command is
issued. During write bursts, the fir s t valid da ta-in element will be registered coincident w ith the Write
command. Subsequent data elem ents will be registered on each successive positive clock edge
(refer to the follow in g figure). The D Q s remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is alread y programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to colu mn 0 and continue).
Figure 10. Burst Write Operation (Burst Length = 4)
CLK
DQ
T0 T1 T2 T3 T4 T5 T6
DIN A
0
DIN A
1
DIN A
2
DIN A
3
T7 T8
COMMAND NOP WRITE A NOP NOP NOP NOP NOP NOP NOP
The first data element and the write
are registered on the same clock edge
Don’t Care
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figu re ).
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Figure 11. Write Interrupted by a Write (Burst Length = 4)
CLK T0 T1
COMMAND
T2 T3 T4 T5 T6 T7 T8
DQ
NOP WRITE A WRITE B NOP NOP NOP NOP NOP NOP
DIN A0DIN B0DIN B1DIN B2DIN B3
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is regis te r e d. In ord er to avoid
data contention, input data m ust be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the d a ta inp u ts w ill be ig no re d an d w rites w ill not b e e xe cu te d.
Figure 12. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
Don’t Care
CLK T0 T1
COMMAND
T2 T3 T4 T5 T6 T7 T8
CAS# latency=2
t
CK2,
DQ
CAS# latency=3
t
CK3,
DQ
Input data must be removed from the DQ at least one clock cycle before
the Read data appears on the outputs to avoid data contention
NOP
WRITE A
READ B NOP NOP NOP NOP NOP NOP
DIN A
0
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
DOUT B
3
DOUT B
2
DOUT B
1
DOUT B
0
DIN A
0
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock e dge in which the last d ata-in element
is re g istered, where m equals tWR/tCK rounded up to the next wh o le number. In addition , the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll comm and is
entered (refer to the following figu r e ) .
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Figure 13. Write to Precharge
Don’t Care
CLK T0 T1
ADDRESS
T2 T3 T4 T5
COMMAND
tRP
DQM
DQ
tWR
WRITE
Precharge NOP NOP
Activate NOP
BANK
COL n BANK(S) ROW
DIN
NDIN
N+1
NOP NOP
T6 T7
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
7 Write and AutoPrecharge command
(RAS# = "H ", C A S # = "L", WE# = "L", BA = Ban k , A1 0 = " H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the
write operation. Once this command is given, any subsequent command can not occur within a time
delay of {(bu rs t le ng th -1) + tWR + tRP(min.)}. A t full-page burst, only the write operation is performed
in this command and the auto precharge function is ignored.
Figure 14. Burst Write with Auto-Precharge (Burst Length = 2)
CLK
DQ
T0 T1 T2 T3 T4 T5 T6
DIN A
0
DIN A
1
T7 T8
COMMAND
Bank A
Activate NOP NOP
WRITE A
Auto Precharge
NOP NOP NOP NOP NOP
T9
Bank A
Activate
t
DAL
=t
WR
+t
RP
t
DAL
Begin AutoPrecharge
Bank can be reactivated at
completion of t
DAL
8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)
The mode register stores the data for controlling the various operating modes of SDR AM. The
Mode Register S et command programs the values of CAS latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The default
values of the Mode Register after power-up are undefined; therefore this command must be issued
at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to
the mo d e register. Two clock cycles are req u ired to c o m p le te th e w rite in the mod e re g iste r (re fer to
the following figur e ). Th e con te n ts of the mo d e registe r ca n be ch a n g e d us in g the sa me command
and the clock cycle requirements during operation as long as all banks are in the idle state.
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Table 4. Mode Register Bitmap
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
W.B.L
TM
CAS Latency
BT
Burst Length
A9
Write Burst Length
A8
A7
Test Mode
A3
Burst Type
0
Burst
0
0
Normal
0
Sequential
1
Single Bit
1
0
Reserved
1
Interleave
0
1
Reserved
A6
A5
A4
CAS Latency
A2
A1
A0
Burst Length
0
0
0
Reserved
0
0
0
1
0
0
1
Reserved
0
0
1
2
0
1
0
2 clocks
0
1
0
4
0
1
1
3 clocks
0
1
1
8
1
0
0
Reserved
1
1
1
Full Page (Sequential)
All other Reserved
All other Reserved
Note: Column address is repeated until terminated in Full Page Mode
Figure 15. Mode Register Set Cycle
CLK
CS#
T0 T1 T2 T3 T4 T5 T6 T7
CKE
Don’t Care
RAS#
tMRD
CAS#
T8 T9 T10
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ tRP
PrechargeAll Mode Register
Set Command Any
Command
Hi-Z
Address Key
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•
Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Table 5. Burst Definition
Burst Length Start Address Sequential
Interleave
A2
A1
A0
2
X
X
0
0, 1
0, 1
X
X
1
1, 0
1, 0
4
X
0
0
0, 1, 2, 3
0, 1, 2, 3
X
0
1
1, 2, 3, 0
1, 0, 3, 2
X
1
0
2, 3, 0, 1
2, 3, 0, 1
X
1
1
3, 0, 1, 2
3, 2, 1, 0
8
0
0
0
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
0
0
1
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
0
1
0
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
0
1
1
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7 , 6 , 5 , 4
1
0
0
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
1
0
1
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
1
1
0
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
1
1
1
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
Full page
location = 0-255
n, n+1, n+2, n+3, …255, 0,
1, 2, … n-1, n, …
Not Support
9 No-Operation command (RAS# = "H", CAS # = "H ", WE# = "H")
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is
Low). This prevents unwanted commands from being re gistered during id le o r wait states.
10 Burst Stop command (RAS# = "H", CAS # = "H ", WE# = "L")
The B urst Stop comm and is used to terminate either fixed-length or full-page bursts. This
command is only effective in a read/write burst without the auto precharge function. The terminated
read burst e n ds after a de lay equal to th e CAS latency (refer to the following figure). The termination
of a write burst is shown in the following figure.
Figure 16. Termination of a Burst Read Operation
(Burst Len gth ＞4, CAS# Latency = 2, 3)
CLK T0 T1
COMMAND
T2 T3 T4 T5 T6 T7 T8
CAS# latency=2
t
CK2,
DQ
CAS# latency=3
t
CK3,
DQ
The burst ends after a delay equal to the CAS# latency
NOPNOP
READ A
DOUT A
0
DOUT A
0
DOUT A
1
NOP
DOUT A
1
DOUT A
2
Burst
Stop
NOP
DOUT A
3
DOUT A
2
NOP
DOUT A
3
NOP NOP
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Figure 17. Termination of a Burst Write Operation (Burst Length = X)
Don’t Care
CLK
DQ
T0 T1
COMMAND
T2 T3 T4 T5 T6 T7 T8
NOP WRITE A
DIN A
0
NOP
DIN A
1
NOP
DIN A
2
Burst
Stop
NOP NOP NOP NOP
11 Device Deselect command (CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#
and Address inputs are ignored, regardless of w hether the C LK is enabled. This command is similar
to the No Operation command.
12 AutoRefresh command
(RAS# = "L ", CA S # = "L ", WE# = "H",CKE = "H", BA0,1 = “Don‘t care, A0-A11 = Don't care)
The A utoRefresh com mand is used during normal operation of the SDR AM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is require d . The add ressing is gen e rated by the intern a l refres h
controller. This makes the address bits a "don't care" during a n AutoRefresh command . The internal
refresh co un te r increments automatica lly on every auto refresh cycle to all of the row s . The re fresh
operation must be performed 4096 times within 64ms. The time required to complete the auto
refresh operation is specified by tRC(min.). To p ro vid e the AutoRe fres h com m a n d, all banks need to
be in the idle state and the device must not be in power down mode (CKE is high in the previous
cycle). This comma nd must be followed by N OP s until the auto refresh operation is completed. The
precharge time requirement, tRP(min), mu st be me t befo re su cc es s ive auto refresh ope ra tion s are
performed.
13 SelfRefresh Entry command
(RAS# = "L ", CA S # = "L ", WE# = "H", CKE = "L ", A0-A11 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh com m and is registered, all
the inputs to the SD RAM becom e "don't care" with the exc e p tio n of CK E , wh ic h m u s t remain LOW.
The refresh addressing and timing is internally generated to reduce power consumption. The
SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by
restarting the exte rn al clo ck an d the n as se rting H IG H o n C K E (S e lfRe fre sh E xit command).
14 SelfRefresh Exit command
(CKE = "H", C S # = "H " o r C K E = "H ", R A S # = "H ", CA S # = "H ", W E # = "H ")
This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP
or Device Deselect com m ands m ust be issued for tRC(min.) be c au s e time is requ ired for the
completion of any ban k currently being internally refreshed. If auto refresh cycles in bursts are
performed during norm al operation, a burst of 4096 auto refresh cycles should be com pleted just
prior to entering and just after exiting the SelfRefresh mode.
15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended (masked) from the
subsequent cycle by issuing this command (asserting CKE "LOW "). The device operation is held
intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command
performs entry into the PowerDow n mode. All input and output buffers (except the CKE buffer) are
turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown
state longer than the refresh period (64m s) since the command does not perform any refresh
operations.
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16 Clock Suspend Mode Exit / PowerDown Mode Exit command
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from
the su b s e q u ent cycle by providing this command (asserting CKE "HIGH", th e command should be
NOP or deselect). When the dev ice is in the PowerDo w n mo de , the dev ice exits this mod e and all
disabled buffers are turned on to the active state. tXSR(min.) is require d whe n the device exits from
the P o werDown mode. Any s u b s e q u e nt commands c a n be is s u e d after o n e clock cycle fro m the end
of this command.
17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")
During a write cycle, the DQM signal functions as a D ata Mask and can con trol every word of the
input data. During a read cycle , the DQM funct io n s as th e contr o lle r of output bu ffe r s . DQM is als o
used for device selection, byte selection and bus control in a memory system.
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Table 6. Absolute Maximum Rating
Symbol
Item
Values
Unit
Note
VIN, VOUT
Input, Ou tp u t Voltage
-1.0 ~ 4.6
V
VDD, VDDQ
Power Supply Voltage
-1.0 ~ 4.6
V
TA
Ambient Temperature
Commercial
0 ~ 70
°C
Industrial
-40 ~ 85
°C
TSTG
Storage Temperature
-55 ~ 150
°C
PD
Power Dissipation
1.1
W
IOS
Short Circuit Output Current
50
mA
Note: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
Table 7. Recommended D.C. Operating Conditions (VDD = 3.3V ±0.3V, TA = -40~85°C)
Symbol
Parameter/ Condition
Min.
Typ.
Max.
Unit
Note
VDD
DRAM Core Supply Voltage
3.0
3.3
3.6
V
2
VDDQ
I/O Supp ly V o lta g e
3.0
3.3
3.6
V
2
VIH
Input Hig h Level Voltage
2
-
VDDQ+0.3
V
2
VIL
Input Low Level Voltage
-0.3
-
0.8
V
2
IIL
Input Leakage Current
( 0V≦VIN≦VDD, All other pins not under test = 0V )
-10
-
10
µA
IOZ
Output Leakage Current
(Output Disable, 0V ≦VIN≦VDDQ )
-10
-
10
µA
VOH
Output High Level Voltage ( IOUT = -2mA )
2.4
-
-
V
VOL
Output Low Level Voltage ( IOUT = 2mA )
-
-
0.4
V
Table 8. Capacitance (VDD = 3.3V, f = 1MHz, TA = 25°C)
Symbol
Parameter
Min.
Max.
Unit
CI
Input Ca p a c ita n c e
3.5
5.5
pF
CI/O
Input/Ou tp u t Capacitance
5.5
7.5
pF
Note: These parameters are periodically sampled and are not 100% tested.
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Table 9. D.C. Characteristics (VDD = 3.3V ±0.3V, TA = -40~85°C)
Description/Test condition Symbol -5-6 -7
Unit
Note
Max.
Operating Current
tRC ≥ tRC(min), O utp u ts O p e n, One bank active
IDD1
200
160
140
mA
3
Precharge Standby Current in power down mode
tCK = 15ns, CKE ≤ VIL(max)
IDD2P
3
3
3
Precharge Standby Current in power down mode
tCK = ∞, CKE ≤ VIL(max)
IDD2PS
3
3
3
Precharge Standby Current in non-power down mode
tCK = 15ns, CS# ≥ VIH(min), CKE ≥ VIH
Input sign a ls a re c h a nged every 2 c lk s
IDD2N
50
50
50
Precharge Standby Current in non-power down mode
tCK = ∞, CLK ≤ VIL(max), CKE ≥ VIH
IDD2NS
30
30
30
Active Standby Current in non-power down mode
tCK = 15ns, CKE ≥ VIH(min), CS# ≥ VIH(min)
Input sign a ls a re c h a nged every 2 c lk s
IDD3N
60
60
60
Active Standby Current in non-power down mode
CKE ≥ VIH(min ), CL K ≤ VIL(max), tCK = ∞
IDD3NS
50
50
50
Operating Current (Burst mode)
tCK =tCK(min), Outputs Open, Multi-bank interleave
IDD4
240
200
170
3, 4
Refresh Current
tRC ≥ tRC(min)
IDD5
300
260
230
3
Self Refresh Current
CKE ≤ 0.2V ; for other inputs VIH≧VDD - 0.2V, VIL ≤ 0.2V
IDD6
3
3
3
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Table 10. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V ±0.3V, TA = -40~85°C) (Note : 5~8)
Symbol
A.C. Parameter
-5 -6 -7
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
tRC
Row cycle time (same bank )
55
-
60
-
63
-
ns
tRCD
RAS# to CAS# delay (same bank)
15
-
18
-
21
-
tRP
Precharge to refresh / row activate
command (same ba n k)
15
-
18
-
21
-
tRRD
Row activate to row active delay
(different banks)
10
-
12
-
14
-
tRAS
Row activate to precharge time
(same bank)
40
100K
42
100K
42
100K
tWR
Write recovery time
2
-
2
-
2
-
tCK
tCCD
CAS# to CAS# Delay time
1
-
1
-
1
-
9
tCK
Clock cycle time
CL* = 2
-
-
10
-
10
-
ns
CL* = 3
5
-
6
-
7
-
tCH
Clock high time
2
-
2.5
-
2.5
-
10
tCL
Clock low time
2
-
2.5
-
2.5
-
10
tAC
Access time from CLK
(positive edge)
CL* = 2
-
-
-
6
-
6.5
CL* = 3
-
5
-
5.4
-
5.4
tOH
Data output hold time
2
-
2.5
-
2.5
-
ns
9
tLZ
Data output low impedance
1
-
1
-
1
-
tHZ
Data output high impedance
CL* = 3
-
5
-
5.4
-
5.4
8
tIS
Data/Address/Control Input set-up time
1.5
-
1.5
-
1.5
-
10
tIH
Data/Address/Control Input hold time
0.8
-
0.8
-
0.8
-
ns
10
tPDE
PowerDown Exit Setup Time
tIS+tCK
-
tIS+tCK
-
tIS+tCK
-
ns
tMRD
Mode Register Set Command Cycle Time
2
-
2
-
2
-
tCK
tREFI
Refresh Interval Time
-
15.6
-
15.6
-
15.6
µs
tXSR
Exit Self-Refresh to any Command
tRC+tIS
-
tRC+tIS
-
tRC+tIS
-
ns
*CL is CAS Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
2. All voltages are referenced to VSS. VIH (Max) = 4.6V for pulse width ≦3ns. VIL(Min) = -1.0V for pulse
width ≦ 3ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle ra te under the
minimum value of tCK and tRC. Input signals are c h a n g e d o ne time during e v e r y 2 tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
6. A.C. Test Conditions
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Table 11. LVTTL Interface
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels (VIH /VIL)
2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Inpu t Sig na ls
1.4V
Output
1.2KΩ
30pF
3.3V
870Ω
Output Z0=50Ω
50Ω
30pF
1.4V
Figure 18.1 LVTTL D.C. Test Load (A) Figure 18.2 LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition ( ris e and fall) of input signals are in a fixed
slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. If clock rising time is longer tha n 1 ns, (tR / 2 -0.5) ns should be added to the parameter.
10. Assumed input rise and fall time tT (tR & tF ) = 1 ns
If tR or tF is longer th an 1 ns, transient tim e compensa t io n should be considered, i.e., [( tr + tf)/2 - 1] ns
should be added to the parameter.
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ (simu ltan eo u sly ) wh e n CKE= “L”, DQM = “H” and all input
signals are held "NOP" state.
2) Start clock and maintain stable condition for minimum 200 µs, then bring CKE = “H” and, it is
recomm e n de d tha t D Q M is h e ld "H IG H " (V DD levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
device.
*The Auto Refresh command can be issue before or after Mode Register Set command
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Timing Waveforms
Figure 19. AC Parameters for Write Timing (Burst Length=4)
T0 T1 T2
Don’t Care
t
CH
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CL
Begin Auto
Precharge Bank B
RAx RBx RAy
RAx CAx RBx CBx RAy CAy
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3
t
RCD
t
RC
t
DAL
t
WR
Write with
Auto Precharge
Command
Bank A
Activate
Command
Bank B
Write with
Auto Precharge
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank A
t
IS
t
IS
t
IH
t
IH
t
IS
Begin Auto
Precharge Bank A
t
IS
t
IH
Hi-Z
CLK
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
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Figure 20. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=3)
Hi-Z
CLK
CS#
T0 T1 T2
CKE
Don’t Care
RAS#
t
CH
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
t
CL
Begin Auto
Precharge Bank B
RAx RBx
RAx CAx RBx CBx RAy
RAy
Ax0 Ax1
t
RRD
t
RC
Read
Command
Bank A
Activate
Command
Bank B
Read with
Auto Precharge
Command
Bank B
Activate
Command
Bank A
t
IS
t
IH
t
IH
t
IS
t
IS
t
IH
t
RAS
t
RCD
t
AC
t
LZ
t
HZ
Bx0 Bx1
t
HZ
t
RP
Precharge
Command
Bank A
t
OH
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Figure 21. Auto Refresh (Burst Length=4, CAS# Latency=3)
T0 T1 T2
Don’t Care
Precharge All
Command
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
RAx
CAxRAx
Ax0
t
RP
t
RC
Auto Refresh
Command Auto Refresh
Command
Activate
Command
Bank A
Read
Command
Bank A
t
RC
t
RCD
CLK
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
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Figure 22. Power on Sequence and Auto Refresh
Hi-Z
T0 T1 T2
Don’t Care
Inputs must be
Stable for
200µs
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
MRD
Mode Register
Set Command
High Level
Is reguired Minimum for 2 Refresh Cycles are required
t
RP
Precharge All
Command 1st Auto Refresh
(*)
Command 2nd Auto Refresh
(*)
Command
Any
Command
Note
(*)
: The Auto Refresh command can be issue before or after Mode Register Set command
CLK
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
Address Key
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
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Rev.1.0 Sep.2015
Figure 23. Self Refresh Entry & Exit Cycle
CLK
CS#
T0 T1 T2
CKE
Don’t Care
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
Self Refresh Entry
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
Self Refresh Exit Auto Refresh
t
IS
Hi-Z
t
IS
t
IH
*Note 1 *Note 2
*Note 3,4 t
PDE
*Note 5
*Note 6
*Note 7
t
XSR
*Note 8
Hi-Z
*Note 9
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
4. Once the device enters SelfRefresh mode, minimum tRAS is required befo r e exit from Self Refresh.
To Exit SelfRefresh Mode
5. System clock restart and be stable before returning CKE high.
6. Enable CKE and CKE should be set high for valid setup time and hold time.
7. CS# starts from high.
8. Minimum tXSR is required af te r CKE going h igh to comp le t e SelfRefresh exit.
9. 4096 cycles of burst AutoRefres h is required befo re SelfRefresh entry and after SelfRefre s h exit if the
system uses burst refresh.
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
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Rev.1.0 Sep.2015
Figure 24. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
Hi-Z
T0 T1 T2
Don’t Care
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
RAx
RAx CAx
Activate
Command
Bank A
Read
Command
Bank A
Ax0 Ax1 Ax2 Ax3
t
HZ
Clock Suspend
1 Cycle Clock Suspend
2 Cycles Clock Suspend
3 Cycles
CLK
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
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-27/47-
Rev.1.0 Sep.2015
Figure 25. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4)
Hi-Z
T0 T1 T2
Don’t Care
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
RAx
RAx CAx
Activate
Command
Bank A Write
Command
Bank A
Clock Suspend
1 Cycle Clock Suspend
2 Cycles Clock Suspend
3 Cycles
CLK
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
DAx0 DAx1 DAx2 DAx3
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
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-28/47-
Rev.1.0 Sep.2015
Figure 26. Power Down Mode and Clock Suspension (Burst Length=4, CAS# Latency=3)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
IS
Power Down
Mode Exit
t
PDE
Power Down
Mode Entry
Read
Command
Bank A
Clock Suspension
Start Power Down
Mode Exit
t
IH
RAx
RAx CAx
Ax2Ax0 Ax3
ACTIVE
STANDBY Clock Suspension
End
Precharge
Command
Bank A
Power Down
Mode Entry
PRECHARGE
STANDBY
Any
Command
Valid
t
HZ
CLK
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ Ax1
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
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-29/47-
Rev.1.0 Sep.2015
Figure 27. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Read
Command
Bank A
RAw
RAw CAx
Aw0 Aw1 Ay2
Precharge
Command
Bank A
CLK
RAz
CAw CAy RAz CAz
Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay3
Read
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
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-30/47-
Rev.1.0 Sep.2015
Figure 28. Random Column Write (Page within same Bank)
(Burst Length=4)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank B
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Write
Command
Bank B
RBw
RBw CBx
DBw0 DBw1 DBy2
Precharge
Command
Bank B
CLK
RBz
CBw CBy RBz CBz
DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy3
Write
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
DBz0 DBz1
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Confidential
-31/47-
Rev.1.0 Sep.2015
Figure 29. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank B
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Read
Command
Bank B
RBx
RBx RAx
Bx0 Bx1 Ax0
Precharge
Command
Bank B
CLK
RBy
CBx CAx RBy CBy
Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax1
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
CS#
CKE
WE#
A10
Ax6 Ax7
High
RAx
Ax2 Ax3 Ax4 Ax5
t
RCD
t
AC
t
RP
A0-A9,
A11
DQM
DQ
BA0,1
RAS#
CAS#
Precharge
Command
Bank A
By0
AS4C4M32SA-6TIN
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Rev.1.0 Sep.2015
Figure 30. Random Row Write (Interleaving Banks)
(Burst Length=8)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Write
Command
Bank A
RAx
RAx RBx
DAx3 DAx4 DBx3
Precharge
Command
Bank A
CLK
RAy
CAx CBx RAy CAy
DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx4
Activate
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank A
CS#
CKE
WE#
A10
DAy1 DAy2
High
RBx
DBx5 DBx6 DBx7 DAy0
t
RCD
t
RP
A0-A9,
A11
DQM
DQ
BA0,1
RAS#
CAS#
Precharge
Command
Bank B
DAy3
t
WR*
t
WR*
DAx0 DAx1 DAx2
*t
WR
>t
WR
(min.)
AS4C4M32SA-6TIN
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AS4C4M32SA-7TCN
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-33/47-
Rev.1.0 Sep.2015
Figure 31. Read and Write Cycle (Burst Length=4, CAS# Latency=3)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Read
Command
Bank A
RAx
RAx
DAy1
CLK
CAx CAz
Ax0 Ax1 Ax2 Ax3 DAy0
Write
Command
Bank A
The Write Data
is Masked with a
Zero Clock
Latency Read
Command
Bank A
The Read Data
is Masked with a
Two Clock
Latency
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
Az1 Az3
CAy
DAy3 Az0
AS4C4M32SA-6TIN
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Rev.1.0 Sep.2015
Figure 32. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Read
Command
Bank A
RAx
RAx RBx
Ax0 Ax1 Bz0
Precharge
Command
Bank B
CLK
RBx
CAx CBx
Ax2 Ax3 Bx0 Bx1 By0 By1 Bz1
Activate
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank A
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
CBy CBz CAy
t
RCD
t
AC
Read
Command
Bank B
Read
Command
Bank A
Ay2Ay0 Ay1 Ay3
Read
Command
Bank B
AS4C4M32SA-6TIN
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Rev.1.0 Sep.2015
Figure 33. Interleaved Column Write Cycle (Burst Length=4)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Write
Command
Bank A
RAx
RAx RBw
DAx0 DAx1 DBy0
Write
Command
Bank B
CLK
RBw
CAx CBw
DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy1
Activate
Command
Bank B
Write
Command
Bank B Precharge
Command
Bank A
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
CBx CBy CAy
t
RCD
Write
Command
Bank B
Write
Command
Bank A
DBz0DAy0 DAy1 DBz1
Write
Command
Bank B
CBz
t
RRD
>t
RRD (min)
t
WR
t
WR
DBz2 DBz3
Precharge
Command
Bank B
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Rev.1.0 Sep.2015
Figure 34. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Read
Command
Bank A
RAx
RAx RBx
Bx2
RBx
CAx CBx
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx3
Activate
Command
Bank B
Read with
Auto Precharge
Command
Bank A
Read with
Auto Precharge
Command
Bank B
CAy
Activate
Command
Bank B
Ay2Ay0 Ay1 Ay3
Read with
Auto Precharge
Command
Bank B
RBy
t
RP
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
RBy
CBy
By2By0 By1
CLK
CS#
CKE
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
High
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Rev.1.0 Sep.2015
Figure 35. Auto Precharge after Write Burst (Burst Length=4)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Write
Command
Bank A
RAx
RAx RBx
DBx2
RBx
CAx CBx
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx3
Activate
Command
Bank B
Write with
Auto Precharge
Command
Bank A
Write with
Auto Precharge
Command
Bank B
CAy
Activate
Command
Bank B
DAy2DAy0 DAy1 DAy3
Write with
Auto Precharge
Command
Bank B
RBy
t
DAL
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
RBy
CBy
DBy2DBy0 DBy1
CLK
CS#
CKE
WE#
BA0,1
A10
DQM
DQ
High
DBy3
RAS#
CAS#
A0-A9,
A11
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
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Rev.1.0 Sep.2015
Figure 36. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Read
Command
Bank A
RAx
RAx
Ax+1
RBx
CAx RBx
Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Bx
Activate
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank B
CBx
Burst Stop
Command
Bx+3Bx+1 Bx+2 Bx+4
The burst counter wraps
from the highest order
page address back to zero
during this time interval
t
RP
RBy
RBy
Bx+5
CLK
CS#
CKE
WE#
A10
DQ
High
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
Activate
Command
Bank B
RAS#
CAS#
BA0,1
A0-A9,
A11
DQM
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Rev.1.0 Sep.2015
Figure 37. Full Page Write Cycle (Burst Length=Full Page)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Write
Command
Bank A
RAx
RAx
DAx+1
RBx
CAx RBx
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DBx
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank B
CBx
Burst Stop
Command
DBx+3DBx+1 DBx+2 DBx+4
The burst counter wraps
from the highest order
page address back to zero
during this time interval
RBy
RBy
DBx+5
CLK
CS#
CKE
WE#
A10
DQ
High
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
Activate
Command
Bank B
RAS#
CAS#
BA0,1
A0-A9,
A11
DQM
Data is ignored
AS4C4M32SA-6TIN
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Rev.1.0 Sep.2015
Figure 38. Byte Read and Write Operation (Burst Length=4, CAS# Latency=3)
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Read
Command
Bank A
RAx
RAx CAx
Upper Byte
is masked Write
Command
Bank A Lower Byte
is masked
CAy
Read
Command
Bank A
Lower Byte
is masked
CAz
CLK
CS#
CKE
WE#
A10
DQ N
High
Lower Byte
is masked
RAS#
CAS#
BA0, 1
A0-A9,
A11
DQM m
DQM n
Ax0 Ax1 Ax2 DAy1 Day2 Az1 Az2
DQ M
Ax1 Ax2 Ax3 DAy0 DAy3DAy1 Az0 Az1 Az2 Az3
Upper Byte
is masked
Note : M represent DQ in the byte m; N represent DQ in the byte n.
AS4C4M32SA-6TIN
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Rev.1.0 Sep.2015
Figure 39. Random Row Read (Interleaving Banks)
(Burst Length=4, CAS# Latency= 3)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate
Command
Bank B
RAx
CAx
By1
RBx
RBx CAy
Ax0 Ax1 Bx0 Ay0 Ay1 By0 By2
Read
Command
Bank A
Read
Command
Bank B
Precharge
Command Bank B
(Precharge Temination)
Bz0By3 Bz1
Read
Command
Bank A
CBz
t
RP
RBw
RBw
Bz2
CLK
CS#
CKE
RAS#
CAS#
WE#
A10
DQM
DQ
RAx CBx CBy
t
RRD
t
RCD
Read
Command
Bank B
Read
Command
Bank B
Activate
Command
Bank B
BA0, 1
A0-A9,
A11
AS4C4M32SA-6TIN
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Rev.1.0 Sep.2015
Figure 40. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=3)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate
Command
Bank B
RAx
CAx
By1
RBx
RBx CAy
Ax0 Ax1 Bx0 Ay0 Ay1 By0 Az0
Read
Command
Bank A
Read
Command
Bank B
Precharge
Command Bank B
(Precharge Temination)
CAz
Read
Command
Bank A
Bz0Az1 Az2 Bz1
Read
Command
Bank A
CBz
t
RP
RBw
RBw
Bz2
CLK
CS#
CKE
RAS#
CAS#
WE#
A10
DQM
DQ
RAx CBx CBy
t
RRD
t
RCD
Read
Command
Bank B
Read
Command
Bank B
Activate
Command
Bank B
BA0,1
A0-A9,
A11
!
AS4C4M32SA-6TIN
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Rev.1.0 Sep.2015
Figure 41. Full Page Random Column Write (Burst Length=Full Page)
Hi-Z
T0 T1 T2
Don’t Care
Activate
Command
Bank A
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate
Command
Bank B
RAx
CAx
DBy1
RBx
RBx CAy
DAx0 DAx1 DBx0 DAy0 DAy1 DBy0 DAz0
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command Bank B
(Precharge Temination)
CAz
Write
Command
Bank A
DBz0DAz1 DAz2 DBz1
Write
Command
Bank A
CBz
t
RP
RBw
RBw
DBz2
CLK
CS#
CKE
RAS#
CAS#
WE#
A10
DQM
DQ
RAx CBx CBy
t
RRD
t
RCD
Write
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
BA0,1
A0-A9,
A11
t
WR
Write Data
are masked
!
AS4C4M32SA-6TIN
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Rev.1.0 Sep.2015
Figure 42. Precharge Termination of a Burst
(Burst Length=4, 8 or Full Page, CAS# Latency=3)
T0 T1 T2
Don’t Care
Activate
Command
Bank B
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
RAx
RAx
Ay0
CAx
DAx0 DAx1 Ay1
Write
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
RAy
Precharge
Command
Bank A
Ay2
Precharge
Command
Bank A
CAy
t
WR
RAz
CLK
CS#
CKE
WE#
A10
DQM
DQ
High
RAz
RAy
t
RP
Read
Command
Bank A
Precharge Termination
of a Read Burst
t
RP
Precharge Termination
of a Write Burst
Write Data are masked
A0-A9,
A11
RAS#
CAS#
BA0,1
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Rev.1.0 Sep.2015
Figure 43. 86 Pin TSOP II Package Outline Drawing Information
y
86
1D
E
H
E
0.254
θ°
L
L
1
A
A
1
A
2
SB
eLL
1
C
43
44
Symbol
Dimension in inch
Dimension in mm
Min
Normal
Max
Min
Normal
Max
A
－
－
0.047
－
－
1.20
A1
0.002
0.004
0.008
0.05
0.10
0.2
A2
0.035
0.039
0.043
0.9
1
1.1
B
0.007
0.009
0.011
0.17
0.22
0.27
C
－
0.005
－
－
0.127
－
D
0.87
0.875
0.88
22.09
22.22
22.35
E
0.395
0.400
0.405
10.03
10.16
10.29
e
－
0.0197
－
－
0.50
－
HE
0.455
0.463
0.471
11.56
11.76
11.96
L
0.016
0.020
0.024
0.40
0.50
0.60
L1
－
0.0315
－
－
0.80
－
S
－
0.024
－
－
0.61
－
y
－
－
0.004
－
－
0.10
θ
0
－
8
0
－
8
Notes:
1. Dimension D&E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
4. Controlling dimension: mm
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
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Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time
without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right
to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be
general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warranty to any user or customer. Alliance does not assume any responsibility or liability arising out of
the application or use of any product described herein, and disclaims any express or implied warranties related to the
sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose,
merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms
and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively
according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a
license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of
Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting
systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the
inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such
use and agrees to indemnify Alliance against all claims arising from such use.
PART NUMBERING SYSTEM
AS4C
4M32SA 6/7 T C/I N
DRAM 128Mb=4Mx32
A die version
6=166MHz T = TSOP II
C=Commercial
(0°C - +70°C)
I=Industrial
(-40°C - +85°C)
Indicates Pb and
Halogen Free
7=143MHz
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Confidential
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Rev.1.0 Sep.2015