Precision, High Speed, BiFET Quad Op Amp
AD713
Rev. F
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FEATURES
AC performance
1 μs settling to 0.01% for 10 V step
20 V/μs slew rate
0.0003% total harmonic distortion (THD)
4 MHz unity gain bandwidth
DC performance
1.5 mV maximum offset voltage
8 μV/°C typical drift
150 V/mV minimum open-loop gain
2 μV p-p typical noise, 0.1 Hz to 10 Hz
True 14-bit accuracy
Single version: AD711, dual version: AD712
Available in 16-lead SOIC, 14-lead PDIP and CERDIP
APPLICATIONS
Active filters
Quad output buffers for 12- and 14-bit DACs
Input buffers for precision ADCs
Photo diode preamplifier applications
CONNECTION DIAGRAMS
00824-001
AD713
TOP VIEW
(Not to Scale)
1
2
3
4
OUTPUT14
–IN13
+IN
12
–VS
11
5+IN10
6–IN
9
7OUTPUT
O
UTPUT
–IN
+IN
+VS
+IN
–IN
O
UTPUT 8
4
1
3
2
Figure 1. 14-Lead PDIP (N) and CERDIP (Q) Packages
00824-002
NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
O
UTPUT
1
–IN
2
+IN
3
+V
S4
OUTPUT
16
–IN
15
+IN
14
–V
S
13
+IN
5
+IN
12
–IN
6
–IN
11
O
UTPUT
7
OUTPUT
10
NC
8
NC
9
4
1
3
2
AD713
TOP VIEW
(Not to Scale)
Figure 2. 16-Lead SOIC_W (RW) Package
GENERAL DESCRIPTION
The AD713 is a quad operational amplifier, consisting of four
AD711 BiFET op amps. These precision monolithic op amps
offer excellent dc characteristics plus rapid settling times, high
slew rates, and ample bandwidths. In addition, the AD713 provides
the close matching ac and dc characteristics inherent to amplifiers
sharing the same monolithic die. The single-pole response of
the AD713 provides fast settling: l µs to 0.01%. This feature,
combined with its high dc precision, makes the AD713 suitable
for use as a buffer amplifier for 12- or 14-bit DACs and ADCs.
It is also an excellent choice for use in active filters in 12-, 14-
and 16-bit data acquisition systems. Furthermore, the AD713
low total harmonic distortion (THD) level of 0.0003% and very
close matching ac characteristics make it an ideal amplifier for
many demanding audio applications. The AD713 is internally
compensated for stable operation at unity gain. The AD713J is
rated over the commercial temperature range of 0°C to 70°C.
The AD713A is rated over the industrial temperature of −40°C
to +85°C.
The AD713 is offered in 16-lead SOIC, 14-lead PDIP, and
14-lead CERDIP packages.
PRODUCT HIGHLIGHTS
1. The AD713 is a high speed BiFET op amp that offers
excellent performance at competitive prices. It upgrades
the performance of circuits using op amps such as the
TL074, TL084, LT1058, LF347, and OPA404.
2. Slew rate is 100% tested for a guaranteed minimum of
16 V/µs (J and A grades).
3. The combination of Analog Devices, Inc., advanced
processing technology, laser wafer drift trimming, and
well-matched ion-implanted JFETs provides outstanding
dc precision. Input offset voltage, input bias current and
input offset current are specified in the warmed-up
condition and are 100% tested.
4. Very close matching of ac characteristics between the four
amplifiers makes the AD713 ideal for high quality active
filter applications.
AD713
Rev. F | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Connection Diagrams...................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Test Circuits..................................................................................... 10
Theory of Operation ...................................................................... 11
Measuring AD713 Settling Time ............................................. 11
Power Supply Bypassing............................................................ 11
A High Speed Instrumentation Amplifier Circuit................. 12
A High Speed 4-Op-Amp Cascaded Amplifier Circuit ........ 12
High Speed Op Amp Applications and Techniques.............. 12
CMOS DAC Applications ......................................................... 14
Filter Applications ...................................................................... 14
GIC and FDNR Filter Applications ......................................... 15
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 18
REVISION HISTORY
7/11—Rev. E to Rev. F
Changes to Figure 2.......................................................................... 1
6/11—Rev. D to Rev. E
Changed 8 µV/°C Maximum Drift to 8 µV/°C Typical Drift in
Features Section ................................................................................ 1
5/11—Rev. C to Rev. D
Updated Format..................................................................Universal
Changes to Features Section, General Description Section, and
Product Highlights Section ............................................................. 1
Deleted S, K, B, and T Grades Throughout................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Added Typical Performance Characteristics Summary .............. 6
Change to Figure 7 ........................................................................... 7
Changes to Figure 15, Figure 17, and Figure 18 ........................... 8
Deleted Figure 9 and Figure 10; Renumbered Sequentially ........9
Changes to Figure 23 Caption and Figure 24 Caption .............. 10
Added Test Circuits Section.......................................................... 11
Moved Figures 26, Figure 27, and Figure 28............................... 11
Changes to Figure 29...................................................................... 12
Changes to DAC Buffers (I-to-V Converters) Section.............. 13
Changes to Figure 37 and Table 5................................................. 14
Changed C1 to CL........................................................................... 14
Changes to Figure 43 and Figure 44............................................. 15
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide.......................................................... 19
10/01—Rev. B to Rev. C
Edits to Features.................................................................................1
Edits to Product Description ...........................................................1
Edits to Ordering Guide ...................................................................3
Edits to Metallization Photograph ..................................................3
AD713
Rev. F | Page 3 of 20
SPECIFICATIONS
VS = ±15 V at TA = 25°C, unless otherwise noted.
Table 1.
AD713J/AD713A
Parameter Test Conditions/Comments Min Typ Max Unit
INPUT OFFSET VOLTAGE1
Initial Offset 0.3 1.5 mV
Offset TMIN to TMAX 0.5 2 mV
vs. Temp 5 μV/°C
vs. Supply 78 95 dB
T
MIN to TMAX 76 95 dB
Long-Term Stability 15 μV/Month
INPUT BIAS CURRENT2 V
CM = 0 V 40 150 pA
V
CM = 0 V at TMAX 3.4/9.6 nA
V
CM = ±10 V 55 200 pA
INPUT OFFSET CURRENT VCM = 0 V 10 75 pA
V
CM = 0 V at TMAX 1.7/4.8 pA
MATCHING CHARACTERISTICS
Input Offset Voltage 0.5 1.8 mV
T
MIN to TMAX 0.7 2.3 mV
Input Offset Voltage Drift 8 μV/°C
Input Bias Current 10 100 pA
Crosstalk f = 1 kHz −130 dB
f = 100 kHz −95 dB
FREQUENCY RESPONSE
Small Signal Bandwidth G = −1 3.0 4.0 MHz
Full Power Response VO = 20 V p-p 200 kHz
Slew Rate G = −1 16 20 V/μs
Settling Time to 0.01% 1.0 1.2 μs
Total Harmonic Distortion f = 1 kHz; RL ≥ 2 kΩ; VO = 3 V rms 0.0003 %
INPUT IMPEDANCE
Differential3 3 × 1012||5.5 Ω||pF
Common Mode4 3 × 1012||5.5 Ω||pF
INPUT VOLTAGE RANGE
Differential ±20 V
Common-Mode Voltage +14.5/−11.5 V
T
MIN to TMAX −11 +13 V
Common Mode VCM = ±10 V 78 88 dB
Rejection Ratio TMIN to TMAX 76 84 dB
V
CM = ±11 V 72 84 dB
T
MIN to TMAX 70 80 dB
INPUT VOLTAGE NOISE 0.1 Hz to 10 Hz 2 μV p-p
f = 10 Hz 45 nV/√Hz
f = 100 Hz 22 nV/√Hz
f = 1 kHz 18 nV/√Hz
f = 10 kHz 16 nV/√Hz
INPUT CURRENT NOISE f = 1 kHz 0.01 pA/√Hz
OPEN-LOOP GAIN VO = ±10 V; RL ≥ 2 kΩ 150 400 V/mV
T
MIN to TMAX 100 V/mV
AD713
Rev. F | Page 4 of 20
AD713J/AD713A
Parameter Test Conditions/Comments Min Typ Max Unit
OUTPUT CHARACTERISTICS
Voltage RL ≥ 2 kΩ +13/−12.5 +13.9/−13.3 V
T
MIN to TMAX ±12 +13.8/−13.1 V
Current Short circuit 25 mA
POWER SUPPLY
Rated Performance ±15 V
Operating Range ±4.5 ±18 V
Quiescent Current 10.0 13.5 mA
TRANSISTOR COUNT Number of transistors 120
1 Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = 25°C.
2 Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = 25°C. For higher temperatures, the current doubles every 10°C.
3 Defined as the voltage between inputs, such that neither exceeds ±10 V from ground.
4 Typically exceeding −14.1 V negative common-mode voltage on either input results in an output phase reversal.
AD713
Rev. F | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±18 V
Input Voltage1 ±18 V
Output Short-Circuit Duration
(For One Amplifier) Indefinite
Differential Input Voltage +VS and −VS
Storage Temperature Range (Q) −65°C to +150°C
Storage Temperature Range (N, R) −65°C to +125°C
Operating Temperature Range
AD713J 0°C to 70°C
AD713A −40°C to +85°C
Lead Temperature Range (Soldering, 60 sec) 300°C
1 For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA θ
JC Unit
14-Lead PDIP (N-14) 100 30 °C/W
14-Lead CERDIP (Q-14) 110 30 °C/W
16-Lead SOIC_W (RW-16) 100 30 °C/W
ESD CAUTION
AD713
Rev. F | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±15 V at TA = 25°C, unless otherwise noted.
20
15
10
5
00 5 10 15 20
SUPPLY VOLTAGE (±V)
INPUT VOLTAGE SWING (V)
00824-003
R
L
= 2kΩ
T
A
= 25°C
Figure 3. Input Voltage Swing vs. Supply Voltage
20
15
+V
OUT
–V
OUT
10
5
00 5 10 15 20
SUPPLY VOLTAGE (±V)
OUTPUT VOLTAGE SWING (V)
00824-004
R
L
= 2kΩ
T
A
= 25°C
Figure 4. Output Voltage Swing vs. Supply Voltage
30
25
20
15
10
5
0
10 100 1k 10k
LOAD RESISTANCE (Ω)
OUTPUT VOLTAGE SWING (V p-p)
00824-005
±15V SUPPLIES
Figure 5. Output Voltage Swing vs. Load Resistance
16
12
8
4
00 5 10 15 20
SUPPLY VOLTAGE (V)
QUIESCENT CURRENT (mA)
00824-006
Figure 6. Quiescent Current vs. Supply Voltage
10
–6
10
–7
10
–8
10
–9
10
–10
10
–11
10
–12
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
INPUT BIAS CURRENT (A)
00824-007
Figure 7. Input Bias Current vs. Temperature
100
10
1
0.1
0.01
1k 10k 100k 1M 10M
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
00824-008
Figure 8. Output Impedance vs. Frequency, G = 1
AD713
Rev. F | Page 7 of 20
50
40
V
S
= ±15V
T
A
= 25°C
30
20
10
0
–10 –5 0 5 10
COMMON-MODE VOLTAGE (V)
INPUT BIAS CURRENT (pA)
00824-009
Figure 9. Input Bias Current vs. Common Mode Voltage
26
24
22
20
18
16
14
12
10
–60 0–20–40 4020 60 80 100 120 140
AMBIENT TEMPERATURE (°C)
SHORT CIRCUIT CURRENT LIMIT (mA)
00824-010
+OUTPUT CURRENT
–OUTPUT CURRENT
Figure 10. Short-Circuit Current Limit vs. Temperature
5.0
4.5
4.0
3.5
3.0
–60 0–20–40 4020 60 80 100 120 140
TEMPERATURE (°C)
UNITY GAIN BANDWIDTH (MHz)
00824-011
Figure 11. Gain Bandwidth vs. Temperature
100
80
60
40
20
0
–20
80
100
60
40
20
0
–2010 100 10k1k 100k 1M 10M
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
PHASE MARGIN (Degrees)
00824-012
GAIN
PHASE
2kΩ||100pF LOAD
Figure 12. Open-Loop Gain and Phase Margin vs. Frequency
125
120
115
110
105
100
95 0 5 10 15 20
SUPPLY VOLTAGE (V)
OPEN-LOOP GAIN (dB)
00824-013
R
L
= 2kΩ
T
A
= 25°C
Figure 13. Open-Loop Gain vs. Supply Voltage
110
100
80
60
40
20
0
10 100 1k 10k 100k 1M
SUPPLY MODULATION FREQUENCY (Hz)
POWER SUPPLY REJECTION (dB)
00824-014
VS = ±15V SUPPLIES WITH
1V p-p SINE WAVE 25°C
+SUPPLY
–SUPPLY
Figure 14. Power Supply Rejection vs. Frequency
AD713
Rev. F | Page 8 of 20
100
80
60
40
20
0
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
CMR (dB)
00824-015
VS = ±15V
VCM = 1V p-p
TA = 25°C
Figure 15. Common-Mode Rejection vs. Frequency
30
25
20
15
10
5
0
100k 10M1M
INPUT FREQUENCY (Hz)
OUTPUT VOLTAGE (V p-p)
00824-016
RL = 2kΩ
TA = 25°C
VS = ±15V
Figure 16. Large Signal Frequency Response
10
8
6
4
2
0
–2
–4
–6
–8
–10
0.5 1.00.7 0.8 0.90.6
SETTLING TIME (µs)
OUTPUT SWING FROM 0V TO FINAL ±VOLTS
00824-017
ERROR 0.1%
1% 0.1% 0.01%
1% 0.01%
Figure 17. Output Swing and Error vs. Settling Time
70
80
90
100
110
120
130
100 1k 10k 100k
FREQUENCY (Hz)
THD (dB)
00824-018
3V RMS
R
L
= 2kΩ
C
L
= 100pF
Figure 18. Total Harmonic Distortion vs. Frequency
1k
100
10
11 10 100 1k 10k 100k
FREQUENCY (Hz)
INPUT NOISE VOLTAGE (nV/ Hz)
00824-019
Figure 19. Input Noise Voltage Spectral Density
25
20
15
10
5
00300200100 500400 600 700 800 900
INPUT ERROR SIGNAL (mV)
(AT SUMMING JUNCTION)
SLEW RATE (V/µs)
00824-020
Figure 20. Slew Rate vs. Input Error Signal
AD713
Rev. F | Page 9 of 20
–
70
–80
–90 1 TO 4
1 TO 2
1 TO 3
–100
–110
–120
–130
–140
10 100 1k 10k 100k
FREQUENCY (Hz)
CROSSTALK (dB)
00824-022
1
2
3
4
14
13
12
11
510
6 9
7 8
1
2
4
3
Figure 21. Crosstalk vs. Frequency (see Figure 26 for Test Circuit)
00824-024
•••••••• •••• •••• •••• ••• • •••• •••• •••• ••••
•••••••• •••• •••• •••• ••• • •••• •••• •••• ••••
100
90
10
0%
5V 1µs
Figure 22. Unity Gain Follower Pulse Response—Large Signal (see Figure 27
for Test Circuit)
00824-026
•••••••• •••• •••• •••• •••• •••• •••• •••• ••••
•••••••• •••• •••• •••• •••• •••• •••• •••• ••••
100
90
10
0%
50mV 100ns
Figure 23. Unity Gain Follower Pulse Response—Small Signal (see Figure 27)
00824-027
•••••••• •••• •••• •••• •••• •••• •••• •••• ••••
•••••••• •••• •••• •••• •••• •••• •••• •••• ••••
100
90
10
0%
5V 1µs
Figure 24. Unity Gain Inverter Pulse Response—Small Signal (see Figure 28)
00824-028
•••••••• •••• ••• • •••• •••• ••• • •••• •••• ••••
•••••••• •••• ••• • •••• •••• ••• • •••• •••• ••••
100
90
10
0%
50mV 200ns
Figure 25. Unity Gain Inverter Pulse Response—Small Signal (see Figure 28)
AD713
Rev. F | Page 10 of 20
TEST CIRCUITS
00824-021
+1µF0.1µF
+1µF0.1µF
+V
S
COM
–V
S
1/4
AD713
9kΩ
1kΩ
OUTPUT
ALL 4 AMPLIFIERS
ARE CONNECTED
AS SHOWN.
INPUT
SIGNAL
OR
GROUND*
1kΩ
AD713
PIN 4
AD713
PIN 11
* THE SIGNAL INPUT (1kHz SINEWAVE, 2V p-p) IS APPLIED TO ONE
AMPLIFIER AT A TIME. THE OUTPUTS OF THE OTHER THREE
AMPLIFIERS ARE THEN MEASURED FOR CROSSTALK.
00824-023
+V
S
V
OUT
V
IN
–V
S
1/4
AD713
4
11
+
1µF 0.1µF
+1µF 0.1µF
S
QUARE
WAVE
INPUT
R
L
2kΩ
C
L
10pF
Figure 26. Crosstalk Test Circuit for Figure 21 Figure 27. Unity Gain Follower Circuit for Figure 22 and Figure 23
00824-025
+V
S
2kΩ
2kΩ
V
OUT
V
IN
–V
S
1/4
AD713
4
11
+
1µF 0.1µF
+1µF
7.5pF
0.1µF
SQUARE
WAVE
INPUT
R
L
2kΩ
C
L
10pF
Figure 28. Unity Gain Inverter Circuit for Figure 24 and Figure 25
AD713
Rev. F | Page 11 of 20
THEORY OF OPERATION
MEASURING AD713 SETTLING TIME The error signal is thus clamped twice: once to prevent overload-
ing amplifier A2 and then a second time to avoid overloading
the oscilloscope preamp. A Tektronix oscilloscope preamp
Type 7A26 was carefully chosen because it recovers from the
approximately 0.4 V overload quickly enough to allow accurate
measurement of the AD713 1 µs settling time. Amplifier A2 is a
very high speed FET input op amp; it provides a voltage gain of
10, amplifying the error signal output of the AD713 under test
(providing an overall gain of 5).
Figure 30 and Figure 31 show the dynamic response of the AD713
while operating in the settling time test circuit of Figure 29.
The input of the settling time fixture is driven by a flat-top pulse
generator. The error signal output from the false summing node
of A1, the AD713 under test, is clamped, amplified by Op Amp
A2, and then clamped again.
00824-029
10kΩ
200Ω
4.99kΩ
10kΩ
4.99kΩ
5pF TO 18pF
+V
S
–V
S
V
IN
+
+
10pF
0.1µF0.1µF
1µF 1µF
5kΩ
1/4
AD713
A1
4
11
+
A2
5pF
+
0.2pF TO 0.8pF
10kΩ
206Ω2 ×
HP2835
2 ×
HP2835
1.1kΩ
+V
S
–V
S
0.47µF0.47µF
V
ERROR × 5
*
FLAT-TOP
PULSE
GENERATOR
DATA
DYNAMICS
5109
OR
EQUIVALENT
*USE VERY
SHORT CABLE
OR TERMINATION
RESISTOR
NOTES
1. USE CIRCUIT BOARD
WITH GROUND PLANE.
TO TEKTRONIX 7A26
OSCILLOSCOPE
PREAMP INPUT
SECTION (VIA LESS
THAN 1FT 50Ω
COAXIAL CABLE)
20pF1MΩ
00824-031
•••••••• •••• ••• • •••• •••• ••• • •••• •••• ••••
•••••••• •••• ••• • •••• •••• ••• • •••• •••• ••••
100
90
10
0%
5mV
5V
500ns
Figure 31. Settling Characteristics to –10 V Step,
Upper Trace: Output of AD713 Under Test (5 V/div),
Lower Trace: Amplified Error Voltage (0.01%/div)
POWER SUPPLY BYPASSING
The power supply connections to the AD713 must maintain a
low impedance to ground over a bandwidth of 4 MHz or more.
This is especially important when driving a significant resistive
or capacitive load because all current delivered to the load
comes from the power supplies. Multiple high quality bypass
capacitors are recommended for each power supply line in any
critical application. As shown in Figure 32, a 0.1 µF ceramic and
a 1 µF electrolytic capacitor placed as close as possible to the
amplifier (with short lead lengths to power supply common)
assures adequate high frequency bypassing in most applications.
A minimum bypass capacitance of 0.1 µF should be used for
any application.
Figure 29. Settling Time Test Circuit
00824-030
•••••••• •••• ••• • •••• •••• ••• • •••• •••• ••••
•••••••• •••• ••• • •••• •••• ••• • •••• •••• ••••
100
90
10
0%
5mV
5V
500ns
00824-032
+
V
S
–VS
1/4
AD713
4
11
+1µF 0.1µF
+1µF 0.1µF
Figure 32. Recommended Power Supply Bypassing
Figure 30. Settling Characteristics 0 V to 10 V Step,
Upper Trace: Output of AD713 Under Test (5 V/div),
Lower Trace: Amplified Error Voltage (0.01%/div)
AD713
Rev. F | Page 12 of 20
A HIGH SPEED INSTRUMENTATION AMPLIFIER
CIRCUIT
The instrumentation amplifier circuit shown in Figure 33 can
provide a range of gains from unity up to 1000 and higher using
only a single AD713. The circuit bandwidth is 1.2 MHz at a gain
of 1 and 250 kHz at a gain of 10; settling time for the entire
circuit is less than 5 µs to within 0.01% for a 10 V step, (G = 10).
Other uses for Amplifier A4 include an active data guard and an
active sense input.
10kΩ
+IN
–IN
SENSE
TO BUFFERED
VOLTAGE
REFERENCE
OR REMOTE
GROUND SENSE
10kΩ**
10kΩ**
10kΩ**
RG
7.5pF
*1.5pF TO 20pF
(TRIM FOR BEST SETTLING TIME)
5pF
A1
1
3
2
A3
8
9
10
A4
14
13
12
A2
7
6
5
7.5pF
10kΩ10kΩ**
1/4
AD713
1/4
AD713
1/4
AD713
1/4
AD713
CIRCUIT GAIN = + 1
20,000
RG
VOLTRONICS SP20 TRIMMER CAPACITOR
OR EQUIVALENT
RATIO MATCHED 1% METAL FILM
RESISTORS
*
**
+1µF0.1µF
+1µF0.1µF
+VS
COM
–VS
AD713
PIN 4
AD713
PIN 11
00824-033
Figure 33. High Speed Instrumentation Amplifier Circuit
Table 4 provides a performance summary for this circuit. Figure 34
shows the pulse response of this circuit for a gain of 10.
Table 4. Performance Summary for the High Speed
Instrumentation Amplifier Circuit
Gain RG Bandwidth Settling Time (0.01%)
1 NC1 1.2 MHz 2 μs
2 20 kΩ 1.0 MHz 2 μs
10 4.04 kΩ 0.25 MHz 2 μs
1 NC = no connect.
00824-034
•••••••• •••• ••• • •••• •••• ••• • •••• •••• ••••
•••••••• •••• ••• • •••• •••• ••• • •••• •••• ••••
100
90
10
0%
5V
2µs
Figure 34. Pulse Response of High Speed Instrumentation Amplifier,
Gain = 10
A HIGH SPEED 4-OP-AMP CASCADED AMPLIFIER
CIRCUIT
Figure 35 shows how the four amplifiers of the AD713 can be
connected in cascade to form a high gain, high bandwidth
amplifier. This gain of 100 amplifier has a −3 dB bandwidth
greater than 600 kHz.
1/4
AD713
–VS
+VS
2.15kΩ
INPUT
+
1µF 0.1µF
1µF 0.1µF
OUTPUT
4-OP-AMP CASCADED AMPLIFIER
GAIN = 100
BANDWIDTH (–3dB) = 632kHz
1/4
AD713
1kΩ
1kΩ
1kΩ
1kΩ
1/4
AD713
2.15kΩ
1/4
AD713
2.15kΩ
2.15kΩ
OPTIONAL VOS
ADJUSTMENT
+VS
–VS
22MΩ
100kΩ
00824-035
34
1
2
12
11
14
13
5
7
6
10
8
9
Figure 35. High Speed 4-Op-Amp Cascaded Amplifier Circuit
00824-036
+V
S
10kΩ
100kΩ
1kΩ
LOW DISTORTION
SINEWAVE INPUT
ERROR SIGNAL
OUTPUT
(ERROR/11)
1kΩ
NULL
ADJUST 10kΩ
–V
S
1/4
AD713
4
11
+
1µF 0.1µF
+1µF
100pF
0.1µF
TO SPECTRUM ANALYZER
Figure 36. THD Test Circuit
HIGH SPEED OP AMP APPLICATIONS AND
TECHNIQUES
DAC Buffers (I-to-V Converters)
The wide input dynamic range of JFET amplifiers makes them
ideal for use in both waveform reconstruction and digital audio
DAC applications. The AD713, in conjunction with a 16-bit
DAC, can achieve 0.0016% THD without requiring the use of a
deglitcher in digital audio applications.
Driving the Analog Input of an Analog-to-Digital
Converter
An op amp driving the analog input of an analog-to-digital
converter (ADC), such as that shown in Figure 37, must be
capable of maintaining a constant output voltage under dynami-
cally changing load conditions. In successive approximation
converters, the input current is compared to a series of switched
trial currents. The comparison point is diode clamped but may
vary by several hundred millivolts, resulting in high frequency
modulation of the analog-to-digital input current. The output
impedance of a feedback amplifier is made artificially low by its
AD713
Rev. F | Page 13 of 20
loop gain. At high frequencies, where the loop gain is low, the
amplifier output impedance can approach its open-loop value.
STS
1
(MSB) DB11
HIGH
BITS
MIDDLE
BITS
LOW
BITS
(LSB) DB0
2
DB10
3
DB9
4
28
27
A
O
26
25
DB8
5
DB7
6
DB6
7
CE
24
REF OUT
23
AC
22
DB5
8
REF IN
21
DB4
9
V
EE
20
DB3
10
BIP OFF
19
DB2
11
10V
IN
18
DB1
12
V
LOGIC
17
13
V
CC
16
DC
14
20V
IN 15
AD574A
TOP VIEW
(Not to Scale)
12/8
CS
R/C
GAIN ADJUST
±10V
ANALOG
INPUT
R2 100Ω
R1 100Ω
OFFSET ADJUST
ANALOG COM
00824-039
1/4
AD713
+15V
0.1µF
4
–15V
0.1µF
11
Figure 37. AD713 as an ADC Buffer
Most IC amplifiers exhibit a minimum open-loop output imped-
ance of 25 Ω, due to current limiting resistors. A few hundred
microamps reflected from the change in converter loading can
introduce errors in instantaneous input voltage. If the analog-
to-digital conversion speed is not excessive and the bandwidth
of the amplifier is sufficient, the amplifier output returns to
the nominal value before the converter makes its comparison.
However, many amplifiers have relatively narrow bandwidths,
yielding slow recovery from output transients. The AD713 is
ideally suited as a driver for ADCs because it offers both a wide
bandwidth and a high open-loop gain.
00824-040
•••••••• •••• •••• •••• •••• •••• •••• •••• ••••
•••••••• •••• •••• •••• •••• •••• •••• •••• ••••
100
90
10
0%
1mV AD713 BUFF
200ns
500mV 10V ADC IN
Figure 38. Buffer Recovery Time Source Current = 2 mA
00824-041
•••••••• •••• ••• • •••• •••• ••• • •••• •••• ••••
•••••••• •••• ••• • •••• •••• ••• • •••• •••• ••••
100
90
10
0%
1mV AD713 BUFF
200ns
500mV –5V ADC IN
Figure 39. Buffer Recovery Time Sink Current = 1 mA
Driving A Large Capacitive Load
The circuit of Figure 40 uses a 100 Ω isolation resistor that
enables the amplifier to drive capacitive loads exceeding
1500 pF; the resistor effectively isolates the high frequency
feedback from the load and stabilizes the circuit. Low frequency
feedback is returned to the amplifier summing junction via the
low-pass filter formed by the 100 Ω series resistor and the load
capacitance, CL. Figure 41 shows a typical transient response for
this connection.
+V
S
–V
S
1/4
AD713
4
11
0.1µF
30pF
4.99kΩ
4.99kΩ
C
L
R
L
100Ω
0.1µF
OUTPUT
INPUT
TYPICAL CAPACITANCE
LIMIT FOR VARIOUS
LOAD RESISTORS
R
L
2kΩ
10kΩ
20kΩ
C
L
UP TO
1500pF
1500pF
1000pF
00824-042
Figure 40. Circuit for Driving a Large Capacitance Load
00824-043
•••••••• •••• •••• •••• •••• •••• •••• •••• ••••
•••••••• •••• •••• •••• •••• •••• •••• •••• ••••
100
90
10
0%
5V 1µs
Figure 41. Transient Response, RL = 2 kΩ, CL = 500 pF
AD713
Rev. F | Page 14 of 20
00824-044
19
OUT1
AGND
3
DGND
2018
V
REF
AD7545
R1*
*REFER TO TABLE 5.
R2*
DB11 TO DB0
GAIN
ADJUST
C1
33pF
V
DD
V
IN
V
OUT
V
DD
R
FB
ANALOG
COMMON
+15V
–15V
0.1µF
0.1µF
1/4
AD713
4
11
1
2
CMOS DAC APPLICATIONS
The AD713 is an excellent output amplifier for CMOS DACs. It
can be used to perform both two- and four-quadrant operation.
The output impedance of a DAC using an inverted R-2R ladder
approaches R for codes containing many 1s, 3R for codes
containing a single 1, and infinity for codes containing all 0s.
For example, the output resistance of the AD7545 modulates
between 11 kΩ and 33 kΩ. Therefore, with the DAC’s internal
feedback resistance of 11 kΩ, the noise gain varies from 2 to
4/3. This changing noise gain modulates the effect of the input
offset voltage of the amplifier, resulting in nonlinear DAC
amplifier performance. The AD713, with its guaranteed 1.5 mV
input offset voltage, minimizes this effect, achieving 12-bit
performance.
Figure 42. Unipolar Binary Operation
FILTER APPLICATIONS
A Programmable State Variable Filter
For the state variable or universal filter configuration of Figure 44
to function properly, DAC A1 and DAC B1 must control the
gain and Q of the filter characteristic, and DAC A2 and DAC B2
must accurately track for the simple expression of fC to be true.
This is readily accomplished using two AD7528 DACs and one
AD713 quad op amp. Capacitor C3 compensates for the effects
of op amp gain bandwidth limitations.
Figure 42 and Figure 43 show the AD713 and a 12-bit CMOS
DAC, the AD7545, configured for either a unipolar binary (two-
quadrant multiplication) or bipolar (four-quadrant multiplication)
operation. Capacitor C1 provides phase compensation, which
reduces overshoot and ringing.
Table 5. Recommended Trim Resistor Values vs. Grades for
AD7545 for VD = 5 V
This filter provides low-pass, high-pass, and band-pass outputs
and is ideally suited for applications where microprocessor
control of filter parameters is required. The programmable
range for component values shown is fC = 0 kHz to 15 kHz and
Q = 0.3 to 4.5.
Trim Resistor JN/AQ KN/BQ LN/CQ GLN/GCQ
R1 500 Ω 200 Ω 100 Ω 20 Ω
R2 150 Ω 68 Ω 33 Ω 6.8 Ω
1/4
AD713
1/4
AD713
00824-045
19
OUT1
AGND
2018
V
REF
AD7545
R1*
R2* R4
20kΩ
1%
R3
10kΩ
1%
R5
20kΩ
1%
12
3
DGND
C1
33pF
V
DD
V
IN
V
OUT
V
DD
R
FB
ANALOG
COMMON
1
2
+15V
0.1µF
4
–15V
0.1µF
11
GAIN
ADJUST
DATA INPUT
DB11 TO DB0
*REFER TO TABLE 5.
Figure 43. Bipolar Operation
AD713
Rev. F | Page 15 of 20
1/4
AD713
A1
+V
S
V
IN
R3
10kΩ
R4
30kΩ
C1
1000pF
C3
33pF
HIGH
PASS
OUTPUT
R5
30kΩ
+
1µF
4
2
3
1
1/4
AD713
A2
6
5
7
1/4
AD713
A3
9
10
8
AD7528
V
DD
DAC B1
R
F
1819202
1
5
61615
17
14 7
DB0 TO
DB7
DATA 1
DAC A/
DACB
WRCS
DAC A1
R
S
AD7528
V
DD 20182
1
5
61615
17
14 7
DB0 TO
DB7
DATA 2
DAC A/
DAC B
WRCS
DAC A2
R1
4
4
C2
1000pF
1/4
AD713
A4
13
12
14
DAC B2
R2
–V
S
BAND PASS
OUTPUT
LOW PASS
OUTPUT
1µF
11
+
CIRCUIT EQUATIONS
C
1
= C
2
, R
1
= R
2
, R
4
= R
5
f
C
= 1
2π R
1
C
1
A
O
= – R
F
R
S
256 × (DAC LADDER RESISTANCE)
DAC DIGITAL CODE
DAC EQUIVALENT RESISTANCE EQUALS
Q = ×
R
3
R
4
R
F
R
FBB1
00824-046
Figure 44. A Programmable State Variable Filter Circuit
GIC AND FDNR FILTER APPLICATIONS
The closely matched and uniform ac characteristics of the AD713
make it ideal for use in generalized impedance converter (GIC)/
gyrator and frequency dependent negative resistor (FDNR)
filter applications. Figure 47 and Figure 48 show the AD713
used in two typical active filters. The first shows a single AD713
simulating two coupled inductors configured as a one-third
octave band-pass filter. A single section of this filter meets
ANSI Class II specifications and handles a 7.07 V rms signal
with <0.002% THD (20 Hz to 20 kHz).
Figure 48 shows a seven-pole antialiasing filter for a 2× over-
sampling (88.2 kHz) digital audio application. This filter has
<0.05 dB pass-band ripple and 19.8 s ± 0.3 s delay, at dc to
20 kHz, and handles a 5 V rms signal (VS = ±15 V) with no
overload at any internal nodes.
The filter of Figure 47 can be scaled for any center frequency by
using the following formula:
R
C
fC
π
2
11.1
=
where all resistors and capacitors scale equally. Resistors R3 to
R8 should not be greater than 2 k in value to prevent parasitic
oscillations caused by the amplifier’s input capacitance.
If this is not practical, add small lead capacitances (10 pF to
20 pF) across R5 and R6. Figure 45 and Figure 46 show the
output amplitude vs. frequency of these filters.
0
–10
–20
–30
–40
–50
–60
–70
0 102030405060708090100
FREQUENCY (MHz)
OUTPUT AMPLITUDE (dBm)
00824-048
OUTPUT AMPLITUDE (dBm)
0
–1
–2
–3
–4
–5 16 18 20
FREQUENCY (MHz)
22 24
Figure 45. Output Amplitude vs. Frequency of 1/3 Octave Filter
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
10k 100k 1M
FREQUENCY (MHz)
RELATIVE OUTPUT AMPLITUDE (dB)
00824-049
3
2
1
0
–1 200 500 1k 2k
µs dB
5k 10k 20k
200 500 1k 2k 5k 10k 20k
18
19
20
21
22
OUTPUT AMPLITUDE
GROUP DELAY
Figure 46. Relative Output Amplitude vs. Frequency of Antialiasing Filter
AD713
Rev. F | Page 16 of 20
5
6
7
1/4
AD713
2
3
1
1/4
AD713
R3
1300Ω
R1
6.19kΩ
R5
1300Ω
R7
1300Ω
R9
1300Ω
C3
6800pF
12
13
14
1/4
AD713
9
10
8
1/4
AD713
R4
1300Ω
R6
1300Ω
R2
6.19kΩ
R8
1300Ω
R10
1300Ω
R11
5.62kΩ
C4
6800pF
OUTPUTINPUT C2
6800pF
C2
6800pF
+1µF0.1µF
+1µF0.1µF
+V
S
COM
–V
S
AD713
PIN 4
AD713
PIN 11
C
1
= C
2
= C
3
= C
4
= C
R
3
= R
4
= R
5
= R
6
= R
7
= R
8
= R
9
= R
10
= R
R
1
= R
2
= 4.76Ω
R
11
= 4.32Ω
f
C
= 1.11
2πRC
00824-047
Figure 47. A 1/3 Octave Filter Circuit
00824-050
INPUT
2
3
1
1/4
AD713
A1
10kΩ
412Ω1.74kΩ1.74kΩ330Ω
100kΩ4700pF OUTPUT
95.3kΩ
4700pF
+1µF0.1µF
+1µF0.1µF
+V
S
COM
–V
S
AD713
PIN 4
AD713
PIN 11
1kΩ
1kΩ
36Ω
1.2kΩ
4700pF
4700pF 1kΩ
1kΩ
6
5
7
1/4
AD713
A2
10
9
8
A3
1/4
AD713
1kΩ
1kΩ
120Ω
1.87kΩ
4700pF
4700pF
13
12
14
1/4
AD713
A4
3
2
1
B1
1/4
AD713
1kΩ
1kΩ
130Ω
1.1kΩ
4700pF
4700pF
6
5
7
1/4
AD713
B2
10
9
8
B3
1/4
AD713
12
13
14
B4
1/4
AD713
Figure 48. An Antialiasing Filter
AD713
Rev. F | Page 17 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
14
17
8
0.100 (2.54)
BSC
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 49. 14-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-14)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.310 (7.87)
0.220 (5.59)
0.005 (0.13) MIN 0.098 (2.49) MAX
0.100 (2.54) BSC
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.785 (19.94) MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
PIN 1
17
814
Figure 50. 14-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-14)
Dimensions shown in inches and (millimeters)
AD713
Rev. F | Page 18 of 20
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
C
OPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 51. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD713AQ −40°C to +85°C 14-Lead CERDIP Q-14
AD713JNZ 0°C to 70°C 14-Lead PDIP N-14
AD713JR-16 0°C to 70°C 16-Lead SOIC_W RW-16
AD713JR-16-REEL 0°C to 70°C 16-Lead SOIC_W RW-16
AD713JR-16-REEL7 0°C to 70°C 16-Lead SOIC_W RW-16
AD713JRZ-16 0°C to 70°C 16-Lead SOIC_W RW-16
AD713JRZ-16-REEL 0°C to 70°C 16-Lead SOIC_W RW-16
AD713JRZ-16-REEL7 0°C to 70°C 16-Lead SOIC_W RW-16
1 Z = RoHS Compliant Part.
AD713
Rev. F | Page 19 of 20
NOTES
AD713
Rev. F | Page 20 of 20
NOTES
©2002–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00824-0-7/11(F)
