TECHNICAL DATA
223
8-Bit Serial-Input/Paralle l-Output
Shift Register
High-Perform ance Silicon-Gate C MOS
The IN74HC164 is identical in pinout to the LS/ALS164. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The IN74HC164 is an 8-bit, serial-input to parallel-output shift
register. Two serial data inputs, A1 and A2, are provided so that one
input may be used as a data enable. Data is entered on each rising edge
of the clock. The active-low asynchronous Reset overrides theClock
and Serial Data inputs.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
IN74HC164
ORDERING INFORMATION
IN74HC164N Plastic
IN74HC164D SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 14 =VCC
PIN 7 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Outputs
Res et Clock A1 A2 QA QB ... QH
L X X X L L ... L
H X X no change
H H D D QAn ... QGn
H D H D QAn ... QGn
D = data input
X = don’t care
QAn - QGn = data shifted from the previous stage on a
rising edge at the clock input.
IN74HC164
224
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PDPower Dissipation in Still Air, Plastic DIP+
SOIC Package+ 750
500 mW
Tstg Storage Temperature -65 to +150 °C
TLLead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types -55 +125 °C
tr, tfInput Rise and Fall Time (Figure 1) VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
ns
Thi s device contains p rote ction c ircuitr y to guard a gainst damage due to hi gh static voltage s or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
IN74HC164
225
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
≤85
°C≤125
°CUnit
VIH Minimum High-Level
Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT≤ 20 µA2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL Maximum Low -
Level Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT ≤ 20 µA2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH Minimum High-Level
Output Voltage VIN= VIH or VIL
IOUT ≤ 20 µA2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN= VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA 4.5
6.0 3.98
5.48 3.84
5.34 3.7
5.2
VOL Maximum Low-Le vel
Output Voltage VIN=VIH or VIL
IOUT ≤ 20 µA2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN=VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA 4.5
6.0 0.26
0.26 0.33
0.33 0.4
0.4
IIN Maximum Input
Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA6.0 8.0 80 160 µA
IN74HC164
226
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC Guaranteed Limit
Symbol Parameter V 25 °C
to
-55°C
≤85°C≤125°CUnit
fmax Maximum Clock Fr equency (50% Duty Cycle)
(Figures 1 and 4) 2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH, tPHL Maximum Prop agation Delay,Clock to Q ( Figures
1 and 4) 2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPHL Maximum Propagation Delay,Reset to Q (Figures
2 and 4) 2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4) 2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
CIN Maximum Input Capacitance - 10 10 10 pF
Power Dissipation Capacitance (Per Package) Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
140 pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC Guaranteed Limit
Symbol Parameter V 25 °C to
-55°C≤85°C≤125°CUnit
tSU Minimum Setup Time,A1 or
A2 to Cl ock (Figure 3) 2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
thMinimum H ol d Ti me, Cloc k
to A1 or A2 (Figure 3) 2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
trec Minimum Recovery T ime,
Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
twMinimum Pul se Width, Re set
(Figure 2) 2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
twMinimum Pul se Width, Clock
(Figure 1) 2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, tfMax imum Input Ri se and Fall
Times ( F igure 1) 2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
IN74HC164
227
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms Figure 4. Test Circuit
TIMING DIAGRAM
EXPANDED LOGIC DIAGRAM
