MKW39/38/37 Data Sheet

An ultra low-power, highly integrated Bluetooth® Low

Energy 5.0 wireless microcontroller

Multi-Standard Radio

• 2.4 GHz Bluetooth Low Energy (Bluetooth LE) version

5.0 compliant supporting up to 8 simultaneous

hardware connections and all optional features

• High speed (2M PHY)

• Bluetooth LE 1 Mbit/s: –98 dBm

• Bluetooth LE LR 500 kbit/s: –101 dBm

• Bluetooth LE LR 125 kbit/s: –105 dBm

• Generic FSK modulation

• Data Rate: 250, 500, 1000 and 2000 kbit/s

• Modulations: GFSK BT = 0.5, MSK

• Modulation Index: 0.32, 0.5, 0.7, and 1.0

• Typical Receiver Sensitivity (250 kbit/s GFSK-

BT=0.5, h=0.5) = –101 dBm

• Programmable Transmitter Output Power: –30 dBm to

System peripherals

• Nine MCU low-power modes to provide power

optimization based on application requirements

• DC-DC Converter supporting Buck and Bypass

operating modes

• Direct Memory Access (DMA) controller

and two 2 channel TPMs

• Programmable Interrupt Timer (PIT)

• Real-Time Clock (RTC)

Communication interfaces

• 2 Serial Peripheral Interface (SPI) modules

• 2 Inter-integrated Circuit (I2C) modules

• Low-power UART (LPUART) module with LIN

support (2x LPUART on KW38)

• Carrier Modulator Timer (CMT)

• FlexCAN module (with CAN FD support up to 3.2

NXP Semiconductors MKW39A512

Data Sheet: Technical Data Rev. 7, 03/2020

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

• AES-128 Hardware Accelerator (AESA)

• True Random Number Generator (TRNG)

• Advanced flash security on Program Flash

• 80-bit unique identification number per chip

• 40-bit unique Media Access Control (MAC) sub-

Generic FSK modes

• 32.768 kHz Crystal Oscillator

• Ambient temperature range: –40 to 105 °C

• AEC Q100 Grade 2 Automotive Qualification

• Industrial Qualification

• General-purpose input/output (GPIO)

KW39/38/37 Part Numbers

Device Qualification

256 KB P-

Second LPUART

Related Resources

Type Description

(operation) of a device.

1 Introduction........................................................................... 5

2 Feature Descriptions............................................................. 6

2.1 Block Diagram............................................................... 6

2.2 Radio features............................................................... 8

2.3 Microcontroller features................................................. 9

2.4 System features.............................................................10

2.5 Peripheral features........................................................ 12

2.6 Security Features...........................................................17

3 Transceiver Description........................................................ 18

3.1 Transceiver Functions................................................... 18

4.2 Receiver Feature Summary...........................................22

4.3 Transmit and PLL Feature Summary.............................26

5 System and Power Management.......................................... 31

5.1 Power Management.......................................................31

5.1.1 DC-DC Converter.............................................. 32

5.2 Modes of Operation....................................................... 32

5.2.1 Power modes.....................................................32

6 KW39/38/37 Electrical Characteristics.................................. 35

6.1 AC electrical characteristics...........................................35

6.2 Nonswitching electrical specifications............................35

6.2.7 SoC Power Consumption.................................. 48

6.2.8 Designing with radiated emissions in mind........49

6.2.9 Capacitance attributes.......................................49

6.3 Switching electrical specifications..................................49

6.3.1 Device clock specifications................................49

6.3.2 General switching specifications....................... 50

6.4 Thermal specifications...................................................51

6.4.1 Thermal operating requirements....................... 51

6.4.2 Thermal attributes..............................................51

6.5 Peripheral operating requirements and behaviors.........52

6.5.1 Core modules.................................................... 52

6.5.2 System modules................................................ 53

6.5.3 Clock modules................................................... 54

6.5.4 Memories and memory interfaces..................... 57

6.5.5 Security and integrity modules.......................... 61

6.5.6 Analog............................................................... 61

6.5.7 Timers................................................................68

6.7.3 ESD handling ratings.........................................76

6.7.4 Voltage and current operating ratings............... 76

7.1 KW39/37 Signal Multiplexing and Pin Assignments...... 77

7.2 KW38 Signal Multiplexing and Pin Assignments........... 79

7.3 KW39/38/37 Pinouts......................................................82

7.4 Module Signal Description Tables................................. 83

7.4.1 Core Modules.................................................... 83

7.4.2 Radio Modules...................................................84

7.4.3 System Modules................................................ 85

8.1 Obtaining package dimensions......................................89

9.1 Description.....................................................................90

9.4 Example.........................................................................91

Serial Wire Debug

AHBLite

Crossbar-Lite Switch (AXBS)

Figure 2. KW38 Detailed Block Diagram

Crossbar-Lite Switch (AXBS)

Table 1. List of IPs in block diagrams

ADC Analog-to-Digital Converter

AESA Advanced Encryption Standard Accelerator

DMAMUX Direct Memory Access Multiplexer

DWT Data Watchpoint and Trace

FLL Frequency-Locked Loop

GPIO General Purpose Input/Output

I2C Inter-integrated Circuit

IRC Internal Reference Clock

LPTMR Low-Power Timer

LPUART Low-Power UART

LTC LP Trusted Cryptography

MCG Multipurpose Clock Generator

Feature Descriptions

Table 1. List of IPs in block diagrams (continued)

General Purpose Input/Output (GPIO)

True Random Number Generator (TRNG)

Flash Memory Protection

Transceiver Description

2.4 GHz ISM1MBAN22.4GHz ISM + MBAN

— — –54 — dBc

— — –70 — dBc

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Transceiver Electrical Characteristics

Table 4. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise

Bluetooth LE LR 125 kbit/s Co-channel Interference

(Wanted signal at –67 dBm, BER <0.1%. Measurement

resolution 1 MHz).

COSELBLELR125 –2 dB

Adjacent/Alternate Channel Performance8

Bluetooth LE LR 125 kbit/s Adjacent +/–1 MHz

Interference offset (Wanted signal at –67 dBm, BER

<0.1%. Measurement resolution 1 MHz.)

SELBLELR125, 1

<0.1%. Measurement resolution 1 MHz.)

Bluetooth LE LR 125 kbit/s Alternate > +/–5 MHz

Interference offset (Wanted signal at –67 dBm, BER

<0.1%. Measurement resolution 1 MHz.)

Bluetooth LE coded 500 kbit/s (Long Range, 2x Spreading)

Bluetooth LE LR 500 kbit/s Sensitivity7SENSBLELR500 — –101 — dBm

Bluetooth LE LR 500 kbit/s Co-channel Interference

(Wanted signal at –67 dBm, BER <0.1%. Measurement

COSELBLELR500 –4 dB

Bluetooth LE LR 500 kbit/s Adjacent +/–2 MHz

Interference offset (Wanted signal at –67 dBm, BER

<0.1%. Measurement resolution 1 MHz.)

SELBLELR500, 2

Bluetooth LE LR 500 kbit/s Alternate +/–3 MHz

Interference offset (Wanted signal at –67 dBm, BER

<0.1%. Measurement resolution 1 MHz.)

SELBLELR500, 3

Bluetooth LE LR 500 kbit/s Alternate > +/–5 MHz

Interference offset (Wanted signal at –67 dBm, BER

1 MHz).

Adjacent/Alternate Channel Selectivity Performance8

Bluetooth LE 1 Mbit/s Selectivity +/–1 MHz Interference

offset (Wanted signal at –67 dBm, BER <0.1%.

Measurement resolution 1 MHz.)

SELBLE1M, 1 MHz — 0 — dB

Table continues on the next page...

Characteristic1Symbol Min. Typ. Max. Unit

IM5-10BLE1M — –23 — dBm

— — 3 — dBm

— — –12 — dBm

— — 5 — dBm

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Transceiver Electrical Characteristics

Table 4. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise

Bluetooth LE 2 Mbit/s Selectivity +/–6 MHz Interference

offset (Wanted signal at –67 dBm, BER <0.1%.

Measurement resolution 2 MHz.)

SELBLE2M, 6 MHz — 50 — dB

Bluetooth LE 2 Mbit/s Selectivity ≥ +/–10 MHz

<0.1%. Measurement resolution 2 MHz.)

at ±20 MHz (Wanted signal at –67 dBm, BER<0.1%.)

Blocking Performance

Bluetooth LE 2 Mbit/s Out of band blocking from 30 MHz

to 1000 MHz and 4000 MHz to 5000 MHz (Wanted

signal at –67 dBm, BER<0.1%. Interferer continuous

wave signal.)9,10

— — 3 — dBm

Bluetooth LE 2 Mbit/s Out of band blocking from 1000

MHz to 2000 MHz and 3000 MHz to 4000 MHz (Wanted

signal at –67 dBm, BER<0.1%. Interferer continuous

wave signal.)

— — –6 — dBm

BER<0.1%. Interferer continuous wave signal.)10

1. All the Rx parameters are measured at the KW39/38/37 RF pins.

2. Transceiver power consumption.

3. Narrow-band RSSI mode.

4. With RSSI_CTRL_0.RSSI_ADJ field calibrated to account for antenna to RF input losses.

5. With one point calibration over frequency and temperature.

6. Exceptions allowed for twice the reference clock frequency(fref) multiples.

7. Measured at 0.1% BER using 37 byte long packets in maximum gain mode and nominal conditions.

8. Bluetooth LE adjacent and alternate selectivity performance is measured with modulated interference signals.

9. Exceptions allowed for carrier frequency sub harmonics.

5.2 Modes of Operation

Normal Run (all

peripherals clock off)

Normal Wait - via

Normal Stop - via

PStop2 (Partial Stop

VLPR (Very Low-

power Run) (all

peripherals off)

— Radio operation is possible

in the way of radio operation.

VLPW (Very Low-

Table 9. Power modes (At 25 deg C) (continued)

Power mode Description CPU

Biasing is disabled when DC-DC is configured for

continuous mode in VLPS.

State retention power mode. LLWU, LPTMR, RTC,

CMP can be operational. All of the radio Sea of

Gates(SOG) logic is in state retention.

Bluetooth LE/Generic FSK

State retention power mode. LLWU, LPTMR, RTC,

VLLS2. The Bluetooth LE/

be active using the 32 KHz

Partial SRAM retention. 16 KB or 32 KB of

programmable RAM can be powered on. LLWU,

LPTMR, RTC, CMP can be operational. All of the

Radio SoG logic is power gated. Radio Tx/Rx

file remains powered for customer-critical data.

LLWU, LPTMR, RTC, CMP can be operational.

VLLS0 is not supported with DC-DC.

The 32-byte system register file remains powered

for customer-critical data. Disable all analog

modules in PMC and retains I/O state and DGO

state. LPO disabled, POR brown-out detection

enabled, Pin interrupt only. Radio logic is power

is power-gated in VLLS0.

for customer-critical data. Disable all analog

modules in PMC and retains I/O state and DGO

state. LPO disabled, POR brown-out detection

disabled, Pin interrupt only. Radio logic is power

1. Biasing is disabled, but the Flash is in a low-power mode for VLPx, so this configuration can realize some power savings

2. DSM refers to Radio's deep sleep mode. DSM does not refer to the Arm sleep deep mode.

System and Power Management

Table 10. Voltage and current operating requirements (continued)

Symbol Description Min. Max. Unit Notes

1. This limit applies in any DCDC mode.

2. All I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN

KW39/38/37 Electrical Characteristics

Symbol Description Min. Typ. Max. Unit Notes

Table 12. Voltage and current operating behaviors (continued)

Symbol Description Min. Max. Unit Notes

2. The reset pin only contains an active pull-up device when configured as the RESET signal or as a GPIO. When

3. Measured at VDD = 3.6 V.

4. Measured at VDD supply voltage = VDD min and Vinput = VSS.

6.2.4 Power mode transition operating behaviors

KW39/38/37 Electrical Characteristics

Table 13. Power mode transition operating behaviors (continued)

1. Normal boot (FTFA_FOPT[LPBOOT]=11). When the DC-DC converter is in bypass mode, TPOR will not meet the 300

6.2.5 Power consumption operating behaviors

CoreMark benchmark code executing from

flash at 3.0 V

MHz core / 24 MHz flash / bus clock disabled,

code of while(1) loop executing from flash at

3.0 V

and flash, all peripheral clocks disabled, code

of while(1) loop executing from flash at 3.0 V

and flash, all peripheral clocks enabled, code of

while(1) loop executing from flash at 3.0 V

at 25 °C

at 70 °C

at 105 °C

3, 4, 5

Table continues on the next page...

KW39/38/37 Electrical Characteristics

mode(3.0 V),

at 25 °C

at 70 °C

at 105 °C

Bypass mode(3.0 V),

at 25 °C

at 70 °C

at 105 °C

Bypass mode(3.0 V),

at 25 °C

KW39/38/37 Electrical Characteristics

Average IC

RUN Enabled Tx (at +3.5

Buck (VDCDC_IN=3.6 V) 11.7 mA

VLPR and VLPS modes1

fSYS System and core clock — 4 MHz

KW39/38/37 Electrical Characteristics

• Slew disabled

• 1.71 ≤ VDD ≤ 2.7 V

Port rise and fall time(low drive strength)

21.4 °C/W 1, 2

0.2 °C/W 1, 3

2. Determined according to JEDEC Standard JESD51-2A.

3. Thermal characterization parameter indicating the temperature difference between the package top and the junction

Table 23. SWD full voltage range electricals

KW39/38/37 Electrical Characteristics

J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns

Table 24. MCG specifications

31.25 — 39.0625 kHz

3 — 5 MHz

640 × ffll_ref

Jcyc_fll FLL period jitter

KW39/38/37 Electrical Characteristics

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock

2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft.

3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.

4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency

Table 25. Recommended Crystal and Oscillator Specification

Crystal frequency

stability and aging

–25 — 25 –25 — 24 ppm 2,4

Oscillator variation –12 — 15 –12 — 16 ppm 5

Total reference

oscillator tolerance

for Bluetooth LE

–50 — 50 –50 — 50 ppm 6

CLLoad capacitance 7 10 13 7 10 13 pF 2, 7

C0Shunt capacitance 0.469 0.67 0.871 0.42 0.6 0.78 pF 2,7

Symbol Description F0 = 32.0 MHz F0 = 26.0 MHz Unit Notes

2. Recommended crystal specification.

3. Measured at 25 °C.

4. Combination of frequency stability variation over desired temperature range and frequency variation due to aging over

5. Variation due to temperature, process, and aging of MCU.

6. Sum of crystal initial frequency tolerance, crystal frequency stability and aging, oscillator variation, and PCB

7. Typical is target. 30% tolerances shown.

TAOperating

–40 — 105 °C 1

Total crystal

–500 — 500 ppm 2,3

CLLoad

— 12.5 — pF 2

ESR Equivalent

— — 80 kOhms 2

2. Recommended crystal specification.