OPA2837DGKEVM - TEXAS INSTRUMENTS

March, 2018 − Rev. 3

1Publication Order Number:

NCV7344/D

NCV7344

High Speed Low Power

CAN, CAN FD Transceiver

Description

The NCV7344 CAN transceiver is the interface between a

controller area network (CAN) protocol controller and the physical

bus. The transceiver provides differential transmit capability to the bus

and differential receive capability to the CAN controller.

The NCV7344 is an addition to the CAN high−speed transceiver

family complementing NCV734x CAN stand−alone transceivers and

previous generations such as AMIS42665, AMIS3066x, etc.

The NCV7344 guarantees additional timing parameters to ensure

robust communication at data rates beyond 1 Mbps to cope with CAN

flexible data rate requirements (CAN FD). These features make the

NCV7344 an excellent choice for all types of HS−CAN networks, in

nodes that require a low−power mode with wake−up capability via the

CAN bus.

Features

•Compatible with ISO 11898−2:2016

•Specification for Loop Delay Symmetry up to 5 Mbps

•VIO pin on NCV7344−3 Version Allowing Direct Interfacing with

3 V to 5 V Microcontrollers

•Very Low Current Standby Mode with Wake−up via the Bus

•Low Electromagnetic Emission (EME) and High Electromagnetic

Immunity

•Very Low EME without Common−mode (CM) Choke

•No Disturbance of the Bus Lines with an Un−powered Node

•Transmit Data (TxD) Dominant Timeout Function

•Under All Supply Conditions the Chip Behaves Predictably

•Very High ESD Robustness of Bus Pins, >8 kV System ESD Pulses

•Thermal Protection

•Bus Pins Short Circuit Proof to Supply Voltage and Ground

•Bus Pins Protected Against Transients in an Automotive

Environment

•These are Pb−free Devices

Quality

•Wettable Flank Package for Enhanced Optical Inspection

•NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

Typical Applications

•Automotive

•Industrial Networks

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See detailed ordering and shipping information on page 11 of

this data sheet.

ORDERING INFORMATION

PIN ASSIGNMENT

MARKING

DIAGRAM

SOIC−8

D1 SUFFIX

CASE 751AZ

NV7344xy= Specific Device Code

x = − or A

y = 0 or 3

− = long filter time

A = short filter time

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

NV7344xy

ALYW G

NCV7344MWx

(Top View)

(Note: Microdot may be in either location)

DFN8

MW SUFFIX

CASE 507AB

NV7344xy

ALYWG

NCV7344D1x

(Top View)

STB

CANH

CANL

TxD

GND

RxD NC (−0)

VIO (−3)

VCC

TxD

GND

RxD

VCC

STB

CANH

CANL

NC (−0)

VIO (−3)

EP Flag

NCV7344

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BLOCK DIAGRAM

Mode &

Wake−up

control

Wake−up

Filter

NCV7344−0

STB

GND

RxD

VCC

COMP

Timer

TxD 1

Driver control

Thermal

shutdown

VCC

CANH

CANL

Figure 1. NCV7344−0 Block Diagram

Mode &

Wake−up

control

Wake−up

Filter

NCV7344−3

STB

GND

RxD

VCC

COMP

Timer

TxD 1

Driver control

Thermal

shutdown

VIO

CANH

CANL

VIO

Figure 2. NCV7344−3 Block Diagram

NCV7344

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TYPICAL APPLICATION

VCC

Micro−

controller

VBAT

GND

CANH

CANL

CAN

BUS

5V −reg

RLT =60W

GND

STB

RxD

TxD 1

IN OUT

VCC

NCV7344

Figure 3. Application Diagram NCV7344−0

5V −reg

VCC

Micro−

controller

VIO

VBAT

GND

CANH

CANL

CAN

BUS

3V −reg

RLT =60W

GND

STB

RxD

TxD 1

NCV7344−3

IN OUT

Figure 4. Application Diagram NCV7344−3

Table 1. PIN FUNCTION DESCRIPTION

Pin Name Description

1 TxD Transmit data input; low input Ù dominant driver; internal pull−up current

2 GND Ground

3 VCC Supply voltage

4 RxD Receive data output; dominant transmitter Ù low output

VIO

Not connected. On NCV7344−0 only

Digital Input / Output pins and other functions supply voltage. On NCV7344−3 only

6 CANL Low−level CAN bus line (low in dominant mode)

7 CANH High−level CAN bus line (high in dominant mode)

8 STB Standby mode control input; internal pull−up current

EP Exposed Pad. Recommended to connect to GND or left floating in application (DFN8 package only).

NCV7344

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FUNCTIONAL DESCRIPTION

Operating Modes

NCV7344 provides two modes of operation as illustrated

in Table 2. These modes are selectable through pin STB.

Table 2. OPERATING MODES

Pin STB Mode Pin RxD

Low Normal Low when bus

dominant

High when bus

recessive

High Standby Follows the bus

when wake−up

detected

High when no

wake−up

request detected

Normal Mode

In the normal mode, the transceiver is able to

communicate via the bus lines. The signals are transmitted

and received to the CAN controller via the pins TxD and

RxD. The slopes on the bus lines outputs are optimized to

give low EME.

Standby Mode

In standby mode both the transmitter and receiver are

disabled and a very low−power differential receiver

monitors the bus lines for CAN bus activity. The bus lines

are biased to ground and supply current is reduced to a

minimum, typically 10 mA. When a wake−up request is

detected by the low−power differential receiver, the signal

is first filtered and then verified as a valid wake signal after

a time period of twake_filt, the RxD pin is driven low by the

transceiver (following the bus) to inform the controller of

the wake−up request.

Wake−up

When a valid wake−up pattern (phase in order

dominant – recessive – dominant) is detected during the

standby mode the RxD pin follows the bus. Minimum length

of each phase is twake_filt – see Figure 5.

Pattern must be received within twake_to to be recognized

as valid wake−up otherwise internal logic is reset.

CANH

CANL

RxD

twake_filt twake_filt

wake_to

twake_filt

Figure 5. NCV7344 Wake−up Behavior

tdwakerd tdwakedr

Overtemperature Detection

A thermal protection circuit protects the IC from damage

by switching off the transmitter if the junction temperature

exceeds a value of approximately 180°C. Because the

transmitter dissipates most of the power, the power

dissipation and temperature of the IC is reduced. All other

IC functions continue to operate. The transmitter off−state

resets when the temperature decreases below the shutdown

threshold and pin TxD goes high. The thermal protection

circuit is particularly needed when a bus line short circuits.

TxD Dominant Timeout Function

A TxD dominant timeout timer circuit prevents the bus

lines being driven to a permanent dominant state (blocking

all network communication) if pin TxD is forced

permanently low by a hardware and/or software application

failure. The timer is triggered by a negative edge on pin TxD.

If the duration of the low−level on pin TxD exceeds the

internal timer value tdom(TxD), the transmitter is disabled,

driving the bus into a recessive state. The timer is reset by a

positive edge on pin TxD.

This TxD dominant timeout time tdom(TxD) defines

the minimum possible bit rate to 17 kbps.

Fail Safe Features

A current−limiting circuit protects the transmitter output

stage from damage caused by accidental short circuit

to either positive or negative supply voltage, although

power dissipation increases during this fault condition.

Standby undervoltage on VCC pin prevents the chip

sending data on the bus when there is not enough VCC

supply voltage by entering standby mode. Undervoltage

detection on VIO pin (NCV7344−3 version only) also

causes transition to standby mode. Switch−off undervoltage

detection level on supply pin(s) forces transceiver to

disengage from the bus until the supply is recovered. After

supply is recovered TxD pin must be first released to high to

allow sending dominant bits again. Recovery time from

undervoltage detection is equal to td(stb−nm) time.

The pins CANH and CANL are protected from

automotive electrical transients (according to ISO 7637; see

Figure 7). Pins TxD and STB are pulled high internally

should the input become disconnected. Pins TxD, STB and

RxD will be floating, preventing reverse supply should the

VCC supply be removed.

VIO Supply Pin

The VIO pin (available only on NCV7344−3 version)

should be connected to microcontroller supply pin. By using

VIO supply pin shared with microcontroller the I/O levels

between microcontroller and transceiver are properly

adjusted. See Figure 4. Pin VIO also provides the internal

supply voltage for low−power differential receiver of the

transceiver. This allows detection of wake−up request even

when there is no supply voltage on pin VCC.

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ELECTRICAL CHARACTERISTICS

Definitions

All voltages are referenced to GND (pin 2). Positive

currents flow into the IC. Sinking current means the current

is flowing into the pin; sourcing current means the current

is flowing out of the pin.

ABSOLUTE MAXIMUM RATINGS

Table 3. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Conditions Min Max Unit

VSUP Supply voltage VCC, VIO −0.3 +6 V

VCANH DC voltage at pin CANH 0 < VCC < 5.25 V; no time limit −42 +42 V

VCANL DC voltage at pin CANL 0 < VCC < 5.25 V; no time limit −42 +42 V

VCANH−CANL DC voltage between CANH and CANL −42 +42 V

VI/O DC voltage at pin TxD, RxD, STB −0.3 +6 V

VesdHBM Electrostatic discharge voltage at all pins,

Component HBM

(Note 1) −8 +8 kV

VesdCDM Electrostatic discharge voltage at all pins,

Component CDM

(Note 2) −750 +750 V

VesdIEC Electrostatic discharge voltage at pins CANH and

CANL, System HBM (Note 4)

(Note 3) −8 +8 kV

Vschaff Voltage transients, pins CANH, CANL. According

to ISO7637−3, Class C (Note 4)

test pulses 1 −100 V

test pulses 2a +75 V

test pulses 3a −150 V

test pulses 3b +100 V

Latch−up Static latch−up at all pins (Note 5) 150 mA

Tstg Storage temperature −55 +150 °C

TJMaximum junction temperature −40 +170 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF

capacitor through a 1.5 kW resistor.

2. Standardized charged device model ESD pulses when tested according to AEC−Q100−011

3. System human body model electrostatic discharge (ESD) pulses in accordance to IEC 61000−4−2. Equivalent to discharging a 150 pF

capacitor through a 330 W resistor referenced to GND.

4. Results were verified by external test house.

5. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78.

Table 4. THERMAL CHARACTERISTICS

Parameter Symbol Value Unit

Thermal characteristics, SOIC−8 (Note 6)

Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 7)

Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 8)

RqJA

131

°C/W

Thermal characteristics, DFN8 (Note 6)

Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 7)

Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 8)

RqJA

125

°C/W

6. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe

Operating parameters.

7. Values based on test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.

8. Values based on test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage.

NCV7344

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ELECTRICAL CHARACTERISTICS

Table 5. ELECTRICAL CHARACTERISTICS VCC = 4.75 V to 5.25 V; VIO = 2.8 to 5.25 V; TJ = −40 to +150°C; RLT = 60 W,

CLT = 100 pF, C1 not used, CRxD = 15 pF unless specified otherwise.

Symbol Parameter Conditions Min Typ Max Unit

SUPPLY (Pin VCC)

VCC Power supply voltage (Note 9) 4.75 5 5.25 V

ICC Supply current Dominant; VTxD = Low 20 45 70 mA

Recessive; VTxD = High 1.9 5 10 mA

ICCS Supply current in standby mode TJ ≤ 100°C, (Note 10) −10 15 mA

VUVD(VCC)(stby) Standby undervoltage detection VCC pin 3.5 4 4.3 V

VUVD(VCC)(swoff) Switch−off undervoltage detection VCC pin 2.0 2.3 2.6 V

VIO SUPPLY VOLTAGE (Pin VIO) Only for NCV7344−3 version

VIO Supply voltage on pin VIO 2.8 −5.5 V

IIOS Supply current on pin VIO in standby mode TJ ≤ 100°C, (Note 10) − − 11 mA

ICCS Supply current on pin VCC in standby

mode

TJ ≤ 100°C, (Note 10) −0 4.0 mA

IIONM Supply current on pin VIO during normal

mode

Dominant; VTxD = Low 0.45 0.65 0.9 mA

Recessive; VTxD = High 0.32 0.43 0.58

VUVDVIO Undervoltage detection voltage on VIO pin 2.0 2.3 2.6 V

TRANSMITTER DATA INPUT (Pin TxD)

VIH High−level input voltage Output recessive 2.0 − − V

VIL Low−level input voltage Output dominant − − 0.8 V

IIH High−level input current VTxD = VCC/VIO −5 0 +5 mA

IIL Low−level input current VTxD = 0 V −300 −150 −75 mA

CiInput capacitance (Note 10) −5 10 pF

TRANSMITTER MODE SELECT (Pin STB)

VIH High−level input voltage Standby mode 2.0 − − V

VIL Low−level input voltage Normal mode − − 0.8 V

IIH High−level input current VSTB = VCC/VIO −1 0 +1 mA

IIL Low−level input current VSTB = 0 V −15 − −1mA

CiInput capacitance (Note 10) −5 10 pF

RECEIVER DATA OUTPUT (Pin RxD)

IOH High−level output current Normal mode

VRxD = VCC/VIO – 0.4 V

−8−3−1 mA

IOL Low−level output current VRxD = 0.4 V 1 6 12 mA

BUS LINES (Pins CANH and CANL)

Io(rec) Recessive output current at pins CANH

and CANL

−27 V < VCANH, VCANL < +32 V;

Normal mode

−5−+5 mA

ILI Input leakage current 0 W < R(VCC to GND) < 1 MW

VCANL = VCANH = 5 V

−5 0 +5 mA

Vo(rec)(CANH) Recessive output voltage at pin CANH Normal mode, VTxD = High;

RLT and CLT not used

2.0 2.5 3.0 V

Vo(rec)(CANL) Recessive output voltage at pin CANL Normal mode, VTxD = High;

RLT and CLT not used

2.0 2.5 3.0 V

Vo(off)(CANH) Recessive output voltage at pin CANH Standby mode;

RLT and CLT not used

−0.1 0 0.1 V

NCV7344

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Table 5. ELECTRICAL CHARACTERISTICS VCC = 4.75 V to 5.25 V; VIO = 2.8 to 5.25 V; TJ = −40 to +150°C; RLT = 60 W,

CLT = 100 pF, C1 not used, CRxD = 15 pF unless specified otherwise.

Symbol UnitMaxTypMinConditionsParameter

BUS LINES (Pins CANH and CANL)

Vo(off)(CANL) Recessive output voltage at pin CANL Standby mode;

RLT and CLT not used

−0.1 0 0.1 V

Vo(off)(diff) Differential bus output voltage

(VCANH − VCANL)

Standby mode;

RLT and CLT not used

−0.2 0 0.2 V

Vo(dom)(CANH) Dominant output voltage at pin CANH VTxD = 0 V; t < tdom(TxD);

50 W < RLT < 65 W

2.75 3.5 4.5 V

Vo(dom)(CANL) Dominant output voltage at pin CANL VTxD = 0 V; t < tdom(TxD);

50 W < RLT < 65 W

0.5 1.5 2.25 V

Vo(dom)(diff) Differential bus output voltage

(VCANH − VCANL)

VTxD = 0 V; dominant;

45 W < RLT < 65 W

1.5 2.25 3.0 V

Vo(dom)(diff)_arb Differential bus output voltage during

arbitration (VCANH − VCANL)

RLT = 2.24 kW (Note 10) 1.5 −5.0 V

Vo(rec)(diff) Differential bus output voltage

(VCANH − VCANL)

VTxD = High; recessive; no load −50 0 +50 mV

Vo(dom)(sym) Dominant output voltage driver symmetry

(VCANH + VCANL)

RLT = 60 W; C1 = 4.7 nF;

TxD = square wave up to 1 MHz

0.9 1.0 1.1 VCC

Io(sc)(CANH) Short circuit output current at pin CANH −3 V < VCANH < +18 V −100 −70 1.5 mA

Io(sc)(CANL) Short circuit output current at pin CANL −3 V < VCANL < +36 V −1.5 70 100 mA

Vi(rec)(diff)_NM Differential input voltage range

recessive state

Normal or Silent mode;

−12 V ≤ VCANH,

VCANL ≤ +12 V; no load

−3.0 −0.5 V

Vi(rec)(diff)_LP Standby or Sleep mode;

−12 V ≤ VCANH,

VCANL ≤ +12 V; no load

−3.0 0.4 V

Vi(dom)(diff)_NM Differential input voltage range

dominant state

Normal or Silent mode;

−12 V ≤ VCANH,

VCANL ≤ +12 V; no load

0.9 − 8.0 V

Vi(dom)(diff)_LP Standby or Sleep mode;

−12 V ≤ VCANH,

VCANL ≤ +12 V; no load

1.05 8.0 V

Vi(diff)(th)_NORM Differential receiver threshold voltage in

normal mode

−12 V ≤ VCANL ≤ +12 V;

−12 V ≤ VCANH ≤ +12 V

0.5 −0.9 V

Vi(diff)(th)_NORM_H Differential receiver threshold voltage in

normal mode, extended range

−30 V < VCANL < +35 V;

−30 V < VCANH < +35 V

0.4 −1.0 V

Vi(diff)(th)_STDBY Differential receiver threshold voltage in

standby mode

−12 V ≤ VCANL ≤ +12 V;

−12 V ≤ VCANH ≤ +12 V

0.4 −1.05 V

Ri(cm)(CANH) Common−mode input resistance at pin

CANH

−2 V ≤ VCANH ≤ +7 V;

−2 V ≤ VCANL ≤ +7 V

15 26 37 kW

Ri(cm)(CANL) Common−mode input resistance at pin

CANL

−2 V ≤ VCANH ≤ +7 V;

−2 V ≤ VCANL ≤ +7 V

15 26 37 kW

Ri(cm)(m) Matching between pin CANH and pin

CANL common mode input resistance

VCANH = VCANL = +5 V −1 0 +1 %

Ri(diff) Differential input resistance −2 V ≤ VCANH ≤ +7 V;

−2 V ≤ VCANL ≤ +7 V

25 50 75 kW

Ci(CANH) Input capacitance at pin CANH VTxD = High; (Note 10) −7.5 20 pF

Ci(CANL) Input capacitance at pin CANL VTxD = High; (Note 10) −7.5 20 pF

Ci(diff) Differential input capacitance VTxD = High; (Note 10) −3.75 10 pF

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Table 5. ELECTRICAL CHARACTERISTICS VCC = 4.75 V to 5.25 V; VIO = 2.8 to 5.25 V; TJ = −40 to +150°C; RLT = 60 W,

CLT = 100 pF, C1 not used, CRxD = 15 pF unless specified otherwise.

Symbol UnitMaxTypMinConditionsParameter

TIMING CHARACTERISTICS (see Figures 6 and 8)

td(TxD−BUSon) Delay TxD to bus active −75 −ns

td(TxD−BUSoff) Delay TxD to bus inactive −85 −ns

td(BUSon−RxD) Delay bus active to RxD −24 −ns

td(BUSoff−RxD) Delay bus inactive to RxD −32 −ns

tpd_dr Propagation delay TxD to RxD dominant to

recessive transition

50 100 210 ns

tpd_rd Propagation delay TxD to RxD recessive

to dominant transition

50 120 210 ns

td(stb−nm) Delay standby mode to normal mode 511 20 ms

twake_filt Filter time for wake−up via bus NCV7344 version 0.5 −5ms

NCV7344A version 0.15 −1.8 ms

tdwakerd Delay to flag wake event

(recessive to dominant transitions)

Valid bus wake−up event 0.5 2.6 6 ms

tdwakedr Delay to flag wake event

(dominant to recessive transitions)

Valid bus wake−up event 0.5 2.6 6 ms

twake_to Bus time for wake−up timeout Standby mode 1−10 ms

tdom(TxD) TxD dominant time for timeout VTxD = Low; Normal mode 1−10 ms

tBit(RxD) Bit time on RxD pin tBit(TxD) = 500 ns 400 −550 ns

tBit(TxD) = 200 ns 120 −220 ns

tBit(Vi(diff)) Bit time on bus (CANH – CANL pin) tBit(TxD) = 500 ns 435 −530 ns

tBit(TxD) = 200 ns 155 −210 ns

DtRec Receiver timing symmetry

DtRec = tBit(RxD) − tBit(Vi(diff))

tBit(TxD) = 500 ns −65 −+40 ns

tBit(TxD) = 200 ns −45 −+15 ns

THERMAL SHUTDOWN

TJ(sd) Shutdown junction temperature Junction temperature rising 160 180 200 °C

9. In the range between VUVD(VCC)(stby) and 4.75 V and from 5.25 V to 6 V the chip is fully functional; some parameters may be outside of

the specification.

10.Values based on design and characterization, not tested in production

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MEASUREMENT SETUPS AND DEFINITIONS

TxD

0.3·VCC *0.3·VCC *

0.7·VCC *

5·tbit(TxD) tbit(TxD)

0.3·VCC *

tbit(RxD)

RxD

500mV

tbit(Vi(diff))

tpd_dr

tpd_rd

900mV

Vi(diff)=V

CANH −VCANL

td(TxD−BUSon)

td(TxD−BUSoff)

0.7·VCC *

td(BUSon−RxD)

Figure 6. Transceiver Timing Diagram

*On NCV7344−3 VCC is replaced by VIO

Edge length below 10 ns

NCV7344

VCC

GND

3CANH

CANL

STB

RxD 4

TxD 1

100nF

+5 V

15pF

1nF

Transient

Generator

VIO

Figure 7. Test Circuit for Automotive Transients

Figure 8. Test Circuit for Timing Characteristics

VCC

GND

3CANH

CANL

RLT/2

CLT

STB

RxD 4

TxD 1

2x 30 W

100 pF

100 nF

+5 V

15 pF

NCV7344

VIO

RLT/2

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Table 6. ISO 11898−2:2016 Parameter Cross−Reference Table

ISO 11898−2:2016 Specification NCV7344

Datasheet

Parameter Notation Symbol

Dominant output characteristics

Single ended voltage on CAN_H VCAN_H Vo(dom)(CANH)

Single ended voltage on CAN_L VCAN_L Vo(dom)(CANL)

Differential voltage on normal bus load VDiff Vo(dom)(diff)

Differential voltage on effective resistance during arbitration VDiff Vo(dom)(diff)_arb

Differential voltage on extended bus load range (optional) VDiff Vo(dom)(diff)

Driver symmetry

Driver symmetry VSYM Vo(dom)(sym)

Driver output current

Absolute current on CAN_H ICAN_H Io(SC)(CANH)

Absolute current on CAN_L ICAN_L Io(SC)(CANL)

Receiver output characteristics, bus biasing active

Single ended output voltage on CAN_H VCAN_H Vo(rec)(CANH)

Single ended output voltage on CAN_L VCAN_L Vo(rec)(CANL)

Differential output voltage VDiff Vo(rec)(diff)

Receiver output characteristics, bus biasing inactive

Single ended output voltage on CAN_H VCAN_H Vo(off)(CANH)

Single ended output voltage on CAN_L VCAN_L Vo(off)(CANL)

Differential output voltage VDiff Vo(off)(diff)

Optional transmit dominant timeout

Transmit dominant timeout, long tdom tdom(TxD)

Transmit dominant timeout, short tdom NA

Static receiver input characteristics, bus biasing active

Recessive state differential input voltage range VDiff Vi(rec)(diff)_NM

Dominant state differential input voltage range VDiff Vi(dom)(diff)_NM

Static receiver input characteristics, bus biasing inactive

Recessive state differential input voltage range VDiff Vi(rec)(diff)_LP

Dominant state differential input voltage range VDiff Vi(dom)(diff)_LP

Receiver input resistance

Differential internal resistance RDiff Ri(diff)

Single ended internal resistance RCAN_H

RCAN_L

Ri(cm)(CANH)

Ri(cm)(CANL)

Receiver input resistance matching

Matching a of internal resistance mRRi(cm)(m)

Implementation loop delay requirement

Loop delay tLoop tpd_rd

tpd_dr

Optional implementation data signal timing requirements for use with bit rates above 1 Mbit/s and up to 2 Mbit/s

Transmitted recessive bit width @ 2 Mbit/s tBit(Bus) tBit(Vi(diff))

Received recessive bit width @ 2 Mbit/s tBit(RXD) tBit(RxD)

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Table 6. ISO 11898−2:2016 Parameter Cross−Reference Table

Parameter SymbolNotation

Receiver timing symmetry @ 2 Mbit/s DtRec DtRec

Optional implementation data signal timing requirements for use with bit rates above 2 Mbit/s and up to 5 Mbit/s

Transmitted recessive bit width @ 5 Mbit/s tBit(Bus) tBit(Vi(diff))

Transmitted recessive bit width @ 5 Mbit/s tBit(RXD) tBit(RxD)

Received recessive bit width @ 5 Mbit/s DtRec DtRec

Maximum ratings of VCAN_H, VCAN_L and VDiff

Maximum rating VDiff VDiff VCANH−CANL

General maximum rating VCAN_H and VCAN_L VCAN_H

VCAN_L

VCANH

VCANL

Optional: Extended maximum rating VCAN_H and VCAN_L VCAN_H

VCAN_L

Maximum leakage currents on CAN_H and CAN_L, unpowered

Leakage current on CAN_H, CAN_L ICAN_H

ICAN_L

ILI

Bus biasing control timings

CAN activity filter time, long tFilter twake_filt

CAN activity filter time, short tFilter twake_filt

Wake−up timeout, short tWake NA

Wake−up timeout, long tWake twake_to

Timeout for bus inactivity (Required for selective wake−up implementation only) tSilence NA

Bus Bias reaction time (Required for selective wake−up implementation only) tBias NA

DEVICE ORDERING INFORMATION (High Speed Low Power CAN, CANFD Transceiver)

Part Number Long FT Short FT Vio NC

Temperature

Range Package Shipping†

NCV7344D10R2G X X

−40°C to +150°C

SOIC 150 8 GREEN (Matte

Sn, JEDEC MS−012)

(Pb−Free)

3000 / Tape &

Reel

NCV7344D13R2G X X

NCV7344AD10R2G X X

NCV7344AD13R2G X X

NCV7344MW0R2G X X

DFN 8

Wettable Flank

(Pb−Free)

NCV7344MW3R2G X X

NCV7344AMW0R2G X X

NCV7344AMW3R2G X X

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

NCV7344

www.onsemi.com

PACKAGE DIMENSIONS

SOIC−8

CASE 751AZ

ISSUE B

7.00

0.76

1.52

1.27

DIMENSIONS: MILLIMETERS

PITCH

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

RECOMMENDED

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.

ALLOWABLE PROTRUSION SHALL BE 0.004 mm IN EXCESS OF

MAXIMUM MATERIAL CONDITION.

4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS

OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS

SHALL NOT EXCEED 0.006 mm PER SIDE. DIMENSION E1 DOES

NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD

FLASH OR PROTRUSION SHALL NOT EXCEED 0.010 mm PER SIDE.

5. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOT

TOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTER

MOST EXTREMES OF THE PLASTIC BODY AT DATUM H.

6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM H.

7. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD

BETWEEN 0.10 TO 0.25 FROM THE LEAD TIP.

8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING

PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.

SEATING

PLANE

DETAIL A

0.10 C

DIM MIN MAX

MILLIMETERS

h0.25 0.41

A--- 1.75

b0.31 0.51

L0.40 1.27

e1.27 BSC

c0.10 0.25

A1 0.10 0.25

0.25 A-B

b8X

TOP VIEW

SIDE VIEW

0.25 BSC

E1 3.90 BSC

E6.00 BSC

0.20 C

0.10 C

NOTE 6

NOTES 4&5

SIDE VIEW

END VIEW

E E1

0.10 C D

NOTES 3&7

NOTE 6

NOTE 8

A2 1.25 ---

D4.90 BSC

SEATING

PLANE

DETAIL A

45 CHAMFER5

NOTE 7

NCV7344

www.onsemi.com

PACKAGE DIMENSIONS

DFNW8 3x3, 0.65P

CASE 507AB

ISSUE C

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.10 AND

0.20mm FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

5. THIS DEVICE CONTAINS WETTABLE FLANK

DESIGN FEATURES TO AID IN FILLET FORMA-

TION ON THE LEADS DURING MOUNTING.

ÉÉÉ

BOTTOM VIEW

0.10 B

0.05

CNOTE 3

PIN ONE

REFERENCE

TOP VIEW

0.05 C

CSEATING

PLANE

SIDE VIEW

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

RECOMMENDED

DETAIL B

DETAIL A

NOTE 4

e/2

SOLDERING FOOTPRINT*

DIM MIN NOM

MILLIMETERS

A0.80 0.85

A1 −−− −−−

b0.25 0.30

D2 2.30 2.40

E2 1.50 1.60

e0.65 BSC

L0.35 0.40

A3 0.20 REF

2.95 3.00

MAX

2.95 3.00

0.90

0.05

0.35

2.50

1.70

0.45

3.05

0.00 0.05 0.10

ALTERNATE

CONSTRUCTION

DETAIL A

SECTION C−C

PLATED

SURFACES

DETAIL B

PLATING

EXPOSED

COPPER

PACKAGE

OUTLINE

0.75

2.55

1.76

0.33

0.65

PITCH

3.30

DIMENSIONS: MILLIMETERS

2.28

0.30 REF

0.13 REF

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NCV7344/D

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