HCPL-7710-XXXE - Agilent / Hewlett-Packard - Datasheet.Live

Features

• +5 V CMOS compatibility

• 8 ns maximum pulse width

distortion

• 20 ns maximum prop. delay skew

• High speed: 12 Mbd

• 40 ns maximum prop. delay

• 10 kV/µs minimum common mode

rejection

• -40°C to 100°C temperature range

• Safety and regulatory approvals

UL Recognized

3750 V rms for 1 min. per

UL 1577

CSA Component Acceptance

Notice #5

IEC/EN/DIN EN 60747-5-2

–V

IORM = 630 Vpeak for

HCPL-7710 Option 060

–V

IORM = 560 Vpeak for

HCPL-0710 Option 060

Applications

• Digital fieldbus isolation:

DeviceNet, SDS, Profibus

• AC plasma display panel level

shifting

• Multiplexed data transmission

• Computer peripheral interface

• Microprocessor system interface

Description

Available in either an 8-pin DIP or

SO-8 package style respectively,

the HCPL-7710 or HCPL-0710

optocouplers utilize the latest

CMOS IC technology to achieve

outstanding performance with

very low power consumption. The

HCPL-x710 require only two

bypass capacitors for complete

CMOS compatibility.

Functional Diagram

Basic building blocks of the

HCPL-x710 are a CMOS LED

driver IC, a high speed LED and a

CMOS detector IC. A CMOS logic

input signal controls the LED

driver IC which supplies current

to the LED. The detector IC

incorporates an integrated

photodiode, a high-speed

transimpedance amplifier, and a

voltage comparator with an

output driver.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this

component to prevent damage and/or degradation which may be induced by ESD.

* Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet

performance. Pin 7 is not connected internally.

** A 0.1

µ

F bypass capacitor must be connected between pins 1 and 4, and 5 and 8.

8

7

6

1

3

SHIELD 5

2

4

**V

DD1

V

I

*

GND

1

V

DD2

**

V

O

GND

2

V

I

, INPUT LED1

H

LOFF

ON

TRUTH TABLE

(POSITIVE LOGIC)

NC*

I

O

LED1

V

O

, OUTPUT

H

L

Agilent HCPL-7710, HCPL-0710

40 ns Propagation Delay,

CMOS Optocoupler

Data Sheet

2

Package Outline Drawing

HCPL-7710 8-Pin DIP Package

9.65 ± 0.25

(0.380 ± 0.010)

1.78 (0.070) MAX.

1.19 (0.047) MAX.

A XXXXV

YYWW

DATE CODE

1.080 ± 0.320

(0.043 ± 0.013) 2.54 ± 0.25

(0.100 ± 0.010)

0.51 (0.020) MIN.

0.65 (0.025) MAX.

4.70 (0.185) MAX.

2.92 (0.115) MIN.

DIMENSIONS IN MILLIMETERS AND (INCHES).

5678

4321

5° TYP. 0.254 + 0.076

- 0.051

(0.010+ 0.003)

- 0.002)

7.62 ± 0.25

(0.300 ± 0.010)

6.35 ± 0.25

(0.250 ± 0.010)

TYPE NUMBER

*OPTION 300 AND 500 NOT MARKED.

NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.

OPTION 060 CODE*

3.56 ± 0.13

(0.140 ± 0.005)

Selection Guide

8-Pin DIP Small Outline

(300 Mil) SO-8

HCPL-7710 HCPL-0710

Ordering Information

Specify Part Number followed by Option Number (if desired)

Example

HCPL-7710#XXXX

060 = IEC/EN/DIN EN 60747-5-2 Option.

300 = Gull Wing Surface Mount Option (HCPL-7710 only).

500 = Tape and Reel Packaging Option.

XXXE = Lead Free Option

No Option and Option 300 contain 50 units (HCPL-7710), 100 units (HCPL-0710) per tube.

Option 500 contain 1000 units (HCPL-7710), 1500 units (HCPL-0710) per reel.

Option data sheets available. Contact Agilent sales representative or authorized distributor.

Remarks: The notation “#” is used for existing products, while (new) products launched since 15th July 2001 and lead free option will use “–”

3

Package Outline Drawing

HCPL-7710 Package with Gull Wing Surface Mount Option 300

Package Outline Drawing

HCPL-0710 Outline Drawing (Small Outline SO-8 Package)

0.635 ± 0.25

(0.025 ± 0.010) 12° NOM.

9.65 ± 0.25

(0.380 ± 0.010)

0.635 ± 0.130

(0.025 ± 0.005)

7.62 ± 0.25

(0.300 ± 0.010)

5

6

7

8

4

3

2

1

9.65 ± 0.25

(0.380 ± 0.010)

6.350 ± 0.25

(0.250 ± 0.010)

1.016 (0.040)

1.27 (0.050)

10.9 (0.430)

2.0 (0.080)

LAND PATTERN RECOMMENDATION

1.080 ± 0.320

(0.043 ± 0.013)

3.56 ± 0.13

(0.140 ± 0.005)

1.780

(0.070)

MAX.

1.19

(0.047)

MAX.

2.54

(0.100)

BSC

DIMENSIONS IN MILLIMETERS (INCHES).

LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.

0.254 + 0.076

- 0.051

(0.010+ 0.003)

- 0.002)

XXXV

YWW

8765

4321

5.994 ± 0.203

(0.236 ± 0.008)

3.937 ± 0.127

(0.155 ± 0.005)

0.406 ± 0.076

(0.016 ± 0.003) 1.270

(0.050)BSC

5.080 ± 0.127

(0.200 ± 0.005)

3.175 ± 0.127

(0.125 ± 0.005) 1.524

(0.060)

45° X 0.432

(0.017)

0.228 ± 0.025

(0.009 ± 0.001)

TYPE NUMBER

(LAST 3 DIGITS)

DATE CODE

0.305

(0.012)MIN.

TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)

5.207 ± 0.254 (0.205 ± 0.010)

DIMENSIONS IN MILLIMETERS (INCHES).

LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.

OPTION NUMBER 500 NOT MARKED.

NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.

0.203 ± 0.102

(0.008 ± 0.004)

7°

PIN ONE

0 ~ 7°

*

*

7.49 (0.295)

1.9 (0.075)

0.64 (0.025)

LAND PATTERN RECOMMENDATION

4

All Agilent data sheets report the

creepage and clearance inherent

to the optocoupler component

itself. These dimensions are

needed as a starting point for the

equipment designer when

determining the circuit insulation

requirements. However, once

mounted on a printed circuit

board, minimum creepage and

clearance requirements must be

met as specified for individual

equipment standards. For

creepage, the shortest distance

path along the surface of a

printed circuit board between the

solder fillets of the input and

output leads must be considered.

There are recommended

techniques such as grooves and

ribs which may be used on a

printed circuit board to achieve

desired creepage and clearances.

Creepage and clearance distances

will also change depending on

factors such as pollution degree

and insulation level.

Regulatory Information

The HCPL-x710 have been

approved by the following

organizations:

UL

Recognized under UL 1577,

component recognition program,

File E55361.

CSA

Approved under CSA Component

Acceptance Notice #5, File CA

88324.

IEC/EN/DIN EN 60747-5-2

Approved under:

IEC 60747-5-2:1997 + A1:2002

EN 60747-5-2:2001 + A1:2002

DIN EN 60747-5-2 (VDE 0884

Teil 2):2003-01.

(Option 060 only)

Recommended Pb-Free IR Profile

0

TIME (SECONDS)

TEMPERATURE (°C)

200

100

50 150100 200 250

300

0

30

SEC.

50 SEC.

30

SEC.

160°C

140°C

150°C

PEAK

TEMP.

245°C

PEAK

TEMP.

240°CPEAK

TEMP.

230°C

SOLDERING

TIME

200°C

PREHEATING TIME

150°C, 90 + 30 SEC.

2.5°C ± 0.5°C/SEC.

3°C + 1°C/–0.5°C

TIGHT

TYPICAL

LOOSE

ROOM

TEMPERATURE

PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.

REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.

Solder Reflow Thermal Profile

Insulation and Safety Related Specifications Value

Parameter Symbol 7710 0710 Units Conditions

Minimum External Air L(I01) 7.1 4.9 mm Measured from input terminals to output

Gap (Clearance) terminals, shortest distance through air.

Minimum External L(I02) 7.4 4.8 mm Measured from input terminals to output

Tracking (Creepage) terminals, shortest distance path along

body.

Minimum Internal Plastic 0.08 0.08 mm Insulation thickness between emitter and

Gap (Internal Clearance) detector; also known as distance through

insulation.

Tracking Resistance CTI ≥175 ≥175 Volts DIN IEC 112/VDE 0303 Part 1

(Comparative Tracking

Index)

Isolation Group IIIa IIIa Material Group (DIN VDE 0110, 1/89,

Table 1)

217 °C

RAMP-DOWN

6 °C/SEC. MAX.

RAMP-UP

3 °C/SEC. MAX.

150 - 200 °C

260 +0/-5 °C

t 25 °C to PEAK

60 to 150 SEC.

20-40 SEC.

TIME WITHIN 5 °C of ACTU AL

PEAK TEMPERA TURE

tp

ts

PREHEAT

60 to 180 SEC.

tL

TL

Tsmax

Tsmin

25

Tp

TIME

TEMPERATURE

NOTES:

THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.

Tsmax = 200 °C, Tsmin = 150 °C

5

IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060) HCPL-7710 HCPL-0710

Description Symbol Option 060 Option 060 Units

Installation classification per DIN VDE 0110/1.89, Table 1

for rated mains voltage ≤150 V rms I-IV I-IV

for rated mains voltage ≤300 V rms I-IV I-III

for rated mains voltage ≤450 V rms I-III

Climatic Classification 55/100/21 55/100/21

Pollution Degree (DIN VDE 0110/1.89) 2 2

Maximum Working Insulation Voltage VIORM 630 560 V peak

Input to Output Test Voltage, Method b† VPR 1181 1050 V peak

VIORM x 1.875 = VPR, 100% Production

Test with tm = 1 sec, Partial Discharge < 5 pC

Input to Output Test Voltage, Method a† VPR 945 840 V peak

VIORM x 1.5 = VPR, Type and Sample Test,

tm = 60 sec, Partial Discharge < 5 pC

Highest Allowable Overvoltage† VIOTM 6000 4000 V peak

(Transient Overvoltage, tini = 10 sec)

Safety Limiting Values

(Maximum values allowed in the event of a failure,

also see Thermal Derating curve, Figure 11.)

Case Temperature TS175 150 °C

Input Current IS,INPUT 230 150 mA

Output Power PS,OUTPUT 600 600 mW

Insulation Resistance at TS, V10 = 500 V RIO ≥109≥109Ω

†Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations section

IEC/EN/DIN EN 60747-5-2, for a detailed description.

Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured

by means of protective circuits.

Note: The surface mount classification is Class A in accordance with CECC 00802.

Absolute Maximum Ratings

Parameter Symbol Min. Max. Units Figure

Storage Temperature TS–55 125 °C

Ambient Operating Temperature TA–40 +100 °C

Supply Voltages VDD1, VDD2 0 6.0 Volts

Input Voltage VI–0.5 VDD1 +0.5 Volts

Output Voltage VO–0.5 VDD2 +0.5 Volts

Input Current II–10 +10 mA

Average Output Current IO10 mA

Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane

Solder Reflow Temperature Profile See Solder Reflow Temperature Profile Section

Recommended Operating Conditions

Parameter Symbol Min. Max. Units Figure

Ambient Operating Temperature TA–40 +100 °C

Supply Voltages VDD1, VDD2 4.5 5.5 V

Logic High Input Voltage VIH 2.0 VDD1 V 1, 2

Logic Low Input Voltage VIL 0.0 0.8 V

Input Signal Rise and Fall Times tr, tf1.0 ms

6

Electrical Specifications

Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications

are at TA = +25°C, VDD1 = VDD2 = +5 V.

Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note

DC Specifications

Logic Low Input IDD1L 6.0 10.0 mA VI = 0 V 1

Supply Current

Logic High Input IDD1H 1.5 3.0 mA VI = V DDI

Supply Current

Input Supply Current IDD1 13.0 mA

Output Supply Current IDD2 5.5 11.0 mA

Input Current II-10 10 µA

Logic High Output VOH 4.4 5.0 V IO = -20 µA, V I = VIH 1, 2

Voltage 4.0 4.8 IO = -4 mA, VI = VIH

Logic Low Output VOL 0 0.1 V IO = 20 µA, VI = VIL

Voltage 0.5 1.0 IO = 4 mA, VI = VIL

Switching Specifications

Propagation Delay Time tPHL 20 40 ns CL = 15 pF 3, 7 2

to Logic Low Output CMOS Signal Levels

Propagation Delay Time tPLH 23 40

to Logic High Output

Pulse Width PW 80 3

Data Rate 12.5 MBd

Pulse Width Distortion PWD 3 8 ns 4, 8 4

|tPHL - tPLH|

Propagation Delay Skew tPSK 20 5

Output Rise Time tR9 5, 9

(10 - 90%)

Output Fall Time tF86,

(90 - 10%) 10

Common Mode |CMH| 10 20 kV/µsV

I = VDD1, VO >6

Transient Immunity at 0.8 VDD1,

Logic High Output VCM = 1000 V

Common Mode |CML|10 20 V

I = 0 V, VO > 0.8 V,

Transient Immunity at VCM = 1000 V

Logic Low Output

Input Dynamic Power CPD1 60 pF 7

Dissipation

Capacitance

Output Dynamic Power CPD2 10

Dissipation

Capacitance

7

Notes:

1. The LED is ON when VI is low and OFF

when VI is high.

2. tPHL propagation delay is measured from

the 50% level on the falling edge of the VI

signal to the 50% level of the falling edge

of the VO signal. tPLH propagation delay is

measured from the 50% level on the rising

edge of the VI signal to the 50% level of the

rising edge of the VO signal.

3. Mimimum Pulse Width is the shortest

pulse width at which 10% maximum, Pulse

Width Distortion can be guaranteed.

Maximum Data Rate is the inverse of

Minimum Pulse Width. Operating the

HCPL-x710 at data rates above 12.5 MBd is

possible provided PWD and data

dependent jitter increases and relaxed

noise margins are tolerable within the

application. For instance, if the maximum

allowable variation of bit width is 30%, the

maximum data rate becomes 37.5 MBd.

Please note that HCPL-x710 performances

above 12.5 MBd are not guaranteed by

Hewlett-Packard.

4. PWD is defined as |tPHL - tPLH|.

%PWD (percent pulse width distortion) is

equal to the PWD divided by pulse width.

5. tPSK is equal to the magnitude of the worst

case difference in tPHL and/or tPLH that will

be seen between units at any given

temperature within the recommended

operating conditions.

6. CMH is the maximum common mode

voltage slew rate that can be sustained

while maintaining VO > 0.8 VDD2. CML is the

maximum common mode voltage slew rate

that can be sustained while maintaining VO

< 0.8 V. The common mode voltage slew

rates apply to both rising and falling

common mode voltage edges.

7. Unloaded dynamic power dissipation is

calculated as follows: CPD * VDD2 * f + IDD *

VDD, where f is switching frequency in

MHz.

8. Device considered a two-terminal device:

pins 1, 2, 3, and 4 shorted together and

pins 5, 6, 7, and 8 shorted together.

9. In accordance with UL1577, each HCPL-

0710 is proof tested by applying an

insulation test voltage ≥4500 VRMS for 1

second (leakage detection current limit, II-O

≤5 µA). Each HCPL-7710 is proof tested by

applying an insulation test voltage ≥ 4500 V

rms for 1 second (leakage detection current

limit, II-O ≤ 5 µA).

10. The Input-Output Momentary Withstand

Voltage is a dielectric voltage rating that

should not be interpreted as an input-output

continuous voltage rating. For the

continuous voltage rating refer to your

equipment level safety specification or

Agilent Application Note 1074 entitled

“Optocoupler Input-Output Endurance

Voltage.”

11. CI is the capacitance measured at pin 2 (VI).

V

O

(V)

0

0

V

I

(V)

5

4

1

4123

5

3

2

0 °C

25 °C

85 °C

VITH (V)

4.5

1.6

VDD1 (V)

5.5

2.1

1.7

5.254.75 5

2.2

2.0

1.8

1.9

0 °C

25 °C

85 °C

TPLH, TPHL (ns)

0

15

TA (C)

80

27

17

6020 30

29

25

19

21

10 40 50 70

23 TPLH

TPHL

Package Characteristics

Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note

Input-Output Momentary 0710 VISO 3750 Vrms RH ≤ 50%, 8, 9,

Withstand Voltage 7710 3750 t = 1 min., 10

TA = 25°C

Resistance RI-O 1012 ΩVI-O = 500 Vdc 8

(Input-Output)

Capacitance CI-O 0.6 pF f = 1 MHz

(Input-Output)

Input Capacitance CI3.0 11

Input IC Junction-to-Case -7710 θjci 145 °C/W Thermocouple

Thermal Resistance -0710 160 located at center

Output IC Junction-to-Case -7710 θjco 140 underside of package

Thermal Resistance -0710 135

Package Power Dissipation PPD 150 mW

Figure 1. Typical output voltage vs. input

voltage. Figure 2. Typical input voltage switching

threshold vs. input supply voltage. Figure 3. Typical propagation delays vs.

temperature.

8

Figure 11. Thermal derating curve, dependence of Safety Limiting Value with case temperature

per IEC/EN/DIN EN 60747-5-2 .

PWD

(ns)

0

0

T

A

(C)

80

3

6020

4

1

40

2

T

R

(ns)

0

8

T

A

(C)

80

10

6020

11

9

40

T

F

(ns)

0

2

T

A

(C)

80

6

6020

7

3

40

5

4

TR (ns)

0

1

CI (pF)

35

19

25

21

5

15

11

1052030

7

15

17

13

9

3

FALL TIME (ns)

0

0

CI (pF)

35

9

25

10

2

15

5

1052030

3

7

8

6

4

1

OUTPUT POWER – P

S

, INPUT CURRENT – I

S

0

0

T

A

– CASE TEMPERATURE – °C

20050

400

12525 75 100 150

600

800

200

100

300

500

700

175

(230)

P

S

(mW)

I

S

(mA)

STANDARD 8 PIN DIP PRODUCT

OUTPUT POWER – P

S

, INPUT CURRENT – I

S

0

0

T

A

– CASE TEMPERATURE – °C

20050

400

12525 75 100 150

600

800

200

100

300

500

700

175

(150)

P

S

(mW)

I

S

(mA)

SURFACE MOUNT SO8 PRODUCT

T

PLH

, T

PHL

(ns)

15

15

C

I

(pF)

50

27

40

29

17

30

23

21

2520 35 45

19

25

T

PLH

T

PHL

PWD

(ns)

15

0

C

I

(pF)

50

5

40

6

1

30

3

2520 35 45

2

4

Figure 4. Typical pulse width distortion vs.

temperature. Figure 5. Typical rise time vs. temperature. Figure 6. Typical fall time vs. temperature.

Figure 7. Typical propagation delays vs.

output load capacitance. Figure 8. Typical pulse width distortion vs.

output load capacitance. Figure 9. Typical rise time vs. load

capacitance.

Figure 10. Typical fall time vs. load

capacitance.

9

Application Information

Bypassing and PC Board Layout

The HCPL-x710 optocouplers are

extremely easy to use. No external

interface circuitry is required

because the HCPL-x710 use high-

speed CMOS IC technology

allowing CMOS logic to be

connected directly to the inputs

and outputs.

As shown in Figure 12, the only

external components required for

proper operation are two bypass

capacitors. Capacitor values

should be between 0.01 µF and

0.1 µF. For each capacitor, the

total lead length between both

ends of the capacitor and the

power-supply pins should not

exceed 20 mm. Figure 13

illustrates the recommended

printed circuit board layout for

the HPCL-x710.

Figure 12. Recommended Printed Circuit Board layout.

Figure 13. Recommended Printed Circuit Board layout.

V

DD2

C1 C2

710

YWW

V

O

GND2

V

DD1

V

I

GND1

C1, C2 = 0.01 µF TO 0.1 µF

7

5

6

8

2

3

4

1

GND

2

C1 C2

NC

V

DD2

NC V

O

V

DD1

V

I

710

YWW

C1, C2 = 0.01 µF TO 0.1 µF

GND

1

Propagation Delay, Pulse-Width

Distortion and Propagation Delay

Skew

Propagation Delay is a figure of

merit which describes how

quickly a logic signal propagates

through a system. The propaga-

tion delay from low to high (tPLH)

is the amount of time required for

an input signal to propagate to the

output, causing the output to

change from low to high.

Similarly, the propagation delay

from high to low (tPHL) is the

amount of time required for the

input signal to propagate to the

output, causing the output to

change from high to low. See

Figure 14.

Figure 14.

INPUT

t

PLH

t

PHL

OUTPUT

V

I

V

O

10% 90%90% 10%

V

OH

V

OL

0 V

50% 5 V CMOS

2.5 V CMOS

10

Figure 15. Propagation delay skew waveform. Figure 16. Parallel data transmission example.

Propagation delay skew repre-

sents the uncertainty of where an

edge might be after being sent

through an optocoupler. Figure 16

shows that there will be

uncertainty in both the data and

clock lines. It is important that

these two areas of uncertainty not

overlap, otherwise the clock

signal might arrive before all of

the data outputs have settled, or

some of the data outputs may

start to change before the clock

signal has arrived. From these

considerations, the absolute

minimum pulse width that can be

sent through optocouplers in a

parallel application is twice tPSK.

A cautious design should use a

slightly longer pulse width to

ensure that any additional

uncertainty in the rest of the

circuit does not cause a problem.

The HCPL-x710 optocouplers

offer the advantage of guaranteed

specifications for propagation

delays, pulse-width distortion,

and propagation delay skew over

the recommended temperature

and power supply ranges.

Pulse-width distortion (PWD) is

the difference between tPHL and

tPLH and often determines the

maximum data rate capability of a

transmission system. PWD can be

expressed in percent by dividing

the PWD (in ns) by the minimum

pulse width (in ns) being trans-

mitted. Typically, PWD on the

order of 20 - 30% of the minimum

pulse width is tolerable. The PWD

specification for the HCPL-x710 is

8 ns (10%) maximum across

recommended operating condi-

tions. 10% maximum is dictated

by the most stringent of the three

fieldbus standards, PROFIBUS.

Propagation delay skew, tPSK, is

an important parameter to con-

sider in parallel data applications

where synchronization of signals

on parallel data lines is a concern.

If the parallel data is being sent

through a group of optocouplers,

differences in propagation delays

will cause the data to arrive at the

outputs of the optocouplers at

different times. If this difference

in propagation delay is large

enough it will determine the

maximum rate at which parallel

data can be sent through the

optocouplers.

Propagation delay skew is defined

as the difference between the

minimum and maximum propa-

gation delays, either tPLH or tPHL,

for any given group of optocoup-

lers which are operating under

the same conditions (i.e., the same

drive current, supply voltage,

output load, and operating

temperature). As illustrated in

Figure 15, if the inputs of a group

of optocouplers are switched

either ON or OFF at the same

time, tPSK is the difference

between the shortest propagation

delay, either tPLH or tPHL, and the

longest propagation delay, either

tPLH or tPHL.

As mentioned earlier, tPSK can

determine the maximum parallel

data transmission rate. Figure 16

is the timing diagram of a typical

parallel data application with

both the clock and data lines

being sent through the

optocouplers. The figure shows

data and clock signals at the

inputs and outputs of the

optocouplers. In this case the data

is assumed to be clocked off of the

rising edge of the clock.

50%

50%

tPSK

VI

VO

VI

VO

2.5 V,

CMOS

2.5 V,

CMOS

DATA

INPUTS

CLOCK

DATA

OUTPUTS

CLOCK

tPSK

tPSK

11

Optical Isolation for Field Bus

Networks

To recognize the full benefits of

these networks, each recommends

providing galvanic isolation using

Agilent optocouplers. Since

network communication is bi-

directional (involving receiving

data from and transmitting data

onto the network), two Agilent

optocouplers are needed. By

providing galvanic isolation, data

integrity is retained via noise

reduction and the elimination of

false signals. In addition, the

Figure 17. Typical field bus communication physical model.

network receives maximum

protection from power system

faults and ground loops.

Within an isolated node, such as

the DeviceNet Node shown in

Figure 18, some of the node’s

components are referenced to a

ground other than V- of the

network. These components could

include such things as devices

with serial ports, parallel ports,

RS232 and RS485 type ports. As

shown in Figure 18, power from

the network is used only for the

transceiver and input (network)

side of the optocouplers.

Isolation of nodes connected to

any of the three types of digital

field bus networks is best

achieved by using the HCPL-x710

optocouplers. For each network,

the HCPL-x710 satisify the critical

propagation delay and pulse

width distortion requirements

over the temperature range of 0°C

to +85°C, and power supply

voltage range of 4.5 V to 5.5 V.

Digital Field Bus Communication

Networks

To date, despite its many draw-

backs, the 4 - 20 mA analog

current loop has been the most

widely accepted standard for

implementing process control

systems. In today’s manufacturing

environment, however, automated

systems are expected to help

manage the process, not merely

monitor it. With the advent of

digital field bus communication

networks such as DeviceNet,

PROFIBUS, and Smart

Distributed Systems (SDS), gone

are the days of constrained

information. Controllers can now

receive multiple readings from

field devices (sensors, actuators,

etc.) in addition to diagnostic

information.

The physical model for each of

these digital field bus communica-

tion networks is very similar as

shown in Figure 17. Each includes

one or more buses, an interface

unit, optical isolation, transceiver,

and sensing and/or actuating

devices.

CONTROLLER

TRANSCEIVER

OPTICAL

ISOLATION

BUS

INTERFACE

TRANSCEIVER

OPTICAL

ISOLATION

BUS

INTERFACE

TRANSCEIVER

OPTICAL

ISOLATION

BUS

INTERFACE

TRANSCEIVER

OPTICAL

ISOLATION

BUS

INTERFACE

TRANSCEIVER

OPTICAL

ISOLATION

BUS

INTERFACE

FIELD BUS

XXXXXX

YYY

SENSOR

DEVICE

CONFIGURATION

MOTOR

STARTER

MOTOR

CONTROLLER

12

Implementing DeviceNet and SDS

with the HCPL-x710

With transmission rates up to 1

Mbit/s, both DeviceNet and SDS

are based upon the same

broadcast-oriented, communica-

tions protocol — the Controller

Area Network (CAN). Three types

of isolated nodes are

recommended for use on these

networks: Isolated Node Powered

by the Network (Figure 19),

Figure 18. Typical DeviceNet node.

Isolated Node with Transceiver

Powered by the Network (Figure

20), and Isolated Node Providing

Power to the Network (Figure 21).

Isolated Node Powered by the

Network

This type of node is very flexible

and as can be seen in Figure 19, is

regarded as “isolated” because not

all of its components have the

same ground reference. Yet, all

Figure 19. Isolated node powered by the network.

components are still powered by

the network. This node contains

two regulators: one is isolated and

powers the CAN controller, node-

specific application and isolated

(node) side of the two optocoup-

lers while the other is non-

isolated. The non-isolated

regulator supplies the transceiver

and the non-isolated (network)

half of the two optocouplers.

NODE/APP SPECIFIC

uP/CAN

HCPL

x710 HCPL

x710

TRANSCEIVER

LOCAL

NODE

SUPPLY

5 V REG.

NETWORK

POWER

SUPPLY

V+ (SIGNAL)

V– (SIGNAL)

V+ (POWER)

V– (POWER)

GALVANIC

ISOLATION

BOUNDARY

AC LINE

DRAIN/SHIELD

SIGNAL

POWER

NODE/APP SPECIFIC

uP/CAN

HCPL

x710 HCPL

x710

TRANSCEIVER REG.

V+ (SIGNAL)

V– (SIGNAL)

V+ (POWER)

V– (POWER)

GALVANIC

ISOLATION

BOUNDARY

DRAIN/SHIELD

SIGNAL

POWER

ISOLATED

SWITCHING

POWER

SUPPLY

NETWORK

POWER

SUPPLY

13

Figure 20. Isolated node with transceiver powered by the network.

Isolated Node with Transceiver

Powered by the Network

Figure 20 shows a node powered

by both the network and another

source. In this case, the trans-

ceiver and isolated (network) side

of the two optocouplers are

powered by the network. The rest

of the node is powered by the AC

line which is very beneficial when

an application requires a

significant amount of power. This

method is also desirable as it does

not heavily load the network.

More importantly, the unique

“dual-inverting” design of the

HCPL-x710 ensure the network

will not “lock-up” if either AC line

power to the node is lost or the

node powered-off. Specifically,

when input power (VDD1) to the

HCPL-x710 located in the

transmit path is eliminated, a

RECESSIVE bus state is ensured

as the HCPL-x710 output voltage

(V

O) go HIGH.

*Bus V+ Sensing

It is suggested that the Bus V+

sense block shown in Figure 20 be

implemented. A locally powered

node with an un-powered isolated

Physical Layer will accumulate

errors and become bus-off if it

attempts to transmit. The Bus V+

sense signal would be used to

change the BOI attribute of the

DeviceNet Object to the “auto-

reset” (01) value. Refer to Volume

1, Section 5.5.3. This would cause

the node to continually reset until

bus power was detected. Once

power was detected, the BOI

attribute would be returned to the

“hold in bus-off” (00) value. The

BOI attribute should not be left in

the “auto-reset” (01) value since

this defeats the jabber protection

capability of the CAN error

confinement. Any inexpensive

low frequency optical isolator can

be used to implement this feature.

NODE/APP SPECIFIC

uP/CAN

HCPL

x710 HCPL

x710

TRANSCEIVER

NON ISO

5 V

REG.

NETWORK

POWER

SUPPLY

V+ (SIGNAL)

V– (SIGNAL)

V+ (POWER)

V– (POWER)

GALVANIC

ISOLATION

BOUNDARY

AC LINE

DRAIN/SHIELD

SIGNAL

POWER

*HCPL

x710

* OPTIONAL FOR BUS V + SENSE

14

Figure 21. Isolated node providing power to the network.

Isolated Node Providing Power to

the Network

Figure 21 shows a node providing

power to the network. The AC line

powers a regulator which

provides five (5) volts locally. The

AC line also powers a 24 volt

isolated supply, which powers the

network, and another five-volt

regulator, which, in turn, powers

the transceiver and isolated

(network) side of the two

optocouplers. This method is

recommended when there are a

limited number of devices on the

network that don’t require much

power, thus eliminating the need

for separate power supplies.

More importantly, the unique

“dual-inverting” design of the

HCPL-x710 ensure the network

will not “lock-up” if either AC line

power to the node is lost or the

node powered-off. Specifically,

when input power (VDD1) to the

HCPL-x710 located in the

transmit path is eliminated, a

RECESSIVE bus state is ensured

as the HCPL-x710 output voltage

(VO) go HIGH.

NODE/APP SPECIFIC

uP/CAN

HCPL

x710 HCPL

x710

TRANSCEIVER 5 V REG.

V+ (SIGNAL)

V– (SIGNAL)

V+ (POWER)

V– (POWER)

GALVANIC

ISOLATION

BOUNDARY

AC LINE

DRAIN/SHIELD

SIGNAL

POWER

ISOLATED

SWITCHING

POWER

SUPPLY

5 V REG.

DEVICENET NODE

15

Power Supplies and Bypassing

The recommended DeviceNet

application circuit is shown in

Figure 22. Since the HCPL-x710

are fully compatible with CMOS

logic level signals, the optocoupler

is connected directly to the CAN

Figure 22. Recommended DeviceNet application circuit.

Implementing PROFIBUS with the

HCPL-x710

An acronym for Process Fieldbus,

PROFIBUS is essentially a

twisted-pair serial link very

similar to RS-485 capable of

achieving high-speed communi-

cation up to 12 MBd. As shown in

Figure 23, a PROFIBUS Controller

(PBC) establishes the connection

of a field automation unit (control

or central processing station) or a

field device to the transmission

medium. The PBC consists of the

line transceiver, optical isolation,

frame character transmitter/

receiver (UART), and the FDL/

APP processor with the interface

to the PROFIBUS user.

transceiver. Two bypass

capacitors (with values between

0.01 and 0.1 µF) are required and

should be located as close as

possible to the input and output

power-supply pins of the HCPL-

x710. For each capacitor, the total

Figure 23. PROFIBUS Controller (PBC).

PROFIBUS USER:

CONTROL STATION

(CENTRAL PROCESSING)

OR FIELD DEVICE

USER INTERFACE

FDL/APP

PROCESSOR

TRANSCEIVER

OPTICAL ISOLATION

UART

PBC

MEDIUM

lead length between both ends of

the capacitor and the power

supply pins should not exceed 20

mm. The bypass capacitors are

required because of the high-

speed digital nature of the signals

inside the optocoupler.

8

7

6

1

3

5

2

4

VDD1

VIN

GND1

VDD2

VO

GND2

HCPL-x710

4

3

2

5

7

1

6

8

GND2

VO

VDD2

GND1

VIN

VDD1

HCPL-x710

GND

ISO 5 V

ISO 5 V

0.01 µF

RX0

0.01 µF

TX0 0.01

µF

0.01

µF

TxD CANH

REF

RXD

82C250

VCC

GND

Rs

CANL

C4

0.01 µF

+

VREF

LINEAR OR

SWITCHING

REGULATOR

5 V

5 V

++

R1

1 M

C1

0.01 µF

500 V

D1

30 V

5 V+

4 CAN+

3 SHIELD

2 CAN–

1 V–

GALVANIC

ISOLATION

BOUNDARY

Figure 24. Recommended PROFIBUS application circuit.

1

2

3

8

6

4

7

5

V

DD2

V

O

GND

2

V

DD1

V

IN

GND

1

HCPL-x710

8

7

6

1

3

5

2

4

V

DD1

V

IN

GND

1

V

DD2

V

O

GND

2

HCPL-x710

5 V

0.01 µF

0.01 µF

0.01

µF

0.01

µF

RA

SN75176B

V

CC

GND

DE

B

0.01

µF

ISO 5 V

1 M

0.01 µF

+

–

GALVANIC

ISOLATION

BOUNDARY

5 V ISO 5 V

RE

D

1

4

3

2

Rx

ISO 5 V

Tx

8

7

6

1

3

5

2

4

ANODE

V

CC

V

O

GND

5 V

0.01

µF

ISO 5 V

Tx ENABLE CATHODE

V

E

680 Ω

HCPL-061N

1, 0 kΩ

5

7

6

8

RT SHIELD

Power Supplies and Bypassing

The recommended PROFIBUS

application circuit is shown in

Figure 24. Since the HCPL-x710

are fully compatible with CMOS

logic level signals, the

optocoupler is connected directly

to the transceiver. Two bypass

capacitors (with values between

0.01 and 0.1 µF) are required and

should be located as close as

possible to the input and output

power-supply pins of the

HCPL-x710. For each capacitor,

the total lead length between both

ends of the capacitor and the

power supply pins should not

exceed 20 mm. The bypass

capacitors are required because of

the high-speed digital nature of

the signals inside the optocoupler.

Being very similar to multi-station

RS485 systems, the HCPL-061N

optocoupler provides a transmit

disable function which is

necessary to make the bus free

after each master/slave

transmission cycle. Specifically,

the HCPL-061N disables the

transmitter of the line driver by

putting it into a high state mode.

In addition, the HCPL-061N

switches the RX/TX driver IC into

the listen mode. The HCPL-061N

offers HCMOS compatibility and

the high CMR performance

(1 kV/µs at VCM = 1000 V)

essential in industrial

communication interfaces.

16

www.agilent.com/semiconductors

For product information and a complete list of

distributors, please go to our web site.

For technical assistance call:

Americas/Canada: +1 (800) 235-0312 or

(916) 788-6763

Europe: +49 (0) 6441 92460

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Hong Kong: (+65) 6756 2394

India, Australia, New Zealand: (+65) 6755 1939

Japan: (+81 3) 3335-8152 (Domestic/Interna-

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Singapore, Malaysia, Vietnam, Thailand,

Philippines, Indonesia: (+65) 6755 2044

Taiwan: (+65) 6755 1843

Data subject to change.

Copyright © 2005 Agilent Technologies, Inc.

Obsoletes 5989-0789EN

February 28, 2005

5989-2134EN