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FEATURES
Integrated NV SRAM, real time clock, crystal,
power-fail control circuit and lithium energy
source
Clock registers are accessed identically to the
static RAM; these registers are resident in the
16 top RAM locations
Century byte register; i.e., Y2K complaint
Totally nonvolatile with over 10 years of
operation in the absence of power
Precision power-on reset
Programmable watchdog timer and RTC alarm
BCD coded year, month, date, day, hours,
minutes, and seconds with automatic leap year
compensation valid up to the year 2100
Battery voltage level indicator flag
Power-fail write protection allows for ±10%
VCC power supply tolerance
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
PIN ASSIGNMENT
DS1554
256K NV Y2KC Timekeeping RAM
PRELIMINARY
www.dalsemi.com
1
IRQ/FT 2
3
NC
NC
RST
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NC
A
14
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
34 NC
X1 GND VBAT X2
34-Pin POWE RCAP MODULE BOARD
(USES DS9034PCX POWERCAP)
RST
13
1
2
3
4
5
6
7
8
9
10
11
12
14
31
A14
A7
A5
A4
A3
A2
A1
A0
DQ1
DQ0
VCC
NC
IRQ/FT
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
DQ7
DQ5
DQ6
32
30
29
28
27
26
25
24
23
22
21
19
20
A16
A12
A6
DQ2
GND
15
16
18
17 DQ4
DQ3
32-PIN ENCAPSULATED PACKAGE
DS1554
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ORDERING INFORMATION
DS1554P-XXX (5-Volt)
-70 70 ns access
-100 100 ns access
blank 32-pin DIP Module
P 34-pin PowerCap Module
board*
*DS1554WP-XXX (3.3 Volt)
-120 120 ns access
-150 150 ns access
blank 32-pin DIP Module
P 34-pin PowerCap Module
board*
*DS9034PCX (PowerCap) Required:
must be ordered seperately
PIN DESCRIPTION
A0-A14 - Address Input
DQ0-DQ7 - Data Input/Outputs
IRQ \FT - Interrupt, Frequency Test Output
(Open Drain)
RST - Power-On Reset Output
(Open Drain)
CE - Chip Enable
OE - Output Enable
WE - Write Enable
VCC - Power Supply Input
GND - Ground
NC - No Connection
X1, X2 - Crystal Connection
VBAT - Battery Connection
DESCRIPTION
The DS1554 is a full function, year 2000-compliant (Y2KC), real-time clock/c alendar (RTC) with a RTC
alarm, watchdog timer, power-on reset, battery monitor, and 32k x 8 non-volatile static RAM. User
access to all registers within the DS1554 is accomplished with a b ytewide interface as shown in Figure 1.
The RTC Registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour
BCD format. Corrections for day of month and leap year are made automatically.
The RTC Registers are double-buffered into an internal and external set. The user has dire ct access to the
external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow
the user to access static data. Assuming the internal oscillator is turned on, the internal set of re gisters are
continuously updated; this occurs regardless of external registers settings to guarantee that accurate RTC
information is always maintained.
DS1554
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The DS1554 has interrupt (IRQ /FT) and reset (RST ) outputs which can be used to control CPU activity.
The IRQ /FT interrupt output can be used to generate an external interrupt when the RTC Re gister values
match user programmed alarm values. The interrupt is always available while the device is powered from
the system supply and can be pro grammed to occur when in the batter y backed state to serv e as a system
wake-up. Either the IRQ /FT or RST outputs can also be used as a CPU watchdog timer, CPU activity is
monitored and an interrupt or reset output will be activated if the correct activity is not detected within
programmed limits. The DS1554 power-on reset can be used to detect a system power down or failure
and hold the CPU in a safe reset state until normal power returns and stabilizes; the RST output is used
for this function.
The DS1554 also contains its own power-fail circuitr y which automatically deselects the device when the
VCC supply enters an out of tolerance condition. This feature provides a high degree of data security
during unpredictable system operation brought on by low VCC levels.
PACKAGES
The DS1554 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap module board is designed with contacts fo r connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1554P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the cr ystal and batter y due to the hi gh tempe ratur es required for solde r
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module board and Pow erCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
DS1554 BLOCK DIAGRAM Figure 1
DS1554
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DS1554 OPERATING MODES Table 1
VCC CE OE WE DQ0-DQ7 MODE POWER
VIH X X HIGH-Z DESELECT STANDBY
VIL XV
IL DIN WRITE ACTIVE
VIL VIL VIH DOUT READ ACTIVE
VCC > VPF
VIL VIH VIH HIGH-Z READ ACTIVE
VSO < VCC <VPF X X X HIGH-Z DESELECT CMOS STANDBY
<VBAT X X X HIGH-Z DATA
RETENTION BATTERY
CURRENT
DATA READ MODE
The DS1554 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data will be available
at the DQ pins within tAA after the last address input is stable, providing that CE and OE access times are
satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable
access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is
controlled by CE and OE . If the outputs are activated before tAA, the data lines are driven to an
intermediate state until tAA. If the address inputs are chan ged while CE and OE remain valid, output data
will remain valid for output data hold time (tOH ) but will then go indeterminate until the next address
access.
DATA WRITE MODE
The DS1554 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent
read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH
afterward. In a t ypical application, the OE signal will be high during a write c ycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
The 5-volt device is fully accessible and data can be written and read only when VCC is greater than VPF.
However, when VCC is below the power-fail point VPF (point at which write protection occurs) the
internal clock r e gisters and SR AM ar e blocked from any access. W hen VCC falls below the battery switch
point VSO (battery supply level), device power is switched from the VCC pin to the internal backup lithium
battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal
levels.
The 3.3-volt device is fully accessible and data can be written and read only when VCC is greater than
VPF. When VCC falls below VPF, access to the device is inhibited. If VPF is less than VBAT, the device
power is switched from VCC to the internal backup lithium battery when VCC drops below VPF. If VPF is
greater than VBAT, the device power is switched from VCC to the internal backup lithium battery when
VCC drops below VBAT. RTC operation and SRAM data are maintained from the battery until VCC is
returned to nominal levels.
All control, data, and address signals must be powered down when VCC is powered down.
DS1554
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BATTERY LONGEVITY
The DS1554 has a lithium power source that is designed to provide energy for the clock activity, and
clock and RAM data retention when the VCC supply is not present. The capability of this internal power
supply is sufficient to power the DS1554 continuously for the life of the equipment in which it is
installed. For specification purposes, the life expectancy is 10 years at 25°C with the internal clock
oscillator running in the absence of VCC. Each DS1554 is shipped from Dallas Semiconductor with its
lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a
level greater than VPF, the lithium energy source is enabled for battery backup operation. Actual life
expectancy of the DS1554 will be much longer than 10 years since no internal battery energy is
consumed when VCC is present.
INTERN AL BATTERY MONITOR
The DS15543 constantly monitors the batter y voltage of the internal b atter. The Batter y Low Flag (BLF )
bit of the Fla gs Register (B4 of 7 F FF0h) is not writable and should alw a ys be a 0 when read. If a 1 is ev er
present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are
questionable.
POWER-ON RESET
A temperature compensated comparator circuit monitors the level of VCC. When VCC falls to the power
fail trip point, the RST signal (open drain) is pulled low. When VCC returns to nominal levels, the
RST signal continues to be pulled low for a period of 40 ms to 200 ms. The power-on reset function is
independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.
CLOCK OPERATIONS
Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions.
DS1554
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DS1554 REGISTER MAP Table 2
DATA
ADDRESS B7B6B5B4B3B2B1B0FUNCTION/RANGE
7FFFh 10 Year YEAR YEAR 00-99
7FFEh X X X 10 M MONTH MONTH 01-12
7FFDh X X 10 Date DATE DATE 01-31
7FFCh X FT X X X DAY DAY 01-07
7FFBh X X 10 HOUR HOUR HOUR 00-23
7FFAh X 10 MINUTES MINUTES MINUTES 00-59
7FF9h OSC 10 SECONDS SECONDS SECONDS 00-59
7FF8h W R 10 CENTURY CENTURY CONTROL 00-39
7FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 WATCHDOG
7FF6h AE Y ABE Y Y Y Y Y INTERRUPTS
7FF5h AM4 Y 10 DATE DATE ALARM DATE 01-31
7FF4h AM3 Y 10 HOURS HOURS ALARM HOURS 00-23
7FF3h AM2 10 MINUTES MINUTES ALARM MINUT ES 00-59
7FF2h AM1 10 SECONDS SECONDS ALARM SECONDS 00-59
7FF1h Y Y Y Y Y Y Y Y UNUSED
7FF0h WF AF 0 BLF 0 0 0 0 FLAGS
X = Unused, read/writable under Write and Read AE = Alarm Flag Enable
bit control Y = Unused, read/writable without Write and Read
FT = Frequency Test bit bit control
OSC = Oscillator start/stop bit ABE = Alarm in battery Back-up mode enable
W = Write bit AM1-AM4 = Alarm Mask bits
R = Read bit WF = Watchdog Flag
WDS = Watchdog Steering bit AF = Alarm Flag
BMB0-BMB4 = Watchdog Multiplier bits 0 = 0 and are read only
RB0-RB1 = Watchdog Resolution bits BLF = Battery Low Flag
CLOCK OSCILLATOR CONTROL
The Clock oscillator ma y be stopped at any time. To increase the shelf life of the backup lithium batter y
source, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the
MSB of the Seconds Register (B7 of 7FF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the
oscillator. The DS1554 is shipped from Dallas Semiconductor with the clock oscillator turned off, OSC
bit set to a 1.
READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
Registers. This puts the external registers into a static state allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register (7FF8h).
As long as a 1 remains in the Control Register read bit, updating is halted. After a halt is issued, the
registers reflect the RTC count (day, date, and time) that was current at the moment the halt command
was issued. Normal updates to the external set of registers will resume within 1 second after the read bit is
set to a 0.
DS1554
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SETTING THE CLOCK
The 8th bit, B7 of the Control Register is the write bit. Setting the write bit to a 1, like the read bit, halts
updates to the DS1554 (7FF8h-7FFFh) registers. After setting the write bit to a 1, RTC Registers can be
loaded with the desired RTC count (da y, date, and time) in 24-hour BCD form at. Setting the write bit to a
0 then transfers the values written to the internal RTC Registers and allows normal operation to resume.
CLOCK ACCURACY (DIP MODULE)
The DS1554 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements. The DS1554 does
not require additional calibration and, in most applications, temperature deviations will have a negli gible
effect on accuracy. For this reason, methods of field clock calibration are not av ailable and not necessar y.
Attempts to calibrate the RTC that may be used with similar device t ypes (M48T5x family) will not have
any effect even though the DS1554 appears to accept calibration data.
CLOCK ACCUR ACY (POWERCAP MODULE)
The DS1554 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C.
FREQUENCY TEST MODE
The DS1554 frequency test mode uses the open drain IRQ /FT output. With the oscillator running, the
IRQ /FT output will toggle at 512 Hz when the FT bit is a 1, the Alarm Flag Enable bit (AE) is a 0, and
the Watchdog Steering bit (WDS) is a 1 or the Watchdog Register is reset (Register 7FF7h = 00h). The
IRQ /FT output and the frequency test mode can be used as a measure of the actual frequency of the
32.768 kHz RTC oscillator. The IRQ /FT pin is an open drain output which requires a pullup resistor for
proper operation. The FT bit is cleared to a 0 on power-up.
USING THE CLOCK ALARM
The alarm settings and control for the DS1554 reside within Registers 7FF2h-7FF5h. Register 7FF6h
contains two alarm enable bits: Alarm Enable (AE) and Alarm in Backup Enable (ABE). The AE and
ABE bits must be set as described below for the IRQ /FT output to be activated for a matched alarm
condition.
The alarm can be programmed to activate on a specific day of the month or repeat every day, hour,
minute, or second. It can also be programmed to go off while the DS1554 is in the batter y backed state of
operation to serve as a system wake-up. Alarm mask bits AM1-AM4 control the alarm mode. Table 3
shows the possible settings. Configurations not listed in the table default to the once per second mode to
notify the user of an incorrect alarm setting.
DS1554
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ALARM MASK BITS Table 3
AM4 AM3 AM2 AM1 ALARM RATE
1111Once per second
1110When seconds match
1100When minutes and seconds match
1000When hours, minutes, and seconds match
0000When date, hours, minutes, and seconds match
When the RTC Register values match Alarm Register settings, the Alarm Flag bit (AF) is set to a 1. If
Alarm Flag Enable (AE) is also set to a 1, the alarm condition activates the IRQ /FT pin. The IRQ /FT
signal is cle ared b y a read or w rite to the Flags Register (Address 7FF0h) as shown in Fi gure 2 and 3. The
IRQ /FT signal may be cleared by having the address stable for as short as 15 ns and either CE or WE
active, but is not guaranteed to be cleared unless tRC is fulfilled. The alarm flag is also cleared by a read or
write to the Flags Register but the flag will not change states until the end of the read/write cyc le and the
IRQ /FT signal has been cleared.
CLE ARING IRQ WAVEFORMS Figure 2
CLE ARING IRQ WAVEFORMS Figure 3
DS1554
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The IRQ /FT pin can also be activated in the battery backed mode. The IRQ /FT will go low if an alarm
occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition,
however an alarm generated during power-up will set AF. Therefore the AF bit can be read after s ystem
power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates alarm
timing during the battery back-up mode and power-up states.
BACK-UP MODE ALARM W AVEFORMS Figure 4
USING THE WATCHDOG TIMER
The watchdog timer can be used to detect an out-of-control processor. The user programs the watchdog
timer by setting the desired amount of time-out into the 8-bit Watchdog Register (Address 7FF7h). The
five Watchdog Register bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-
RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. The
watchdog time-out value is then determined by the multiplication of the 5-bit multiplier value with the 2-
bit resolution value. (For example: writing 00001110 in the Watchdog Register = 3 X 1 second or 3
seconds.) If the processor does not reset the timer within the specified period, the W atchdog Flag (WF) is
set and a processor interrupt is generated and stays active until either the Watchdog Flag (WF) is read or
the Watchdog Register (7FF7) is read or written.
The most significant bit of the Watchdog Register is the Watchdog Steering Bit (WDS). When set to a 0,
the watchdog will activate the IRQ /FT output when the watchdog times out.
When WDS is set to a 1, the watchdog will output a negative pulse on the RST output for a duration of
40 ms to 200 ms. The Watchdog Re gister (7FF7) and the FT bit will reset to a 0 at the end of a watchdo g
time-out when the WDS bit is set to a 1.
The watchdog timer resets when the processor performs a read or write of the Watchdog Register. The
time-out period then starts over. The watchdog timer is disabled by writing a value of 00h to the
Watchdog Register. The watchdog function is automatically disabled upon power-up and the Watchdog
Register is cl eared. If the watchdog function is set to output to the IRQ /FT output and the frequency test
function is activated, the watchdog function prevails and the frequency test function is denied.
DS1554
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POWER-ON DEFAULT STATES
Upon application of power to the device, the following register bits are set to a 0:
WDS=0, BMB0-BMB4=0, RB0-RB1=0, AE=0, ABE=0.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -5.0V to +6.0V
Operating Temperature 0°C to 70°C
Storage Temper ature -55°C to +125°C
Soldering Temperature 260°C for 10 seconds (See Note 8)
* This is a stress rating only and functional operation of the d evice at these or an y other conditions abov e
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATI NG CONDI TIONS (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Logic 1 Voltage All Inputs
VCC = 5V ±10% VIH 2.2 VCC +0.3V V 1
VCC = 3.3V ±10% VIH 2.0 VCC +0.3V V 1
Logic 0 Voltage All Inputs
VCC = 5V ±10% VIL -0.3 0.8 1
VCC = 3.3V ±10% VIL -0.3 0.6 1
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5.0V ±=10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Active Supply Current ICC X 75 mA 2, 3
TTL Standby Current (CE =VIH ) ICC1 X 6 mA 2, 3
CMOS Standby Current
(CE ≥=VCC - 0.2V) ICC2 X 4 mA 2, 3
Input Leakage Current (an y input) IIL -1 +1 µA
Output Leakage Current (any
output) IOL -1 +1 µA
Output Logic 1 Voltage
(IOUT = -1.0 mA) VOH 2.4 V 1
Output Logic 0 Voltage
(IOUT = 2.1 mA, DQ0-7 Outputs) VOL1 0.4 V 1
(IOUT = 10.0 mA, IRQ /FT and
RST outputs)
VOL2 0.4 V 1, 5
Write Protection Voltage VPF 4.25 4.37 4.50 V 1
Battery Switch Over Voltage VSO VBAT V 1, 4
DS1554
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DC ELECTRICAL CHARACTERISTI CS (0°C to 70°C; VCC = 3.3V ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Active Supply Current ICC 10 30 mA 2, 3
TTL Standby Current (CE = VIH ) ICC1 0.7 3 mA 2, 3
CMOS Standby Current
(CE ≥=VCC - 0.2V) ICC2 0.7 2 mA 2, 3
Input Leakage Current (an y input) IIL -1 +1 µA
Output Leakage Current
(any output) IOL -1 +1 µA
Output Logic 1 Voltage
(IOUT = -1.0 mA) VOH 2.4 V 1
Output Logic 0 Voltage
(IOUT =2.1 mA, DQ0-7 Outputs) VOL1 0.4 V 1
(IOUT =10.0 mA, IRQ /FT and
RST Outputs)
VOL2 0.4 V 1, 5
Write Protection Voltage VPF 2.80 2.88 2.97 V 1
Battery Switch Over Voltage VSO VBAT or
VPF
V 1, 4
READ CYCLE TIMING DIAGRAM Figure 5
DS1554
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READ CYCLE, AC CHARACTERISTIC S (0°C to 70°C; VCC = 5.0V ±10%)
70 ns access 100 ns access
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Read Cycle Time tRC 70 100 ns
Address Access Time tAA 70 100 ns
CE to DQ Low-Z tCEL 55 ns
CE Access Time tCEA 70 100 ns
CE Data Off time tCEZ 25 35 ns
OE to DQ Low-Z tOEL 55 ns
OE Access Time tOEA 35 55 ns
OE Data Off Time tOEZ 25 35 ns
Output Hold from Address tOH 55 ns
READ CYCLE, AC CHARACTERISTIC S (0°C to 70°C; VCC = 3.3V ±10%)
120 ns access 150 ns access
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Read Cycle Time tRC 120 150 ns
Address Access Time tAA 120 150 ns
CE to DQ Low-Z tCEL 55 ns
CE Access Time tCEA 120 150 ns
CE Data Off time tCEZ 40 50 ns
OE to DQ Low-Z tOEL 55 ns
OE Access Time tOEA 100 130 ns
OE Data Off Time tOEZ 35 35 ns
Output Hold from Address tOH 55 ns
DS1554
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WRITE CYCLE, AC CHARACTERISTI CS (0°C to 70°C; VCC = 5.0V ±10%)
70 ns access 100 ns access
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Write Cycle Time tWC 70 100 ns
Address Access Time tAS 00 ns
WE Pulse Width tWEW 50 70 ns
CE Pulse Width tCEW 60 75 ns
Data Setup Time tDS 30 40 ns
Data Hold time tDH1 0 0 ns 9
Data Hold time tDH2 X X ns 10
Address Hold Time tAH1 5 5 ns 9
Address Hold Time tAH2 X X ns 10
WE Data Off Time tWEZ 25 35 ns
Write Recovery Time tWR 55 ns
WRITE CYCLE, AC CHARACTERISTI CS (0°C to 70°C; VCC = 3.3V ±10%)
120 ns access 150 ns access
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Write Cycle Time tWC 120 150 ns
Address Setup Time tAS 00 ns
WE Pulse Width tWEW 100 130 ns
CE Pulse Width tCEW 110 140 ns
Data Setup Time tDS 80 90 ns
Data Hold Time tDH1 0 0 ns 9
Data Hold Time tDH2 X X ns 10
Address Hold Time tAH1 0 0 ns 9
Address Hold Time tAH2 X X ns 10
WE Data Off Time tWEZ 40 50 ns
Write Recovery Time tWR 10 10 ns
DS1554
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WRITE CYCLE TIMI NG, WRITE ENABLE CONTROLLED Figure 6
WRITE CYCLE TIMI NG, CHIP ENABLE CONTROLLED Figure 7
DS1554
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POWER-UP/DOWN CHARACTERISTICS (0°C to 70°C; VCC = 5.0V ±10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE or WE at VIH , Before
Power-Down tPD 0µs
VCC Fall Time: VPF(MAX) to
VPF(Min) tF300 µs
VCC Fall Time: VPF(MIN) to VSO tFB 10 µs
VCC Rise Time: VPF(MIN) to
VPF(MAX) tR0µs
VPF to RST High tREC 40 200 ms
Expected Data Retention Time
(Oscillator On) tDR 10 years 6, 7
POWER-UP/DOWN WAVEFORM TIMING 5-VOLT DEVICE Figure 8
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POWER-UP/DOWN CHARACTERISTICS (0°C to 70°C; VCC = 3.3V ±10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE or WE at VIH , Before
Power-Down tPD 0µs
VCC Fall Time: VPF(MAX) to
VPF(Min) tF300 µs
VCC Rise Time: VPF(MIN) to
VPF(MAX) tR0µs
VPF to RST High tREC 40 200 ms
Expected Data Retention Time
(Oscillator On) tDR 10 years 6, 7
POWER-UP/DOWN WAVEFORM TIMING 3.3-VOLT DEVICE Figure 9
CAPACITANCE (TA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Capacitance on all input pins CIN 7pF1
Capacitance on IRQ /FT, RST ,
and DQ pins CIO 10 pF 1
DS1554
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AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0.0 to 3.0 Volts
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5 ns
NOTES:
1. Voltage referenced to ground.
2. Typical values are at 25°C and nominal supplies.
3. Outputs are open.
4. Battery switch over occurs at the lower of either the battery voltage or VPF.
5. The IRQ /FT and RST outputs are open drain.
6. Data retention time is at 25°C.
7. Each DS1554 has a built-in switch that disconnects the lithium source until VCC is first applied by the
user. The expected tDR is defined for DIP modules and PowerCap modules as a cumulative time in
the absence of VCC starting from the time power is first applied by the user.
8. Real Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85°C. Post solder cleaning with water washing techniques is acceptable, provided that
ultrasonic vibration is not used.
In addition, for the PowerCap:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow oriented with the label side up (“live-bug”).
b. Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3
seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove
the part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to
remove solder.
9. tAH1, tDH1 are measured from WE going high.
10. tAH1, tDH1 are measured from CE going high.
DS1554
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DS1554 32-PIN PACKAGE
PKG 32-PIN
DIM MIN MAX
A IN.
MM 1.670
38.42 1.690
38.93
B IN.
MM 0.715
18.16 0.740
18.80
C IN.
MM 0.335
8.51 0.365
9.27
D IN.
MM 0.075
1.91 0.105
0.67
E IN.
MM 0.015
0.38 0.030
0.76
F IN.
MM 0.140
3.56 0.180
4.57
G IN.
MM 0.090
2.29 0.110
2.79
H IN.
MM 0.590
14.99 0.630
16.00
J IN.
MM 0.010
0.25 0.018
0.45
K IN.
MM 0.015
0.38 0.025
0.64
DS1554
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DS1554P
NOTE:
Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder
reflow oriented with the label side up (“live-bug”).
Hand Soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3 seconds.
To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply flux,
heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
PKG INCHES
DIM MIN NOM MAX
A0.920 0.925 0.930
B0.980 0.985 0.990
C- - 0.080
D0.052 0.055 0.058
E0.048 0.050 0.052
F0.015 0.020 0.025
G0.025 0.027 0.030
DS1554
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DS1554P WITH DS9034PCX ATTACHED
PKG INCHES
DIM MIN NOM MAX
A0.920 0.925 0.930
B0.955 0.960 0.965
C0.240 0.245 0.250
D0.052 0.055 0.058
E0.048 0.050 0.052
F0.015 0.020 0.025
G0.020 0.025 0.030
DS1554
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RECOMME NDED POWERC AP MODULE L AND PATTERN
INCHES
PKG
DIM MIN NOM MAX
A- 1.050 -
B- 0.826 -
C- 0.050 -
D- 0.030 -
E- 0.112 -
