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IS66WVE4M16ALL
IS67WVE4M16ALL
Rev. B | Feb. 2012 www.issi.com - SRAM@issi.com
Overview
The IS66WVE4M16ALL is an i ntegrated memory device containing 64Mbit Pseudo Static Random Access
Memory using a self-refresh DRAM array organize d as 4M words by 16 bits. The device includes several
power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and
Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power
rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.
Asynchronous and pag e mode interface
Dual voltage rails for optional performance
VDD 1.8V, VDDQ 1.8V
Page mode read acces s
Interpag e Read access : 70ns
Intrapage Read acce ss : 20ns
Low Power Consumption
Asynchronous Operation < 30 mA
Intrapage Read < 18mA
Standby < 180 uA (max.)
Deep power -down (DPD) < 3uA (Typ)
Lo w Power F eatu re
Temperature Controlled Refresh
Partial Array Refresh
Deep power -down (DPD) mode
Operating temperature Range
Industrial and Automotive, A1: -40°C~85°C
Package:
48-ba ll TFBGA, 48-pin TSOP-I
1.8V Core Async/Page PSRAM
Features
Copyright © 2012 Integrated Silic on Solution, Inc. All rights reserved. ISS I reserves the right to make changes to thi s specifi cation and its
products at any tim e without noti ce. ISSI ass umes no liabilit y arisi ng out of the appl i cation or use of any i nf ormati on, products or services
described herein. Custom ers are advised to obtain the latest version of this device specif ic ation before relying on any publi shed inf orm ati on
and before pl acing orders f or produc ts.
Integrated Sili con Solution, Inc. does not recommend the use of any of i ts products i n l i fe support appli cations where the failure or
malfunction of the product can reasonabl y be expected to cause f ai l ure of the l i f e support system or to signific antly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance t o
its satisfactio n, that:
a.) the risk of injury or damage has been minimized;
b.) the user ass ume all such risk s ; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Notes :
1. The 48-pin TSOP -I package option is not yet available. Please contact SRAM marketing at sram@issi.com for
additional information.
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IS66WVE4M16ALL
IS67WVE4M16ALL
Rev. B | Feb. 2012 www.issi.com - SRAM@issi.com
General Desc ription
PSRAM p roducts are high-speed, CMOS pseudo-static random access memory developed
for low-power, portable applications. The 64Mb DRAM core device is organized
as 4 Meg x 16 bits. These devices include the industry-sta ndard, asynchronous memory
interface found on other l ow -power SRAM or pseudo-SRAM (PSRAM) offerings.
For seamless operation on an asynchronous memory bus , PSRA M products incorporated a
transparent self-refr esh m echa nism . The hidde n re fres h req uire s no ad dit iona l support
from the system mem ory controller and has no significant impact on device read/write
performance.
A user-accessible configuration registe r s (CR) defines how the PSRAM device performs on-
chip refresh and whether page mode read accesses are permitted. This register is
automatically loaded with a default setting during power-up and can be updated at any
time during normal operation.
Special atte ntion ha s be en focused on curr ent cons umpt ion duri ng se lf-re fresh. This
product includes two system-accessible mechanisms to minimize refresh current.
Setting sleep enable (ZZ#) to LOW enables one of two low-power modes: partial-array
refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the
DRAM array tha t contains essential data. DPD halts refresh operation altogether and is
used when no vital information is stored in the device. The system-configurable refres h
mechanisms are accessed through the CR.
[ Functional Block Diagram]
Address
Decode Logic
Configuration Register
(CR)
4096K X 16
DRAM
Memory Array
Input
/Output
Mux
And
Buffers
DQ0~DQ15
A0~A21
Control
Logic
CE#
WE#
OE#
LB#
UB#
ZZ#
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IS66WVE4M16ALL
IS67WVE4M16ALL
Rev. B | Feb. 2012 www.issi.com - SRAM@issi.com
48Ball TFBGA Ball Assignment
[Top View]
(Ball Down)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB# OE# A0
DQ8 UB# A3
DQ9 DQ10 A5
VSSQ DQ11 A17
DQ14 DQ13 A14
DQ15 A19 A12
A18 A8 A9
A1 A2 ZZ#
A4 CE# DQ0
A6 DQ1 DQ2
A7 DQ3 VDD
A15 DQ5 DQ6
A13 WE# DQ7
A10 A11 A20
VDDQ DQ12 A21 A16 DQ4 VSS
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IS66WVE4M16ALL
IS67WVE4M16ALL
Rev. B | Feb. 2012 www.issi.com - SRAM@issi.com
Signal Descriptions
All signals for the device are listed below in Table 1.
Symbol Type Description
VDD Power Supply Core Power supply (1.7V~1.95V)
VDDQ Power Supply I/O Power supply (1.7V~1.95V)
VSS Power Supply All VSS supply pins m ust be connecte d to Ground
VSSQ Power Supply All VSSQ supply pins must be connected to Ground
DQ0~DQ15 Input / Output Data Inputs/Outputs (DQ0~DQ15)
A0~A21 Input Address Input(A0~A21)
LB# Input Lower By te select
UB# Input Upper By te select
CE# Input Chip Enable/Select
OE# Input Output Enab le
WE# Input Write Enable
ZZ# Input Sleep enable : When ZZ# is LOW, the CR can be loaded, or the device
can enter one of two low-power modes ( DPD or PAR).
Table 1. Signal D es cr iptions
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IS67WVE4M16ALL
Rev. B | Feb. 2012 www.issi.com - SRAM@issi.com
Functional Description
All functions for the device are listed below in Table 2.
Mode Power CE# WE# OE# UB#/LB# ZZ# DQ
[15:0]4 Note
Standby Standby H X X X H High-Z 2,5
Read Active L H L L H Data-Out 1,4
Write Active L L X L H Data-In 1,3,4
No oper a t i on Idle L X X X H X 4,5
PAR PAR H X X X L High-Z 6
DPD DPD H X X X L High-Z 6
Load
Configuration
register Active L L X X L High-Z
Table 2. Functional D esc ri ptions
Notes 1. When UB# and LB# are in select mode (LOW), DQ0~DQ15 are affected as shown.
When only LB# is in select mode, DQ 0~DQ7 are affected as shown. When only UB# is
in select mode, DQ8 ~ DQ15 are affected as shown.
2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data
inputs/outputs are internally isolated from any external influence.
3. When WE# is active, the OE# input is internally disabled and has no effect on the I/Os.
4. The device will consume active power in this mode whenever addresses are changed.
5. Vin=VDDQ or 0V, all device pins be static ( unswitched) i n orde r to achieve sta ndby curr ent .
6. DPD is enabled when configuration re g ister bit CR[4] is “0”; otherwise , PAR is enabled.
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IS66WVE4M16ALL
IS67WVE4M16ALL
Rev. B | Feb. 2012 www.issi.com - SRAM@issi.com
Functional Description
In general, this device is high-de nsit y a lt er nat ives t o SRAM a nd Pseudo SRAM prod ucts po pula r
in low-power, portable applications.
The 64Mb device contains a 67,108,864-bit DRAM core organized as 4,194,304 addresses by
16 bits. This device include the industry-sta nda rd , a synchronou s memory interface found on
other low-power SRAM or PSRAM offerings
Page mode access is also supported as a bandwidth-enhancing extension to the asynchronous
read protocol.
Power-Up Initialization
PSRAM p roducts include a n on-chip vo ltage s ensor that i s used to launch the power-up
initialization process. Initialization will load the CR with its default settings (see Table 3).
VDD and VDDQ must be applied simultaneously. When they reach a stable level above
1.8V, the device will require 150μs to complete its self-initialization process ( see Figure 1).
During the initialization period, CE# should remain HIGH. When initialization is complete,
the device is ready for normal operation.
Figure 1: Power-Up Initialization Timing
VDD=1.8V
Device Initialization
tPU > 150us Device ready for
normal operation
VDD
VDDQ
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IS66WVE4M16ALL
IS67WVE4M16ALL
Rev. B | Feb. 2012 www.issi.com - SRAM@issi.com
Bus Operating Modes
PSRAM product s incorp ora te s the indust ry -sta ndard, a synchronous i nterface . This bus interface
supports asynchronous Rea d and WRITE operations as well as page mode READ operation for
enhanced b andw id th. The sup port ed inte rface is define d by the value l oad ed into the CR.
Asynchronous Mode Operation
PSRAM products power up in the asynchronous operating mode. This mode uses the industry-
standard SRAM control interface (CE#, OE#, WE#, and LB#/UB#).
READ operations are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH
(see Figure 2). Valid data will be driven out of the I/Os after the specified access time has elapsed.
WRITE opera t ions occur w hen CE #,WE #, and LB#/UB# a re driven LOW (se e Figure 3). During
WRITE operations, the level of OE# is a “Don’t Care”; WE# overrides OE#. The d ata to be written is
latched on the rising e d g e of CE#, WE#, or LB#/UB#, whichever occurs first. WE# LOW tim e must be
limited to tCEM.
Address
DQ0-
DQ15
CE#
UB#/LB#
OE#
WE#
VALID
ADDRESS
VALID
DATA
Figure 2. Asynchronous Read Operation
tRC = READ cycle Time
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IS67WVE4M16ALL
Rev. B | Feb. 2012 www.issi.com - SRAM@issi.com
Page Mode READ Operation
Page mode is a performan c e-enhancing extension to the legacy asynchronous READ
operation. In page-mode-capable products, an initial asynchronous read access is
preformed, then adjacent addresses can be read quickly by simply changing the low-
order address. Addresses A[3:0] are used to determine the members of the 16-address
PSRAM page. Any change in add r esses A[4] or higher will initiate a new tAA access time.
Figure 4 shows the timing for a page mode access.
Page mode takes advantage of the fact that adjacent addresses can be read faster than
random addresses. WRITE operations do not include comparable page mode functionality.
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer
than tCE M.
Figure 4. Page Mode READ Oper ation
Address
DQ0-
DQ15
CE#
UB#/LB#
OE#
WE#
tAA
ADD3 ADD2 ADD1 ADD0
D0 D1 D2 D3
tAPA tAPA tAPA
UB#/LB# Operation
The UB#/LB# enable signals accommodate byte-wid e data transfers. During READ operations,
enabled bytes are driven onto the DQ. The DQ signals a ssocia ted with a disabled byte are
put into a High-Z state during a READ operation. During WRITE operations, disabled bytes
are not transfer re d to the m em ory arra y. and the inte rna l val ue re ma ins unchanged . During
a WRITE cycle the data to be written is latched on the rising edge of CE#, WE#, LB# or UB#,
whicheve r occ urs fir st .
When both the UB#/LB# are disabled (HIGH) during an operation, the device prevents t he
data bus from receiving or transmitting data. Although the device may appear to be deselected,
it remains in active mode as long as CE# remains LOW.
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IS67WVE4M16ALL
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Low-Power Feature
Standby Mode Opera tion
During stand by, the de vice curr ent consump tion is reduce d t o the leve l necess ary t o
perform the DRAM refresh oper ation. Standby operation occurs when CE# and ZZ# are HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE
operations when the address and control inputs remain static for an extended period of time.
This mode will continue until a change occurs to the address or control inputs.
Temperature Compensa ted Refresh
Temperature compensated refresh (TCR) is used to adjust the refresh rate depending on the
device operating temperature. DRAM technology requires more frequent refresh operations to
maintain data integrity as temperatures increase. More frequent refresh is required due to the
increased leakage of the DRAM's capacitive storage elements as temperatures rise. A decreased
refresh rate at lower temperatures will result in a savings in standby current.
TCR allows for adequate refresh at four different temperature thresholds: +15°C, +45°C , + 70 °C,
and +85°C. The setting selected must be for a temperature higher than the case temperature
of the device. If the case temperature is +50°C, the system can minimize self refresh current
consumption by sele cti ng the +70°C set ting. The +15°C and +45°C settings would result in
inadequa te refreshing a nd caus e da ta corrupt ion.
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IS67WVE4M16ALL
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Partial-Array Refresh
Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory
array. This feature e nables the devi ce to reduce standby current by refreshing only that
part of the memory array that is absolutely necessary. The refresh options are full array,
and none of the array. Data stored in addresses not receiving refresh will become
corrupted. Read and WRITE operations are ignored during PAR operation.
The device only enters PAR mode if the sleep bit in the CR has been set HIGH (CR[4] = 1).
PAR can be initiated by taking the ZZ# ball to the LOW state for longer than 10us.
Returning ZZ# to HIGH will cause an exit from PAR, and the entire array will be immediately
available for READ and WRITE operations.
Alternatively, PAR can b e initiated using the CR software-access sequence (see “Software
Access to the Configuration Register”). Using this method, PAR is enabled
immediately upon setting CR[4] to “1” However, using software access to write to t he CR
alter s the function of ZZ# so that ZZ# LOW no l onger initiat es PAR , even tho ugh ZZ#
continues to e nable WRITEs to the CR. This functional change persists unt il the next
time the device is powered up.
Deep Power-Dow n O pera tion
Deep power-down (DPD) operation disables all refresh-re late d activity. This mode is
used if the system does not require the storage provided by the PSRAM device. Any
stored data will become corrupted upon entering DPD. When refresh activity has been
re-enabled, the PSRAM device will require 150μs to perform an initialization procedure
before normal opera ti ons can resum e. R E AD and WR ITE o per at ions a re ignored during
DPD operation.
The device can only enter DPD if the sleep bit in the CR has been set LOW (CR[4] =0).
DPD is initiated by bringing ZZ# to the LOW sta te for longer tha n 10us. R e turning ZZ# to
HIGH will cause the device to exit DPD and begin a 150us initia lization process. During
this time, the current consumption will be higher than the specified standby levels, but
considerably lower than the active current specification.
Driving ZZ# LOW puts t he de vice in PAR mode if the SLEEP bit in the CR has be en se t
HIGH (CR[4] = 1).
The device should not be put into DPD using the CR software-access sequence.
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IS67WVE4M16ALL
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Configuration Regis ters Opera tion
The configuration register (CR) defines how the PSRAM device performs a transparent self refresh.
Altering the refresh parameters can dramatically reduce current consumption during standby mode.
Page mode controls is embedded in the CR. This register can be updated any time the device is
operating in a standby state. The control bits used in the CR are shown in Table 3. At power-up,
the CR is set to 0070h.
Access Using ZZ#
The CR can be loaded using a WRITE operation immediately after ZZ# makes a HIGH-to-LOW
transition (see Figure 5). The values placed on addresses A[21:0] are latched into the CR on the
rising edge of CE# or WE#, whichever occurs first. LB#/UB# ar e “Don’t Care.” Access using ZZ#
is WRITE only.
Figure 5: Load Configuration Register Operation Using ZZ#
Address
CE#
ZZ#
WE#
VALID
ADDRESS
t < 500ns
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Software Access Sequence
The contents of the CR can be read or modified using a software access sequence. The
nature of this access mechanism can potentially eliminat e the need for the ZZ# ball.
If the software-access mechanism is used, ZZ# can simply be tied to VDDQ; the port line
typically used for ZZ# control purposes will no longer be required. However, ZZ# should
not be tied to VDDQ if the syste m will use DP D; DPD cannot be enabled or disable d using
the software-access sequence.
The CR is loaded using a four-step sequence consisting of two READ operations followed
by two WRITE operations (see Figure 6). The REA D seq uence is virtually identical
except that an asynchronous READ is pe rformed during the fourth operation (see
Figure 7).
The address used during all READ and WRITE operations is the highest address of the
PSRAM device be ing access ed (3FFFF F h); t he cont ent o f this addr es s is not change d by
using the soft wa re -access sequence. The da ta bus is used to transfer data into or out of
bit[15:0] of the CR.
Writing to the CR using the software-access sequence modifies the function of the ZZ#
ball. After the software sequence loads the CR, the level of the ZZ# ball no longer enables
PAR operation. PAR operation is updated whenever the software-access sequence loads
a new value into the CR. This ZZ# functionality will remain active until the next time the
device is powered up. The operation of the ZZ# ball is not affected if the software-access
sequence is only used to read the contents of the CR. Use of the software-access sequence
does not affect the performa n ce of standar d (ZZ#-controlled) CR loading.
Figure 6 : Configuration Register Write
Notes : 1. CR : 0000h
MAX
ADDRESS
OUTPUT
DATA
MAX
ADDRESS
OUTPUT
DATA
MAX
ADDRESS MAX
ADDRESS
CR
VALUE IN
*Note1
OE#
Address
DQ0-
DQ15
CE#
UB#/LB#
WE#
Read Read Write Write
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Bit Num ber Definition Remark
21 – 8 Reserved All Must be set t o “0 ”
7 Page 0 = Page mode disabled (default)
1 = Page mode enabled
6 – 5 TCR
1 1 = +85°C (default)
0 0 = +70°C
0 1 = +45°C
1 0 = +15°C
4 Sleep 0 = DPD enabled
1 = PAR enabled (default)
3 Reserved Mu st be set to “0”
2 – 0 PAR1 000 = Full array (default)
100 = None of array
Table 3. Configuration Register
Notes : 1. Use of o t h er set t in g will result in ful l-ar ray ref resh co verage.
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Partial-Array Refresh (CR[2:0]) Default = Full-Array Refresh
The PAR bits restrict REFRESH operation to a portion of the total memory array. The
refresh options are “full array” and “ none of the array.”
Sleep Mode (CR[4 ] ) Default = PAR En abled, D P D D is a bled
The sleep mode bit defines the low-power mode to be entered when ZZ# is driven LOW.
If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is enabled. PAR can
also be enabled directly by writing to the CR using the software-access sequence. Note
that this disables ZZ# initiation of PAR. DPD cannot properly be enabled or disabled
using the soft wa re -access sequence; DPD should only be enabled or disabled using ZZ#
to access the CR.
DPD operation disables all refresh-relat ed activity. This mode is used when the system
does not require the storage provided by the PSRAM device. When DPD is enabled, any
stored data will become corrupted. When refresh activity has been re-enabled. The
PSRAM device will require 150us to per form an initia lization procedure before normal
operation can resume. DPD should not be enabled using CR software access.
Temperature Compensated Refresh (CR[6:5]) Default = +85oC Operation
Temperature compensated refresh register bits can be programmed using the CR [5, 6]
configuration registers and has four different temperature levels: +15°C, +45°C, +70°C,
and +85°C. The temperature selected must be equal to or higher than the case
temperature of the device. Setting a lower temperature level would cause data to be
corrupte d due t o insufficient r efresh rate.
Page Mode READ Operation (CR[7]) Default = Disabled
The page mode operation bit determines whether page mode READ operations are
enabled. In the power-up default state, page mode is disabled.
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Electrical Characteristics
Parameter Rating
Voltage to Any Ball Except VDD, VDDQ Relative to VSS -0.5V to 4.0V or VDDQ + 0.3V
Voltage on VDD Supply Rel ative to VSS -0.2V to + 2.45V
Volta ge on VDDQ Supply R el at ive to VSS -0.2V to + 2.45V
Storage T emperatu re (plastic) -55°Cto + 150°C
Operating Temperature -40°C to + 85°C
Soldering Temperature and Time
10s (solder ball only) + 260°C
Table 4. Absolute Maximum Ratings
Notes: Stresses gr eat er tha n th o se l ist ed m ay cause per m an en t damage to th e devi c e. Th i s is a
stress ratin g only, and func tion al operation o f the device at these or any other
conditions above those indicated in this specification is not implied. Exposure to
absolut e maximum rating con ditio ns for extended perio ds may aff ect reliabilit y.
Description Conditions Symbol MIN MAX Unit Note
Supply Voltage VDD 1.7 1.95 V
I/O Supply Voltage VDDQ 1.7 1.95 V
Input High Voltage VIH VDDQ-0.4 VDDQ+0.2 V 1
Input Low Voltage VIL -0.20 0.4 V 2
Output High Voltage IOH = -0.2mA VOH 0.80 VDDQ V
Output Low Voltage IOL = +0.2mA VOL 0.20 VDDQ V
Input Leakage Current VIN = 0 to VDDQ ILI 1 uA
Output Leakage Current OE#=VIH or
Chip Disabled ILO 1 uA
Operating Current Conditions Symbol Typ MAX Unit Note
Asynchronous Rand om
READ/WRITE VIN = VDDQ or 0V
Chip enabled,
IOUT = 0
IDD1 -70 30 mA 3
Asynchronous
PAGE READ IDD1P -70 18 mA 3
Standby Current VIN=VDDQ or 0V
CE# = VDDQ ISB 180 uA 4
Table 5. Electrica l Cha r ac teris tic s a nd O pera ting Condi tions
Industrial Temperature (–40ºC < TC < +85ºC)
Notes: 1. Input sign al s m ay oversho o t to V D D Q + 1. 0V for periods less th a n 2n s duri n g t r an sit ions.
2. Input sign al s may u n der sh o o t to Vss – 1.0 V for per iods less t h an 2 n s du ri n g tr an si ti o n s.
3. This paramet er is spec i f ied w i th the o u t pu ts di sabled to av o id extern al lo adi n g ef f ec t s.
User must add requir ed cu r r en t to dri ve ou t pu t capac i tan ce expec t ed in th e actual syst em.
4. ISB (MAX) values measu red w ith PAR set to FULL ARR AY at +85°C . In order to achieve low
standby curren t , all inpu ts m u st be dr iven to eit h er V D D Q o r V S S . IS B migh t be set sli gh tl y
higher for u p to 500m s after power-up, or when entering st andby mode.
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Description Conditions Symbol TYP MAX Unit
Deep Pow er-Down VIN=VDDQ or 0V; +25°C
ZZ# = 0V, CR[4] = 0 Izz 3 10 uA
Table 6. Deep Power-Down Spec ifica tions
Description Conditions Symbol MIN MAX Unit Note
Input Capacitance TC=+25°C;
f=1Mhz;
VIN=0V
CIN 2.0 6.5 pF 1
Input/Output Capacitance (DQ) CIO 3.5 6.5 pF 1
Table 7. Ca p a ci tance
Notes: 1. These param eters ar e ver ified in device c harac teri zatio n and are no t 100% tested.
VDDQ/23 Output
Figure 8. AC Input/Output Reference Waveform
Test Points
∫∫
∫∫
VDDQ/22 Input1
VDDQ
VSS
Notes: 1. AC test input s are driven at V DDQ for a logic 1 and VSS for a logic 0. Input rise and fal l times
(10% to 90%) < 1.6ns.
2. Input timin g begins at VDDQ/ 2.
3. Output timing ends at VDDQ/2.
DUT
30pF
50Ω VDDQ/2
Test Point
Figure 9. Output Load Circuit
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Table 8 . Asynchronous REA D Cyc le T iming Requiremen ts
Symbol Parameter -70 Unit Notes
Min Max
tAA Address Acess Time 70 ns
tAPA Page access Time 20 ns
tBA LB# /UB# acce ss Time 70 ns
tBHZ LB#/UB# disable to High-Z output 8 ns 1
tBLZ LB#/UB# enable to Low-Z output 10 ns 2
tCEM Maximum CE# pulse width 8 us 3
tCO Chip select access time 70 ns
tHZ Chip disable to High-Z output 8 ns 1
tLZ Chip enable to Low-Z output 10 ns 2
tOE Output enable to valid output 20 ns
tOH Output hold fr om addres s change 5 ns
tOHZ Output disable to High-Z output 8 ns 1
tOLZ Output enable to Low-Z output 3 ns 2
tPC Page cycle time 20 ns
tRC Read cycle time 70 ns
AC Chara cteristics
Notes: 1. Low-Z to High-Z timin gs are tested wi t h the circuit shown in Figur e 9 . The H igh -Z timings
measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 9. The Low-Z timings
measure a 100m V transition away from the High-Z ( V D D Q / 2 ) lev el tow ar d eit h er VOH o r VOL.
3. Page mode enable only.
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Table 9 . Asynchronous WRIT E Cy cl e Timi ng Requirem ents
Symbol Parameter -70 Unit Notes
Min Max
tAS Address setup Time 0 ns
tAW Address valid to end of write 70 ns
tBW Byte select to end of write 70 ns
tCPH CE# HIGH time during write 5 ns
tCW Chip enable to end of Write 70 ns
tDH Data hold from write time 0 ns
tDW D ata write setu p time 23 ns
tLZ Chip enable to Low-Z output 10 ns 1
tOW End write to Low-Z output 5 ns 1
tWC Write cycle time 70 ns
tWHZ Write to High-Z output 8 ns 2
tWP Write pulse width 46 ns 3
tWPH Write pulse width HIGH 10 ns
tWR Write reco v ery time 0 ns
Notes: 1. Low-Z to High-Z timings are tested with the circuit shown in Figure 9. The
High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 9. The
Low-Z timings measure a 10 0 m V transition away f r o m th e High-Z (VDDQ/2) level toward
either VOH or VOL.
3. WE# LOW mu st be l im it ed to tCEM (8us)
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IS66WVE4M16ALL
IS67WVE4M16ALL
Rev. B | Feb. 2012 www.issi.com - SRAM@issi.com
Table10 . Load Configuration Register Timing Requirements
Symbol Parameter -70 Unit Note
Min Max
tAS Address setup time 0 ns
tAW Address valid to end of write 70 ns
tCDZZ Chip deselect to ZZ# LOW 5 ns
tCW Chip enable to end of write 70 ns
tWC Write cycle time 70 ns
tWP Write pulse width 46 ns
tWR Write reco v ery time 0 ns
tZZWE ZZ# LOW t o WE# LO W 10 500 ns
Symbol Parameter -70 Unit Notes
Min Max
tCDZZ Chip deselect to ZZ# LOW 5 ns
tR Deep Power-down recovery 150 us
tZZ( MIN) Minimum ZZ# pulse width 10 us
Table11 . DPD Timing Requirements
Symbol Parameter -70 Unit Notes
Min Max
tPU Initialization Period (required before normal operations) 150 us
Table12 . Initialization Timing Requirements
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IS66WVE4M16ALL
IS67WVE4M16ALL
Rev. B | Feb. 2012 www.issi.com - SRAM@issi.com
Timing Di agrams
Figure 10: Power-Up Initializ ation Timing
VDD, VDDQ=1.8V
Device Initialization
tPU > 150us Device ready for
normal operation
VDD(MIN)
Figure 11: Load Configuration Register
Address
CE#
OPCODE
tCW
tWR
tWP
tAW
tZZWE
tWC
UB#/LB#
tAS
tCDZZ
ZZ#
WE#
OE#
ZZ#
tZZ (MIN)
tR
Device read y for
normal operation
Figure 12: DPD Entry and Exit Timing
CE#
tCDZZ
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IS66WVE4M16ALL
IS67WVE4M16ALL
Rev. B | Feb. 2012 www.issi.com - SRAM@issi.com
Figure 13: Single Read Operation
Address
DQ0-
DQ15
CE#
UB#/LB#
OE#
WE#
VALID
ADDRESS
VALID
OUTPUT
tCO
tOE
tHZ
tOLZ
tBA
tLZ
tAA
tBHZ
tOHZ
tRC
Figure 14: PAGE MODE READ
A4-A21
DQ0-
DQ15
CE#
UB#/LB#
OE#
WE#
VALID
ADDRESS
VALID
OUTPUT
tCO
tOE
tHZ
tOLZ
tBA
tLZ
tAA
tBHZ
tOHZ
tRC
A0-A3 VALID
ADDRESS
VALID
OUTPUT VALID
OUTPUT VALID
OUTPUT
VALID
ADDRESS VALID
ADDRESS VALID
ADDRESS
tPC
tAPA
tOH
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IS66WVE4M16ALL
IS67WVE4M16ALL
Rev. B | Feb. 2012 www.issi.com - SRAM@issi.com
Ordering Information – VDD = 1.8V
Industrial Temperature Range: (-40oC to +85oC)
Config. Speed
(ns) Order P a rt No. Package
4Mx16 70 IS66WVE4M16ALL-70BLI 48-ball TFBGA, Lead-free
Notes :
1. The 48-pin TSOP-I package o p ti on is not yet a v ailab le. Please con ta ct SRA M mark eti ng at
sram@issi.com for addit io nal in forma tio n.
Automoti ve, A1 Temperature Range: (-40oC to +85oC)
Config. Speed
(ns) Order P a rt No. Package
4Mx16 70 IS67WVE4M16ALL-70BLA1 48-ball TFBGA, Lead-free
