83947AYI-147 http://www.icst.com/products/hiperclocks.html REV. A SEPTEMBER 24, 2004
1
Integrated
Circuit
Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS83947I-147 is a low skew, 1-to-9
LVCMOS/LVTTL Fanout Buffer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50Ω
series or parallel terminated transmission lines. The effective
fanout can be increased from 9 to 18 by utilizing the ability of
the outputs to drive two series terminated lines.
Guaranteed output and part-to-part skew characteristics make
the ICS83947I-147 ideal for high performance, 3.3V or 2.5V
single ended applications.
BLOCK DIAGRAM PIN ASSIGNMENT
FEATURES
•9 LVCMOS/LVTTL outputs
•Selectable CLK0 and CLK1 can accept the following
input levels: LVCMOS and LVTTL
•Maximum output frequency: 250MHz
•Output skew: 115ps (maximum)
•Part-to-part skew: 500ps (maximum)
•Additive phase jitter, RMS: 0.02ps (typical) @ 3.3V
•Full 3.3V or 2.5V operating supply
•-40°C to 85°C ambient operating temperature
•Pin compatible with the MPC947
HiPerClockS™
ICS
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
Q3
VDDO
Q4
GND
Q5
VDDO
GND
GND
CLK_SEL
CLK0
CLK1
CLK_EN
OE
VDD
GND
GND
Q6
VDDO
Q7
GND
Q8
VDDO
GND
GND
Q2
VDDO
Q1
GND
Q0
VDDO
GND
ICS83947I-147
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CLK0
CLK1
0
1
CLK_EN
CLK_SEL
D
Q
LE
OE
83947AYI-147 http://www.icst.com/products/hiperclocks.html REV. A SEPTEMBER 24, 2004
2
Integrated
Circuit
Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
TABLE 3. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE
rebmuNemaNepyTnoitpircseD
,71,61,21,9,8,1
23,92,52,42,02 DNGrewoP.dnuorgylppusrewoP
2LES_KLCtupnIpulluP ,WOLnehW.1
KLCstceles,HGIHnehW.tupnitceleskcolC
.slevelecafretniLTTVL/SOMCVL.0KLCstceles
4,31KLC,0KLCtupnIpulluP.sleve
lecafretniLTTVL/SOMCVL.stupnikcolcecnerefeR
5NE_KLCtupnIpulluP.slevelecafretniLTTVL/SOMCVL.elbanekcolC
6EOtup
nIpulluP.slevelecafretniLTTVL/SOMCVL.elbanetuptuO
7V
DD
rewoP.nipylppuseroC
13,72,22,81,41,01V
ODD
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,12,91,51,31,11
03,82,62,32
,5Q,6Q,7Q,8Q
0Q,1Q,2Q,3Q,4Q tuptuO .stuptuokcolc8Qurht0Q
.
slevelecafretniLTTVL/SOMCVL
:ETON
pulluP
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)tuptuorep( 21Fp
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ecnadepmItuptuO 7 Ω
83947AYI-147 http://www.icst.com/products/hiperclocks.html REV. A SEPTEMBER 24, 2004
3
Integrated
Circuit
Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V OR 2.5V±5%, TA = -40°C TO 85°C
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSeroC 0.33.36.3V
573.25.2526.2V
V
ODD
egatloVylppuStuptuO 0.33.36.3V
573.25.2526.2V
I
DD
tnerruCylppuStupnI 05Am
I
ODD
tnerruCylppuStuptuO 9Am
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5 V
Outputs, VO-0.5V to VDDO + 0.5V
Package Thermal Impedance, θ
JA 47.9°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI 2V
DD
3.0+V
V
LI
egatloVwoLtupnI 1KLC,0KLC3.0-3.1V
EO,NE_KLC,LES_KLC3.0-8.0V
I
HI
tnerruChgiHtupnI ,EO,1KLC,0KLC
NE_KLC,LES_KLC V
DD
V=
NI
V526.2=5Aµ
I
LI
tnerruCwoLtupnI ,EO,1KLC,0KLC
NE_KLC,LES_KLC
V
DD
,V526.23=
V
NI
V0= 051-Aµ
V
HO
1ETON;egatloVhgiHtuptuO 8.1V
V
LO
1ETON;egatloVwoLtuptuO 5.0V
05htiwdetanimretstuptuO:1ETON ΩVot
ODD
,noitceSnoitamrofnItnemerusaeMretemaraPeeS.2/
tseTdaoLtuptuOV5.2
.margaiDtiucriC
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI 26.3V
V
LI
egatloVwoLtupnI 8.0V
I
NI
tnerruCtupnI ,EO,1KLC,0KLC
NE_KLC,LES_KLC 001-Aµ
V
HO
1ETON;egatloVhgiHtuptuOI
HO
Am02-=5.2V
V
LO
1ETON;egatloVwoLtuptuOI
LO
Am02=4.0V
05htiwdetanimretstuptuO:1ETON ΩVot
ODD
,noitceSnoitamrofnItnemerusaeMretemaraPeeS.2/
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.margaiDtiucriC
83947AYI-147 http://www.icst.com/products/hiperclocks.html REV. A SEPTEMBER 24, 2004
4
Integrated
Circuit
Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
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XAM
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t
DP
1ETON,yaleDnoitagaporPf≤ZHM0522 2.4sn
t
)o(ks5,2ETON;wekStuptuO noderusaeM
V@egdegnisir
ODD
2/ 511sp
t
)pp(ks5,3ETON;wekStraP-ot-traP noderusaeM
V@egdegnisir
ODD
2/ 005sp
)Ø(tijt
,rettiJesahPevitiddAreffuB
esahPevitiddAotrefer;SMR
noitceSrettiJ
)zHM02otzHK21( 2.0 sp
t
R
t/
F
emiTllaF/esiRtuptuOV0.2otV8.02.01sn
t
WP
htdiWesluPtuptuOzHM331>ft
doireP
1-2/t
doireP
1+2/sn
cdoelcyCytuDtuptuOf≤zHM3310406%
t
NE
4ETON;emiTelbanEtuptuO 01sn
t
SID
4ETON;emiTelbasiDtuptuO 01sn
t
S
emiTputeSelbanEkcolC0sn
t
S
emiTdloHelbanEkcolC1sn
.esiwrehtodetonsselnuzHM052otlauqeronahtsselseicneuqerftaderusaemsretemarapllA
Vmo
rfderusaeM:1ETON
DD
Vottupniehtfo2/
ODD
.tuptuoehtfo2/
VtaderusaeM.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD
:2ETON
ODD
.2/
htiwdnasegatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
Vtaderus
aemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqe
ODD
.2/
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.56dradnatSCEDEJhtiwecn
adroccanidenifedsiretemarapsihT:5ETON
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 052zHM
t
DP
1ETON,yaleDnoitagaporPf≤ZHM0524.25.4sn
t
)o(ks5,2ETON;wekStuptuO noderusaeM
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ODD
2/ 031sp
t
)pp(ks5,3ETON;wekStraP-ot-traP noderusaeM
V@egdegnisir
ODD
2/ 006sp
t
)Ø(tij
,rettiJesahPevitiddAreffuB
esahPevitiddAotrefer;SMR
noitceSrettiJ
)zHM02otzHK21(1.0sp
t
R
t/
F
emiTllaF/esiRtuptuO%08-%02003008sp
t
WP
htdiWesluPtuptuOt
doireP
2.1-2/t
doireP
2.1+2/sn
t
NE
4ETON;emiTelbanEtuptuO 01sn
t
SID
4ETON;emiTelbasiDtuptuO 01sn
t
S
emiTputeSelbanEkcolC0sn
t
S
emiTdloHelbanEkcolC1sn
.esiwrehtodetonsselnuzHM052otlauqeronahtsselseicneuqerftaderusaemsretemarapllA
Vmo
rfderusaeM:1ETON
DD
Vottupniehtfo2/
ODD
.tuptuoehtfo2/
VtaderusaeM.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD
:2ETON
ODD
.2/
htiwdnasegatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
Vtaderusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqe
ODD
.2/
.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarapesehT:4ETON
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:5ETON
83947AYI-147 http://www.icst.com/products/hiperclocks.html REV. A SEPTEMBER 24, 2004
5
Integrated
Circuit
Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
Additive Phase Jitter, RMS @
156.25MHz (12KHz to 20MHz)
= 0.01ps typical @ 2.5V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
Additive Phase Jitter, RMS @
156.25MHz (12KHz to 20MHz)
= 0.02ps typical @ 3.3V
83947AYI-147 http://www.icst.com/products/hiperclocks.html REV. A SEPTEMBER 24, 2004
6
Integrated
Circuit
Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
t
PD
V
DD
2
V
DDO
2
PARAMETER MEASUREMENT INFORMATION
2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
LVCMOS
1.65V ± 0.15V
-1.65V ± 0.15V
SCOPE
Qx
LVCMOS
1.25V±5%
-1.25V±5%
PART-TO-PART SKEW
PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Clock
Outputs
0.8V
2V 2V
0.8V
t
R
t
F
t
sk(o)
V
DDO
2
V
DDO
2
Qx
Qy
OUTPUT SKEW
t
sk(pp)
V
DDO
2
V
DDO
2
Qx
Qy
PART 1
PART 2
CLK0,CLK1
Q0:Q8
Q0:Q8
3.3V OUTPUT RISE/FALL TIME
Clock
Outputs
20%
80% 80%
20%
t
R
t
F
t
PW
t
PERIOD
V
DDO
2
V
DDO
2
V
DDO
2
t
PW
t
PERIOD
odc =
VDD,
VDDO
VDD,
VDDO
2.5V OUTPUT RISE/FALL TIME
GND
GND
83947AYI-147 http://www.icst.com/products/hiperclocks.html REV. A SEPTEMBER 24, 2004
7
Integrated
Circuit
Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
APPLICATION SCHEMATIC EXAMPLE
Figure 1
shows an example of ICS83947I-147 application sche-
matic. In this example, the device is operated at VCC=3.3V. The
decoupling capacitors should be located as close as possible
to the power pin. The input is driven by a 3.3V LVCMOS driver.
C4
0.1u
VCC
Zo = 50 Ohm
R3 43
R2 43
R1 43
C2
0.1u
(U1-22)
C3
0.1u
C1
0.1u
C3
0.1u
(U1-10)
VDDO
(U1-18)
C5
0.1u
VDDO
(U1-14)
Zo = 50
U1
ICS83947I-147
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
GND
CLK_SEL
CLK0
CLK1
CLK_EN
OE
VDD
GND
GND
VDDO
Q8
GND
Q7
VDDO
Q6
GND
GND
VDDO
Q5
GND
Q4
VDDO
Q3
GND
GND
VDDO
Q0
GND
Q1
VDDO
Q2
GND
VCC
VDD=3.3V
LVCMOS
Zo = 50
Zo = 50 Ohm
(U1-27)
VDD
V DDO=3. 3V
LVCMOS
C2
0.1u
(U1-31)
R3 43
For the LVCMOS output drivers, only one termination example
is shown in this schematic. Additional termination approaches
are shown in the LVCMOS Termination Application Note (refer
to ICS website).
FIGURE 1. ICS83947I-147 SCHEMATIC LAYOUT
83947AYI-147 http://www.icst.com/products/hiperclocks.html REV. A SEPTEMBER 24, 2004
8
Integrated
Circuit
Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS83947I-147 is: 1040
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
83947AYI-147 http://www.icst.com/products/hiperclocks.html REV. A SEPTEMBER 24, 2004
9
Integrated
Circuit
Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
NOITAIRAVCEDEJ
SRETEMILLIMNISNOISNEMIDLLA
LOBMYS
ABB
MUMINIMLANIMONMUMIXAM
N23
A----06.1
1A 50.0--51.0
2A 53.104.154.1
b03.073.054.0
c90.0--02.0
DCISAB00.9
1D CISAB00.7
2D .feR06.5
ECISAB00.9
1E CISAB00.7
2E .feR06.5
eCISAB08.0
L54.006.057.
0
θθ
θ
θθ 0
°
-- 7
°
ccc ----01.0
Reference Document: JEDEC Publication 95, MS-026
83947AYI-147 http://www.icst.com/products/hiperclocks.html REV. A SEPTEMBER 24, 2004
10
Integrated
Circuit
Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
741-IYA74938SCI741IA74938SCIPFQLdaeL23yartrep052C°58otC°04-
T741
-IYA74938SCI741IA74938SCIleeRdnaepaTnoPFQLdaeL230001C°58otC°04-
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
