FN6754 Rev 2.00 Page 1 of 20
June 2, 2016
FN6754
Rev 2.00
June 2, 2016
ISL6754
ZVS Full-Bridge PWM Controller with Adjustable Synchronous Rectifier Control
DATASHEET
The ISL6754 is a high performance extension of the Intersil
family of Zero-Voltage Switching (ZVS) full-bridge PWM
controllers. Like the ISL6752, it achieves ZVS operation by
driving the upper bridge FETs at a fixed 50% duty cycle while
the lower bridge FETs are trailing-edge modulated with
adjustable resonant switching delays.
Adding to the ISL6752’s feature set are average current
monitoring and soft-start. The average current signal may be
used for average current limiting, current sharing circuits and
average current mode control. Additionally, the ISL6754
supports both voltage- and current-mode control.
The ISL6754 features complemented PWM outputs for
Synchronous Rectifier (SR) control. The complemented
outputs may be dynamically advanced or delayed relative to
the PWM outputs using an external control voltage.
This advanced BiCMOS design features precision dead time
and resonant delay control, and an oscillator adjustable to
2MHz operating frequency. Additionally, multi-pulse
suppression ensures alternating output pulses at low duty
cycles where pulse skipping may occur.
Applications
• ZVS full-bridge converters
• Telecom and datacom power
• Wireless base station power
• File server power
• Industrial power systems
Features
• Adjustable resonant delay for ZVS operation
• Synchronous rectifier control outputs with adjustable
delay/advance
• Voltage- or current-mode control
• 3% current limit threshold
• Adjustable average current limit
• Adjustable dead time control
• 175µA start-up current
• Supply UVLO
• Adjustable oscillator frequency up to 2MHz
• Internal over-temperature protection
• Buffered oscillator sawtooth output
• Fast current sense to output delay
• Adjustable cycle-by-cycle peak current limit
• 70ns leading edge blanking
• Multi-pulse suppression
• Pb-free (RoHS compliant)
Related Literature
•AN1603, “ISL6752/54EVAL1Z ZVS DC/DC Power Supply
with Synchronous Rectifiers User Guide”
•AN1619, “Designing with ISL6752DBEVAL1Z and
ISL6754DBEVAL1Z Control Cards”
Pin Configuration
ISL6754
(20 LD QSOP)
TOP VIEW
RTD
SS
CT
OUTUR
OUTUL
CTBUF
OUTLRRESDEL
RAMP
OUTLL
VDD
VERR
VREF
CS
GND
1
2
4
3
5
6
7
8
19
20
11
12
13
14
15
16
IOUT
FB
OUTLLN
OUTLRN9
10
17
18
VADJ
ISL6754
FN6754 Rev 2.00 Page 2 of 20
June 2, 2016
Ordering Information
PART NUMBER
(Notes 1, 2, 3) PART MARKING TEMP. RANGE (°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL6754AAZA 6754 AAZ -40 to +105 20 Ld QSOP M20.15
ISL6752/54EVAL1Z Evaluation Board
ISL6754DBEVAL1Z ISL6754 Evaluation Daughter Board
NOTES:
1. Add -T suffix for 2.5k unit tape and reel option. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL6754. For more information on MSL, please see tech brief TB363.
Pin Descriptions
PIN
NUMBER
PIN
NAME DESCRIPTION
1 VREF The 5.00V reference voltage output having 3% tolerance over line, load and operating temperature. Bypass to GND with a
0.1µF to 2.2µF low ESR capacitor.
2 VERR The control voltage input to the inverting input of the PWM comparator. The output of an external Error Amplifier (EA) is applied
to this input, either directly or through an opto-coupler, for closed loop regulation. VERR has a nominal 1mA pull-up current
source.
When VERR is driven by an opto-coupler or other current source device, a pull-up resistor from VREF is required to linearize the
gain. Generally, a pull-up resistor on the order of 5kΩ is acceptable.
3 CTBUF CTBUF is the buffered output of the sawtooth oscillator waveform present on CT and is capable of sourcing 2mA. It is offset
from ground by 0.40V and has a nominal valley-to-peak gain of 2. It may be used for slope compensation.
4 RTD This is the oscillator timing capacitor discharge current control pin. The current flowing in a resistor connected between this
pin and GND determines the magnitude of the current that discharges CT. The CT discharge current is nominally 20x the
resistor current. The PWM dead time is determined by the timing capacitor discharge duration. The voltage at RTD is nominally
2.00V.
5 RESDEL Sets the resonant delay period between the toggle of the upper FETs and the turn on of either of the lower FETs. The voltage
applied to RESDEL determines when the upper FETs switch relative to a lower FET turning on. Varying the control voltage from
0V to 2.00V increases the resonant delay duration from 0 to 100% of the dead time. The control voltage divided by 2
represents the percent of the dead time equal to the resonant delay. In practice the maximum resonant delay must be set
lower than 2.00V to ensure that the lower FETs, at maximum duty cycle, are OFF prior to the switching of the upper FETs.
6 CT The oscillator timing capacitor is connected between this pin and GND. It is charged through an internal 200µA current source
and discharged with a user adjustable current source controlled by RTD.
7 FB FB is the inverting inputs to the Error Amplifier (EA). The amplifier may be used as the error amplifier for voltage feedback or
used as the average current limit amplifier (IEA). If the amplifier is not used, FB should be grounded.
8 RAMP This is the input for the sawtooth waveform for the PWM comparator. The RAMP pin is shorted to GND at the termination of
the PWM signal. A sawtooth voltage waveform is required at this input. For current-mode control this pin is connected to CS
and the current loop feedback signal is applied to both inputs. For voltage-mode control, the oscillator sawtooth waveform
may be buffered and used to generate an appropriate signal, RAMP may be connected to the input voltage through a RC
network for voltage feed forward control, or RAMP may be connected to VREF through a RC network to produce the desired
sawtooth waveform.
9 CS This is the input to the overcurrent comparator. The overcurrent comparator threshold is set at 1.00V nominal. The CS pin is
shorted to GND at the termination of either PWM output.
Depending on the current sensing source impedance, a series input resistor may be required due to the delay between the
internal clock and the external power switch. This delay may result in CS being discharged prior to the power switching device
being turned off.
10 IOUT Output of the 4X buffer amplifier of the sample and hold circuitry that captures and averages the CS signal.
11 GND Signal and power ground connections for this device. Due to high peak currents and high frequency operation, a low
impedance layout is necessary. Ground planes and short traces are highly recommended.
ISL6754
FN6754 Rev 2.00 Page 3 of 20
June 2, 2016
12 OUTLRN These outputs are the complements of the PWM (lower) bridge FETs. OUTLLN is the complement of OUTLL and OUTLRN is the
complement of OUTLR. These outputs are suitable for control of synchronous rectifiers. The phase relationship between each
output and its complement is controlled by the voltage applied to VADJ.
13 OUTLLN
14 OUTUR These outputs control the upper bridge FETs and operate at a fixed 50% duty cycle in alternate sequence. OUTUL controls the
upper left FET and OUTUR controls the upper right FET. The left and right designation may be switched as long as they are
switched in conjunction with the lower FET outputs, OUTLL and OUTLR.
15 OUTUL
16 OUTLR These outputs control the lower bridge FETs, are pulse width modulated, and operate in alternate sequence. OUTLL controls
the lower left FET and OUTLR controls the lower right FET. The left and right designation may be switched as long as they are
switched in conjunction with the upper FET outputs, OUTUL and OUTUR.
17 OUTLL
18 VDD VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to
the VDD and GND pins as possible. VDD is monitored for supply voltage Undervoltage Lockout (UVLO). The start and stop
thresholds track each other resulting in relatively constant hysteresis.
19 VADJ A 0V to 5V control voltage applied to this input sets the relative delay or advance between OUTLL/OUTLR and
OUTLLN/OUTLRN. The phase relationship between OUTUL/OUTUR and OUTLL/OUTLR is maintained regardless of the phase
adjustment between OUTLL/OUTLR and OUTLLN/OUTLRN.
Voltages below 2.425V result in OUTLLN/OUTLRN being advanced relative to OUTLL/OUTLR. Voltages above 2.575V result in
OUTLLN/OUTLRN being delayed relative to OUTLL/OUTLR. A voltage of 2.50V ±75mV results in zero phase difference. A weak
internal 50% divider from VREF results in no phase delay if this input is left floating.
The range of phase delay/advance is either zero or 40 to 300ns with the phase differential increasing as the voltage deviation
from 2.5V increases. The relationship between the control voltage and phase differential is non-linear. The gain (t/V) is low
for control voltages near 2.5V and rapidly increases as the voltage approaches the extremes of the control range. This behavior
provides the user increased accuracy when selecting a shorter delay/advance duration.
When the PWM outputs are delayed relative to the SR outputs (VADJ < 2.425V), the delay time should not exceed 90% of the
dead time as determined by RTD and CT.
20 SS Connect the soft-start timing capacitor between this pin and GND to control the duration of soft-start. The value of the
capacitor and the internal current source determine the rate of increase of the duty cycle during start-up.
SS may also be used to inhibit the outputs by grounding through a small transistor in an open collector/drain configuration.
Pin Descriptions (Continued)
PIN
NUMBER
PIN
NAME DESCRIPTION
FN6754 Rev 2.00 Page 4 of 20
June 2, 2016
ISL6754
Functional Block Diagram
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
PWM
STEERING
LOGIC
IOUT
UVLO
OVER-
TEMPERATURE
PROTECTION
VREF
OSCILLATOR
CT
RTD
VDD
GND
VREF
+
-
+
-
0.6V
0.33
80mV
VREF
SOFT-START
CONTROL
VREF
VERR
FB
1 mA
SS
CS
PWM
COMPARATOR
+
-1.00V
OVERCURRENT
COMPARATOR
+70 nS
LEADING
EDGE
BLANKING
SAMPLE
AND
HOLD
4X
RAMP
CTBUF
RESDEL
50%
PWM
OUTLL
OUTLR
OUTUL
OUTUR
VDD
OUTLLN
OUTLRN
DELAY/
ADVANCE
TIMING
CONTROL
VADJ
FN6754 Rev 2.00 Page 5 of 20
June 2, 2016
ISL6754
Typical Application - High Voltage Input Primary Side Control ZVS Full-Bridge Converter
FIGURE 2. HIGH VOLTAGE INPUT PRIMARY SIDE CONTROL ZVS FULL-BRIDGE CONVERTER
VI N+
VI N-
RETURN
T2
R4
C15
40 0 VD C
U1
L1
T1
R2
R6
+ VOUT
C16
C1
Q2
Q3
R16R15
R18
R17
C11
C5
C4
C3
C2
C14
C13
T3
Q5A
Q5B
Q8A
Q8B
CR3
CR2
+
+
Q6A
Q6B
Q7A
Q7B
VDD
R25
R24
C18
C17
U3
TL431
R23
R19
R20
Q9A
Q9B
Q10A
Q10B
U2
CR1
Q1
Q4
R1
R3
C7
U5
T4
C12
R7
R8
R9 R10
R21
R22
CR4
Q12
Q13
EL 72 12
EL 72 12
C6
U4
RTD
SS
CT
OUTUR
OUTUL
CTBUF
OUTLRRESD E L
RAMP
OUTLL
VDD
VE RR
VREF
CS
GND
1
2
4
3
5
6
7
8
19
20
11
12
13
14
15
16
IOUT
FB
OUTLLN
OUTLRN9
10
17
18
VADJ
BIAS
R5
R11
R12
R13
R14
C8
C9
C10
U1
IS L6754
FN6754 Rev 2.00 Page 6 of 20
June 2, 2016
ISL6754
Typical Application - High Voltage Input Secondary Side Control ZVS Full-Bridge Converter
(20 ld QSOP)
FIGURE 3. HIGH VOLTAGE INPUT SECONDARY SIDE CONTROL ZVS FULL-BRIDGE CONVERTER(20 LD QSOP)
VIN+
VIN-
RETURN
T2
R4
C2
400 VDC
U1
L1
T1
Np:Ns:Ns=9:2:2
R2
R12
+ Vout
C15
C1
Q2
Q3
R18
R17
R20
R19
C5C3
C12
C14
C13
T3
1:1:1
Q5
CR3
CR2
+
+
SECONDARY
BIAS SUPPLY
R25
R24
C17
C16
U3
R23
Q9A
Q9B
Q10A
Q10B
CR1
Q1
Q4
R1
R3
C4
R10
R6
Q16
Q15
C9
Q12A
Q12B
Q11A
Q11B
R16
CR5
R15
CR4
Q13A
Q13B
Q14A
Q14B
Q7A
Q7B
C10
Q8A
Q8B
Q6
T4
1:1:1
C11
Np
Ns
Ns
C8
+
-
VREF
R22
R21
C18
VREF
RTD
SS
CT
OUTUR
OUTUL
CTBUF
OUTLRRESDEL
RAMP
OUTLL
VDD
VERR
VREF
CS
GND
1
2
4
3
5
6
7
8
19
20
11
12
13
14
15
16
IOUT
FB
OUTLLN
OUTLRN9
10
17
18
VADJ
R5
R7
R8
R9
R11
R13
R14
CR6
C6
C7
ISL6754
ISL6754
FN6754 Rev 2.00 Page 7 of 20
June 2, 2016
Absolute Maximum Ratings Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to +22.0V
OUTxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to VDD
Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to VREF + 0.3V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1A
Latch-Up (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level B at +85°C
Operating Conditions
Temperature Range
ISL6754AAxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . . . 9VDC to 16VDC
Thermal Resistance Junction to Ambient (Typical) JA (°C/W)
20 Lead QSOP (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. All voltages are with respect to GND.
6. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are using a pulse limited to 50mA.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 4
and “Typical Application schematics” beginning on page 5. 9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF, TA= -40°C to +105°C, Typical values are at
TA= +25°C; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
Supply Voltage - - 20 V
Start-Up Current, IDD VDD = 5.0V - 175 400 µA
Operating Current, IDD RLOAD, COUT = 0 - 11.0 15.5 mA
UVLO START Threshold 8.00 8.75 9.00 V
UVLO STOP Threshold 6.50 7.00 7.50 V
Hysteresis -1.75-V
REFERENCE VOLTAGE
Overall Accuracy IVREF = 0mA to -10mA 4.850 5.000 5.150 V
Long Term Stability TA = +125°C, 1000 hours (Note 7)-3-mV
Operational Current (source) -10 - - mA
Operational Current (sink) 5- -mA
Current Limit VREF = 4.85V -15 - -100 mA
CURRENT SENSE
Current Limit Threshold VERR = VREF 0.97 1.00 1.03 V
CS to OUT Delay Excl. LEB - 35 - ns
Leading Edge Blanking (LEB) Duration - 70 - ns
CS to OUT Delay + LEB TA = +25°C - - 150 ns
CS Sink Current Device Impedance VCS = 1.1V - - 20 Ω
Input Bias Current VCS = 0.3V -1.0 - 1.0 µA
IOUT Sample and Hold Buffer Amplifier Gain TA = +25°C 3.85 4.00 4.15 V/V
IOUT Sample and Hold VOH VCS = max, ILOAD = -300µA 3.9 - - V
IOUT Sample and Hold VOL VCS = 0.00V, ILOAD = 10µA - - 0.3 V
ISL6754
FN6754 Rev 2.00 Page 8 of 20
June 2, 2016
RAMP
RAMP Sink Current Device Impedance VRAMP = 1.1V - - 20 W
RAMP to PWM Comparator Offset TA = +25°C 65 80 95 mV
Bias Current VRAMP = 0.3V -5.0 - -2.0 µA
PULSE WIDTH MODULATOR
Minimum Duty Cycle VERR < 0.6V - - 0 %
Maximum Duty Cycle (per half-cycle) VERR = 4.20V, VCS = 0V (Note 8)-94-%
RTD = 2.00kΩ, CT = 220pF - 97 - %
RTD = 2.00kΩ, CT = 470pF - 99 - %
Zero Duty Cycle VERR Voltage 0.85 - 1.20 V
VERR to PWM Comparator Input Offset TA = +25°C 0.7 0.8 0.9 V
VERR to PWM Comparator Input Gain 0.31 0.33 0.35 V/V
Common-Mode (CM) Input Range (Note 7)0-4.45V
ERROR AMPLIFIER
Input Common-Mode (CM) Range (Note 7)0-V
REF V
GBWP (Note 7)5--MHz
VERR VOL ILOAD = 2mA - - 0.4 V
VERR VOH ILOAD = 0mA 4.20 - - V
VERR Pull-Up Current Source VERR = 2.5V 0.8 1.0 1.3 mA
EA Reference TA = +25°C 0.594 0.600 0.606 V
EA Reference + EA Input Offset Voltage 0.590 0.600 0.612 V
OSCILLATOR
Frequency Accuracy, Overall (Note 7) 165 183 201 kHz
-10 - 10 %
Frequency Variation with VDD TA = +25°C, (F20V- - F10V)/F10V - 0.3 1.7 %
Temperature Stability VDD = 10V, |F-40°C - F0°C|/F0°C -4.5-%
|F0°C - F105°C|/F25°C (Note 7)-1.5-%
Charge Current TA = +25°C -193 -200 -207 µA
Discharge Current Gain 19 20 23 µA/µA
CT Valley Voltage Static Threshold 0.75 0.80 0.88 V
CT Peak Voltage Static Threshold 2.75 2.80 2.88 V
CT Peak-to-Peak Voltage Static Value 1.92 2.00 2.05 V
RTD Voltage 1.97 2.00 2.03 V
RESDEL Voltage Range 0 - 2.00 V
CTBUF Gain (VCTBUFP-P/VCTP-P)V
CT = 0.8V, 2.6V 1.95 2.00 2.05 V/V
CTBUF Offset from GND VCT = 0.8V 0.34 0.40 0.44 V
CTBUF VOH V(ILOAD = 0mA, ILOAD = -2mA), VCT = 2.6V - - 0.10 V
CTBUF VOL V(ILOAD = 2mA, ILOAD = 0mA), VCT = 0.8V - - 0.10 V
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 4
and “Typical Application schematics” beginning on page 5. 9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF, TA= -40°C to +105°C, Typical values are at
TA= +25°C; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested. (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISL6754
FN6754 Rev 2.00 Page 9 of 20
June 2, 2016
SOFT-START
Charging Current SS = 3V -60 -70 -80 µA
SS Clamp Voltage 4.410 4.500 4.590 V
SS Discharge Current SS = 2V 10 - - mA
Reset Threshold Voltage TA = +25°C 0.23 0.27 0.33 V
OUTPUT
High Level Output Voltage (VOH)I
OUT = -10mA, VDD - VOH -0.51.0V
Low Level Output Voltage (VOL)I
OUT = 10mA, VOL - GND - 0.5 1.0 V
Rise Time COUT = 220pF, VDD = 15V (Note 7) - 110 200 ns
Fall Time COUT = 220pF, VDD = 15V (Note 7) - 90 150 ns
UVLO Output Voltage Clamp VDD = 7V, ILOAD = 1mA (Note 9)--1.25V
Output Delay/Advance Range
OUTLLN/OUTLRN relative to OUTLL/OUTLR
VADJ = 2.50V - 2 - ns
VADJ < 2.425V -40 - -300 ns
VADJ > 2.575V 40 - 300 ns
Delay/Advance Control Voltage Range
OUTLLN/OUTLRN relative to OUTLL/OUTLR
OUTLxN Delayed 2.575 - 5.000 V
OUTLxN Advanced 0 - 2.425 V
VADJ Delay Time TA = +25°C (OUTLx Delayed) (Note 10)
VADJ = 0 - 300 - ns
VADJ = 0.5V - 105 - ns
VADJ = 1.0V - 70 - ns
VADJ = 1.5V - 55 - ns
VADJ = 2.0V - 50 - ns
TA = +25°C (OUTLxN Delayed)
VADJ = VREF - 300 - ns
VADJ = VREF - 0.5V - 100 - ns
VADJ = VREF - 1.0V - 68 - ns
VADJ = VREF - 1.5V - 55 - ns
VADJ = VREF - 2.0V - 48 - ns
THERMAL PROTECTION
Thermal Shutdown (Note 7)-140-°C
Thermal Shutdown Clear (Note 7)-125-°C
Hysteresis, Internal Protection (Note 7) - 15 - °C
NOTES:
7. Limits established by characterization and are not production tested.
8. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained using
other values for these components. See Equations 1 through 3.
9. Adjust VDD below the UVLO stop threshold prior to setting at 7V.
10. When OUTLx is delayed relative to OUTLxN (VADJ < 2.425V), the delay duration as set by VADJ should not exceed 90% of the CT discharge time (dead
time) as determined by CT and RTD.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 4
and “Typical Application schematics” beginning on page 5. 9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF, TA= -40°C to +105°C, Typical values are at
TA= +25°C; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested. (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISL6754
FN6754 Rev 2.00 Page 10 of 20
June 2, 2016
Typical Performance Curves
FIGURE 4. REFERENCE VOLTAGE vs TEMPERATURE FIGURE 5. CT DISCHARGE CURRENT GAIN vs RTD CURRENT
FIGURE 6. DEAD TIME (DT) vs CAPACITANCE FIGURE 7. CAPACITANCE vs FREQUENCY
-40 -25 -10 5 20 35 50 65 80 95 110
0.98
0.99
1
1.01
1.02
TEMPERATURE (°C)
NORMALIZED VREF
0 200 400 600 800 1000
18
19
20
21
22
23
24
25
RTD CURRENT (µA)
CT DISCHARGE CURRENT GAIN
0 102030405060708090100
10
100
RTD (kΩ)
DEAD TIME (ns)
1-104
1-103
CT = 1000pF
CT = 680pF
CT = 470pF
CT = 100pF
CT = 220pF
CT = 330pF
CT = 1000pF
CT = 680pF
CT = 470pF
CT = 100pF
CT = 220pF
CT = 330pF
0.1 1 10
10
100
CT (nF)
FREQUENCY (kHz)
1-103
RTD = 100kΩ
RTD = 50kΩ
RTD = 10kΩ
ISL6754
FN6754 Rev 2.00 Page 11 of 20
June 2, 2016
Functional Description
Features
The ISL6754 PWM is an excellent choice for low cost ZVS full-
bridge applications requiring adjustable synchronous rectifier
drive. With its many protection and control features, a highly
flexible design with minimal external components is possible.
Among its many features are a very accurate overcurrent limit
threshold, thermal protection, a buffered sawtooth oscillator
output suitable for slope compensation, synchronous rectifier
outputs with variable delay/advance timing, and adjustable
frequency.
If synchronous rectification is not required, please consider the
ISL6755 controller.
Oscillator
The ISL6754 has an oscillator with a programmable frequency
range to 2MHz, which can be programmed with a resistor and
capacitor.
The switching period is the sum of the timing capacitor charge
and discharge durations. The charge duration is determined by
CT and a fixed 200µA internal current source. The discharge
duration is determined by RTD and CT.
Where tC and tD are the charge and discharge times,
respectively, CT is the timing capacitor in Farads, RTD is the
discharge programming resistance in ohms, tSW is the oscillator
period, and fSW is the oscillator frequency. One output switching
cycle requires two oscillator cycles. The actual times will be
slightly longer than calculated due to internal propagation delays
of approximately 10ns/transition. This delay adds directly to the
switching duration, but also causes overshoot of the timing
capacitor peak and valley voltage thresholds, effectively
increasing the peak-to-peak voltage on the timing capacitor.
Additionally, if very small discharge currents are used, there will
be increased error due to the input impedance at the CT pin. The
maximum recommended current through RTD is 1mA, which
produces a CT discharge current of 20mA.
The maximum duty cycle, D, and percent Dead Time, DT, can be
calculated from:
Overcurrent Operation
Two overcurrent protection mechanisms are available to the
power supply designer. The first method is cycle-by-cycle peak
overcurrent protection which provides fast response. The
cycle-by-cycle peak current limit results in pulse-by-pulse duty cycle
reduction when the current feedback signal exceeds 1.0V. When
the peak current exceeds the threshold, the active output pulse is
immediately terminated. This results in a decrease in output
voltage as the load current increases beyond the current limit
threshold. The ISL6754 operates continuously in an overcurrent
condition without shutdown.
The second method is a slower, averaging method which
produces constant or “brick-wall” current limit behavior. If
voltage-mode control is used, the average overcurrent protection
also maintains flux balance in the transformer by maintaining
duty cycle symmetry between half-cycles. If voltage-mode control
is used in a bridge topology, it should be noted that peak current
limit results in inherently unstable operation. The DC blocking
capacitors used in voltage-mode bridge topologies become
unbalanced, as does the flux in the transformer core. Average
current limit will prevent the instability and allow continuous
operation in current limit provided the control loop is designed
with adequate bandwidth.
The propagation delay from CS exceeding the current limit
threshold to the termination of the output pulse is increased by
the Leading Edge Blanking (LEB) interval. The effective delay is
the sum of the two delays and is nominally 105ns.
The current sense signal applied to the CS pin connects to the
peak current comparator and a sample and hold averaging
circuit. After a 70ns Leading Edge Blanking (LEB) delay, the
current sense signal is actively sampled during the on time, the
average current for the cycle is determined, and the result is
amplified by 4x and output on the IOUT pin. If an RC filter is
placed on the CS input, its time constant should not exceed
~50ns or significant error may be introduced on IOUT.
Figure 8 on page 11 shows the relationship between the CS
signal and IOUT under steady state conditions. IOUT is 4x the
tC11.5 103CT S(EQ. 1)
tD0.06 RTD CT50 10 9–
+S(EQ. 2)
tSW tCtD
+1
fSW
----------
== S(EQ. 3)
D
tC
tSW
----------
=(EQ. 4)
DT 1 D–= (EQ. 5)
FIGURE 8. CS INPUT vs IOUT
CHANNEL 1 (YELLOW): OUTLL
CHANNEL 3 (BLUE): CS
CHANNEL 2 (RED): OUTLR
CHANNEL 4 (GREEN): IOUT
ISL6754
FN6754 Rev 2.00 Page 12 of 20
June 2, 2016
average of CS. Figure 9 shows the dynamic behavior of the
current averaging circuitry when CS is modulated by an external
sine wave. Notice IOUT is updated by the sample and hold
circuitry at the termination of the active output pulse.
The average current signal on IOUT remains accurate provided
the output inductor current remains continuous (CCM operation).
Once the inductor current becomes discontinuous (DCM
operation), IOUT represents 1/2 the peak inductor current rather
than the average current. This occurs because the sample and
hold circuitry is active only during the on time of the switching
cycle. It is unable to detect when the inductor current reaches
zero during the off time.
If average overcurrent limit is desired, IOUT may be used with the
error amplifier of the ISL6754. Typically IOUT is divided down and
filtered as required to achieve the desired amplitude. The
resulting signal is input to the current error amplifier (IEA). The
IEA is similar to the voltage EA found in most PWM controllers,
except it cannot source current. Instead, VERR has a separate
internal 1mA pull-up current source.
Configure the IEA as an integrating (Type I) amplifier using the
internal 0.6V reference. The voltage applied at FB is integrated
against the 0.6V reference. The resulting signal, VERR, is applied
to the PWM comparator where it is compared to the sawtooth
voltage on RAMP. If FB is less than 0.6V, the IEA will be open loop
(can’t source current), VERR will be at a level determined by the
voltage loop, and the duty cycle is unaffected. As the output load
increases, IOUT will increase, and the voltage applied to FB will
increase until it reaches 0.6V. At this point the IEA will reduce
VERR as required to maintain the output current at the level that
corresponds to the 0.6V reference. When the output current
again drops below the average current limit threshold, the IEA
returns to an open loop condition, and the duty cycle is again
controlled by the voltage loop.
The average current control loop behaves much the same as the
voltage control loop found in typical power supplies except it
regulates current rather than voltage.
The EA available on the ISL6754 may also be used as the voltage
EA for the voltage feedback control loop rather than the current
EA as described above. An external op-amp may be used as
either the current or voltage EA providing the circuit is not
allowed to source current into VERR. The external EA must only
sink current, which may be accomplished by adding a diode in
series with its output.
The 4x gain of the sample and hold buffer allows a range of 150
to 1000mV peak on the CS signal, depending on the resistor
divider placed on IOUT. The overall bandwidth of the average
current loop is determined by the integrating current EA
compensation and the divider on IOUT.
The current EA cross-over frequency, assuming R6 >> (R4||R5),
is:
Where fCO is the cross-over frequency. A capacitor in parallel with
R4 may be used to provide a double-pole roll-off.
The average current loop bandwidth is normally set to be much
less than the switching frequency, typically less than 5kHz and
often as slow as a few hundred hertz or less. This is especially
useful if the application experiences large surges. The average
current loop can be set to the steady state overcurrent threshold
and have a time response that is longer than the required
transient. The peak current limit can be set higher than the
expected transient so that it does not interfere with the transient,
but still protects for short-term larger faults. In essence a 2-stage
overcurrent response is possible.
The peak overcurrent behavior is similar to most other PWM
controllers. If the peak current exceeds 1.0V, the active output
pulse is terminated immediately.
If voltage-mode control is used in a bridge topology, it should be
noted that peak current limit results in inherently unstable
operation. DC blocking capacitors used in voltage-mode bridge
topologies become unbalanced, as does the flux in the
transformer core. The average overcurrent circuitry prevents this
behavior by maintaining symmetric duty cycles for each
FIGURE 9. DYNAMIC BEHAVIOR OF CS vs IOUT
CHANNEL 1 (YELLOW): OUTLL
CHANNEL 3 (BLUE): CS
CHANNEL 2 (RED): OUTLR
CHANNEL 4 (GREEN): IOUT
FIGURE 10. AVERAGE OVERCURRENT IMPLEMENTATION
fCO
1
2R6C10

---------------------------------
=Hz (EQ. 6)
ISL6754
FN6754 Rev 2.00 Page 13 of 20
June 2, 2016
half-cycle. If the average current limit circuitry is not used, a
latching overcurrent shutdown method using external
components is recommended.
The CS to output propagation delay is increased by the Leading
Edge Blanking (LEB) interval. The effective delay is the sum of
the two delays and is 130ns maximum.
Voltage Feed Forward Operation
Voltage feed forward is a technique used to regulate the output
voltage for changes in input voltage without the intervention of
the control loop. Voltage feed forward is implemented in
voltage-mode control loops, but is redundant and unnecessary in
peak current-mode control loops.
Voltage feed forward operates by modulating the sawtooth ramp
in direct proportion to the input voltage. Figure 11 demonstrates
the concept.
Input voltage feed forward may be implemented using the RAMP
input. An RC network connected between the input voltage and
ground, as shown in Figure 12, generates a voltage ramp whose
charging rate varies with the amplitude of the source voltage. At
the termination of the active output pulse, RAMP is discharged to
ground so that a repetitive sawtooth waveform is created. The
RAMP waveform is compared to the VERR voltage to determine
duty cycle. The selection of the RC components depends upon
the desired input voltage operating range and the frequency of
the oscillator. In typical applications, the RC components are
selected so that the ramp amplitude reaches 1.0V at minimum
input voltage within the duration of one half-cycle.
The charging time of the ramp capacitor is:
For optimum performance, the maximum value of the capacitor
should be limited to 10nF. The maximum DC current through the
resistor should be limited to 2mA maximum. For example, if the
oscillator frequency is 400kHz, the minimum input voltage is
300V, and a 4.7nF ramp capacitor is selected, the value of the
resistor can be determined by rearranging Equation 7.
Where t is equal to the oscillator period minus the dead time. If
the dead time is short relative to the oscillator period, it can be
ignored for this calculation.
If feed forward operation is not desired, the RC network may be
connected to VREF rather than the input voltage. Alternatively, a
resistor divider from CTBUF may be used as the sawtooth signal.
Regardless, a sawtooth waveform must be generated on RAMP
as it is required for proper PWM operation.
Gate Drive
The ISL6754 outputs are capable of sourcing and sinking 10mA
(at rated VOH, VOL) and are intended to be used in conjunction
with integrated FET drivers or discrete bipolar totem pole drivers.
The typical on resistance of the outputs is 50Ω.
FIGURE 11. VOLTAGE FEED FORWARD BEHAVIOR
VIN
ERROR VOLTAGE
RAMP
CT
OUTLL, LR
R3
C7
RAMP
GND
1
2
4
3
5
6
7
8
19
20
11
12
13
14
15
16
ISL6754
9
10
17
18
VIN
FIGURE 12. VOLTAGE FEED FORWARD CONTROL
tR
3C71
VRAMP PEAK
VIN MIN
----------------------------------------
–



ln–= S(EQ. 7)
R3
t–
C71
VRAMP PEAK
VIN MIN
----------------------------------------
–



ln
-------------------------------------------------------------------------2.5–10 6–
4.7 10 9–11
300
----------
–


ln
------------------------------------------------------------
==
159=k(EQ. 8)
ISL6754
FN6754 Rev 2.00 Page 14 of 20
June 2, 2016
Slope Compensation
Peak current-mode control requires slope compensation to
improve noise immunity, particularly at lighter loads, and to
prevent current loop instability, particularly for duty cycles
greater than 50%. Slope compensation may be accomplished by
summing an external ramp with the current feedback signal or by
subtracting the external ramp from the voltage feedback error
signal. Adding the external ramp to the current feedback signal is
the more popular method.
From the small signal current-mode model [1] it can be shown
that the naturally-sampled modulator gain, Fm, without slope
compensation, is:
Where Sn is the slope of the sawtooth signal and tSW is the
duration of the half-cycle. When an external ramp is added, the
modulator gain becomes:
Where Se is slope of the external ramp and:
The criteria for determining the correct amount of external ramp
can be determined by appropriately setting the damping factor of
the double-pole located at half the oscillator frequency. The
double-pole will be critically damped if the Q-factor is set to 1,
and over-damped for Q > 1, and under-damped for Q < 1. An
under-damped condition can result in current loop instability.
Where D is the percent of on time during a half cycle. Setting
Q = 1 and solving for Se yields:
Since Sn and Se are the on time slopes of the current ramp and
the external ramp, respectively, they can be multiplied by tON to
obtain the voltage change that occurs during tON.
Where Vn is the change in the current feedback signal during the
on time and Ve is the voltage that must be added by the external
ramp.
Vn can be solved for in terms of input voltage, current transducer
components, and output inductance yielding:
Where RCS is the current sense burden resistor, NCT is the
current transformer turns ratio, LO is the output inductance, VO is
the output voltage, and NS and NP are the secondary and
primary turns, respectively.
The inductor current, when reflected through the isolation
transformer and the current sense transformer to obtain the
current feedback signal at the sense resistor yields:
Where VCS is the voltage across the current sense resistor and IO
is the output current at current limit.
Since the peak current limit threshold is 1.00V, the total current
feedback signal plus the external ramp voltage must sum to this
value.
Substituting Equations 15 and 16 into Equation 17 and solving
for RCS yields:
For simplicity, idealized components have been used for this
discussion, but the effect of magnetizing inductance must be
considered when determining the amount of external ramp to
add. Magnetizing inductance provides a degree of slope
compensation to the current feedback signal and reduces the
amount of external ramp required. The magnetizing inductance
adds primary current in excess of what is reflected from the
inductor current in the secondary.
Where VIN is the input voltage that corresponds to the duty cycle
D and Lm is the primary magnetizing inductance. The effect of
the magnetizing current at the current sense resistor, RCS, is:
If VCS is greater than or equal to Ve, then no additional slope
compensation is needed and RCS becomes:
If VCS is less than Ve, then Equation 16 is still valid for the value
of RCS, but the amount of slope compensation added by the
external ramp must be reduced by VCS.
Adding slope compensation may be accomplished in the
ISL6754 using the CTBUF signal. CTBUF is an amplified
representation of the sawtooth signal that appears on the CT pin.
It is offset from ground by 0.4V and is 2x the peak-to-peak
Fm 1
SntSW
-------------------
=(EQ. 9)
Fm 1
Sn Se+tSW
--------------------------------------1
mcSntSW
---------------------------
== (EQ. 10)
mc1Se
Sn
-------
+= (EQ. 11)
Q1
mc1D–0.5–
-------------------------------------------------
=(EQ. 12)
SeSn
1
---0.5+


1
1D–
------------- 1–


=(EQ. 13)
VeVn
1
---0.5+


1
1D–
------------- 1–


=(EQ. 14)
Ve
tSW VORCS
NCT LO
----------------------------------------NS
NP
--------
1
---D0.5–+


=V(EQ. 15)
VCS
NSRCS
NPNCT
------------------------ IO
DtSW
2LO
------------------- VIN
NS
NP
--------
VO
–



+



=V(EQ. 16)
VeVCS
+1=(EQ. 17)
RCS
NPNCT
NS
------------------------ 1
IO
VO
LO
--------tSW
1
---D
2
----
+


+
----------------------------------------------------
=(EQ. 18)
IP
VIN DtSW
Lm
-----------------------------
=A(EQ. 19)
VCS
IPRCS
NCT
--------------------------
=V(EQ. 20)
RCS
NCT
NS
NP
--------IO
DTSW
2LO
----------------- VIN
NS
NP
--------
VO
–



+



VIN DtSW
Lm
-----------------------------
+
------------------------------------------------------------------------------------------------------------------------------------
=
(EQ. 21)
ISL6754
FN6754 Rev 2.00 Page 15 of 20
June 2, 2016
amplitude of CT (0.4V to 4.4V). A typical application sums this
signal with the current sense feedback and applies the result to
the CS pin as shown in Figure 13.
Assuming the designer has selected values for the RC filter
placed on the CS pin, the value of R9 required to add the
appropriate external ramp can be found by superposition.
Rearranging to solve for R9 yields:
The value of RCS determined in Equation 18 or 21 must be
rescaled so that the current sense signal presented at the CS pin
is that predicted by Equation 16. The divider created by R6 and
R9 makes this necessary.
Example:
VIN = 280V
VO = 12V
LO = 2.0µH
Np/Ns = 20
Lm = 2mH
IO = 55A
Oscillator Frequency, fSW = 400kHz
Duty Cycle, D = 85.7%
NCT = 50
R6 = 499Ω
Solve for the current sense resistor, RCS, using Equation 18.
RCS = 15.1Ω.
Determine the amount of voltage, Ve, that must be added to the
current feedback signal using Equation 15.
Ve = 153mV
Next, determine the effect of the magnetizing current from
Equation 20.
VCS = 91mV
Using Equation 23, solve for the summing resistor, R9, from
CTBUF to CS.
R9 = 30.1kΩ
Determine the new value of RCS, R’CS, using Equation 24.
R’CS = 15.4Ω
The above discussion determines the minimum external ramp
that is required. Additional slope compensation may be
considered for design margin.
If the application requires dead time less than about 500ns, the
CTBUF signal may not perform adequately for slope
compensation. CTBUF lags the CT sawtooth waveform by 300ns
to 400ns. This behavior results in a non-zero value of CTBUF
when the next half-cycle begins when the dead time is short.
Under these situations, slope compensation may be added by
externally buffering the CT signal as shown in Figure 14.
Using CT to provide slope compensation instead of CTBUF
requires the same calculations, except that Equations 22 and 23
require modification. Equation 22 becomes:
and Equation 23 becomes:
FIGURE 13. ADDING SLOPE COMPENSATION
R6
C4
R9
RCS
CTBUF
RAMP
CS
GND
1
2
4
3
5
6
7
8
19
20
11
12
13
14
15
16
ISL6754
9
10
17
18
VeVCS
–
DV
CTBUF 0.4–0.4+R6
R6R9
+
------------------------------------------------------------------------------
=V(EQ. 22)
R9
DV
CTBUF 0.4–VeVCS 0.4++–R6
VeVCS
–
------------------------------------------------------------------------------------------------------------------
=
(EQ. 23)
RCS
R6R9
+
R9
---------------------RCS
=(EQ. 24)
FIGURE 14. ADDING SLOPE COMPENSATION USING CT
R6
C4
R9
RCS CT
CT
RAMP
VREF
CS
GND
1
2
4
3
5
6
7
8
19
20
11
12
13
14
15
16
ISL6754
9
10
17
18
VeVCS
–
2D R6
R6R9
+
---------------------
=V(EQ. 25)
R9
2D VeVCS
+–R6
VeVCS
–
------------------------------------------------------------
=(EQ. 26)
ISL6754
FN6754 Rev 2.00 Page 16 of 20
June 2, 2016
The buffer transistor used to create the external ramp from CT
should have a sufficiently high gain (>200) so as to minimize the
required base current. Whatever base current is required reduces
the charging current into CT and will reduce the oscillator
frequency.
ZVS Full-Bridge Operation
The ISL6754 is a full-bridge Zero-Voltage Switching (ZVS) PWM
controller that behaves much like a traditional hard-switched
topology controller. Rather than drive the diagonal bridge
switches simultaneously, the upper switches (OUTUL, OUTUR) are
driven at a fixed 50% duty cycle and the lower switches (OUTLL,
OUTLR) are pulse width modulated on the trailing edge.
To understand how the ZVS method operates one must include
the parasitic elements of the circuit and examine a full switching
cycle.
In Figure 16, the power semiconductor switches have been
replaced by ideal switch elements with parallel diodes and
capacitance, the output rectifiers are ideal, and the transformer
leakage inductance has been included as a discrete element.
The parasitic capacitance has been lumped together as switch
capacitance, but represents all parasitic capacitance in the
circuit including winding capacitance. Each switch is designated
by its position, Upper Left (UL), Upper Right (UR), Lower Left (LL),
and Lower Right (LR). The beginning of the cycle, shown in
Figure 17, is arbitrarily set as having switches UL and LR on and
UR and LL off. The direction of the primary and secondary
currents are indicated by IP and IS, respectively.
The UL - LR power transfer period terminates when switch LR
turns off as determined by the PWM. The current flowing in the
primary cannot be interrupted instantaneously, so it must find an
alternate path. The current flows into the parasitic switch
capacitance of LR and UR which charges the node to VIN and
then forward biases the body diode of upper switch UR.
The primary leakage inductance, LL, maintains the current which
now circulates around the path of switch UL, the transformer
primary, and switch UR. When switch LR opens, the output
inductor current free-wheels through both output diodes, D1 and
D2. During the switch transition, the output inductor current
assists the leakage inductance in charging the upper and lower
bridge FET capacitance.
The current flow from the previous power transfer cycle tends to
be maintained during the free-wheeling period because the
transformer primary winding is essentially shorted. Diode D1
may conduct very little or none of the free-wheeling current,
depending on circuit parasitics. This behavior is quite different
than occurs in a conventional hard-switched full-bridge topology
where the free-wheeling current splits nearly evenly between the
output diodes, and flows not at all in the primary.
This condition persists through the remainder of the half-cycle.
During the period when CT discharges, also referred to as the
dead time, the upper switches toggle. Switch UL turns off and
switch UR turns on. The actual timing of the upper switch toggle
is dependent on RESDEL, which sets the resonant delay. The
voltage applied to RESDEL determines how far in advance the
toggle occurs prior to a lower switch turning on. The ZVS
transition occurs after the upper switches toggle and before the
diagonal lower switch turns on. The required resonant delay is
1/4 of the period of the LC resonant frequency of the circuit
FIGURE 15. BRIDGE DRIVE SIGNAL TIMING
CT
DEADTIME
OUTLL
OUTLR
OUTUR
OUTUL RESDEL
WINDOW
RESONANT
DELAY
PWM
PWM
PWM
PWM
FIGURE 16. IDEALIZED FULL-BRIDGE
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
LL
D2
D1
FIGURE 17. UL - LR POWER TRANSFER CYCLE
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
IP
IS
LL
D2
D1
FIGURE 18. UL - UR FREE-WHEELING PERIOD
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
IP
IS
LL
D2
D1
ISL6754
FN6754 Rev 2.00 Page 17 of 20
June 2, 2016
formed by the leakage inductance and the parasitic capacitance.
The resonant transition may be estimated from Equation 27.
Where is the resonant transition time, LL is the leakage
inductance, CP is the parasitic capacitance, and R is the
equivalent resistance in series with LL and CP.
The resonant delay is always less than or equal to the dead time
and may be calculated using Equation 28.
Where resdel is the desired resonant delay, Vresdel is a voltage
between 0V and 2V applied to the RESDEL pin, and DT is the
dead time (see Equations 1 through 5).
When the upper switches toggle, the primary current that was
flowing through UL must find an alternate path. It
charges/discharges the parasitic capacitance of switches UL and
LL until the body diode of LL is forward biased. If RESDEL is set
properly, switch LL will be turned on at this time. The output
inductor does not assist this transition. It is purely a resonant
transition driven by the leakage inductance.
The second power transfer period commences when switch LL
closes. With switches UR and LL on, the primary and secondary
currents flow as indicated in Figure 20.
The UR - LL power transfer period terminates when switch LL
turns off as determined by the PWM. The current flowing in the
primary must find an alternate path. The current flows into the
parasitic switch capacitance which charges the node to VIN and
then forward biases the body diode of upper switch UL. As before,
the output inductor current assists in this transition. The primary
leakage inductance, LL, maintains the current, which now
circulates around the path of switch UR, the transformer primary,
and switch UL. When switch LL opens, the output inductor
current free-wheels predominantly through diode D1. Diode D2
may actually conduct very little or none of the free-wheeling
current, depending on circuit parasitics. This condition persists
through the remainder of the half-cycle.
When the upper switches toggle, the primary current that was
flowing through UR must find an alternate path. It
charges/discharges the parasitic capacitance of switches UR
and LR until the body diode of LR is forward biased. If RESDEL is
set properly, switch LR will be turned on at this time.
The first power transfer period commences when switch LR
closes and the cycle repeats. The ZVS transition requires that the
leakage inductance has sufficient energy stored to fully charge
the parasitic capacitances. Since the energy stored is
proportional to the square of the current (1/2 LLIP2), the ZVS
resonant transition is load dependent. If the leakage inductance
is not able to store sufficient energy for ZVS, a discrete inductor
may be added in series with the transformer primary.
2
---1
1
LLCP
---------------R2
4LL
2
----------
–
-----------------------------------
=(EQ. 27)
resdel
Vresdel
2
-------------------- DT=S(EQ. 28)
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
LL
D2
D1 IS
IP
FIGURE 19. UPPER SWITCH TOGGLE AND RESONANT TRANSITION
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
LL
D2
D1
FIGURE 20. UR - LL POWER TRANSFER CYCLE
FIGURE 21. UR - UL FREE-WHEELING PERIOD
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
IP
IS
LL
D2
D1
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
IP
IS
LL
D2
D1
FIGURE 22. UPPER SWITCH TOGGLE AND RESONANT TRANSITION
ISL6754
FN6754 Rev 2.00 Page 18 of 20
June 2, 2016
Synchronous Rectifier Outputs and Control
The ISL6754 provides double-ended PWM outputs, OUTLL and
OUTLR, and Synchronous Rectifier (SR) outputs, OUTLLN and
OUTLRN. The SR outputs are the complements of the PWM
outputs. It should be noted that the complemented outputs are
used in conjunction with the opposite PWM output, i.e., OUTLL
and OUTLRN are paired together and OUTLR and OUTLLN are
paired together.
Referring to Figure 23, the SRs alternate between being both on
during the free-wheeling portion of the cycle (OUTLL/LR off), and
one or the other being off when OUTLL or OUTLR is on. If OUTLL is
on, its corresponding SR must also be on, indicating that OUTLRN
is the correct SR control signal. Likewise, if OUTLR is on, its
corresponding SR must also be on, indicating that OUTLLN is the
correct SR control signal.
A useful feature of the ISL6754 is the ability to vary the phase
relationship between the PWM outputs (OUTLL, OUT LR) and the
their complements (OUTLLN, OUTLRN) by ±300ns. This feature
allows the designer to compensate for differences in the
propagation times between the PWM FETs and the SR FETs. A
voltage applied to VADJ controls the phase relationship.
Setting VADJ to VREF/2 results in no delay on any output. The no
delay voltage has a ±75mV tolerance window. Control voltages
below the VREF/2 zero delay threshold cause the PWM outputs,
OUTLL/LR, to be delayed. Control voltages greater than the
VREF/2 zero delay threshold cause the SR outputs, OUTLLN/LRN,
to be delayed. It should be noted that when the PWM outputs,
OUTLL/LR, are delayed, the CS to output propagation delay is
increased by the amount of the added delay.
The delay feature is provided to compensate for mismatched
propagation delays between the PWM and SR outputs as may be
experienced when one set of signals crosses the
primary-secondary isolation boundary. If required, individual
output pulses may be stretched or compressed as required using
external resistors, capacitors, and diodes.
When the PWM outputs are delayed, the 50% upper outputs are
equally delayed, so the resonant delay setting is unaffected.
On/Off Control
The ISL6754 does not have a separate enable/disable control pin.
The PWM outputs, OUTLL/OUTLR, may be disabled by pulling VERR
to ground. Doing so reduces the duty cycle to zero, but the upper
50% duty cycle outputs, OUTUL/OUTUR, will continue operation.
Likewise, the SR outputs OUTLLN/OUTLRN will be active high.
Pulling soft-start to ground will disable all outputs and set them
to a low condition
Fault Conditions
A fault condition occurs if VREF or VDD fall below their Undervoltage
Lockout (UVLO) thresholds or if the thermal protection is triggered.
When a fault is detected the outputs are disabled low. When the
fault condition clears the outputs are re-enabled.
An overcurrent condition is not considered a fault and does not
result in a shutdown.
Thermal Protection
Internal die over-temperature protection is provided. An
integrated temperature sensor protects the device should the
junction temperature exceed +140°C. There is approximately
+15°C of hysteresis.
FIGURE 23. BASIC WAVEFORM TIMING
CT
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
FIGURE 24. WAVEFORM TIMING WITH PWM OUTPUTS DELAYED,
0V < VADJ < 2.425V
CT
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
FIGURE 25. WAVEFORM TIMING WITH SR OUTPUTS DELAYED,
2.575V < VADJ < 5.00V
CT
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
FN6754 Rev 2.00 Page 19 of 20
June 2, 2016
ISL6754
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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© Copyright Intersil Americas LLC 2008-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device.
A good ground plane must be employed. VDD and VREF should
be bypassed directly to GND with good high frequency
capacitance.
References
[1] Ridley, R., “A New Continuous-Time Model for Current Mode
Control”, IEEE Transactions on Power Electronics, Vol. 6, No.
2, April 1991.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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Reliability reports are also available from our website at www.intersil.com/support.
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision.
DATE REVISION CHANGE
June 2, 2016 FN6754.2 Updated entire datasheet applying Intersil’s new standards.
Added Related Literature, Revision History and About Intersil sections.
Updated Note 1.
Added Note 3.
Added evaluation boards to the ordering information table on page 2.
In the “Electrical Specifications” on page 7 under the “REFERENCE VOLTAGE” section updated the test
conditions from “IVREF = 0mA to 10mA” to “IVREF = 0mA to -10mA”.
Updated POD M20.15 to the latest revision changes are as follows:
- Note 2 changed from “Dimensioning and tolerancing per ANSI Y14.5M-1982.” to “Dimensioning and
tolerancing conform to AMSE Y14.5m-1994.”
-Changed title from “20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE” to “20 LEAD QUARTER SIZE
OUTLINE PLASTIC PACKAGE (QSOP)”
- Update to new POD format by removing table with dimensions and placing dimensions on drawing
instead. Added land pattern.
ISL6754
FN6754 Rev 2.00 Page 20 of 20
June 2, 2016
Package Outline Drawing
M20.15
20 LEAD QUARTER SIZE OUTLINE PLASTIC PACKAGE (QSOP)
Rev 2, 1/11
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
0.010 (0.25)
0.007 (0.18)
8°
0.050 (1.27)
0.016 (0.41)
20
123
INDEX
AREA
(0.635 BSC)
0.025
1 2
0.025 (0.64) x 18
0.220(5.59)
SEATING PLANE
0.015 (0.38) x 20
0.060 (1.52) x 20
3
20
3
4
5
0.244 (6.19)
0.228 (5.80)
0.157 (3.98)
0.150 (3.81)
0.344 (8.74)
0.337 (8.56)
0.069 (1.75)
0.053 (1.35)
0.010 (0.25)
0.004 (0.10)
0.012 (0.30)
0.008 (0.20)
0°
0.0196 (0.49)
0.0099 (0.26)
0.061 MAX (1.54 MIL)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. Length of terminal for soldering to a substrate.
7. Terminal numbers are shown for reference only.
8. Dimension does not include dambar protrusion. Allowable
dambar protrusion shall be 0.10mm (0.004 inch) total in excess of
dimension at maximum material condition.
9. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
6
0.25
0.010
GAUGE
PLANE
8
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