Document Number: 37073
Revision 03-Aug-01
www.vishay.com
58
APD-256G064A
Vishay Dale Plasma Panel Display Module
256 x 64 Graphics Display with Drive Electronics,
+ 5V CMOS Level Video Interface and Integrated DC Converter
*Recommended operating voltages. All maximums are absolute
maximum.
FEATURES
•+ 5V CMOS level video interface (with 4.7k pull-up
resistors).
•On board DC converter.
•Slim Profile.
•Large, bright characters and graphics.
•Highly visible for long distance viewing.
ELECTRICAL SPECIFICATIONS
Voltages Required: VDC: + 12 to + 24VDC.
Vcc: + 5VDC.
Power Required: Typical = 20 watts, Maximum = 65 watts.
OPTICAL SPECIFICATIONS
Viewing Area: 15.85” W x 5.00” H.
Pixel Pitch: 0.062”.
Pixel Size: 0.038” diameter.
Color: Neon orange.
Text with typical 5x7 character matrix using 1 column
between characters and 1 row between lines.
Maximum Number of Characters per Line: 42.
Maximum Number of Lines: 16.
Luminance: 40 foot lamberts minimum.
ENVIRONMENTAL SPECIFICATIONS
Operating Temperature: 0°C to + 70°C.
Storage Temperature: - 20°C to + 85°C.
Relative Operating Humidity: To 95% non-condensing.
Mechanical Shock: 30G.
Vibration: 3G.
Operating Altitude: 10,000 feet.
GENERAL DESCRIPTION
The APD-256G064A DC Plasma display offers viewing
qualities designers seek such as high contrast, viewing
angle of 150° minimum, and long distance readability.
It is bright (40 foot lamberts minimum) with characters and
graphics figures presented in a pleasing neon orange color
against a black background. Plasma is much more read-
able and eye-pleasing than liquid crystal or vacuum fluores-
cent displays and is filterable to red, amber, or neutral
density.
These plasma display panels are driven in a standard row -
column refresh method much like a CRT display. The
designer need only supply + 5V CMOS level signals for
SERIAL DATA, DOT CLOCK, COLUMN LATCH, ROW
DATA, ROW CLOCK and DISPLAY ENABLE. The SERIAL
DATA is entered with the DOT CLOCK up to frequencies as
high as 8mHz. After a row of 256 pixels is clocked in, the
COLUMN LATCH signal is toggled and the data is latched.
At the time the data is latched, the display is briefly disabled
using the DISPLAY ENABLE signal, then the row pointer is
advanced with the ROW CLOCK signal. Once each frame
the ROW DATA must be asserted to synchronize the column
serial data with the beginning row. The recommended
scanning
frequency is approximately 70 Hz but may be as high as
200 Hz. The high clock rate on the data clock allows for
rapid refresh and maximum access time to the refresh ram.
The APD-256G064A has been designed to offer high
brightness and superior viewing aesthetics in a package that
is very affordable. This display is ideal for low to
medium level information content messages and would be
ideal for applications such as arcade games, process
control, POS terminals, medical equipment, message
centers and ATM machines.
DIMENSIONS in inches [millimeters]
18.112
8.906 8.906 0.150
DIA (6)
16.95
15.848 0.420 0.426
4.995
3.944
5.686
5.986
0.551
0.150
0.581
256 X 64 FULL FIELD
0.038 DIAMETER PIXEL
0.062 PIXEL PITCH
1.10 MAX
0.425 MAX
0.062 PCB
COMPONENT
AREA
10.511
12.236 PIN 1
STANDARD ELECTRICAL SPECIFICATIONS*
DESCRIPTION
Logic supply
DC converter input
DC converter
power @ + 12V
Logic 1 Input
Logic 0 Input
SYMBOL
Vcc
VDC
IDC
Vih
Vil
MIN.
+ 4.5
+ 10
Screen Clear
0.13
2/3Vcc
—
TYP.
+ 5.0
+ 24.0
50% Lit
2.7
—
—
MAX.
+ 5.5
+ 28.0
100% Lit
5.5
—
1/3Vcc
UNITS
VDC
VDC
ADC
VDC
VDC
0.150
www.vishay.com
59
APD-256G064A
Vishay Dale
Document Number: 37073
Revision 03-Aug-01
DESCRIPTION OF INPUT SIGNALS
DOT CLOCK - This signal enters the SERIAL DATA on each
low to high transition. A total of 256 DOT CLOCK transitions
must be present for each line of column/anode data.
SERIAL DATA - This signal presents the pixel data in
positive logic format. A logic one represents a lit pixel and a
logic zero represents an extinguished pixel. Data is entered
from right to left. The first pixel data entered will represent
the leftmost pixel in the row.
COLUMN LATCH - This signal latches the pixel data into the
driver outputs. When the COLUMN LATCH signal goes to
logic one the data entered previously will fall through to the
driver outputs. When the signal returns to a logic zero, the
data is latched and the shift register is now ready to accept
the next row of data. Must be held low while entering new
SERIAL DATA.
DISPLAY ENABLE - This signal enables the output drivers.
Using a duty cycle control, this signal may also be used for
intensity control. The DISPLAY ENABLE must be at logic
zero before the COLUMN LATCH signal transitions. To
avoid display blurring, the ROW CLOCK signal should also
transition while DISPLAY ENABLE is a logic zero. It is
recommended that this signal remain low for 10µS min.
ROW DATA - This signal is the first line marker for the scan.
This input should be held high to correspond to the first row
of pixel data.
ROW CLOCK - This signal clocks ROW DATA on the falling
edge. The ROW CLOCK signal is repetitive and must be
present for proper scanning of the display module.
The APD-256G064A has a unique input protection circuit
that assures the column drivers stay blanked on power up.
The protection circuit unblanks the column drivers when the
ROW CLOCK signal begins (i.e. the display begins
scanning).
ORDERING INFORMATION
Plasma Display Module with Drivers, CMOS Video Interface, and DC/DC Converter...............................................................APD-256G064A
Data Connector Kit...................................................................................................................................................... ................ 280105-05
Power Connector Kit................................................................................................................................................... ................ 280108-13
Video Controller (+5V) Parallel and Serial Interface.......................................................................................................................PDS-500
Video Controller (+12V) Parallel and Serial Interface................................................................................................................. PDS-500-1
PIN DESCRIPTION
P3, POWER CONNECTOR
PIN
1
2
3
4
5
DESCRIPTION
GROUND
DC Converter Supply
Logic Supply
Used to key connector
GROUND
SIGNAL
GND
VDC
Vcc
KEY
GND
AMP #640445-5 or equivalent.
(Mates with AMP 640428-5, MOLEX 09-05-3051 or equivalent.)
P2, DATA CONNECTOR
AMP #103309-2 or equivalent.
(Mates with AMP 746195-2, MOLEX 39-27-1146 or equivalent.)
DESCRIPTION
DISPLAY ENABLE
ROW DATA
ROW CLOCK
COLUMN LATCH
DOT CLOCK
SERIAL DATA
No connect
PIN
1
3
5
7
9
11
13
PIN
2
4
6
8
10
12
14
DESCRIPTION
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
Display Enable
LOGIC AND DATA TIMING
Serial Data
Dot Clock t7
1st Bit of Row Will Appear in Leftmost Column
01 2 254 255
t6
t5
Positive Edge x 256
Row Data
Row Clock
Display Enable
0
t2
t1
t4
163
62
2
1
0
6362210
t3
01
Row Clock
Column Latch
PARAMETER
t1
t2
t3
t4
t5
t6
t7
MINIMUM
100
5
1
—
25
75
75
TYPICAL
—
—
—
70
—
—
—
MAXIMUM
—
—
—
200
—
—
—
UNITS
nS
uS
uS
Hz
nS
nS
nS
