March 2010 Doc ID 12754 Rev 4 1/35
35
L6726A
Single phase PWM controller
Feature
■Flexible power supply from 5 V to 12 V
■Power conversion input as low as 1.5 V
■1% output voltage accuracy
■High-current integrated drivers
■Adjustable output voltage
■0.8 V internal reference
■Sensorless and programmable OCP across
Low-side RdsON
■Oscillator internally fixed at 270 kHz
■Programmable soft-start
■Ls-less start up
■Disable function
■FB disconnection protection
■SO-8 package
Applications
■Subsystem power supply (MCH, IOCH, PCI...)
■Memory and termination supply
■CPU and DSP power supply
■Distributed power supply
■General DC / DC converters
Table 1. Device summary
Description
L6726A is a single-phase step-down controller
with integrated high-current drivers that provides
complete control logic, protections and reference
voltage to realize in an easy and simple way
general DC-DC converters by using a compact
SO-8 package.
Device flexibility allows managing conversions
with power input VIN as low as 1.5 V and device
supply voltage ranging from 5 V to 12 V.
L6726A provides simple control loop with trans-
conductance error amplifier. The integrated 0.8 V
reference allows regulating output voltage with
±1% accuracy over line and temperature
variations. Oscillator is internally fixed to 270 kHz.
L6726A provides programmable over current
protection. Current information is monitored
across the low-side MOSFET RdsON saving the
use of expensive and space-consuming sense
resistors.
FB disconnection protection prevents excessive
and dangerous output voltages in case of floating
FB pin.
SO-8
Order codes Package Packaging
L6726A SO-8 Tube
L6726ATR SO-8 Tape and reel
www.st.com
Contents L6726A
2/35 Doc ID 12754 Rev 4
Contents
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4
1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Soft start and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1 Low-side-less start up (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2 Enable / disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1.1 Overcurrent threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2 Feedback disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.3 Undervoltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.1 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.2 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.3 Soft-start time calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.4 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.5 Embedding L6726A-based VRs… . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
L6726A Contents
Doc ID 12754 Rev 4 3/35
9 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.1 Output inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10 20 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10.1 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.1.1 Power input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.1.2 Power output (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.1.3 IC additional supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.1.4 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.1.5 Demonstration board efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11 5 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.1 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.1.1 Power input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.1.2 Power output (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.1.3 IC additional supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.1.4 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.1.5 Demonstration board efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
12 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Typical application circuit and block diagram L6726A
4/35 Doc ID 12754 Rev 4
1 Typical application circuit and block diagram
1.1 Application circuit
Figure 1. Typical application circuit
1.2 Block diagram
Figure 2. Block diagram
1
2
8
BOOT
UGATE
PHASE
LGATE
/ OC
4
HS
LS
V
IN
= 1.5V to 19V
(1)
L
C
OUT
Vout
LOAD
C
HF
C
BULK
C
DEC
GND
3
R
FB
COMP
/ DIS
7
R
F
C
F
C
P
VCC
R
OS
VCC = 5V to 12V
5
6 FB
L6726A Reference Schematic
(1) Up to 12V with Vcc > 5V
L6726A
R
OCSET
R
D
C
SN
R
SN
C
BOOT
R
gHS
R
gLS
D
VCC
BOOT
LGATE
/ OC
FB
UGATE
COMP
/ DIS
GND
ADAPTIVE ANTI
CROSS CONDUCTION
HS
LS
VCC
TRANSCONDUCTANCE
ERROR AMPLIFIER
+
-0.8V
OSCILLATOR
PWM
PHASE
CONTROL LOGIC
& PROTECTIONS
V
OCTH
DISABLE
I
SS
OCP
CLOCK S
R
Q
L6726A
I
OCSET
L6726A Pins description and connection diagrams
Doc ID 12754 Rev 4 5/35
2 Pins description and connection diagrams
Figure 3. Pins connection (top view)
2.1 Pin descriptions
Table 2. Pins descriptions
1
2
3
4
VCC
FB
COMP / DIS
PHASE
LGATE / OC
GND
UGATE
BOOT
5
6
7
8
L6726A
Pin n Name Function
1BOOT
HS driver supply.
Connect through a capacitor (100 nF) to the floating node (LS-drain) pin
and provide necessary bootstrap diode from VCC.
2 UGATE HS driver output. Connect to HS MOSFET gate.
3GND
All internal references, logic and drivers are connected to this pin.
Connect to the PCB ground plane.
4 LGATE / OC
LGATE. LS driver output. Connect to LS MOSFET gate.
OC. Over current threshold set. During a short period of time following VCC
rising over UVLO threshold, a 10μA current is sourced from this pin.
Connect to GND with an ROCSET resistor greater than 5kΩ to program OC
Threshold. The resulting voltage at this pin is sampled and held internally
as the OC set point. Maximum programmable OC threshold is 0.55 V. A
voltage greater than 0.75V (max) activates an internal clamp and causes
OC threshold to be set at 400 mV. ROCSET not connected sets the 400 mV
default threshold.
5VCC
Device and LS driver power supply.
Operative range from 4.1 V to 13.2 V. Filter with at least 1μF MLCC to GND.
6FB
Error amplifier inverting input.
Connect with a resistor RFB to the output regulated voltage. Additional
resistor ROS to GND may be used to regulate voltages higher than the
reference.
7 COMP / DIS
COMP. Error amplifier output. Connect with an RF - CF // CP to GND to
compensate the device control loop in conjunction to the FB pin.
During the soft-start phase, a 10 μA current is sourced from this pin so the
compensation capacitors also act to program the SS time.
DIS. The device can be disabled by pulling this pin lower than 0.4 V (min).
Setting free the pin, the device enables again.
8 PHASE
HS driver return path, current-reading and adaptive-dead-time monitor.
Connect to the LS drain to sense RdsON drop to measure the output current.
This pin is also used by the adaptive-dead-time control circuitry to monitor
when HS MOSFET is OFF.
Pins description and connection diagrams L6726A
6/35 Doc ID 12754 Rev 4
2.2 Thermal data
Table 3. Thermal data
Symbol Parameter Value Unit
R
thJA
Thermal resistance junction to ambient(1)
1. Measured with the component mounted on a 2S2P board in free air (6.7 cm x 6.7 cm, 35 μm (P) and
17.5 μm (S) copper thickness).
85 °C/W
T
MAX
Maximum junction temperature 150 °C
T
STG
Storage temperature range -40 to 150 °C
T
J
Junction temperature range -20 to 150 °C
L6726A Electrical specifications
Doc ID 12754 Rev 4 7/35
3 Electrical specifications
3.1 Absolute maximum ratings
Table 4. Absolute maximum ratings
3.2 Electrical characteristics
VCC = 12 V; TA = -20 °C to +85 °C unless otherwise specified.
Symbol Parameter Value Unit
VCC to GND -0.3 to 15 V
V
BOOT
to PHASE
to GND
15
45 V
V
UGATE
to PHASE
to PHASE; t < 50ns
to GND
-0.3 to (VBOOT - V
PHASE
)
+ 0.3
-1
VBOOT + 0.3
V
V
PHASE
to GND -8 to 30 V
V
LGATE
to GND
to GND; t < 50ns
-0.3 to VCC + 0.3
-2.5 V
FB, COMP to GND -0.3 to 3.6 V
Table 5. Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
Recommended operating conditions
VCC Device supply voltage See Figure 1 4.1 13.2 V
VIN Conversion input voltage
13.2 V
VCC < 7.0 V 19.0 V
Supply current and power-ON
ICC VCC supply current UGATE and LGATE = OPEN 6 mA
IBOOT BOOT supply current UGATE = OPEN; PHASE to GND 0.5 mA
UVLO VCC Turn-ON VCC rising 4.1 V
Hysteresis 0.2 V
Oscillator
FSW Main oscillator accuracy TA = 0 °C to +70 °C 243 270 297 kHz
225 270 315
ΔVOSC PWM ramp amplitude 1.1 V
dMAX Maximum duty cycle 80 %
Electrical specifications L6726A
8/35 Doc ID 12754 Rev 4
Reference
Output voltage accuracy VOUT = 0.8 V, TA = 0 °C to 70 °C -1 - 1 %
VOUT = 0.8 V -1.5 - 1.5
Transconductance error amplifier
gm Transconductance(1) 5mS
IFB Input bias current Sourced from FB 100 nA
A0Open loop gain(1) 70 dB
F0Unity gain(1) 4MHz
ICOMP Current capability Source current 360 μA
Sink current -360 μA
Soft-Start and disable
ISS Soft-start current From COMP pin 10 μA
DIS Disable threshold COMP falling 0.4 0.5 V
Gate drivers
IUGATE HS source current BOOT - PHASE = 5 V to 12 V 1.5 A
RUGATE HS sink resistance BOOT - PHASE = 5 V to 12 V 1.1 Ω
ILGATE LS source current VCC = 5 V to 12 V 1.5 A
RLGATE LS sink resistance VCC = 5 V to 12 V 0.65 Ω
Over-current protection
IOCSET OCSET current source Sourced from LGATE pin.
See Section 7.1.1 10 μA
VOC_SW OC switch-over threshold VLGATE/OC rising 780 mV
VOCTH_FIXED Fixed OC threshold VPHASE to GND -400 mV
1. Guaranteed by design, not subject to test.
Table 5. Electrical characteristics (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
L6726A Device description
Doc ID 12754 Rev 4 9/35
4 Device description
L6726A is a single-phase PWM controller with embedded high-current drivers that provides
complete control logic and protections to realize in an easy and simple way a general DC-
DC step-down converter. Designed to drive N-channel MOSFETs in a synchronous buck
topology, with its high level of integration this 8-pin device allows reducing cost and size of
the power supply solution.
L6726A is designed to operate from a 5 V or 12 V supply bus. Thanks to the high precision
0.8V internal reference, the output voltage can be precisely regulated to as low as 0.8 V with
±1% accuracy over line and temperature variations (between 0 °C and +70 °C). The
switching frequency is internally set to 270 kHz.
This device provides a simple control loop with externally compensated transconductance
error-amplifier and programmable soft start. Low-side-less feature allows the device to
perform soft-start over pre-charged output avoiding negative spikes at the load side.
In order to avoid load damages, L6726A provides programmable threshold over current
protection. Output current is monitored across low-side MOSFET RdsON, saving the use of
expensive and space-consuming sense resistor. L6726A also features FB disconnection
protection, preventing dangerous uncontrolled output voltages in case of floating FB pin.
Driver section L6726A
10/35 Doc ID 12754 Rev 4
5 Driver section
The integrated high-current drivers allow using different types of power MOSFET (also
multiple MOSFETs to reduce the equivalent RdsON), maintaining fast switching transition.
The driver for high-side MOSFET uses BOOT pin for supply and PHASE pin for return. The
driver for low-side MOSFET uses the VCC pin for supply and GND pin for return.
The controller embodies an anti-shoot-through and adaptive dead-time control to minimize
low side body diode conduction time, maintaining good efficiency while saving the use of
Schottky diode:
●to check for high-side MOSFET turn off, PHASE pin is sensed. When the voltage at
PHASE pin drops down, the low-side MOSFET gate drive is suddenly applied;
●to check for low-side MOSFET turn off, LGATE pin is sensed. When the voltage at
LGATE has fallen, the high-side MOSFET gate drive is suddenly applied.
If the current flowing in the inductor is negative, voltage on PHASE pin will never drop. To
allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if
the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so
allowing the negative current of the inductor to recirculate. This mechanism allows the
system to regulate even if the current is negative.
Power conversion input is flexible: 5 V, 12 V bus or any bus that allows the conversion (See
maximum duty cycle limitation and recommended operating conditions) can be chosen
freely.
L6726A Driver section
Doc ID 12754 Rev 4 11/35
5.1 Power dissipation
L6726A embeds high current MOSFET drivers for both high side and low side MOSFETs: it
is then important to consider the power that the device is going to dissipate in driving them
in order to avoid overcoming the maximum junction operative temperature.
Two main terms contribute in the device power dissipation: bias power and drivers power.
●Device bias power (PDC) depends on the static consumption of the device through the
supply pins and it is simply quantifiable as follow (assuming to supply HS and LS
drivers with the same VCC of the device):
●Drivers power is the power needed by the driver to continuously switch on and off the
external MOSFETs; it is a function of the switching frequency, the voltage supply of the
driver and total gate charge of the selected MOSFETs. It can be quantified considering
that the total power PSW dissipated to switch the MOSFETs (easy calculable) is
dissipated by three main factors: external gate resistance (when present), intrinsic
MOSFET resistance and intrinsic driver resistance. This last term is the important one
to be determined to calculate the device power dissipation. The total power dissipated
to switch the MOSFETs results:
where VBOOT - VPHASE is the voltage across the bootstrap capacitor.
External gate resistors helps the device to dissipate the switching power since the same
power PSW will be shared between the internal driver impedance and the external resistor
resulting in a general cooling of the device.
Figure 4. Soft start (left) and disable (right)
PDC VCC ICC IBOOT
+()⋅=
PSW FSW QgHS VBOOT VPHASE
–()QgLS VCC
⋅+⋅[]⋅=
Soft start and disable L6726A
12/35 Doc ID 12754 Rev 4
6 Soft start and disable
L6726A implements a soft start to smoothly charge the output filter avoiding high in-rush
currents to be required from the input power supply. The device sources a 10 µA soft start
current from COMP, linearly charging the compensation network capacitors. The ramping
COMP voltage is compared to the oscillator triangular waveform generating PWM pulses of
increasing width that charge the output capacitors.
When the FB voltage crosses 800 mV, the output voltage is in regulation: soft start phase
will end and the transconductance error amplifier output will be enabled closing the control
loop.
In the event of an over current during soft start, the over current logic will override the soft
start sequence and will shut down the PWM logic and both the high side and low side gates.
This condition is latched, cycle VCC to recover.
The device sources soft start current only when VCC power supply is above UVLO
threshold and over current threshold setting phase has been completed.
6.1 Low-side-less start up (LSLess)
L6726A performs a special sequence in enabling LS driver to switch: during the soft-start
phase, the LS driver results disabled (LS = OFF) until the HS starts to switch. This avoids
the dangerous negative spike on the output voltage that can happen if starting over a pre-
charged output and limits the output discharge (amount of output discharge depends on
programmed SS time length: the shorter the programmed SS, the more limited the output
discharge).
If the output voltage is pre-charged to a voltage higher than the final one, the HS would
never start to switch. In this case, LS is enabled and discharges the output to the final
regulation value.
Figure 5. LSLess startup (left) vs non-LSLess startup (right)
6.2 Enable / disable
The device can be disabled by pushing COMP / DIS pin under 0.4 V (min). In this condition
HS and LS MOSFETs are turned off, and the 10 μA SS current is sourced from COMP / DIS
pin. Setting free the pin, the device enables again performing a new SS.
L6726A Protections
Doc ID 12754 Rev 4 13/35
7 Protections
7.1 Overcurrent protection
The overcurrent feature protects the converter from a shorted output or overload, by sensing
the output current information across the low side MOSFET drain-source on-resistance,
RdsON. This method reduces cost and enhances converter efficiency by avoiding the use of
expensive and space-consuming sense resistors.
The low side RdsON current sense is implemented by comparing the voltage at the PHASE
node when LS MOSFET is turned on with the programmed OCP threshold voltage,
internally held. If the monitored voltage drop (GND to PHASE) exceeds this threshold, an
Overcurrent event is detected. If two overcurrent events are detected in two consecutive
switching cycles, the protection will be triggered and the device will turn off both LS and HS
MOSFETs in a latched condition.
To recover from over current protection triggered, VCC power supply must be cycled.
7.1.1 Overcurrent threshold setting
L6726A allows to easily program an overcurrent threshold ranging from 50 mV to 550 mV,
simply by adding a resistor (ROCSET) between LGATE and GND.
During a short time following VCC rising over UVLO threshold, an internal 10µA current
(IOCSET) is sourced from LGATE pin, determining a voltage drop across ROCSET
. This
voltage drop will be sampled and internally held by the device as overcurrent Threshold. The
OC setting procedure overall time length ranges from 5.5 ms to 6.5 ms, proportionally to the
threshold being set.
Connecting a ROCSET resistor between LGATE and GND, the programmed threshold will be:
ROCSET values range from 5 kΩ to 55 kΩ.
If the voltage drop across ROCSET is too low, the system will be very sensitive to start-up
inrush current and noise. This can result in undesired OCP triggering. In this case, consider
increasing ROCSET value.
In case ROCSET is not connected, the device switches the OCP threshold to a 400 mV
default value: an internal safety clamp on LGATE is triggered as soon as LGATE voltage
reaches 700 mV (typ), enabling the 400 mV default threshold and suddenly ending OC
setting phase.
See Figure 6 for OC threshold setting procedure timings picture and oscilloscope sample
waveforms.
7.2 Feedback disconnection protection
In order to provide load protection even if FB pin is not connected, a 100 nA bias current is
always sourced from this pin. If FB pin is not connected, bias current will permanently pull
up FB: this forces COMP pin low, avoiding output voltage rising to dangerous levels.
IOCth
IOCSET ROCSET
⋅
RdsON
--------------------------------------------=
Protections L6726A
14/35 Doc ID 12754 Rev 4
Figure 6. OC threshold setting procedure timings (top) and waveforms (bottom)
7.3 Undervoltage lock out
In order to avoid anomalous behaviors of the device when the supply voltage is too low to
support its internal rails, UVLO is provided: the device will start up when VCC reaches
UVLO upper threshold and will shutdown when VCC drops below UVLO lower threshold.
The 4.1 V maximum UVLO upper threshold allows L6726A to be supplied from 5 V and 12 V
busses in or-ing diode configuration.
Figure 7. OCP trip, default threshold, LS: STD38NH02L (left) UVLO turn off (right)
VCC
Enable Th
COMP
700mV
LGATE
PWM ramp
bottom edge
UVLO Th
R
OCSET
not connected
Setting Procedure
VCC
Enable Th
COMP
700mV
LGATE
PWM ramp
bottom edge
UVLO Th
5.5ms - 6.5ms
R
OCSET
connected
Setting Procedure t
DELAY
t
DELAY
L6726A Application details
Doc ID 12754 Rev 4 15/35
8 Application details
8.1 Output voltage selection
L6726A is capable to precisely regulate an output voltage as low as 0.8 V. In fact, the device
comes with a fixed 0.8 V internal reference that guarantees the output regulated voltage to
be within ±1% tolerance over line and temperature variations between 0 °C and 70 °C
(excluding output resistor divider tolerance, when present).
Output voltage higher than 0.8 V can be achieved by adding a resistor ROS between FB pin
and ground. Referring to Figure 1, the steady state DC output voltage will be:
where VREF is 0.8 V.
8.2 Compensation network
The control loop shown in Figure 8 is a voltage mode control loop. The error amplifier is a
transconductance type with fixed gain (3.3 ms typ.). The FB voltage is regulated to the
internal reference, thus the output voltage is fixed accordingly to the output resistor divider
(when present).
Transconductance error amplifier output current generates a voltage across ZF
, which is
compared to oscillator saw-tooth waveform to provide PWM signal to the driver section.
PWM signal is then transferred to the switching node with VIN amplitude. This waveform is
filtered by the output filter.
Figure 8. PWM control loop
The converter transfer function is the small signal transfer function between the voltage at
the output node of the EA (COMP) and VOUT
. This function has a double pole (complex
conjugate) at frequency FLC depending on the L-COUT resonance and a zero at FESR
VOUT VREF 1RFB
ROS
-----------+
⎝⎠
⎛⎞
⋅=
L R
C
OUT
ESR
R
FB
OSC
V
IN
ΔV
OSC
+
+
_
_
V
OUT
V
REF
Z
F
OUTPUT
DIVIDER
PWM
COMPARATOR
OTA
R
F
C
F
C
P
R
OS
FB
COMP
Application details L6726A
16/35 Doc ID 12754 Rev 4
depending on the output capacitor ESR. The DC gain of the modulator is simply the input
voltage VIN divided by the peak-to-peak oscillator voltage ΔVOSC.
VOUT is scaled and transferred to FB node by the output resistor divider.
The compensation network closes the loop joining FB and COMP node with transfer
function ideally equal to -gm·ZF.
Compensation goal is to close the control loop assuring high DC regulation accuracy, good
dynamic performances and stability. To achieve this, the overall loop needs high DC gain,
high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F0dB) can be fixed choosing the right RF; however, for stability, it
should not exceed FSW/2π. To achieve a good phase margin, the control loop gain has to
cross 0 dB axis with -20 dB/decade slope.
As an example, Figure 9 shows an asymptotic bode plot of a type II compensation.
Figure 9. Example of type II compensation.
●Open loop converter singularities:
a)
b)
●Compensation Network singularities frequencies:
a)
b)
Gain
[dB]
Log (Freq)
0dB
OTA
open loop
gain
closed loop
gain
compensation
gain
converter
open loop
gain
F
LC
F
ESR
F
Z
F
P
20log (gm·R
F
)
20log [V
IN
/ΔV
OSC
·R
OS
/(R
FB
+R
OS
)]
F
0dB
FLC
1
2πLC
OUT
⋅
----------------------------------=
FESR
1
2πCOUT ESR⋅⋅
--------------------------------------------=
FZ
1
2πRFCF
⋅⋅
------------------------------=
FP
1
2πRF
CFCP
⋅
CFCP
+
---------------------
⎝⎠
⎛⎞
⋅⋅
--------------------------------------------------=
L6726A Application details
Doc ID 12754 Rev 4 17/35
Type II compensation relies on the zero introduced by the output capacitors bank to achieve
stability. Thus, a needed condition to successfully apply type II compensation is
(usually true when output capacitor is based on electrolytic, aluminium electrolytic or
tantalum capacitor).
To define compensation network components values, the below suggestions may be
followed:
a) Set the output resistor divider in order to obtain the desired output voltage:
Usual values of RFB and ROS ranges from some hundreds of Ω to some kΩ
(consider trade-off between power dissipation on output resistor divider and offset
introduced by FB bias current).
If the desired output voltage is equal to internal reference, ROS has to be NC and
FB pin can be directly connected to VOUT
.
b) Set RF in order to obtain the desired closed loop regulator bandwidth according to
the approximated formula:
If VOUT = VREF
, just consider (RFB+ROS)/ROS factor equal to 1.
c) Place FZ below FLC (typically 0.2·FLC):
d) Place FP at 0.5·FSW:
e) Check that compensation network gain is lower than open loop transconductance
EA gain.
f) Estimate phase margin obtained (it should be greater than 45°) and repeat,
modifying parameters, if necessary.
FESR F0dB
<
RFB
ROS
-----------
VOUT
VREF
-------------- 1–=
RF
F0dB FESR
⋅
FLC
2
-------------------------------
ΔVOSC
VIN
-------------------1
gm
--------
RFB ROS
+
ROS
----------------------------
⋅⋅⋅=
CF
5
2πRFFLC
⋅⋅
---------------------------------=
CP
CF
πRFCFFSW 1–⋅⋅⋅
---------------------------------------------------- 1
πRFFSW
⋅⋅
-------------------------------
≅=
Application details L6726A
18/35 Doc ID 12754 Rev 4
8.3 Soft-start time calculation
To calculate SS time (tSS), the following approximated equation can be used (CP<<CF):
The previous equation refers only to VOUT ramp up time. The time elapsed from the end of
OC setting phase or COMP set free to the beginning of VOUT ramp up (see Figure 6) can be
approximately estimated as follow:
Once calculated tSS, also the current delivered by the converter during SS to charge the
output capacitor bank can be estimated:
8.4 Layout guidelines
L6726A provides control functions and high current integrated drivers to implement high-
current step-down DC-DC converters. In this kind of application, a good layout is very
important.
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) power connections (highlighted in
Figure 10) must be a part of a power plane and anyway realized by wide and thick copper
traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs,
must be close one to the other. The use of multi-layer printed circuit board is recommended.
Figure 10. Power connections (heavy lines)
The input capacitance (C
IN
), or at least a portion of the total capacitance needed, has to be
placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be
connected near the HS drain.
Use proper number of vias when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
same high-current trace on more than one PCB layer will reduce the parasitic resistance
associated to that connection.
tSS
CF
VOUT
VIN
-------------- ΔVOSC
⋅⋅
ISS
--------------------------------------------------=
tdelay
CF0.8V⋅
ISS
------------------------=
Istartup
COUT VOUT
⋅
tSS
----------------------------------=
L
C
IN
V
IN
UGATE
PHASE
LGATE
GND
LOAD
L6726A
C
OUT
L6726A Application details
Doc ID 12754 Rev 4 19/35
Connect output bulk capacitors (C
OUT
) as near as possible to the load, minimizing parasitic
inductance and resistance associated to the copper trace, also adding extra decoupling
capacitors along the way to the load when this results in being far from the bulk capacitors
bank.
Gate traces and phase trace must be sized according to the driver RMS current delivered to
the power MOSFET. The device robustness allows managing applications with the power
section far from the controller without losing performances. Anyway, when possible, it is
recommended to minimize the distance between controller and power section. See
Figure 11 for drivers current paths.
Small signal components and connections to critical nodes of the application, as well as
bypass capacitors for the device supply, are also important. Locate bypass capacitor (VCC
and Bootstrap capacitor) and loop compensation components as close to the device as
practical. For over current programmability, place ROCSET close to the device and avoid
leakage current paths on LGATE / OC pin, since the internal current source is only 10 μA
Systems that do not use Schottky diode in parallel to the Low-Side MOSFET might show big
negative spikes on the PHASE pin. This spike must be limited within the absolute maximum
ratings (for example, adding a gate resistor in series to HS MOSFET gate, or a phase
resistor in series to PHASE pin), as well as the positive spike, but has an additional
consequence: it causes the bootstrap capacitor to be over-charged. This extra-charge can
cause, in the worst case condition of maximum input voltage and during particular
transients, that boot-to-phase voltage overcomes the absolute maximum ratings also
causing device failures. It is then suggested in this case to limit this extra-charge by adding a
small resistor in series to the bootstrap diode (RD in Figure 1).
Figure 11. Drivers turn-on and turn-off paths
R
GATE
R
INT
C
GD
C
GS
C
DS
VCC
LS DRIVER LS MOSFET
GND
LGATE
R
GATE
R
INT
C
GD
C
GS
C
DS
BOOT
HS DRIVER HS MOSFET
PHASE
UGATE
R
PHASE
Application details L6726A
20/35 Doc ID 12754 Rev 4
8.5 Embedding L6726A-based VRs…
When embedding the VR into the application, additional care must be taken since the whole
VR is a switching DC/DC regulator and the most common system in which it has to work is a
digital system such as MB or similar. In fact, latest MBs have become faster and more
powerful: high speed data busses are more and more common and switching-induced noise
produced by the VR can affect data integrity if additional layout guidelines are not followed.
Few easy points must be considered mainly when routing traces in which switching high
currents flow (switching high currents cause voltage spikes across the stray inductance of
the traces causing noise that can affect the near traces):
When reproducing high current path on internal layers, keep all layers the same size in order
to avoid “surrounding” effects that increase noise coupling.
Keep safe guard distance between high current switching VR traces and data busses,
especially if high-speed data busses, to minimize noise coupling.
Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that
must walk near the VR.
Possible causes of noise can be located in the PHASE connections, MOSFETs gate drive
and Input voltage path (from input bulk capacitors and HS drain). Also GND connection
must be considered if not insisting on a power ground plane. These connections must be
carefully kept far away from noise-sensitive data busses.
Since the generated noise is mainly due to the switching activity of the VR, noise emissions
depend on how fast the current switches. To reduce noise emission levels, it is also possible,
in addition to the previous guidelines, to reduce the current slope and thus to increase the
switching times: this will cause, as a consequence of the higher switching time, an increase
in switching losses that must be considered in the thermal design of the system.
L6726A Application Information
Doc ID 12754 Rev 4 21/35
9 Application Information
9.1 Output inductor
Inductor value is defined by a compromise between dynamic response, ripple, efficiency,
cost and size. Usually, inductance is calculated to maintain inductor ripple current (ΔIL)
between 20% and 30% of maximum output current. Given the switching frequency (FSW),
the input voltage (VIN), the output voltage (VOUT) and the desired ripple current (ΔIL),
inductance can be calculated as follows:
Figure 12 shows the ripple current vs. the output voltage for different inductance, with
VIN = 5 V and VIN = 12 V.
Increasing inductance reduces inductor ripple current (and output voltage ripple
accordingly) but, at the same time, increases the converter response time to load transients.
Higher inductance means that the inductor needs more time to change its current from initial
to final value. Until the inductor has not finished its charging, the additional output current is
supplied by output capacitors. Minimizing the response time lead to minimize the output
capacitance required. If the compensation network is designed with high bandwidth, during
an heavy load transient the device is able to saturate duty cycle (0% or 80%). When this
condition is reached, the response time is limited only by the time required to charge the
inductor.
Figure 12. Inductor current ripple vs output voltage
LVIN VOUT
–
FSW ΔIL
⋅
------------------------------
VOUT
VIN
--------------
⋅=
0
2
4
6
8
10
12
012345
I
n
d
u
c
t
o
r
c
u
r
r
e
n
t
r
i
p
p
l
e
[
A
]
Output voltage [V]
Vin=12V, L=1uH
Vin=12V, L=2uH
Vin=5V, L=500nH
Vin=5V, L=1.5uH
Application Information L6726A
22/35 Doc ID 12754 Rev 4
9.2 Output capacitors
Output capacitors choice depends on the application constraints in point of output voltage
ripple and output voltage deviation during a load transient.
During steady-state conditions, the output voltage ripple is influenced by ESR and
capacitance of the output capacitors as follows:
Where ΔIL is the inductor current ripple. These contribution are not in phase, so total ripple
will be lower than the sum of their moduli. Even ESL and board parasitic inductance can
contribute significantly to output ripple.
During a load variation, the output capacitors supply to the load the additional current or
absorb the current in excess delivered by the inductor until converter reaction is completed.
In fact, even if the controller react immediately to the load transient saturating the duty cycle
to 80% or 0%, the current slew rate is limited by the inductance. At first approximation,
output voltage drop, based on ESR and capacitor charge/discharge and considering an
ideal load-step, can be estimated as follows:
Where ΔVL is the voltage applied to the inductor during the transient ( for
the load appliance or VOUT for the load removal).
MLCC capacitors typically have low ESR to minimize the ripple but also have low
capacitance that do not minimize the capacitive voltage deviation during load transient. On
the contrary, electrolytic capacitors usually have higher capacitance to minimize capacitive
voltage deviation during load transient, but also higher ESR value resulting in higher ripple
voltage and resistive voltage drop. For these reasons, a mix between electrolytic and MLCC
capacitor is usually suggested to minimize ripple as well as reducing voltage deviation in
dynamic conditions.
9.3 Input capacitors
The input capacitor bank is designed mainly to stand input rms current, which depends on
output current (IOUT) and duty-cycle (D) for the regulation as follows:
The equation reaches its maximum value, IOUT/2, when D = 0.5. Losses depend on input
capacitor ESR:
ΔVOUT_ESR ΔILESR⋅=
ΔVOUT_C ΔIL
1
8C
OUT FSW
⋅⋅
---------------------------------------
⋅=
ΔVOUT_ESR ΔIOUT ESR⋅=
ΔVOUT_C
LΔIOUT
2
⋅
2C
OUT ΔVL
⋅⋅
--------------------------------------=
DMAX VIN VOUT
–⋅
Irms IOUT D1D–()⋅⋅=
PESRI
rms
2
⋅=
L6726A 20 A demonstration board
Doc ID 12754 Rev 4 23/35
10 20 A demonstration board
L6726A demonstration board realizes on a four-layer PCB a step-down DC/DC converter
and shows the operation of the device in a general purpose application. Input voltage can
range from 5 V to 12 V bus. Output voltage is programmed to 1.25 V. The voltage regulator
can deliver up to 20 A output current. The switching frequency is 270 kHz.
Figure 13. 20 A demonstration board (left) and components placement (right)
Figure 14. 20 A demonstration board top (left) and bottom (right) layers
20 A demonstration board L6726A
24/35 Doc ID 12754 Rev 4
Figure 15. 20 A demonstration board inner layers
L6726A 20 A demonstration board
Doc ID 12754 Rev 4 25/35
Figure 16. 20 A demonstration board schematic
HSDHSD
VIN_POWER
LSG1
UGATE
BOOT
BOOT PHASE
GND
VCC
GND
COMP
FB
COMP
VCC_PIN
FB
OUT
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
PHASE
OUT
LSG2LSG2LSG2LSG2LSG2LSG2LSG2LSG2LSG2LSG2LSG2LSG2
UGATE HSG
LGATELGATE
VCCVCC_PINLGATE
PHASE OUT
HSG
PHASE
HSD
GND
LSG1
PHASE
GND
LSG2
PHASE
0
0 0 0
0 0
0
VIN_POWER
GNDIN_POWER
0
VCC
GNDCC
00
0 0 0 0 0 0 0 0 0
VOUT
0
GNDOUT
0
0 0 0 0 0 0 0 0 0 0
0 0 00 0 00
0
0
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$GGLWLRQDO62PRVIHWDQG,QGXFWRU
ᤡ
IRUIXUWKHUFRPSDWLELOLW\
ᤢ
C33
NC
C33
NC
R14
NC
R14
NC
COMPCOMP
12
L2
T60-18 6Ts
L2
T60-18 6Ts
1
3 2
Q6
NC
Q6
NC
FBFB
GNDGND
VOUT1VOUT1
C21
NC
C21
NC
R4
1.8
R4
1.8
UGATEUGATE
C13
4.7uF
C13
4.7uF
4
51
6
7
8
2
3
Q1
NC
Q1
NC
C34
NC
C34
NC
R13
3.9k
R13
3.9k
4
51
6
7
8
2
3
Q2
NC
Q2
NC
C37
NC
C37
NC
R8
NC
R8
NC
C23
6.8nF
C23
6.8nF
R3
0
R3
0
C36
NC
C36
NC
R11
0
R11
0
C15
NC
C15
NC
C22
NC
C22
NC
C27
NC
C27
NC
GNDOUT1GNDOUT1
GNDIN1GNDIN1
1
3 2
Q4
STD70NH02LT4
Q4
STD70NH02LT4
C16
NC
C16
NC
C3
NC
C3
NC
R9
2.2k
R9
2.2k
C381uF C381uF
R17
3.3
R17
3.3
C5
NC
C5
NC
C14
1uF
C14
1uF
VIN1VIN1
C28
NC
C28
NC
PHASEPHASE
C19
NC
C19
NC
C10
100nF
C10
100nF
C4
NC
C4
NC
C35
470pF
C35
470pF
C17
NC
C17
NC
C11
4.7uF
C11
4.7uF
R6
NC
R6
NC
R12
0
R12
0
1
3 2
Q5
STD95NH02LT4
Q5
STD95NH02LT4
C7
NC
C7
NC
C31
NC
C31
NC
R10
NC
R10
NC
C29
NC
C29
NC
C6
NC
C6
NC
R18
20k
R18
20k
C18
2200uF
C18
2200uF
C25
2200uF
C25
2200uF
R7
2k
R7
2k
R5
0
R5
0
1 2
L1
NC
L1
NC
R15
NC
R15
NC
C2
1800uF
C2
1800uF
C1
1800uF
C1
1800uF
R1
3.3
R1
3.3
LGATELGATE
C9
NC
C9
NC
C32
NC
C32
NC
C20
NC
C20
NC
C24
68nF
C24
68nF
D1
1N4148
D1
1N4148
C12
4.7uF
C12
4.7uF
R16
0
R16
0
VCC 5
GND
3FB 6
UGATE
2
BOOT
1
COMP 7
PHASE 8
LGATE
4
L6726A/27
U1
L6726A/27
U1
4
51
6
7
8
2
3
Q3
NC
Q3
NC
VCCVCC
C30
NC
C30
NC
C26
NC
C26
NC
C8
NC
C8
NC
R2
3.3
R2
3.3
20 A demonstration board L6726A
26/35 Doc ID 12754 Rev 4
Table 6. 20 A demonstration board - bill of material
Qty Reference Description Package
Capacitors
2C1, C2 Electrolytic Cap 1800 μF 16 V
Nippon Chemi-Con KZJ or KZG Radial 10 x 25 mm
1 C10 MLCC, 100 nF, 25 V, X7R SMD0603
3 C11 to C13 MLCC, 4.7 μF, 1 6 V, X 5 R
Murata GRM31CR61C475MA01 SMD1206
2 C14, C38 MLCC, 1 μF, 16 V, X7R SMD0805
2C18, C25 Electrolytic Cap 2200 μF 6.3 V
Nippon Chemi-Con KZJ or KZG Radial 10 x 20mm
1 C23 MLCC, 6.8 nF, X7R
SMD06031 C24 MLCC, 68 nF, X7R
1 C35 MLCC, 470 pF, X7R
Resistors
3 R1, R2, R17 Resistor, 3R3, 1/16 W, 1% SMD0603
3 R3, R5, R16 Resistor, 0R, 1/8 W, 1% SMD0805
1 R4 Resistor, 1R8, 1/8 W, 1%
2 R11, R12 Resistor, 0R, 1/16 W, 1%
SMD0603
1 R9 Resistor, 2K2, 1/16 W, 1%
1 R13 Resistor, 3K9, 1/16 W, 1%
1 R7 Resistor, 2K, 1/16 W, 1%
1 R18 Resistor, 20K, 1/16 W, 1%
Inductor
1L1 Inductor, 1.25 μH, T60-18, 6Turns
Easymagnet AP106019006P-1R1M na
Active components
1 D1 Diode, 1N4148 or BAT54 SOT23
1 Q5 STD70NH02LT4 DPACK
1 Q6 STD95NH02LT4
1 U1 Controller, L6726A SO8
L6726A 20 A demonstration board
Doc ID 12754 Rev 4 27/35
10.1 Board description
10.1.1 Power input (VIN)
This is the input voltage for the power conversion. The high-side MOSFET drain is
connected to this input. Supply must be compliant with VIN recommended operating
conditions and capacitors rating.
If VIN voltage is compliant also to VCC range listed in recommended operating conditions, it
can supply also the device through R16 resistor.
10.1.2 Power output (VOUT)
This is the output voltage of the power conversion. The output voltage is programmed to
1.25 V. It can be changed by replacing R13 (adjusting of compensation network may be
needed). R18 allows to adjust OCP threshold.
10.1.3 IC additional supply (VCC)
The controller can be supplied separately from the power conversion through VCC input. In
this case, to separate VCC from VIN, R16 resistor must be removed.
10.1.4 Test points
The following test points are provided to allow easy probing of important signals:
– COMP: Output of the error amplifier;
– FB: Inverting input of the error amplifier;
– PH: Phase pin of the device;
– LG: Low-side gate pin of the device;
– UG: High-side gate pin of the device.
10.1.5 Demonstration board efficiency
Figure 17. 20 A demonstration board efficiency
50
55
60
65
70
75
80
85
90
95
100
0 2 4 6 8 10 12 14 16 18 20 22
Output Current [A]
Efficiency [%]
Vin=12V, Vout=1.25V
Vin=5V, Vout=1.25V
Vin=12V, Vout=2.5V
Vin=5V, Vout=2.5V
5 A demonstration board L6726A
28/35 Doc ID 12754 Rev 4
11 5 A demonstration board
L6726A demonstration board realizes on a two-layer PCB a step-down DC/DC converter
and shows the operation of the device in a general-purpose low-current application. Input
voltage can range from 5 V to 12 V bus. Output voltage is programmed at 1.25 V. The
application can deliver an output current in excess of 5 A. The switching frequency is 270
kHz.
Figure 18. 5 A demonstration board (left) and components placement (right)
Figure 19. 5 A demonstration board top (left) and bottom (right) layers
L6726A 5 A demonstration board
Doc ID 12754 Rev 4 29/35
Figure 20. 5 A demonstration board schematic
PHASE PIN
BOOT
BOOT
GND
FB
COMP
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
UGATE HSG1
LGATELGATE
VCCVCC_PIN
GND
LGATE
UGATE
PHASE PIN
COMP
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
OUTOUT
LSG1LSG1LSG1
VCCVCCVCCVCCVCCVCCVCCVCCVCCVCC
OUTOUTOUTOUTOUTOUTOUTOUT OUTOUT
VIN_POWER
FBFBFB
PHASE
HSD
0
0
0
VIN_POWER
GNDIN_POWER
0
VCC
GNDCC
0
0 0
VOUT
0
GNDOUT
0
0
0
0 0
0
0
0
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C12
10uF
C12
10uF
R1
3.3
R1
3.3
R13
3.9K
R13
3.9K
R16
0
R16
0
C39
22uF
C39
22uF
C35
2.2nF
C35
2.2nF
R14
NC
R14
NC
1
2
87
U5A
STS9D8NH3LL
U5A
STS9D8NH3LL
GNDGND
R5 0R5 0
PHASEPHASE
C23
6.8nF
C23
6.8nF
R4
1.8
R4
1.8 C18
NC
C18
NC
R10
0
R10
0
C30
330uF
C30
330uF
VCCVCC
C14
1uF
C14
1uF
R17 3.3R17 3.3
GNDIN1GNDIN1
C40
NC
C40
NC
VIN1VIN1
C29A
NC
C29A
NC
C36
NC
C36
NC
R3 0R3 0
D1
BAT54
D1
BAT54
C38
1uF
C38
1uF
R8
NC
R8
NC
12
L2
2.2uH
L2
2.2uH
BOOT
1
UGATE
2
GND
3
LGATE/OC
4VCC 5
FB 6
COMP 7
PHASE 8
L6726A
U1
L6726A
L6726A
U1
L6726A
R7
820
R7
820
C29
NC
C29
NC
C10
100nF
C10
100nF
C51
10uF
C51
10uF
R18
NC
R18
NC
3
4
65
U5B
STS9D8NH3LL
U5B
STS9D8NH3LL
COMPCOMP
UGATEUGATE
FBFB
VOUT1VOUT1
R9
2.2k
R9
2.2k
GNDOUT1GNDOUT1
C24
220nF
C24
220nF
12
L3 NCL3 NC
R2 3.3R2 3.3
LGATELGATE
5 A demonstration board L6726A
30/35 Doc ID 12754 Rev 4
Table 7. 5 A demonstration board - bill of material
11.1 Board description
11.1.1 Power input (VIN)
This is the input voltage for the power conversion. The high-side MOSFET drain is
connected to this input. Supply must be compliant with VIN recommended operating
conditions and capacitors rating.
If VIN voltage is compliant also to VCC range listed in recommended operating conditions, it
can supply also the device through R16 resistor.
Qty Reference Description Package
Capacitors
2C12, C51 10 μF, 2 5 V, X 5 R
Murata GRM31CR61E106KA12 SMD1206
1 C10 MLCC, 100nF, 25V, X7R SMD0603
2 C14, C38 MLCC, 1 μF, 16 V, X7R SMD0805
1C39 MLCC, 22 μF, 6.3 V, X5R
Murata GRM31CR60J226ME19 SMD1206
1C30 330 μF, 6.3 V, 40 mΩ
Sanyo 6TPB330M SMD7343
1 C23 MLCC, 6.8 nF, X7R
SMD06031 C24 MLCC, 220 nF, X7R
1 C35 MLCC, 2.2 nF, X7R
Resistors
1 R4 Resistor, 1R8, 1/8 W, 1% SMD0805
4 R3, R5, R10, R16 Resistor, 0R, 1/16 W, 1% SMD0603
3 R1, R2, R17 Resistor, 3R3, 1/16 W, 1%
1 R9 Resistor, 2K2, 1/16 W, 1%
SMD06031 R13 Resistor, 3K9, 1/16 W, 1%
1 R7 Resistor, 820R, 1/16 W, 1%
Inductor
1L1 Inductor, 2.20 μH,
Wurth 744324220LF na
Active Components
1 D1 Diode, BAT54 SOT23
1 Q5 Mosfet, STS9D8NH3LL SO8
1 U1 Controller, L6726A SO8
L6726A 5 A demonstration board
Doc ID 12754 Rev 4 31/35
11.1.2 Power output (VOUT)
This is the output voltage of the power conversion. The output voltage is programmed to
1.25 V. It can be changed by replacing R13 (adjusting of compensation network may be
needed). Adding R18 allows to adjust OCP threshold.
11.1.3 IC additional supply (VCC)
The controller can be supplied separately from the power conversion through VCC input. In
this case, to separate VCC from VIN, R16 resistor must be removed.
11.1.4 Test points
The following test points are provided to allow easy probing of important signals:
– COMP: output of the error amplifier;
– FB: inverting input of the error amplifier;
– PH: Phase pin of the device;
– LG: Low-side gate pin of the device;
– UG: High-side gate pin of the device.
11.1.5 Demonstration board efficiency
Figure 21. 5 A demonstration board efficiency
50
55
60
65
70
75
80
85
90
95
100
0123456
Output Current [A]
Efficiency [%]
Vin = 12V, Vout = 1.25V
Vin = 5V, Vout = 1.25V
Vin = 12V, Vout = 2.5V
Vin = 5V, Vout = 2.5V
Package mechanical data L6726A
32/35 Doc ID 12754 Rev 4
12 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
L6726A Package mechanical data
Doc ID 12754 Rev 4 33/35
Table 8. SO-8 mechanical data
Dim.
mm. inch
Min Typ Max Min Typ Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D (1)
1. D and F does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm
(.006inch) per side.
4.80 5.00 0.189 0.197
E 3.80 4.00 0.15 0.157
e 1.27 0.050
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
k 0° (min.), 8° (max.)
ddd 0.10 0.004
Figure 22. Package dimensions
Revision history L6726A
34/35 Doc ID 12754 Rev 4
13 Revision history
Table 9. Document revision history
Date Revision Changes
16-Oct-2006 1 Initial release.
26-Oct-2006 2 Mechanical data dimensions updated
30-Jul-2007 3 Updated Figure 1 on page 4, tables 2, 3, 4, 5
23-Mar-2010 4
Added:
Section 9 on page 21, Section 10 on page 23, Section 11 on page 28
Updated: Table 5 on page 7
L6726A
Doc ID 12754 Rev 4 35/35
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