ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY BURST CellularRAMTM MT45W4MW16BFB MT45W2MW16BFB Features Figure 1: Ball Assignment 54-Ball FBGA For the latest data sheet, please refer to Micron's Web site: www.micron.com/datasheets. * Single device supports asynchronous, page, and burst operations * VCC, VCCQ Voltages 1.70V-1.95V VCC 1.70V-2.25V VCCQ (Option W) * Random Access Time: 70ns * Burst Mode Write Access Continuous burst * Burst Mode Read Access 4, 8, or 16 words, or continuous burst MAX clock rate: 104 MHz (tCLK = 9.62ns) Burst initial latency: 39ns (4 clocks) @ 104 MHz t ACLK: 6.5ns @ 104 MHz * Page Mode Read Access Sixteen-word page size Interpage read access: 70ns Intrapage read access: 20ns * Low Power Consumption Asynchronous READ < 25mA Intrapage READ < 15mA Initial access, burst READ: (39ns [4 clocks] @ 104 MHz) < 35mA Continuous burst READ < 15mA Standby: 90A (32Mb), 100A (64Mb) Deep power-down < 10A * Low-Power Features Temperature Compensated Refresh (TCR) Partial Array Refresh (PAR) Deep Power-Down (DPD) Mode Options * VCC Core Voltage Supply: 1.80V - MT45WxMx16BFB * VCCQ I/O Voltage 3.0V - MT45WxML16BFB 2.5V - MT45WxMV16BFB 1.8V - MT45WxMW16BFB * Timing 60ns access 70ns access 85ns access * Frequency 66 MHz 104 MHz 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CRE B DQ8 UB# A3 A4 CE# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSSQ DQ11 A17 A7 DQ3 VCC E VCCQ DQ12 A21 A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 J WAIT CLK ADV# NC NC NC Top View (Ball Down) NOTE: See Table 1 on page 6 for ball descriptions, and Figure 40 on page 50 for 54-ball mechanical drawing. Options (continued) * Configuration: 4 Meg x 16 2 Meg x 16 * Package 54-ball FBGA * Operating Temperature Range Wireless (-25C to +85C) Industrial (-40C to +85C) Marking W (contact factory) (contact factory) W (contact factory) -70 -85 NOTE: Marking MT45W4Mx16BFB MT45W2Mx16BFB FB WT IT (contact factory) A part marking guide for the FBGA devices can be found on Micron's Web site: www. micron.com/numberguide Part Number Example: 1 6 MT45W2MW16BFB-701WT 1 (c)2003 Micron Technology, Inc. All Rights Reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Wait Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Partial Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Burst Length (BCR[2:0]) Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Burst Wrap (BCR[3]) Default = Burst Wraps Within Address Boundaries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock Configuration (BCR[6]) Default = Transactions Processed on Rising Edge of Clock. . . . . . . . . . . . . . . . . . 18 WAIT Configuration (BCR[8])Default = WAIT Transitions One Clock Before Data Valid/Invalid . . . . . . . . . . . . 18 WAIT Polarity (BCR[10]) Default = WAIT Active HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Latency Counter (BCR[13:11]) Default = Three-Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Deep Power-Down (rcr[4]) Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Temperature Compensated Refresh (rcr[6:5]) Default = +85C Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Page Mode Operation (rcr[7]) Default = Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Asynchronous Random READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Asynchronous Page READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Initial Access, Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Continuous Burst READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Burst CellularRAM Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 How Extended Timings Impact CellularRAMtm Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Asynchronous and Page-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Burst-Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: FBGA Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bus Operations - Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus Operations - Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviated Component Marks - CellularRAM FBGA-Packaged Components . . . . . . . . . . . . . . . . . . . . . 8 Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 64Mb Address Patterns for PAR (A4 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 32Mb Address Patterns for PAR (A4 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Temperature Compensated Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Partial Array Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Asynchronous READ Cycle Timing Requirements1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Burst READ Cycle Timing Requirements1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Initialization Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Asynchronous READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Asynchronous READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Asynchronous READ Timing Parameters (Page Mode Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Burst READ Timing Parameters (with LB#/UB#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Asynchronous WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Asynchronous WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Asynchronous WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Asynchronous WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Burst WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Burst WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Ball Assignment 54-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional Block Diagram - 4 Meg x 16 and 2 Meg x 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Power-Up Initialization Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Page Mode READ Operation (ADV = LOW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Burst Mode READ (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Burst Mode WRITE (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Wired or WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Refresh Collision During READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Refresh Collision During WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Configuration Register WRITE in Asynchronous Mode Followed by READ . . . . . . . . . . . . . . . . . . . . . . . 15 Configuration Register WRITE in Synchronous Mode Followed by READ . . . . . . . . . . . . . . . . . . . . . . . . 15 WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 WAIT Configuration During Burst Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Latency Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Asynchronous READ Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Single-Access Burst READ Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4-Word Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4-Word Burst READ Operation (with LB#/UB#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Continuous Burst READ with Output Delay, BCR[8] = 0(1) for End-of-Row Condition . . . . . . . . . . . . . 38 CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 LB#/UB#-Controlled Asynchronous WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Asynchronous WRITE Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Burst WRITE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Continuous Burst WRITE with Output Delay, BCR[8] = 0(1) for End-of-Row Condition . . . . . . . . . . . . 44 Burst WRITE Followed by Burst READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Asynchronous WRITE Followed By Burst READ--ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Asynchronous WRITE Followed by Asynchronous READ--ADV# LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 54-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Extended Timing for tCEM, Page Mode Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Extended Timing for tTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Extended Timing for tCEM, Page Mode Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Extended Asynchronous Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY General Description Micron CellularRAMTM products are high-speed, CMOS dynamic random access memories developed for low-power, portable applications. The MT45W4MW16BFB is a 64Mb device organized as 4 Meg x 16 bits; the MT45W2MW16BFB is a 32Mb device organized as 2 Meg x 16 bits. These devices include an industry-standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or Pseudo SRAM offerings. To operate seamlessly on a burst Flash bus, CellularRAM products have incorporated a transparent selfrefresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. CellularRAM products include three system-accessible mechanisms used to minimize standby current. Partial array refresh (PAR) limits refresh to only that part of the DRAM array that contains essential data. Temperature compensated refresh (TCR) is used to adjust the refresh rate according to the case temperature. The refresh rate can be decreased at lower temperatures to minimize current consumption during standby. Deep powerdown (DPD) halts the refresh operation altogether and is used when no vital information is stored in the device. These three refresh mechanisms are adjusted through the RCR. Figure 2: Functional Block Diagram - 4 Meg x 16 and 2 Meg x 16 A[20:0] (for 32Mb) A[21:0] (for 64Mb) Address Decode Logic 2,048K x 16 (4,096K x 16) DRAM MEMORY ARRAY Input/ Output MUX and Buffers DQ[7:0] DQ[15:8] Refresh Configuration Register (RCR) Bus Configuration Register (BCR) CE# WE# OE# CLK ADV# CRE WAIT LB# UB# Control Logic NOTE: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed information. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY l 1: Table FBGA Ball Descriptions FBGA ASSIGNMENT SYMBOL TYPE DESCRIPTION A3, A4, A5, B3, B4, C3, C4, D4, H2, H3, H4, H5, G3, G4, F3, F4, E4, D3, H1, G2, H6, E3 J2 A[21:0] Input Address Inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the bus configuration register or the refresh configuration register. On the 32Mb device, A21 (ball E3) is not internally connected. CLK Input J3 ADV# Input A6 CRE Input B5 CE# Input A2 OE# Input G5 WE# Input A1 B2 B6, C5, C6, D5, E5, F5, F6, G6, B1, C1, C2, D2, E2, F2, F1, G1 J1 LB# UB# DQ[15:0] Input Input Input/ Output Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When configured for synchronous operation, the address is latched on the first rising (or falling, depending upon the bus configuration register setting) CLK edge when ADV# is active, or upon a rising ADV# edge, whichever occurs first. CLK is static during asynchronous access READ and WRITE operations and during PAGE READ ACCESS operations. CLK must be held LOW during asynchronous or page mode transactions. Address Valid: Indicates that a valid address is present on the address inputs. Addresses can be latched on the rising edge of ADV# during READ and WRITE operations. ADV# may be driven LOW during asynchronous READ and WRITE operations. Configuration Register Enable: When CRE is HIGH, WRITE operations load the refresh configuration register or bus configuration register. Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby or deep power-down mode. Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a configuration register or to the memory array. Lower Byte Enable. DQ[7:0] Upper Byte Enable. DQ[15:8] Data Inputs/Outputs. WAIT Output J4, J5, J6 D6 E1 E6 D1 NC VCC VCCQ VSS VSSQ - Supply Supply Supply Supply Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary. WAIT is also used to mask the delay associated with opening a new internal page. WAIT is asserted and should be ignored during asynchronous and page mode operations. Not internally connected. Device Power Supply: (1.70V-1.95V) Power supply for device core operation. I/O Power Supply: (1.70V-1.95V) Power supply for input/output buffers. VSS must be connected to ground. VSSQ must be connected to ground. NOTE: The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. The WAIT signal will be driven to an undefined state when operating in asynchronous or page mode. Otherwise, during asynchronous operation, WAIT will be in a High-Z condition. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 2: MODE Bus Operations - Asynchronous Mode POWER Active > Standby Read Active > Standby Write Standby Standby Standby Standby Active Configuration Register Deep DPD Power-Down Table 3: CLK ADV# CE# OE# WE# CRE LB#/ UB# WAIT1 DQ[15:0]2 NOTES L L X X L L L X X L L L H L L L X X X H H L X X L L L L L H L1 L1 X X X L L X X L Data-Out Data-In High-Z X High-Z 3 3 4 3, 5 L X H X X X X X High-Z 6 Bus Operations - Burst Mode POWER CLK ADV# CE# OE# WE# CRE LB#/ UB# WAIT1 DQ[15:0]2 NOTES Async Read Async Write Standby Standby Initial Burst Read Active > Standby Active > Standby Standby Standby Active > Standby L L X X L L X X L L L H L L L X X X X H L X X H L L L L L L L X X L L L X X L Data-Out Data-In High-Z X Data-Out 2, 3 2, 3 4 3, 5 2, 3, 7, 8 Initial Burst Write Active > Standby L L H L L X L Data-In 3, 7, 8 Burst Continue Active > Standby H L X X L X X Data-In or Data-Out 3, 7, 8 L X L L L X H X L L H X X X X High-Z High-Z 3, 7 7, 8 L X H X X X X X High-Z 6 MODE Burst Suspend Active > Standby Active Configuration Register DPD Deep Power-Down NOTE: 1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are affected. 2. The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. The device will consume active power in this mode whenever addresses are changed. 4. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 5. VIN = VCC or 0V; all device balls must be static (unswitched) in order to achieve standby current. 6. DPD is maintained until RCR is reconfigured. 7. Burst mode operation is initialized through the bus configuration register (BCR[15]). 8. The clock polarity is configured through the bus configuration register (BCR[6]). 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 4: Abbreviated Component Marks - CellularRAM FBGA-Packaged Components ENGINEERING SAMPLE QUALIFIED SAMPLE MT45W4MW16BFB-701 WT MT45W4MW16BFB-706 WT MT45W4MW16BFB-856 WT PX344 PX340 PX345 PW344 PW340 PW345 MT45W2MW16BFB-701 WT MT45W2MW16BFB-706 WT MT45W2MW16BFB-856 WT PX244 PX240 PX245 PW244 PW240 PW245 MT45W4MW16BFB-706 IT PX3521 PW3521 MT45W4MW16BFB-856 IT PX3541 PW3541 MT45W4ML16BFB-856 IT PX3551 PW3551 MT45W4ML16BFB-706 IT PX3571 PW3571 MT45W2MW16BFB-706 IT PX2481 PW2481 MT45W2MW16BFB-856 IT PX2501 PW2501 MT45W2ML16BFB-856 IT PX2511 PW2511 MT45W2ML16BFB-706 IT PX2531 PW2531 PART NUMBER NOTE: 1. Contact factory for availability. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Functional Description WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations (Figure 5) occur when CE#, WE#, and LB#/ UB# are driven LOW. During asynchronous WRITE operations, the OE# level is a "Don't Care," and WE# will override OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode disabled) can either use the ADV input to latch the address, or ADV can be driven LOW during the entire READ/WRITE operation. During asynchronous operation, the CLK input should be held LOW. WAIT will be driven while the device is enabled and its state should be ignored. In general, the MT45W4MW16BFB device and the MT45W2MW16BFB device are high-density alternatives to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The MT45W4MW16BFB device contains 67,108,864 bits organized as 4,194,304 addresses by 16 bits. The MT45W2MW16BFB contains 33,554,432 bits organized as 2,097,152 addresses by 16 bits. Both devices implement the same high-speed bus interface found on burst mode Flash products. The CellularRAM bus interface supports both asynchronous and burst mode transfers. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. Figure 4: READ Operation (ADV = LOW) Power-Up Initialization CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will configure the BCR and the RCR with their default settings (see Table 5 on page 16 and Table 8 on page 21). VCC and VCCQ must be applied simultaneously. When they reach a stable level at or above 1.70V, the device will require 150s to complete its self-initialization process. During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. CE# OE# WE# ADDRESS DATA ADDRESS VALID DATA VALID LB#/UB# Figure 3: Power-Up Initialization Timing Vcc = 1.70V Vcc VccQ tPU > 150s Device Initialization tRC = READ Cycle Time DON'T CARE Device ready for normal operation NOTE: ADV must remain LOW for page mode operation. Bus Operating Modes The MT45W4MW16BFB and MT45W2MW16BFB CellularRAM products incorporate a burst mode interface found on Flash products targeting low-power, wireless applications. This bus interface supports asynchronous, page mode, and burst mode read and write transfers. The specific interface supported is defined by the value loaded into the bus configuration register. Page mode is controlled by the refresh configuration register (RCR[7]). Figure 5: WRITE Operation (ADV = LOW) CE# OE# WE# ADDRESS DATA Asynchronous Mode CellularRAM products power up in the asynchronous operating mode. This mode uses the industrystandard SRAM control bus (CE#, OE#, WE#, LB#/ UB#). READ operations (Figure 4) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN ADDRESS VALID DATA VALID LB#/UB# tWC = WRITE Cycle Time DON'T CARE 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Page Mode READ Operation Burst Mode Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In pagemode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low-order address. Addresses A[3:0] are used to determine the members of the 16-address CellularRAM page. Addresses A[4] and higher must remain fixed during the entire page mode access. Figure 6 shows the timing for a page mode access. Page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. WRITE operations do not include comparable page mode functionality. During asynchronous page mode operation, the CLK input must be held LOW. CE# must be driven HIGH upon completion of a page mode access. WAIT will be driven while the device is enabled and its state should be ignored. Page mode is enabled by setting RCR[7] to HIGH. WRITE operations do not include comparable page mode functionality. ADV must be driven LOW during all page mode read accesses. Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multiclock sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is latched on the next rising edge of CLK or ADV# (whichever occurs first). During this first clock rising edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH, Figure 7 on page 11) or WRITE (WE# = LOW, Figure 8 on page 11). The size of a burst can be specified in the BCR as either a fixed length or continuous. Fixed-length bursts consist of four, eight, or sixteen words. Continuous bursts have the ability to start at a specified address and burst through the entire memory. The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between the processor and CellularRAM device. The WAIT output will be asserted as soon as a burst is initiated, and will be de-asserted to indicate when data is to be transferred into (or out of ) the memory. WAIT will again be asserted if the burst crosses a row boundary. Once the CellularRAM device has restored the previous row's data and accessed the next row, WAIT will be de-asserted and the burst can continue (see Figure 28 on page 38). Figure 6: Page Mode READ Operation (ADV = LOW) CE# OE# WE# ADDRESS DATA Add[0] Add[1] tAA tAPA D[0] Add[2] tAPA D[1] Add[3] tAPA D[2] D[3] LB#/UB# DON'T CARE 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 7: Burst Mode READ (4-word burst)1 CLK A[21:0] ADDRESS VALID ADV# Latency Code 2 (3 clocks) CE# OE# WE# WAIT DQ[15:0] D[0] D[1] D[2] D[3] LB#/UB# READ Burst Identified (WE# = HIGH) DON'T CARE Figure 8: Burst Mode WRITE (4-word burst)1 CLK A[21:0] ADDRESS VALID ADV# CE# Latency Code 2 (3 clocks) OE# WE# WAIT DQ[15:0] D[0] D[1] D[2] D[3] LB#/UB# DON'T CARE WRITE Burst Identified (WE# = LOW) NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; Hold data one clock; WAIT asserted during delay. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Mixed-Mode Operation be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges. CE# must remain asserted at least as long as WAIT is asserted. Bringing CE# HIGH while WAIT is asserted may cause data corruption. WAIT output also performs an arbitration role when a READ or WRITE operation is launched while an onchip refresh is in progress. If a collision occurs, WAIT pin be asserted for additional clock cycles, until the refresh has completed (see Figures 10 and 11 on page 13). When the refresh operation has completed, the READ or WRITE operation will continue normally. WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary. The WAIT assertion allows time for the new row to be accessed, and permits any pending refresh operations to be performed. The device can support a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for synchronous operation. The asynchronous WRITE operation requires that the clock (CLK) remain LOW during the entire sequence. The ADV# signal can be used to latch the target address, or it can remain LOW during the entire WRITE operation. CE# must return HIGH when transitioning between mixed-mode operations. Note that the tCKA period is the same as a READ or WRITE cycle. This time is required to ensure adequate refresh. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash memory controllers. See Figure 36 on page 46 for the "Asynchronous WRITE Followed by Burst READ" timing diagram. Wait Operation WAIT output on the CellularRAM device is typically connected to a shared, system-level WAIT signal (see Figure 9 below). The shared WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. LB#/UB# Operation The LB# enable and UB# enable signals support byte-wide data transfers. During READ operations, the enabled byte(s) are driven onto the DQs. The DQs associated with a disabled byte are put into a High-Z state during a READ operation. During WRITE operations, any disabled bytes will not be transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW. Figure 9: Wired or WAIT Configuration CellularRAM WAIT External Pull-Up/ Pull-Down Resistor READY Processor WAIT WAIT Other Device Other Device Once a READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires additional time before data can 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 10: Refresh Collision During READ Operation1 CLK A[21:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] VIH VIL VIH VALID ADDRESS VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High-Z VOH D[0] VOL D[1] D[2] D[3] Additional WAIT states inserted to allow refresh completion. DON'T CARE NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; Hold Data one clock; WAIT asserted during delay. Figure 11: Refresh Collision During WRITE Operation1 CLK A[21:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] VIH VIL VIH VIL VALID ADDRESS VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High-Z VOH D[0] VOL Additional WAIT states inserted to allow refresh completion. D[1] D[2] D[3] DON'T CARE NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; Hold data one clock; WAIT asserted during delay. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Low-Power Operation Standby Mode Operation Deep Power-Down Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH and there are no transactions in progress. The device will enter standby operation upon completion of a READ or WRITE operation, or when the address and control inputs remain static for an extended period of time. This "active" standby mode will continue until a change occurs to the address or control inputs. Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. During this 150s period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. Temperature Compensated Refresh Configuration Registers Temperature compensated refresh (TCR) is used to adjust the refresh rate depending on the device operating temperature. DRAM technology requires increasingly frequent refresh operations to maintain data integrity as temperatures increase. More frequent refresh is required due to increased leakage of the DRAM capacitive storage elements as temperatures rise. A decreased refresh rate at lower temperatures will facilitate a savings in standby current. TCR allows for adequate refresh at four different temperature thresholds (+15C, +45C, +70C, and +85C). The setting selected must be for a temperature higher than the case temperature of the CellularRAM device. If the case temperature is +50C, the system can minimize self refresh current consumption by selecting the +70C setting. The +15C and +45C settings would result in inadequate refreshing and cause data corruption. Two WRITE-only, user-accessible configuration registers have been included to define device operation. The bus configuration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up, and can be updated any time the devices are operating in a standby state. Bus Configuration Register The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. The BCR is loaded using either a synchronous or an asynchronous WRITE operation when A[19] is HIGH and the configuration register enable (CRE) input is also HIGH (see Figures 12 and 13 on page 15). When CRE is LOW, a READ or WRITE operation will access the memory array. The values placed on address pins A[21:0] are latched into the BCR on the rising edge of ADV#, CE#, or WE#, whichever occurs first. LB# and UB# are "Don't Care." Table 5 on page 16 describes the control bits in the BCR. At power-up, the BCR is set to 9F4Fh. Partial Array Refresh Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, three-quarters array, one-half array, one-quarter array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Tables 9 and 10 on page 21). READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 12: Configuration Register WRITE in Asynchronous Mode Followed by READ CLK A[21:0] (except A19) OPCODE ADDRESS tAVS Select Control Register A192 ADDRESS tAVS CRE tVPH ADV# tVP tWC Initiate Control Register Access CE# tCW OE# tWP WE# Write Address Bus Value to Control Register LB#/UB# DQ[15:0] DATA VALID DON'T CARE NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; Hold data one clock; WAIT asserted during delay. 2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR. Figure 13: Configuration Register WRITE in Synchronous Mode Followed by READ1 CLK Latch Control Register Value A[21:0] (except A19) ADDRESS OPCODE tSP Latch Control Register Address A192 ADDRESS CRE tSP ADV# tHD tWC tCSP CE# OE# tSP WE# tHD LB#/UB# WAIT tCW High-Z High-Z DQ[15:0] DON'T CARE NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; Hold data one clock; WAIT asserted during delay. 2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 5: Bus Configuration Register Definition A[21:20] A19 A[18:16] 21-20 Reserved 18-16 19 Register Select Reserved A15 15 14 Operating Mode Must be set to "0" All must be set to "0" A14 A13 A12A11 A10 Reserved 13 12 11 Latency Counter Must be set to "0" BCR[13] BCR[12] BCR[11] 10 A8 A9 9 WAIT Polarity A7 7 8 WAIT Configuration (WC) Reserved Must be set to "0" Reserved A5 A6 Output Impedance Must be set to "0" Reserved A2 A1 A0 2 1 0 Burst Burst Wrap (BW)* Length (BL)* Must be set to "0" Latency Counter 0 0 0 Code 0-Reserved 0 0 1 Code 1-Reserved 0 1 0 Code 2 0 1 1 Code 3 (Default) 1 0 0 Code 4-Reserved 1 0 1 Code 5-Reserved 1 1 0 Code 6-Reserved 1 1 1 Code 7-Reserved BCR[10] WAIT Polarity 0 Active LOW 1 Active HIGH (default) Burst Wrap (Note 1) BCR[3] BCR[8] BCR[15] 3 4 5 6 Clock Configuration (CC) A3 A4 0 Burst wraps within the burst length 1 Burst no wrap (default) WAIT Configuration 0 Asserted during delay 1 Asserted one data cycle before delay (default) Output Impedance BCR[5] 0 Full Drive (default) 1 1/4 Drive Operation Mode 0 Synchronous burst access mode 1 Asynchronous access mode (default) BCR[6] Clock Configuration 0 Falling edge 1 Rising edge (default) Register Select BCR[19] 0 Select RCR 1 Select BCR BCR[2] BCR[1] BCR[0] Burst Length (Note 2) 0 0 1 4 words 0 1 0 8 words 0 1 1 16 words 1 1 1 Continuous burst (default) NOTE: 1. All burst WRITEs are continuous. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 6: Sequence and Burst Length WRAP NO WRAP 4-WORD BURST LENGTH -(DEC) BCR[3] BCR3 LINEAR LINEAR LINEAR LINEAR 0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-... 1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-4-5-6-7-... 2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-5-6-7-8-... 3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-6-7-8-9-... 4 0 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-7-8-9-10-... 5-6-7-8-9-10-11-... STARTING ADDRESS 8-WORD BURST LENGTH 16-WORD BURST LENGTH CONTINUOUS BURST 5 0 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 6 0 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-9-10-11-12- 7 0 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-10-11-12-13-... ... ... 14 0 15 0 ... ... 0 ... ... ... ... 1 0-1-2-3 ... 0-1-2-3-4-5-6-7 ... ... 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-17-18-19-20-.. 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-20-21.. ... ... 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-... 1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-4-5-6-7-... 2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 2-3-4-5-6-7-8-... 3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 3-4-5-6-7-8-9-... 4 1 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 4-5-6-7-8-9-10-... 5 1 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20 5-6-7-8-9-10-11... 6 1 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21 6-7-8-9-10-11-12... 7 1 7-8-9-10-11-12-1314 7-8-9-10-11-12-13-14-...-17-18-19-20-21-22 7-8-9-10-11-12-13... ... ... ... ... ... ... ... 14 1 ... 14-15-16-17-18-19-...-23-24-25-26-27-28-29 14-15-16-17-18-19-20-... 15 1 15-16-17-18-19-20-...-24-25-26-27-28-29-30 15-16-17-18-19-20-21-... Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength The output driver strength can be altered to adjust for different data bus loading scenarios. The reducedstrength option will be more than adequate in stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-drive-strength option is included to minimize noise generated on the data bus during READ operations. Normal output impedance should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. CellularRAM devices are tested using the full drive strength setting. Partial drive is approximately one-quarter full drive strength. Outputs are configured at full drive strength during testing. Burst Length (BCR[2:0]) Default = Continuous Burst Burst lengths define the number of words the device outputs during a burst READ operation. The device supports a burst length of 4, 8, or 16 words. The device can also be set in continuous burst mode where data is output sequentially without regard to address boundaries. WRITE bursts are always performed using continuous burst mode. Burst Wrap (BCR[3]) Default = Burst Wraps Within Address Boundaries The burst wrap option determines if a 4-, 8-, or 16word burst READ wraps within the burst length or steps through sequential addresses. If the wrap option is not enabled, the device outputs data from sequential addresses without regard to burst boundaries. When continuous burst operation is selected, the internal address wraps to 000000h if the device is read past the last address. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 15: WAIT Configuration (BCR[8] = 1) Clock Configuration (BCR[6]) Default = Transactions Processed on Rising Edge of Clock The clock configuration bit indicates whether synchronous operations are dependant upon the rising or falling edge of the clock input. All of the timing diagrams in this data sheet show the bus interaction aligned with the rising edge of the clock. CLK WAIT D[15:0] High-Z Data[0] Data valid (or invalid) after one clock delay WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively (Figure 14, below, and Figure 16 on page 19). When A8 = 1, the WAIT signal transitions one clock period prior to the data bus going valid or invalid (Figures 15 below and 16 on page 18). NOTE: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 16 on page 19. WAIT Polarity (BCR[10]) Default = WAIT Active HIGH The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state. Latency Counter (BCR[13:11]) Default = Three-Clock Latency The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred. Only latency code two (three clocks) or latency code three (four clocks) is allowed (see Table 7 on page 20 and Figure 17 on page 20). Figure 14: WAIT Configuration (BCR[8] = 0) CLK WAIT DQ[15:0] High-Z Data[0] Data[1] Data immediately valid (or invalid) NOTE: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 15. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 16: WAIT Configuration During Burst Operation1 CLK BCR[8] = 0 DATA VALID IN CURRENT CYCLE WAIT BCR[8] = 1 DATA VALID IN NEXT CYCLE WAIT DQ[15:0] D[0] D[1] D[2] D[3] D[4] DON'T CARE NOTE: 1. Clocked on rising edge. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 7: Latency Configuration MAX INPUT CLK FREQUENCY (MHZ) LATENCY CONFIGURATION CODE -701 2 (3 clocks) 75 (13.3 ns) 3 (4 clocks) - default 104 (9.62 ns) -856 1 44 (22.7 ns) 66 (15.2 ns) NOTE: 1. Clock rates below 50 MHz are allowed as long as tCSP specifications are met. Figure 17: Latency Counter CLK VIH VIL A[21:0] VIH VIL ADV# VALID ADDRESS VIH VIL Code 2 DQ[15:0] VOH VALID OUTPUT VOL Code 3 DQ[15:0] VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT (Default) VOH VOL DON'T CARE UNDEFINED Operating Mode (BCR[15]) Default = Asynchronous Operation The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation. parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Table 8 on page 21 describes the control bits used in the RCR. At power-up, the RCR is set to 0070h. Refresh Configuration Register Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, three-quarters array, one-half array, one-quarter array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Tables 9 and 10 on page 21). The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. The RCR is loaded using either a synchronous or an asynchronous WRITE operation when A[19] is LOW and the configuration register enable (CRE) input is HIGH (see Figures 12 and 13 on page 15). When CRE is LOW, a READ or WRITE operation will access the memory array. The values placed on addresses A[21:0] are latched into the RCR on the rising edge of ADV#, CE#, or WE#, whichever occurs first. LB# and UB# are "Don't Care." Altering the refresh 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 8: Refresh Configuration Register Mapping A[21:20] 21-20 RESERVED 19 18-8 RESERVED A6 A7 7 PAGE 6 A5 A4 5 4 DPD TCR A3 Select RCR 1 Select BCR RCR[7] 3 RESERVED PAR Page Mode Disabled (default) Page Mode Enable RCR[6] RCR[5] RCR[1] RCR[0] 0 0 0 0 0 1 Bottom 3/4 array Bottom 1/2 array 1 0 0 1 1 Bottom 1/4 array 1 0 0 None of array 1 0 1 Top 3/4 array 1 1 0 Top 1/2 array 1 Top 1/4 array 1 Maximum Case Temp. RCR[4] Full array (default) 0 1 Deep Power-Down 1 +85C (default) 0 DPD Enable 0 0 +70C 1 DPD Disable (default) 0 1 +45C 1 0 +15C 1 Refresh Coverage RCR[2] Page Mode Enable/Disable 1 Read Configuration Register 0 1 2 Address Bus A0 Must be set to "0" All must be set to "0" 0 A1 A2 Register Select 0 Table 9: A[18:8] Register Select All must be set to "0" RCR[19] A19 64Mb Address Patterns for PAR (A4 = 1) RCR[2] RCR[1] RCR[0] ACTIVE SECTION ADDRESS SPACE SIZE DENSITY 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Full die Three-quarters of die One-half of die One-quarter of die None of die Three-quarters of die One-half of die One-quarter of die 000000h-3FFFFFh 000000h-2FFFFFh 000000h-1FFFFFh 000000h-0FFFFFh 0 100000h-3FFFFFh 200000h-3FFFFFh 300000h-3FFFFFh 4 Meg x 16 3 Meg x 16 2 Meg x 16 1 Meg x 16 0 Meg x 16 3 Meg x 16 2 Meg x 16 1 Meg x 16 64Mb 48Mb 32Mb 16Mb 0Mb 48Mb 32Mb 16Mb Table 10: 32Mb Address Patterns for PAR (A4 = 1) RCR[2] RCR[1] RCR[0] ACTIVE SECTION ADDRESS SPACE SIZE DENSITY 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Full die Three-quarters of die One-half of die One-quarter of die None of die Three-quarters of die One-half of die One-quarter of die 000000h-1FFFFFh 000000h-17FFFFh 000000h-0FFFFFh 000000h-07FFFFh 0 080000h-1FFFFFh 100000h-1FFFFFh 180000h-1FFFFFh 2 Meg x 16 1.5 Meg x 16 1 Meg x 16 512K x 16 0 Meg x 16 1.5 Meg x 16 1 Meg x 16 512K x 16 32Mb 24Mb 16Mb 8Mb 0Mb 24Mb 16Mb 8Mb 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Deep Power-Down (RCR[4]) Default = DPD Disabled The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. Deep power-down is enabled when RCR[4] = 0, and remains enabled until RCR[4] is set to "1." perature higher than the case temperature of the CellularRAM device. If the case temperature is +50C, the system can minimize self refresh current consumption by selecting the +70C setting. The +15C and +45C settings would result in inadequate refreshing and cause data corruption. Page Mode Operation (RCR[7]) Default = Disabled The page mode operation bit determines whether page mode is enabled for asynchronous READ operations. In the power-up default state, page mode is disabled. Temperature Compensated Refresh (RCR[6:5]) Default = +85C Operation The TCR bits allow for adequate refresh at four different temperature thresholds (+15C, +45C, +70C, and +85C). The setting selected must be for a tem- 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Absolute Maximum Ratings* Voltage to Any Ball Except VCC, VCCQ Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50V to (4.0V or VccQ + 0.3V, whichever is less) Voltage on VCC Supply Relative to VSS . . -0.2V to +2.45V Voltage on VCCQ Supply Relative to VSS . -0.2V to +4.0V Storage Temperature (plastic). . . . . . . . -55C to +150C Operating Temperature (case) Wireless. . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C Industrial . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Soldering Temperature and Time 10s (lead only) . . . . . . . . . . . . . . . . . . . . . . . . . . . +260C *Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 11: Electrical Characteristics and Operating Conditions Wireless Temperature (-25C < TC < +85C) Industrial Temperature (-40C < TC < +85C) -70 (104 MHz) DESCRIPTION CONDITIONS Supply Voltage I/O Supply Voltage Input High Voltage SYMBOL MIN MAX MIN MAX VCC VCCQ (1.8V) VIH 1.70 1.70 1.40 1.70 1.70 1.40 1.95 2.25 VCCQ + 0.2 0.4 V V V -0.20 0.80 VCCQ 1.95 2.25 VCCQ + 0.2 0.4 0.20 VCCQ 1 1 0.20 VCCQ 1 1 V ICC2 25 15 35 11 25 ISB ISB Input Low Voltage Output High Voltage IOH = -0.2mA VIL VOH Output Low Voltage IOL = +0.2mA VOL VIN = 0 to VCCQ OE# = VIH or Chip Disabled ILI ILO Input Leakage Current Output Leakage Current READ Operating Current Asynchronous Random READ VIN = VCCQ or 0V Chip Enabled, Asynchronous Page READ IOUT = 0 Initial Access, Burst READ Continuous Burst READ VIN = VCCQ or 0V WRITE Operating Current Chip Enabled VIN = VCCQ or 0V Standby Current (32Mb) Chip Disabled VIN = VCCQ or 0V Standby Current (64Mb) Chip Disabled -85 (66 MHz) ICC1 -0.20 0.80 VCCQ UNITS NOTES V V A A 2 25 15 35 11 25 mA 1, 2 mA 1, 2 90 90 A 2, 3 100 100 A 2, 3 NOTE: 1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. 2. This device assumes a standby mode if the chip is disabled (CE# HIGH). It will also automatically go into a standby mode whenever all input signals are quiescent (not toggling), regardless of the state of CE#. In order to achieve low standby current, all inputs must be driven to either VCCQ or VSS. 3. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85C. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 12: Temperature Compensated Refresh Specifications and Conditions DESCRIPTION Temperature Compensated Refresh Standby Current CONDITIONS SYMBOL DENSITY VIN = VCC or 0V Chip Disabled ITCR 64Mb 32Mb MAX CASE TEMPERATURES TYP +85C +70C +45C +15C +85C +70C +45C +15C MAX UNITS 100 TBD TBD 50 90 TBD TBD 50 A A A A A A A A MAX UNITS 100 TBD TBD TBD 50 90 TBD TBD TBD 50 A A A A A A A A A A MAX UNITS 10 A NOTE: ITCR (MAX) values measured with PAR set to FULL ARRAY. Table 13: Partial Array Refresh Specifications and Conditions DESCRIPTION Partial Array Refresh Standby Current CONDITIONS SYMBOL DENSITY VIN = VCC or 0V, Chip Disabled IPAR 64Mb ARRAY PARTITION TYP Full 3/4 1/2 1/4 0 Full 3/4 1/2 1/4 0 32Mb NOTE: IPAR (MAX) values measured with TCR set to 85C. Table 14: Deep Power-Down Specifications DESCRIPTION Deep Power-Down 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN CONDITIONS SYMBOL VIN = VCC or 0V; +25C IZZ 24 TYP Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 15: Capacitance DESCRIPTION Input Capacitance Input/Output Capacitance (DQ) CONDITIONS SYMBOL MIN MAX UNITS NOTES TC = +25C; f = 1 MHz; VIN = 0V CIN CI/O - - 6 6 pF pF 1 1 NOTE: 1. These parameters are verified in device characterization and are not 100% tested. Figure 18: AC Input/Output Reference Waveform VCCQ VCCQ/2 Input VCCQ/2 Test Points Output VSS NOTE: AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input timing begins at VCCQ/2, and output timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 1.6ns. Figure 19: Output Load Circuit Table 16: Output Load Circuit VccQ R1 Test Point DUT 30pF R2 VCCQ R1/R2 1.8V 2.5V 3.0V 2.7 3.7 4.5 NOTE: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 17: Asynchronous READ Cycle Timing Requirements1 -701, -706 PARAMETER SYMBOL Address Access Time tAA 70 85 ns ADV# Access Time t AADV 70 85 ns Page Access Time t APA 20 25 ns Address Hold from ADV# HIGH t AVH 5 5 ns Address Setup to ADV# HIGH t AVS 10 10 ns LB#/UB# Access Time tBA LB#/UB# Disable to High-Z Output tBHZ LB#/UB# Enable to Low-Z Output t CE# HIGH between Subsequent Mixed-Mode Operations tCBPH Maximum CE# Pulse Width tCEM BLZ MIN MAX -856 MIN 70 0 8 0 MAX UNITS NOTES 85 ns 8 ns 4 3 10 10 ns 5 5 ns 10 1 7.5 1 10 s 7.5 ns 85 ns CE# LOW to WAIT Valid tCEW Chip Select Access Time tCO CE# LOW to ADV# HIGH tCVS Chip Disable to High-Z Output tHZ 0 Chip Enable to Low-Z Output tLZ 10 Output Enable to Valid Output tOE Output Hold from Output Disable tOH 5 5 ns Output Hold from Address Change tOHA 5 5 ns Output Disable to High-Z Output tOHZ 0 Output Enable to Low-Z Output tOLZ 5 Page Cycle Time tPC READ Cycle Time tRC Address Setting Time tS ADV# Pulse Width LOW t VP 10 10 ns ADV# Pulse Width HIGH tVPH 10 10 ns 70 10 10 8 0 ns 8 10 20 8 20 0 2 4 ns 3 ns ns 4 5 ns 3 20 25 ns 70 85 ns 10 8 ns 10 s 2 NOTE: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). 2. See the Appendix at the end of this data sheet. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 19 on page 25. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 4. Low-Z to High-Z timings are tested with the circuit shown in Figure 19 on page 25. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 18: Burst READ Cycle Timing Requirements1 -701 PARAMETER SYMBOL Burst to READ Access Time tABA CLK to Output Delay t ACLK Address Setup to ADV# HIGH t AVS Burst OE# LOW to Output Delay t BOE CE# HIGH between Subsequent Mixed-Mode Operations tCBPH tCEW CE# LOW to WAIT Valid MIN -706, -856 MAX MAX UNITS 33 55 ns 6.5 10 ns 10 MIN 10 20 5 ns 20 5 ns ns 1 7.5 1 7.5 ns 9.62 20 15 20 ns 20 4 20 ns CLK Period tCLK CE# Setup Time to Active CLK Edge t CSP 4 Hold Time from Active CLK Edge tHD 1 Chip Disable to High-Z Output tHZ 0 CLK Rise or Fall Time tKHKL CLK to WAIT Valid tKHTL CLK to High-Z Output tKHZ 3 8 CLK to Low-Z Output tKLZ 2 5 Output HOLD from CLK tKOH 2 2 ns CLK HIGH or LOW Time tKP 3 3 ns Output Disable to High-Z Output tOHZ 0 Output Enable to Low-Z Output tOLZ 5 Setup Time to Active CLK Edge tSP 3 1 8 ns 1.6 1.6 ns 6.5 10 ns 3 8 ns 2 5 ns 0 4 ns 8 8 0 NOTES 8 2 ns 2 5 ns 3 3 ns NOTE: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 19 on page 25. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 19 on page 25. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 4. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifcations are met. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 19: Asynchronous WRITE Cycle Timing Requirements -701, -706 PARAMETER SYMBOL Address Hold from ADV# Going HIGH t 5 5 ns Address Setup to ADV# Going HIGH t AVS 10 10 ns Address Valid to End of Write tAW 70 85 ns LB#/UB# Select to End of Write t 70 85 ns Maximum CE# Pulse Width t CE# LOW to WAIT Valid t 1 Async Address-to-Burst Transition Time t CKA 70 85 ns CE# Low to ADV# HIGH tCVS 10 10 ns Chip Enable to End of Write tCW 70 85 ns Data Hold from Write Time tDH 0 0 ns Data Hold from Write Time tDH 0 0 ns Data to WRITE Time Overlap tDW 23 23 ns 1 Chip Enable to Low-Z Output tLZ 10 10 ns 3 End WRITE to Low-Z Output tOW 5 5 ns 3 Address Setup Time tAS 0 0 ns 1 ADV# Pulse Width tVP 10 10 ns ADV# Pulse Width HIGH tVPH 10 10 ns ADV# Setup to End of WRITE tVS 70 85 ns WRITE Cycle Time tWC 70 85 ns WRITE to High-Z Output tWHZ WRITE Pulse Width tWP 46 WRITE Pulse Width HIGH tWPH WRITE Recovery Time tWR AVH BW MIN MIN 10 CEM CEW MAX -856 0 7.5 8 1 0 MAX UNITS 10 s 7.5 ns 8 NOTES 1 ns 2 55 ns 1 10 10 ns 0 0 ns NOTE: 1. See the Appendix at the end of this data sheet. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 19 on page 25. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 19 on page 25. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 20: Burst WRITE Cycle Timing Requirements -701 PARAMETER SYMBOL MIN -706, -856 MAX MIN MAX CE# HIGH between Subsequent Mixed-Mode Operations tCBPH 5 CE# LOW to WAIT Valid t 1 7.5 1 7.5 ns Clock Period tCLK 9.62 20 15 20 ns CE# Setup to CLK Active Edge t CSP 4 20 4 20 ns Hold Time from Active CLK Edge t HD 1 CLK Rise or Fall Time t KHKL 1.6 1.6 ns Clock to WAIT Valid t KHTL 6.5 10 ns CLK HIGH or LOW Time tKP 3 3 ns Setup Time to Activate CLK Edge tSP 3 3 ns CEW 5 UNITS NOTES ns 1 1 ns NOTE: 1. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 21: Initialization Timing Requirements -701, -706 PARAMETER SYMBOL Initialization Period (required before normal operations) tPU 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 29 MIN MAX 150 -856 MIN MAX UNITS 150 s NOTE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Burst CellularRAM Timing Diagrams Figure 20: Initialization Period Vcc (MIN) Vcc, VccQ = 1.70V tPU Device ready for normal operation Table 22: Initialization Timing Parameters -701, -706 PARAMETER SYMBOL Initialization Period tPU 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 30 MIN MAX 150 -856 MIN MAX UNITS 150 s NOTE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 21: Asynchronous READ tRC VIH A[21:0] VALID ADDRESS VIL tAA ADV# VIH VIL tCBPH CE# tHZ VIH VIL LB#/UB# tCO tBA VIH tBHZ VIL tOE OE# WE# tOHZ VIH VIL tOH VIH VIL tBLZ tOLZ tLZ VOH DQ[15:0] High-Z VOL VALID OUTPUT tCEW VIH WAIT High-Z VIL High-Z DON'T CARE UNDEFINED Table 23: Asynchronous READ Timing Parameters -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL AA 70 85 ns t tBA 70 85 ns tLZ 8 ns t t t BHZ 0 8 0 HZ MIN MAX 0 8 10 -856 MIN MAX 0 8 10 20 OE UNITS ns ns 20 10 10 ns tOH 5 tCBPH 5 5 ns tOHZ 0 t 1 7.5 ns t 5 5 ns 85 ns tRC 70 85 ns tBLZ CEW tCO 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 7.5 70 1 31 OLZ 5 ns 8 0 ns 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 22: Asynchronous READ Using ADV# VIH A[21:0] VALID ADDRESS VIL tAA tAVS tVPH tAVH VIH ADV# VIL tAADV tVP tCBPH tCVS tHZ VIH CE# VIL tCO tBA tBHZ VIH LB#/UB# VIL tOE tOHZ VIH OE# VIL tOH VIH WE# tOLZ tBLZ VIL tLZ VOH DQ[15:0] High-Z VOL VALID OUTPUT tCEW VIH WAIT High-Z VIL High-Z DON'T CARE UNDEFINED Table 24: Asynchronous READ Timing Parameters -701, -706 SYMBOL tAA tAADV t AVH tAVS t MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL 70 85 ns tCVS 70 85 MIN MAX 10 MIN MAX 10 ns 5 ns t 10 10 ns tOE 85 ns t OH 5 8 ns tOHZ 0 5 5 ns 70 20 20 5 ns 10 10 ns tOLZ 5 5 ns t VP 10 10 ns 7.5 ns tVPH 10 10 ns 85 ns 1 tCO 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 7.5 70 1 32 0 ns tBLZ tCEW 8 ns ns 0 CBPH 0 8 10 tBHZ t 8 10 0 ns 5 BA 8 UNITS tHZ LZ 0 -856 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 23: Page Mode READ tRC A[21:4] VIH VALID ADDRESS VIL VIH A[3:0] ADV# VALID ADDRESS VIL VALID ADDRESS VALID ADDRESS tPC tAA VIH VALID ADDRESS VIL VIH tCBPH tHZ tCO tCBPH CE# VIL LB#/UB# tBA VIH tBHZ VIL tOHZ tOE VIH OE# VIL tOH VIH WE# tOLZ tBLZ VIL VOH DQ[15:0] tAPA tOHA tLZ Valid Output High-Z VOL Valid Output Valid Output Valid Output tCEW VIH WAIT High-Z VIL High-Z DON'T CARE UNDEFINED Table 25: Asynchronous READ Timing Parameters (Page Mode Operation) -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL MIN MAX MIN MAX 70 85 ns tLZ t 20 25 ns t 70 85 ns tOH 5 5 ns 8 ns t OHA 5 5 ns tBA t BHZ 0 8 0 20 OE 10 10 ns tOHZ 0 tCBPH 5 5 ns tOLZ 5 t 1 7.5 ns t PC 85 ns tRC 8 ns tBLZ CEW tHZ 7.5 1 70 tCO 0 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 8 0 33 10 UNITS tAA APA 10 -856 8 ns 20 0 8 ns ns 5 ns 20 25 ns 70 85 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 24: Single-Access Burst READ Operation1 tCLK tKP VIH CLK A[21:0] VIL tSP VIH tHD VALID ADDRESS VIL tAVS VIH ADV# tSP VIL tHD CE# tCSP VIH tHZ tABA VIL tBOE tOHZ VIH OE# VIL tSP WE# tOLZ tHD VIH VIL tSP tHD VIH LB#/UB# VIL tCEW VOH WAIT tKHTL High-Z High-Z VOL DQ[15:0] tKOH tACLK VOH VALID OUTPUT High-Z VOL READ Burst Identified (WE# = HIGH) DON'T CARE UNDEFINED NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 26: Burst READ Timing Parameters -706, -856 -701 SYMBOL MAX UNITS tABA 33 55 ns tHZ tACLK 6.5 10 ns tKHTL ns tKOH 2 2 ns 20 ns t 3 3 ns tAVS MIN MAX 10 MIN -706, -856 -701 10 20 t BOE SYMBOL KP MIN MAX MIN MAX UNITS 0 8 0 8 ns 10 ns 6.5 1 7.5 1 7.5 ns t OHZ 0 tCLK 9.62 20 15 20 ns tOLZ 5 5 ns tCSP 4 20 4 20 ns tSP 3 3 ns t 1 t CEW HD 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 1 8 0 8 ns ns 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 25: 4-Word Burst READ Operation1 tKP tCLK CLK A[21:0] ADV# CE# VIH VIL tSP VIH tHD VALID ADDRESS tAVS VIL tSP VIH VIL tHD tABA tCSP VIH VIL tCBPH tHZ tBOE OE# WE# LB#/UB# VIH VIL tOHZ tSP tHD tSP tHD tOLZ VIH VIL VIH VIL tKHTL tCEW WAIT VOH High-Z VOL High-Z tACLK DQ[15:0] VOH VALID OUTPUT High-Z VOL tKOH VALID OUTPUT VALID OUTPUT VALID OUTPUT READ Burst Identified (WE# = HIGH) UNDEFINED DON'T CARE NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 27: Burst READ Timing Parameters -701 SYMBOL tABA t MIN ACLK tAVS CBPH MAX MIN -701 MAX UNITS 33 55 6.5 10 10 10 20 tBOE t -706, -856 5 20 5 SYMBOL MIN -706, -856 MAX MIN 8 0 MAX UNITS 8 ns 10 ns ns tHD 1 ns t 0 ns tKHTL ns tKOH 2 2 ns ns t 3 3 ns HZ KP 1 6.5 tCEW 1 7.5 1 7.5 ns tOHZ 0 tCLK 9.62 20 15 20 ns tOLZ 5 5 ns tCSP 4 20 4 20 ns tSP 3 3 ns 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 35 8 0 ns 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 26: 4-Word Burst READ Operation (with LB#/UB#)1 tKP tCLK CLK A[21:0] ADV# CE# VIH VIL tHD tSP VIH VALID ADDRESS tAVS VIL tSP VIH VIL tHD tABA tCSP VIH tCBPH VIL tHZ tBOE OE# WE# LB#/UB# VIH VIL tOHZ tSP tHD tSP tHD tOLZ VIH VIL VIH VIL tCEW WAIT tKHTL VOH High-Z VOL High-Z DQ[15:0] VOH VALID OUTPUT High-Z VOL tKHZ tKOH tACLK tKHZ tKLZ VALID OUTPUT VALID OUTPUT High-Z READ Burst Identified (WE# = HIGH) DON'T CARE UNDEFINED NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. BCR configured with a burst length of four. Table 28: Burst READ Timing Parameters (with LB#/UB#) -706, -856 -701 SYMBOL MIN MAX UNITS tABA 33 55 ns tHZ t 6.5 10 ns t ns tKHZ 3 8 ns t KLZ 2 5 ns t KOH 2 2 ns 3 ns ACLK tAVS MAX 10 MIN -706, -856 -701 10 20 20 SYMBOL MIN MAX MIN MAX UNITS 0 8 0 8 ns 10 ns 3 8 ns 2 5 ns 6.5 KHTL t BOE t CBPH 5 t CEW 1 7.5 1 7.5 ns t KP 3 5 CLK 9.62 20 15 20 ns t OHZ 0 tCSP 4 20 4 20 ns tOLZ 5 5 ns t 1 ns t 3 3 ns t HD 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 1 36 SP 8 0 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 27: READ Burst Suspend1 tKP tCLK VIH CLK VIL tHD tSP VIH A[21:0] VIL VALID ADDRESS VALID ADDRESS tAVS VIH tSP ADV# VIL tCBPH VIH tHZ tCSP CE# VIL tOHZ OE# tOHZ VIH VIL VIH WE# VIL VIH LB#/UB# VIL tHD tSP tSP tHD tBOE VOH tOLZ WAIT VOL High-Z VOH DQ[15:0] VOL High-Z tKOH VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT tACLK DON'T CARE UNDEFINED NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 29: Burst READ Timing Parameters -701 SYMBOL t MIN MAX MIN 6.5 ACLK tAVS -706, -856 10 UNITS 10 ns t ns tKOH 2 2 ns ns tKP 3 3 ns MAX MIN MAX UNITS 0 8 0 8 ns ns OHZ 0 tCLK 9.62 20 15 20 ns tOLZ 5 5 ns tCSP 4 20 4 20 ns tSP 3 3 ns tHD 1 CBPH 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 5 HZ MIN t t 5 20 SYMBOL -706, -856 MAX 10 20 tBOE -701 1 8 0 8 ns ns 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 28: Continuous Burst READ Showing an Output Delay with BCR[8] = 0(1) for End-of-Row Condition1 CLK tKP VIH VIL tCLK A[21:0] tKHKL VIH VIL ADV# VIH VIL LB#/UB# VIH VIL CE# VIH VIL OE# VIH VIL WE# VIH VIL tKHTL tKHTL WAIT VOH VOL DQ[15:0] VOH VALID OUTPUT VALID OUTPUT VOL VALID OUTPUT VALID OUTPUT tKOH tACLK WAIT CONFIG (BCR8) = 0 DON'T CARE WAIT CONFIG (BCR8) = 1 NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 30: Burst READ Timing Parameters -701 SYMBOL t MIN MAX MIN 6.5 ACLK tCLK -706, -856 9.62 tKHKL 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 20 1.6 15 -701 SYMBOL MAX UNITS 10 ns t 20 ns tKOH 2 2 ns 1.6 ns tKP 3 3 ns 38 MIN -706, -856 MAX MIN 6.5 KHTL MAX UNITS 10 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 29: CE#-Controlled Asynchronous WRITE tWC A[21:0] VIH VALID ADDRESS VIL tAW tWR tAS VIH ADV# VIL tCEM CE# tCW VIH VIL tBW VIH LB#/UB# OE# VIL VIH VIL tWPH tWP VIH WE# VIL tDH tDW DQ[15:0] IN VIH DQ[15:0] OUT VOH High-Z VIL tWHZ tLZ WAIT VALID INPUT VOL tCEW VIH High-Z VIL High-Z DON'T CARE Table 31: Asynchronous WRITE Timing Parameters -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL MIN MAX -856 MIN MAX UNITS AS 0 0 ns t 23 23 ns tAW 70 85 ns tLZ 10 10 ns t 70 85 ns t WC 70 85 ns 10 s tWHZ 0 7.5 ns tWP 46 55 ns 10 10 ns 0 0 ns t BW 10 tCEM tCEW 1 7.5 1 DW CW 70 85 ns t tDH 0 0 ns tWR t 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN WPH 39 8 0 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 30: LB#/UB#-Controlled Asynchronous WRITE tWC A[21:0] VIH VALID ADDRESS VIL tAW tAS ADV# CE# LB#/UB# OE# tWR VIH VIL tCEM tCW VIH VIL tBW VIH VIL VIH VIL tWP tWPH VIH WE# VIL tDW DQ[15:0] IN VIH DQ[15:0] OUT VOH High-Z VIL tDH VALID INPUT tWHZ tLZ VOL tCEW VIH WAIT High-Z VIL High-Z DON'T CARE Table 32: Asynchronous WRITE Timing Parameters -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL MIN MAX -856 MIN MAX UNITS AS 0 0 ns t 23 23 ns tAW 70 85 ns tLZ 10 10 ns t 70 85 t BW 10 tCEM tCEW t CW tDH 1 7.5 1 DW ns t WC 70 10 s tWHZ 0 7.5 ns tWP 46 55 ns 10 10 ns 0 0 ns 70 85 ns t 0 0 ns tWR 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 40 WPH 85 8 0 ns 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 31: WE#-Controlled Asynchronous WRITE tWC VIH A[21:0] VALID ADDRESS VIL tAW tWR VIH ADV# VIL tCEM tCW VIH CE# VIL tBW VIH LB#/UB# VIL VIH OE# VIL tAS tWP tWPH VIH WE# VIL tDH tDW DQ[15:0] IN VIH High-Z VIL tOW tWHZ tLZ DQ[15:0] OUT VALID INPUT VOH VOL tCEW VIH WAIT High-Z VIL High-Z DON'T CARE Table 33: Asynchronous WRITE Timing Parameters -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL MIN MAX MIN MAX 0 0 ns AW 70 85 ns t OW 5 5 ns tBW 70 85 ns tWC 70 85 ns 10 s tWHZ 7.5 ns t WP 46 55 ns 10 10 ns 0 0 ns t 10 tCEM t CEW 1 7.5 1 tCW 70 85 ns tWPH tDH 0 0 ns tWR tDW 23 23 ns 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 41 0 10 UNITS tLZ tAS 10 -856 8 0 ns 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 32: Asynchronous WRITE Using ADV# A[21:0] VIH VALID ADDRESS VIL tAVH tAVS tVS tVPH ADV# tVP VIH VIL tAW tCEM tCW VIH CE# VIL tBW VIH LB#/UB# OE# VIL VIH VIL tAS WE# tWPH tWP VIH VIL tDW DQ[15:0] VIH IN VIL High-Z DQ[15:0] VOH OUT VOL VALID INPUT tWHZ tLZ tDH tOW tCEW WAIT VIH High-Z VIL High-Z DON'T CARE Table 34: Asynchronous WRITE Timing Parameters -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL 0 0 ns t 5 5 ns tLZ AVS 10 10 ns t tAW 70 85 ns tBW 70 85 t AS tAVH t t 10 CEM tCEW 1 7.5 1 MIN MAX -856 MIN MAX UNITS 23 23 ns 10 10 ns 5 5 ns tVP 10 10 ns ns tVPH 10 10 ns 10 s t 70 7.5 ns tWHZ DW OW VS 0 85 8 0 ns 8 ns tCW 70 85 ns tWP 46 55 ns tDH 0 0 ns tWPH 10 10 ns 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 33: Burst WRITE Operation1 tCLK CLK VIH VIL A[21:0] VIH VALID ADDRESS VIL tSP ADV# VIH VIL LB#/UB# tSP tHD tCSP VIH VIL CE# tHD VIH tCBPH VIL OE# VIH VIL tSP WE# tHD VIH VIL tCEW VOH WAIT tKHTL High-Z VOL High-Z tSP tHD VIH DQ[15:0] D[0] VIL D[1] D[2] D[3] WRITE Burst Identified (WE# = LOW) DON'T CARE NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 35: Burst WRITE Timing Parameters -701 SYMBOL MIN -706, -856 MAX MIN tCBPH 5 tCEW 1 7.5 1 CLK 9.62 20 tCSP 4 20 t 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN MAX 5 -701 UNITS SYMBOL ns tHD 7.5 ns tKHTL 15 20 ns t 4 20 ns SP 43 MIN -706, -856 MAX 1 MIN 6.5 3 MAX 1 ns 10 3 UNITS ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 34: Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0(1) for End-of-Row Condition1 CLK VIH VIL tCLK A[21:0] tKP tKHKL VIH VIL ADV# VIH VIL LB#/UB# VIH VIL CE# VIH VIL VIH WE# VIL VIH OE# VIL tKHTL tKHTL WAIT VOH VOL tSP VIH DQ[15:0] tHD VALID INPUT D[n] VIL VALID INPUT D[n+1] VALID INPUT D[n+2] VALID INPUT D[n+3] END OF ROW DON'T CARE NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 36: Burst WRITE Timing Parameters -701 -706, -856 -701 SYMBOL MIN MAX MIN MAX UNITS t 9.62 20 15 20 ns t ns tKP 3 3 ns ns tSP 3 3 ns CLK tHD 1 tKHKL 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 1 1.6 1.6 SYMBOL 44 MIN -706, -856 MAX MIN 6.5 KHTL MAX UNITS 10 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 35: Burst WRITE Followed by Burst READ1 tCLK CLK VIH VIL A[21:0] VIH VIL ADV# VIH VIL tSP tSP tHD LB#/UB# tSP tHD VIH VIL tCSP CE# OE# tHD VIH VIL tCBPH1 tABA tCSP VIH VIL tOHZ tSP tHD VIH WE# VIL WAIT tHD VALID ADDRESS VALID ADDRESS tSP tHD VOH VOL tBOE High-Z tSP tHD DQ[15:0] VIH IN/OUT VIL High-Z D[0] D[1] D[2] D[3] VOL High-Z tKOH tACLK VOH VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT DON'T CARE UNDEFINED NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. To allow self-refresh operations to occur between transactions, CE# must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. 3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 37: WRITE Timing Parameters -701 SYMBOL t CBPH tCLK t CSP MIN -706, -856 MAX 5 MIN MAX -701 UNITS 5 SYMBOL ns t tSP 9.62 20 15 20 ns 4 20 4 20 ns HD MIN -706, -856 MAX MIN MAX UNITS 1 1 ns 3 3 ns Table 38: READ Timing Parameters -701 SYMBOL MIN -706, -856 MAX MIN -701 MAX UNITS SYMBOL MIN -706, -856 MAX MIN MAX UNITS ABA 33 55 ns t HD 1 1 ns tACLK 6.5 10 ns tKOH 2 2 ns tBOE 20 20 ns tOHZ 0 8 0 8 ns 8 0 8 ns t tCLK 9.62 20 15 20 ns tOHZ 0 tCSP 4 20 4 20 ns tSP 3 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 45 3 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 36: Asynchronous WRITE Followed by Burst READ1 tCLK VIH CLK VIL VIH A[21:0] VIL VIH ADV# VIL VALID ADDRESS tAVS tSP VALID ADDRESS tAVH tAW tHD VALID ADDRESS tWR tVPH tVS tBW tVP tCVS VIH LB#/UB# VIL CE# tCKA tWC tWC tSP tHD tCBPH1 tCW VIH VIL tABA tCSP tOHZ VIH OE# VIL tWC tWP VIH WE# VIL WAIT tSP tHD tWPH tCEW VOH VOL DQ[15:0] VIH IN/OUT VIL tBOE tWHZ High-Z DATA tDH VOH DATA VOL tDW High-Z tKOH tACLK VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT DON'T CARE UNDEFINED NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and burst operations, CE# must go HIGH. CE# must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. 3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 39: WRITE Timing Parameters -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL MIN MAX -856 MIN MAX UNITS tAVH 5 5 ns tVP 10 10 ns tAVS 10 10 ns tVPH 10 10 ns tAW 70 85 ns tVS 70 85 ns tBW 70 85 ns tWC 70 85 tCKA 70 85 ns tWHZ tCVS 10 10 ns tWP 46 55 ns tCW 70 85 ns tWPH 10 10 ns tDH 0 0 ns tWR 0 0 ns tDW 20 23 ns 0 8 0 ns 8 ns Table 40: READ Timing Parameters -701 SYMBOL MIN -706, -856 MAX MIN -701 MAX UNITS MIN MAX MIN MAX tABA 33 55 ns tCSP 4 20 4 20 tACLK 6.5 10 ns tHD 1 20 ns tKOH 2 ns tOHZ 0 tSP 3 20 tBOE tCBPH 5 tCEW 1 7.5 1 7.5 ns tCLK 9.62 20 15 20 ns 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 5 SYMBOL -706, -856 46 1 0 3 ns ns 2 8 UNITS ns 8 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 37: Asynchronous WRITE Followed By Burst READ--ADV# LOW1 CLK VIH VIL A[21:0] VIH VIL ADV# VIH VIL LB#/UB# CE# tCLK tWC tWC VALID ADDRESS VALID ADDRESS tWR tAW tSP tCKA tKP tHD VALID ADDRESS tSP tBW VIH tSP tHD VIL tCW VIH tCSP tCBPH1 tABA VIL tOHZ OE# WE# WAIT VIH tWP VIH tSP tHD tWPH VIL VOH tCEW tBOE VOL VIH DQ[15:0] IN/OUT tWC VIL VIL tWHZ High-Z DATA tDH VOH DATA VOL tDW HIGH-Z tKOH tACLK VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT UNDEFINED DON'T CARE NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and burst operations, CE# must go HIGH. CE# must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. 3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 41: WRITE Timing Parameters -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL MIN MAX 70 -856 MIN MAX UNITS 8 ns tAW 70 85 ns tWC 85 tBW 70 85 ns tWHZ t CKA 70 85 ns t WP 46 55 ns t CW 70 85 ns t WPH 10 10 ns tDH 0 0 ns tWR 0 0 ns tDW 23 23 ns 0 8 0 ns Table 42: READ Timing Parameters -701 SYMBOL t t MIN -706, -856 MAX UNITS ABA 33 55 ns t ACLK 6.5 10 ns t 20 20 ns tBOE MAX MIN -701 MIN MAX MIN MAX CSP 4 20 4 20 HD 1 1 tKOH 2 2 ns ns tKP 3 3 ns tCBPH 5 t CEW 1 7.5 1 7.5 ns t OHZ 0 CLK 9.62 20 15 20 ns t SP 3 t 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 5 SYMBOL -706, -856 47 8 0 3 UNITS ns ns 8 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 38: Asynchronous WRITE Followed by Asynchronous READ--ADV# LOW A[21:0] VIH VALID ADDRESS VIL VALID ADDRESS VALID ADDRESS tAA tWR tAW VIH ADV# LB#/UB# CE# tHZ tS VIL tBLZ tBW VIH VIL tBHZ tCEM tCBPH1 tCW VIH VIL tLZ OE# VIH tWC VIL tWPH tWP WE# WAIT tOHZ tOE VIH VIL VOH VOL DQ[15:0] VIH IN/OUT VIL tOLZ tWHZ High-Z DATA VOH High-Z DATA VALID OUTPUT VOL tDW tDH UNDEFINED DON'T CARE NOTE: CE# must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. Table 43: WRITE Timing Parameters -856 -701, -706 SYMBOL MIN MAX MIN -856 -701, -706 MAX UNITS SYMBOL MIN MAX MIN MAX 85 UNITS AW 70 85 ns t WC 70 t BW 70 85 ns t WHZ 0 t CW 70 85 ns t WP 46 55 ns t DH 0 0 ns t WPH 10 10 ns tDW 23 23 ns tWR 0 0 ns t 8 ns 0 8 ns Table 44: READ Timing Parameters -856 -701, -706 SYMBOL t BLZ tCBPH t 0 MIN 8 0 MAX UNITS 85 ns SYMBOL t 8 ns tOE LZ MIN 10 ns OHZ 0 5 5 ns tOLZ 5 10 s t 8 ns 0 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 8 0 48 S MIN MAX 10 20 10 10 MAX 10 t CEM tHZ MAX 70 AA tBHZ t MIN -856 -701, -706 8 0 ns 20 ns 8 ns 5 10 UNITS ns 10 s Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 39: Asynchronous WRITE Followed by Asynchronous READ A[21:0] VIH VIL VALID ADDRESS tAVS ADV# LB#/UB# CE# VIH tVPH VALID ADDRESS tAVH tAW VALID ADDRESS tAA tWR tVS tVP tHZ tS VIL tBW tCVS VIH tBLZ VIL tCW VIH tCEM tCBPH1 tBHZ VIL tLZ OE# WE# WAIT tOHZ VIH VIL tWC tWP VIH tOLZ tWPH VIL VOH VOL DQ[15:0] VIH IN/OUT VIL tOE tWHZ High-Z DATA VOH DATA VALID OUTPUT High-Z VOL tDW tDH DON'T CARE UNDEFINED NOTE: CE# must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. Table 45: WRITE Timing Parameters -701, -706 SYMBOL MAX -856 t AVH MIN 5 MIN 5 t AVS 10 10 -701, -706 MAX UNITS ns SYMBOL MIN 10 t VP ns t VPH 10 MAX -856 MIN 10 MAX 10 UNITS ns ns AW 70 85 ns t VS 70 85 ns t BW 70 85 ns t WC 70 85 ns t CVS 10 10 ns t WHZ 0 CW 70 85 ns t WP 46 55 ns tDH 0 0 ns tWPH 10 10 ns tDW 23 23 ns tWR 0 0 ns t t 8 0 8 ns Table 46: READ Timing Parameters -701, -706 SYMBOL MIN t AA t BHZ 0 BLZ 10 5 t tCBPH MAX 70 MIN 8 0 0 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 8 -701, -706 MAX 85 UNITS ns 8 SYMBOL MIN 10 t LZ ns t OE 10 ns t OHZ 0 5 5 10 tCEM tHZ -856 0 ns tOLZ 10 s tS 8 ns 49 MAX -856 MIN 10 20 8 0 MAX UNITS ns 20 ns 8 ns 10 s 5 10 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 40: 54-Ball FBGA 0.700 0.075 SEATING PLANE C 0.10 C SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or 62% Sn, 36% Pb, 2% Ag SOLDER BALL PAD: O 0.27mm BALL A6 54X O 0.35 TYP SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS O 0.33 SUBSTRATE: PLASTIC LAMINATE ENCAPSULATION MATERIAL: EPOXY NOVOLAC BALL A1 ID 0.75 TYP BALL A1 0.75 TYP 8.00 0.10 BALL A1 ID 6.00 3.00 0.05 4.00 1.875 0.050 3.00 0.05 1.00 MAX 6.00 0.10 NOTE: 1. All dimensions in millimeters; MAX/MIN, or typical, as noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. Data Sheet Designation: ADVANCE This data sheet contains initial descriptions of products still in development. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, and the Micron and M Logos are trademarks and/or service marks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc., inside the U.S. and a trademark of Infineon Technologies outside the U.S. All other trademarks are the property of their respective owners. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY APPENDIX A How Extended Timings Impact CellularRAMTM Operation When a CellularRAM device is configured for pagemode operation, the address inputs are used to accelerate READ accesses and cannot be used by the onchip circuitry to schedule refresh. CE# must return HIGH upon completion of all WRITE operations when page mode is enabled (see Figure 43 below). The total time taken for a WRITE operation should not exceed 10s to accommodate orderly scheduling of refresh. Introduction This note describes CellularRAM timing requirements in systems that perform extended operations. CellularRAM products use a DRAM technology that periodically requires refresh to ensure against data corruption. CellularRAM devices include on-chip circuitry that performs the required refresh in a manner that is completely transparent in systems with normal bus timings. The refresh circuitry imposes constraints on timings in systems that take longer than 10s to complete an operation. WRITE operations are affected if the device is configured for asynchronous operation. Both READ and WRITE operations are affected if the device is configured for burst-mode operation. Figure 43: Extended Timing for tCEM1 tCEM < 10s CE# NOTE: 1. Timing constraints when page mode is enabled. Asynchronous and Page-Mode Operation CellularRAM products require that asynchronous WRITE operations must be completed within 10s. After completing an operation, the device must either enter standby (by transitioning CE# HIGH), or perform a second operation using a new address. Figures 41 and 42 demonstrate these constraints as they apply during an asynchronous (page-mode-disabled) operation. Either the CE# active period (tCEM in Figure 41) or the address valid period (tTM in Figure 42) must be less than 10s during any operation to accommodate orderly scheduling of refresh. Modified timings are only required during extended WRITE operations (see Figure 44 below). An extended WRITE operation requires that both the WRITE pulse width (tWP) and the data valid period (tDW) be lengthened to at least the minimum WRITE cycle time (tWC [MIN]). These increased timings ensure that time is available for both a refresh and successful completion of the WRITE operation. Figure 44: Extended Asynchronous Write Operation Figure 41: Extended Timing for tCEM tCEM < 10s CE# tCEM or tTM > 10s ADDRESS ADDRESS CE# NOTE: Timing constraints when page mode is disabled. LB#/UB# t Figure 42: Extended Timing for TM WE# CE# tWP > tWC (MIN) tDW > tWC (MIN) tTM < 10s DATA-IN Data Valid ADDRESS NOTE: 1. Timing constraints when page mode is disabled. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Burst-Mode Operation Summary When configured for burst-mode operation, it is necessary to allow the device to perform a refresh within any 10s window. One of two conditions will enable the device to schedule a refresh within 10s. The first condition is when all burst operations complete within 10s. A burst completes when the CE# signal is registered HIGH on a positive (BCR[6] = 1) or a negative (BCR[6] = 0) clock edge. The second condition that allows a refresh is when a burst access crosses a row boundary. The row-boundary crossing causes WAIT to be asserted while the next row is accessed and enables the scheduling of refresh. CellularRAM products are designed to ensure that any possible asynchronous timings do not cause data corruption due to lack of refresh. Slow bus timings will only affect asynchronous WRITE operations (READs are unaffected). The impact on asynchronous WRITE operations is that some of the timing parameters (tWP and tDW) are lengthened. Burst mode timings must allow the device to perform a refresh within any 10s period. A burst operation must either complete (CE# registered HIGH) or cross a row boundary within 10s to ensure successful refresh scheduling. These timing requirements are likely to have little or no impact when interfacing a CellularRAM device with a lowspeed memory bus. 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved. ADVANCE 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 47: Revision History CHANGE DATE CHANGED BY 7 07/10/03 ddb 6 06/23/03 ddb 5 4 06/20/03 06/19/03 ddb ddb 3 06/18/03 ddb 2 1 06/09/03 06/06/03 ddb ddb 09005aef80be2036/09005aef80be1fbd Burst CellularRAM.fm - Rev. A 7/03 EN DESCRIPTION Input/Output leakage to 1A. Added tAS, removed tS. Incorporated Industrial Temperature data where applicable. Rounded initial latency and initial access to 39ns. Added -706 part information where applicable. Removed tSP and tHD from CE# in Burst diagrams. Changed standby power to 90A and 100A as marked; changed specified values to "TBD." Absolute Maximum Signal Input value changed. Initial release. 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All Rights Reserved.