MT45W4MW16BFB-701 WT - Micron

‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

09005aef80be2036/09005aef80be1fbd

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE‡

BURST

CellularRAMTM

MT45W4MW16BFB

MT45W2MW16BFB

For the latest data sheet, please refer to Micron’ s Web site:

www.micron.com/datasheets.

Features

• Si ngle device supports asynchronous, page, and

burst operations

•V

CC, VCCQ Voltages

1.70V–1.95V VCC

1.70V–2.25V VCCQ (Option W)

• Random Access Time: 70ns

• Burst Mode Wr ite Access

Continuous burst

• Burst Mode Read Access

4, 8, or 16 words, or continuous burst

MAX clock rate: 104 MHz (tCLK = 9.62ns)

Burst initial latency: 39ns (4 clocks) @ 104 MHz

tACLK: 6.5ns @ 104 MHz

• Page Mode Read Access

Sixteen-word page size

Interpage read access: 70ns

Intrapage read access: 20ns

•Low Power Consumption

Asynchronous READ < 25mA

Intrapag e READ < 1 5mA

Initial access, burst READ: (39ns [4 clocks]

@ 104 MHz) < 35mA

Continuous burst READ < 15mA

Standby: 90µA (32Mb), 100µA (64Mb)

Deep power-down < 10µA

• Low-Power Features

Temperature Compensated Refresh (TCR)

Partial Array Refresh (PAR)

Deep Power-Down (DPD) Mode

Figure 1: Ball Assignment 54-Ball FBGA

OTE:

See Table 1 on page 6 for ball descriptions, and

Figure 40 on page 50 for 54-ball mechanical drawing.

NOTE: A part marking guide for the FBGA devices can be found

on Micron’s Web site: www. micron.com/numberguide

Part Numbe r Exampl e:

MT45W2MW16BFB-701WT

Options Marking

•V

CC Core Voltage Supply:

1.80V – MT45WxMx16BFB W

•V

CCQ I/O Voltage

3.0V – MT45WxML16BFB (contact factory)

2.5V – MT45WxMV16BFB (contact factory)

1.8V – MT45WxMW16BFB W

• Timing

60ns access (contact factory)

70ns access -70

85ns access -85

•Frequency

66 MHz 1

104 MHz 6

Options (continued) Marking

• Configuration:

4 Meg x 16 MT45W4Mx16BFB

2 Meg x 16 MT45W2Mx16BFB

•Package

54-ball FBGA FB

• Operating Temperature Range

Wireless (-25°C to +85°C) WT

Industrial (-40°C to +85° C) IT (contact factory)

1 2 3 4 5 6

Top View

(Ball Down)

LB#

DQ8

DQ9

VSSQ

VCCQ

DQ14

DQ15

A18

WAIT

OE#

UB#

DQ10

DQ11

DQ12

DQ13

A19

CLK

A17

A21

A14

A12

ADV#

CE#

DQ1

DQ3

DQ4

DQ5

WE#

A11

CRE

DQ0

DQ2

VCC

VSS

DQ6

DQ7

A20

A16

A15

A13

A10

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

List of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Bus Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Wait Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

LB#/UB# Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Partial Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Deep Power-Down Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Burst Length (BCR[2:0]) Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Burst Wrap (BCR[3]) Default = Burst Wraps Within Address Boundaries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Clock Configuration (BCR[6]) Default = Transactions Processed on Rising Edge of Clock. . . . . . . . . . . . . . . . . . 18

WAIT Configuration (BCR[8])Default = WAIT Transitions One Clock Before Data Valid/Invalid. . . . . . . . . . . . 18

WAIT Polarity (BCR[10]) Default = WAIT Active HIGH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Latency Counter (BCR[13:11]) Default = Three-Clock Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Refresh Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Deep Power-Down (rcr[4]) Default = DPD Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Temperature Compensated Refresh (rcr[6:5]) Default = +85°C Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Page Mode Operation (rcr[7]) Default = Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Asynchronous Random READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Asynchronous Page READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Initial Access, Burst READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Continuous Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Burst CellularRAM Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

How Extended Timings Impact CellularRAMtm Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Asynchronous and Page-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Burst-Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

List of Tables

Table 1: FBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2: Bus Operations – Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3: Bus Operations – Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4: Abbreviated Component Marks – CellularRAM FBGA-Packaged Components. . . . . . . . . . . . . . . . . . . . . 8

Table 5: Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6: Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 7: Latency Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8: Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 9: 64Mb Address Patterns for PAR (A4 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10: 32Mb Address Patterns for PAR (A4 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11: Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 12: Temperature Compensated Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13: Partial Array Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14: Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 15: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 16: Output Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17: Asynchronous READ Cycle Timing Requirements1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 18: Burst READ Cycle Timing Requirements1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19: Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 20: Burst WRITE Cycle Tim ing Requ irem e n ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 21: Initialization Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 22: Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 23: Asynchronous READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 24: Asynchronous READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 25: Asynchronous READ Timing Parameters (Page Mode Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 26: Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 27: Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 28: Burst READ Timing Parameters (with LB#/UB#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 29: Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 30: Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 31: Asynchronous WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 32: Asynchronous WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 33: Asynchronous WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 34: Asynchronous WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 35: Burst WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 36: Burst WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 37: WRITE Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 38: READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 39: WRITE Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 40: READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 41: WRITE Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 42: READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 43: WRITE Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 44: READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 45: WRITE Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 46: READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 47: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

List of Figures

Figure 1 Ball Assignment 54-Ball FBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2 Functional Block Diagram – 4 Meg x 16 and 2 Meg x 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3 Power-Up Initialization Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4 READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5 WRITE Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6 Page Mode READ Operation (ADV = LOW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 7 Burst Mode READ (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 8 Burst Mode WRITE (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 9 Wired or WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 10 Refresh Collision During READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 11 Refresh Collision Duri ng WR ITE Op eration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 12 Configuration Register WRITE in Asynchronous Mode Followed by READ . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 13 Configuration Register WRITE in Synchronous Mode Followed by READ . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 14 WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 15 WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 16 WAIT Configuration During Burst Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 17 Latency Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 18 AC Input/Output Reference Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 19 Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 20 Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 21 Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 22 Asynchronous READ Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 23 Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 24 Single-Access Burst READ Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 25 4-Word Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 26 4-Word Burst READ Operation (with LB#/UB# ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 27 READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 28 Continuous Burst READ with Output Delay, BCR[8] = 0(1) for End-of-Row Condition . . . . . . . . . . . . . 38

Figure 29 CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 30 LB#/UB#-Controlled Asynchronous WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 31 WE#-Controlled Asynchronous WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 32 Asynchronous WRITE Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 33 Burst WRITE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 34 Continuous Burst WRITE with Output Delay, BCR[8] = 0(1) for End-of-Row Condition . . . . . . . . . . . . 44

Figure 35 Burst WRITE Followed by Burst READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 36 Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 37 Asynchronous WRITE Followed By Burst READ—ADV# LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 38 Asynchronous WRITE Followed by Asynchronous READ—ADV# LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 39 Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 40 54-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 41 Extended Timing for tCEM, Page Mode Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 42 Extended Timing for tTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 43 Extended Timing for tCEM, Page Mode Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 44 Extended Asynchronous Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

General Description

Micron CellularRAM™ products are high-speed,

CMOS dynamic random access memories developed

for low-power, portable applications. The

MT45W4MW16BFB is a 64Mb device organized as 4

Meg x 16 bits; the MT45W2MW16BFB is a 32Mb

device organized as 2 Meg x 16 bits. These devices

include an industry-standard burst mode Flash inter-

face that dramatically increases read/write bandwidth

compared with other low-power SRAM or Pseudo

SRAM offerings.

To operate seamlessly on a burst Flas h bus, Ce llular-

RAM products have incorporated a transparent self-

refresh mechanism. The hidden refresh requires no

additional support from the system memory controller

and has no significant impact on device read/write

performance.

Two user-accessible control registers define device

operation. The bus configuration register (BCR)

defines how the CellularRAM device interacts with the

system memor y bus and is nearly identical to its coun-

terpart on burst mode Flash devices.

The refresh configuration register (RCR) is used to

control how refresh is performed on the DRAM array.

These registers are automatically loaded with default

settings during power-up and can be updated anytime

during normal operation.

Special attention has been focused on standby cur-

rent consumption during self refresh. CellularRAM

products include three system-accessible mechanisms

used to minimize stand by current. Partial array refresh

(PAR) limits r efr esh to only that part of the DRAM array

that contains essential data. Temperature compen-

sated refresh (TCR) is used to adjust the refresh rate

according to the case temperature. The refresh rate

can be decreased at lower temperatures to minimize

current consumption during standby. Deep power-

down (DPD) halts the refresh operation altogether and

is used when no vital information is stored in the

device. These three refresh mechanisms are adjusted

through the RCR.

Figure 2: Functional Block Diagram – 4 Meg x 16 and 2 Meg x 16

OTE:

Functional bl ock diagrams illustrate simplified device operation. Se e truth table, ball descriptions, and timing

diagrams for detailed information.

A[20:0]

(for 32Mb)

A[21:0]

(for 64Mb) Input/

Output

MUX

and

Buffers

Control

Logic

2,048K x 16

(4,096K x 16)

DRAM

MEMORY

ARRAY

CE#

WE#

OE#

CLK

DV#

CRE

WAIT

LB#

UB#

DQ[7:0

]

DQ[15:

Address Decode

Logic

Refresh Configuration

Bus Configuration

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

OTE:

The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. The WA IT

signal will be driven to an undefi ned state when ope rating in asynchronous or page mode . Otherwise, during asynchro-

nous operation, WAIT will be in a High-Z condition.

Table 1: FBGA Ball Descriptions

FBGA

ASSIGNMENT SYMBOL TYPE DESCRIPTION

A3, A4, A5, B3,

B4, C3, C4, D4,

H2, H3, H4, H5,

G3, G4, F3, F4,

E4, D3, H1, G2,

H6, E3

A[21:0] Input Address In puts: Inputs for ad dr esses during READ and WRITE operations.

Addresses are internally latched during READ and WRITE cycles. The address lines

are also used to define the value to be loaded into the bus configuration register

or the refresh configuration register. On the 32Mb device, A21 (ball E3) is not

internally connected.

J2 CLK Input Clock: Synchronizes the memory to the system operating frequency during

synchronous o perations. When configured for synchronous operation, the address

is latched on the first rising (or falling, depending upon the bus configuration

whichever occurs first. CLK is static during asynchro nous access READ and WRITE

operations and d uring PAGE READ ACCESS ope rations. CLK must be h eld LOW

during asynchronous or page mo de transactio ns.

J3 ADV# Input Address Valid: Indicates that a valid address is present on the address inputs.

Addresses ca n be latched on the rising edge of ADV# du ring READ and WRITE

operations. ADV# may be driven LOW during asynchronous READ and WRITE

operations.

A6 CRE Input Configuration Register Enable: When CRE is HIGH, WRITE operation s load the

refresh configuration register or bus configura tion register.

B5 CE# Input Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is

disabled and goes into standby or deep power-down mode.

A2 OE# Input Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the

output buffers are disabled.

G5 WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW , the cycle

is a WRITE to either a configuration register or to the memory array.

A1 LB# Input Lower Byte Enable. DQ[7:0]

B2 UB# Input Upper Byte Enable. DQ[15:8]

B6, C5, C6, D5,

E5, F5, F6, G6,

B1, C1, C2, D2,

E2, F2, F1, G1

DQ[15:0] Input/

Output Data Inputs/Outputs.

J1 WAIT Output Wait: Prov ides data-valid feedback during burst READ and WRITE operations. The

signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and

READ/WRITE operations. W AIT is asserted when a burst crosses a row boundary.

WAIT is also used to mask the delay associated with opening a new internal page.

WAIT is asserted and should be ignored during asynchr onous and page mo de

operations.

J4, J5, J6 NC – Not inte rnally connected.

D6 VCC Supply Device Power Supply: (1.70V–1.95V) Power supply for device core operation.

E1 VCCQ Supply I/O Power Supply: (1.70V–1.95V) Power supply for input/output buffers.

E6 VSS Supply VSS must be connected to ground.

D1 VSSQ Supply VSSQ must be connected to ground.

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

OTE:

1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are

affected. When only UB# is in the select mode, DQ[15:8] are affected.

2. The WAIT polarity is configured through the bus configuration register (BCR[10]).

3. The device will consume active power in this mode whenever addresses are changed.

4. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any

external influence.

5. VIN = VCC or 0V; all device balls must be static (unswitched) in order to achieve standby current.

6. DPD is maintained until RCR is reconfigured.

7. Burst mode operation is initialized through the bus co nfiguration register (BCR[15]).

8. The clock polarity is configured through the bus configuration register (BCR[6]).

Table 2: Bus Operations – Asynchronous Mode

MODE POWER CLK ADV# CE# OE# WE# CRE LB#/

UB# WAIT1DQ[15:0]2NOTES

Read Active > Standby L L L L H L L1 L Data-Out 3

Write Active > Standby L L L X L L L1 L Data-In 3

Standby Standby X X H X X L X X High-Z 4

Standby Standby X X L X X L X X X 3, 5

Configuration

DPD Deep

Power-Down LXHXXXXXHigh-Z 6

Table 3: Bus Operations – Burst Mode

MODE POWER CLK ADV# CE# OE# WE# CRE LB#/

UB# WAIT1DQ[15:0]2NOTES

Async Read Active > Standby L L L L HLLLData-Out2, 3

Async Write Active > Standby L L L X L L L L Data-In 2, 3

Standby Standby X X H X X L X X High-Z 4

Standby Standby X X L X X L X X X 3, 5

Initial Burst

Read Active > Standby L L X H L L L Data-Out 2, 3, 7,

Initial Burst

Write Active > Standby L L H LLXLData-In3, 7, 8

Burst

Continue Active > Standby H L X X L X X Data-In or

Data-Out 3, 7, 8

Burst Suspend Active > Standby L X L X X L X X High-Z 3, 7

Configuration

DPD Deep

Power-Down LXHXXXXXHigh-Z6

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

OTE:

1. Contact factory for availability.

Table 4: Abbreviated Component Marks –

CellularRAM FBGA-Packaged Components

PART NUMBER ENGINEERING

SAMPLE QUALIFIED

SAMPLE

MT45W4MW16BFB-701 WT PX344 PW344

MT45W4MW16BFB-706 WT PX340 PW340

MT45W4MW16BFB-856 WT PX345 PW345

MT45W2MW16BFB-701 WT PX244 PW244

MT45W2MW16BFB-706 WT PX240 PW240

MT45W2MW16BFB-856 WT PX245 PW245

MT45W4MW16BFB-706 IT PX3521PW3521

MT45W4MW16BFB-856 IT PX3541PW3541

MT45W4ML16BFB-856 IT PX3551PW3551

MT45W4ML16BFB-706 IT PX3571PW3571

MT45W2MW16BFB-706 IT PX2481PW2481

MT45W2MW16BFB-856 IT PX2501PW2501

MT45W2ML16BFB-856 IT PX2511PW2511

MT45W2ML16BFB-706 IT PX2531PW2531

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Functional Description

In general, the MT45W4MW16BFB device and the

MT45W2MW16BFB device are high-density alterna-

tives to SRAM and Pseudo SRAM products, popular in

lo w-power, portable applications.

The MT45W4MW16BFB device contains 67,108,864

bits organized as 4,194,304 addresses by 16 bits. The

MT45W2MW16BFB contains 33,554,432 bits organized

as 2,097,152 addresses by 16 bits. Both devices imple-

ment the same high-speed bus interface found on

burst mode Flash products.

The CellularRAM bus interface supports both asyn-

chronous and burst mode transfers. Page mode

accesses are also included as a bandwidth-enhancing

extension to the asynchronous read protocol.

Power-Up Initialization

CellularRAM products include an on-chip voltage

sensor used to launch the power-up initialization pro-

cess. Initialization will configure the BCR and the RCR

with their default settings (see Table 5 on page16 and

Table 8 on page 21). VCC and VCCQ must be applied

simultaneously. When they reach a stable level at or

above 1.70V, the device will require 150µs to complete

its self-initialization process. During the initialization

period, CE# should remain HIGH. When initialization

is complete, the device is ready for normal operation.

Figure 3: Power-Up Initialization

Timing

Bus Operating Modes

The MT45W4MW16BFB and MT45W2MW16BFB

CellularRAM products incorporate a burst mode inter-

face found on Flash products targeting low-power,

wireless applications. This bus interface supports

asynchronous, page mode, and burst mode read and

write transfers. The specific interface supported is

defined by the value loaded into the bus configuration

uration register (RCR[7]).

Asynchronous Mode

CellularRAM products power up in the asynchro-

nous operating mode. This mode uses the industry-

standard SRAM control bus (CE#, OE#, WE#, LB#/

UB#). READ operations (Figure4) are initiated by

bringing CE#, OE#, and LB#/UB# LOW while keeping

WE# HIGH. Valid data will be driven out of the I/Os

after the specified access time has elapsed. WRITE

operations (Figure 5) occur when CE#, WE#, and LB#/

UB# are driven LOW. During asynchronous WRITE

operations, the OE# level is a “Don't Care,” and WE#

will override OE#. The data to be written is latched on

the rising edge of CE#, WE#, or LB#/UB# (whichever

occurs first). Asynchronous operations (page mode

disabled) can either use the ADV input to latch the

address, or ADV can be driven LOW during the entire

READ/WRITE operation.

During asynchronous operation, the CLK input

should be held LOW. WAIT will be driven while the

device is enabled and its state should be ignored.

Figur e 4: READ Operation (ADV = LOW)

OTE:

ADV must remain LOW for page mode operation.

Figure 5: WRITE Operation (ADV = LOW)

Vcc

ccQ Device Initialization

Vcc = 1.70V Device ready for

normal operation

tPU > 150µs

ADDRESS VALID

DATA

CE#

DON’T CAR

DATA VALID

OE#

WE#

LB#/UB#

tRC = READ Cycle Time

DDRESS

ADDRESS VALID

DATA

CE#

DON’T CAR

DATA VALID

OE#

WE#

LB#/UB#

tWC = WRITE Cycle Time

DDRESS

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Page Mode READ Operation

Page mode is a performance-enhancing extension

to the legacy asynchronous READ operation. In page-

mode-capable products, an initial asynchronous read

access is performed, then adjacent addresses can be

read quickly by simply changing the low-order

address. Addresses A[3:0] are used to determine the

members of the 16-address CellularRAM page.

Addresses A[4] and higher must remain fixed during

the entire pag e mode access . F igure 6 shows the timing

for a page mode access. Page mode takes advantage of

the fact that adjacent addresses can be read in a

shorter period of time than random addresses. WRITE

operations do not include comparable page mode

functionality.

During asynchronous page mode operation, the

CLK input must be held LOW. CE# must be driven

HIGH upon completion of a page mode access. WAIT

will be driven while the device is enabled and its state

should be ignored. Page mode is enabled by setting

RCR[7] to HIGH. WRITE operations do not include

comparable page mode functionality. ADV must be

driven LOW during all page mode read accesses.

Figure 6: Page Mode READ Operation

(ADV = LOW)

Burst Mode Operation

Burst mode operations enable high-speed synchro-

nous READ and WRITE operations. Burst operations

consist of a multiclock sequence that must be per-

formed in an ordered fashion. After CE# goes LOW, the

address to access is latched on the next rising edge of

CLK or ADV# (whichever occurs first). During this first

clock rising edge , WE# indicates whether the oper ation

is going to be a READ (WE# = HIGH, Figure 7 on

page 11) or WRITE (WE# = LOW, Figure8 on page 11).

The size of a burst can be specified in the BCR as

either a fixed length or continuous. Fixed-length

bursts consist of four, eight, or sixteen words. Continu-

ous bursts have the ability to start at a specified

address and burst through the entire memory. The

latency count stored in the BCR defines the number of

clock cycles that elapse before the initial data value is

transferred between the processor and CellularRAM

device.

The WAIT output will be asserted as soon as a burst

is initiated, and will be de-asserted to indicate when

data is to be transferred into (or out of ) the memory.

WAIT will again be asserted if the burst crosses a row

boundary. Once the CellularRAM device has restored

the previous row's data and accessed the next row,

WAIT will be de-asserted and the burst can continue

(see Figure 28 on page 38).

DATA

CE#

DON’T CAR

OE#

WE#

LB#/UB#

DDRESS Add[0] Add[1] Add[2] Add[3]

D[1] D[2] D[3]

tAA tAPA tAPA tAPA

D[0]

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 7: Burst Mode READ (4-word burst)1

Figure 8: Burst Mode WRITE (4-word burst)1

OTE:

1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; Hold data one clock; WAIT asserted during delay.

A[21:0]

D[0]

ADV#

CE#

OE#

D[1] D[2] D[3]

WE#

WAIT

Q[15:0]

LB#/UB#

Latency Code 2 (3 clocks)

CLK

DON’T CARE

READ Burst Identified

(WE# = HIGH)

ADDRESS

VALID

A[21:0]

D[0]

ADV#

CE#

OE#

D[1] D[2] D[3]

WE#

WAIT

Q[15:0]

LB#/UB#

ADDRESS

VALID

Latency Code 2 (3 clocks)

CLK

DON’T CAR

WRITE Burst Identified

(WE# = LOW)

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Mixed-Mode Operation

The device can support a combination of synchro-

nous READ and asynchronous WRITE operations

when the BCR is configured for synchronous opera-

tion. The asynchronous WRITE operation requires that

the clock (CLK) remain LOW during the entire

sequence. The ADV# signal can be used to latch the

target address, or it can remain LOW during the entire

WRITE operation. CE# must return HIGH when transi-

tioning between mixed-mode operations. Note that

the tCKA period is the same as a READ or WRITE cycle.

This time is required to ensure adequate refresh.

Mixed-mode operation facilitates a seamless interface

to legacy burst mode Flash memory controllers. See

Figure 36 on page46 for the “Asynchronous WRITE

Followed by Burst READ” timing diagram.

Wait Operation

WAIT output on the CellularRAM device is typically

connected to a shared, system-level WAIT signal (see

Figure 9 below). The shared WAIT signal is used by the

processor to coordinate transactions with multiple

memories on the synchronous bus .

Figure 9: Wired or WAIT Configuration

Once a READ or WRITE operation has been initi-

ated, WAIT goes active to indicate that the Cellular-

RAM device requires additional time before data can

be transferred. For READ operations, WAIT will remain

active until valid data is output from the device. For

WRITE operations, WAIT will indicate to the memory

controller when data will be accepted into the Cellu-

larRAM device. When WAIT transitions to an inactive

state, the data burst will progress on successive clock

edges.

CE# must remain asserted at least as long as WAIT is

asserted. Bringing CE# HIGH while WAIT is asserted

may cause data corruption .

WAIT output also performs an arbitration role when

a READ or WRITE operation is launched while an on-

chip refresh is in progress. If a collision occurs, WAIT

pin be asserted for additional clock cycles, until the

refresh has completed (see Figures 10 and 11 on

page 13). When the refresh operation has completed,

the READ or WRITE operation will conti n ue normally.

WAIT is also asserted when a continuous READ or

WRITE burst crosses a row boundary. The WAIT asser-

tion allows time for the new row to be accessed, and

permits any pending refresh operations to be per-

formed.

LB#/UB# Operation

The LB# enable and UB# enable signals support

byte-wide data transfers. During READ operations, the

enabled byte(s) are driven onto the DQs. The DQs

associated with a disabled byte are put into a High-Z

state during a READ operation. During WRITE opera-

tions, any disabled bytes will not be transferred to the

RAM array and the internal value will remain

unchanged. During an asynchronous WRITE cycle, the

data to be written is latched on the rising edge of CE#,

WE#, LB#, or UB#, whichever occurs first.

When both the LB# and UB# are disabled (HIGH)

during an operation, the device will disable the data

bus from receiving or transmitting data. Although the

device will seem to be deselected, it remains in an

active mode as long as CE# remains LOW.

CellularRAM External

Pull-Up/

Pull-Dow

Resistor

Processor

READY

Other

Device

WAIT

Other

Device

WAIT

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

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Figure 10: Refresh Collision During READ Operation1

OTE:

1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; Hold Data one clock; WAIT asserted during delay.

Figure 11: Refresh Collision During WRITE Operation1

OTE:

1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; Hold data one clock; WAIT asserted during delay.

A[21:0]

ADV#

CE#

OE#

WE#

WAIT

Q[15:0]

CLK VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

D[2]D[1] D[3]

VALID

ADDRESS

Additional WAIT states inserted to allow refresh completion.

LB#/UB#

DON’T CARE

D[0]

High-Z

A[21:0]

ADV#

CE#

OE#

WE#

WAIT

Q[15:0]

CLK

D[1]D[0] D[3]D[2]

VALID

ADDRESS

Additional WAIT states inserted to allow refresh completion.

LB#/UB#

DON’T CARE

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL High-Z

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Low-Power Operation

Standby Mode Operation

During standby, the device current consumption is

reduced to the level necessary to perform the DRAM

refresh operation. Standby operation occurs when CE#

is HIGH and there ar e no transactions in progress.

The device will enter standby operation upon com-

pletion of a READ or WRITE operation, or when the

address and control inputs remain static for an

extended period of time. This “active” standby mode

will continue until a change occurs to the address or

control inputs.

Temperature Compensated Refresh

Temperature compensated refresh ( TCR) is used to

adjust the refr esh r ate dependi ng on the de vice oper at-

ing temperature. DRAM technology requires increas-

ingly frequent refresh operations to maintain data

integrity as temperatures increase. More frequent

refresh is required due to increased leakage of the

DRAM capacitive storage elements as temperatures

rise. A decreased refresh rate at lower temperatures

will facilitate a savings in standby curr ent.

TCR allows for adequate refresh at four different

temperature thresholds (+15°C, +45°C, +70°C, and

+85°C). The setting selected must be for a temperature

higher than the case temperature of the CellularRAM

device. If the case temperature is +50°C, the system can

minimize self refr esh current consumption by selecting

the +70°C setting. The +15°C and +45°C settings would

result in inadequate refreshing and cause data corrup-

tion.

Partial Array Refresh

Partial array refresh (PAR) restricts refresh operation

to a portion of the total memory array. This feature

enables the device to reduce standby current by

refreshing only that part of the memory array required

by the host system. The refresh options are full array,

three-quarters array, one-half array, one-quar ter array,

or none of the array. The mapping of these partitions

can start at either the beginning or the end of the

address map (see Tables 9 and 10 on page 21). READ

and WRITE operations to address ranges receiving

refresh will not be affected. Data stored in addresses

not receiving refresh will become corrupted.

Deep Power-Down Operation

Deep power-down (DPD) operation disables all

refresh-related activity. This mode is used if the system

does not require the storage provided by the Cellular-

RAM device. Any stored data will become corrupted

when DPD is enabled. When refresh activity has been

re-enabled, the CellularRAM device will require 150µs

to perform an initialization procedure before normal

operations can resume. During this 150µs period, the

current consumption will be higher than the specified

standby levels, but considerably lower than the active

current specification.

Configuration Registers

Two WRITE-only, user-accessible configuration reg-

isters have been included to define device operation.

The bus configuration register (BCR) defines how the

CellularRAM interacts with the system memory bus and

is nearly identical to its counterpart on burst mode

Flash devices. The refresh configuration register (RCR)

is used to control how refresh is performed on the

DRAM array. These registers are automatically loaded

with default settings during power-up, and can be

updated any time the devices are operating in a

standby state.

Bus Configuration Register

The BCR defines how the CellularRAM device inter-

acts with the system memory bus. Page mode opera-

tion is enabled by a bit contained in the RCR. The BCR

is loaded using either a synchronous or an asynchro-

nous WRITE operation when A[19] is HIGH and the

configuration register enable (CRE) input is also HIGH

(see Figures 12 and 13 on page 15). When CRE is LOW,

a READ or WRITE operation will access the memory

array. The values placed on address pins A[21:0] are

latched into the BCR on the rising edge of ADV#, CE#,

or WE#, whichever occurs first. LB# and UB# ar e “ Don’t

Care.” Table 5 on page 16 describes the control bits in

the BCR. At power-up, the BCR is set to 9F4Fh.

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

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Figure 12: Configuration Register WRITE in Asynchr onous Mode Followed by READ

NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; Hold data one clock; WAIT asserted during delay.

2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR.

Figure 13: Configuration Register WRITE in Synchr onous Mode Followed by READ1

NOTE: 1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; Hold data one clock; WAIT asserted during delay.

2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR.

A[21:0]

(

except A19)

CLK

OPCODE ADDRESS

ADDRESS

DATA VALID

A192

ADV#

CE#

OE#

WE#

LB#/UB#

DQ[15:0]

Initiate Control Register Access

Write Address Bus

Value to Control

CRE

tAVS

tVP

tVPH

tWC

tWP

tCW

DON’T CAR

Select Control Register

CLK

A[21:0]

(

except A19)

A192

CRE

ADV#

CE#

OE#

WE#

LB#/UB#

WAIT

DQ[15:0]

Latch Control Register Address

tSP

tHD

tCSP

tSP tHD

High-Z

DON’T CARE

OPCODE ADDRESS

ADDRESS

High-Z

tCW

tWC

Latch Control Register Value

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

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Table 5: Bus Configuration Register Definition

OTE:

1. All burst WRITEs are continuous.

A13

13 12 11 0

Latency

Counter

321

WAIT

Polarity

WAIT

Configuration (WC)

Clock

Configuration (CC)

Output

Impedance Burst

Wrap (BW)*

A12A11 A10 A9 A8 A7 A6 A5 A4 A3 A2A1A

Operation Mode

Synchronous burst access mode

Asynchronous access mode (default)

BCR[12] BCR[11]

Latency Counter

BCR[13]

Code 0–Reserved

Code 1–Reserved

Code 2

Code 3 (Default)

Code 4–Reserved

Code 5–Reserved

Code 6–Reserved

Code 7–Reserved

WAIT Polarity

Active LOW

Active HIGH (default)

BCR[10]

WAIT Configuration

Asserted during delay

Asserted one data cycle before delay (default)

Clock Configuration

Falling edge

Rising edge (default)

BCR[6]

Output Impedance

Full Drive (default)

1/4 Drive

BCR[5]

Burst Wrap (Note 1)

Burst wraps within the burst length

Burst no wrap (default)

BCR[3]

BCR[1] BCR[0] Burst Length (Note 2)

BCR[2]

Burst

Length (BL)*

Reserved

Operating

Mode

Reserved

21–20

A14A15

A[18:16]

Select RCR

Select BCR

Must be set to "0"

19 18–16

Select

Reserved

A19A[21:20]

Reserved

Must be set to "0"Must be set to "0"Must be set to "0"Must be set to "0"

ll must be set to "0"

BCR[8]

BCR[15]

BCR[19]

4 words

8 words

16 words

Continuous burst (default)

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Burst Length (BCR[2:0])

Default = Continuous Burst

Burst lengths define the number of words the device

outputs during a burst READ operation. The device sup-

ports a burst length of 4, 8, or 16 words. The device can

also be set in continuous burst mode where data is out-

put sequentially without regard to address boundaries.

WRITE bursts are always performed using continuous

burst mode.

Burst Wrap (BCR[3])

Default = Burst Wraps

Within Address Boundaries

The burst wrap option determines if a 4-, 8-, or 16-

word burst READ wraps within the burst length or

steps through sequen tial addresses. If the wrap option

is not enabled, the device outputs data fr om sequenti al

addresses without regard to burst boundaries. When

continuous burst operation is selected, the internal

address wraps to 000000 h if the device is read past the

last address.

Output Impedance (BCR[5])

Default = Outputs Use Full Drive Strength

The output driver strength can be altered to adjust

for different data bus loading scenarios. The reduced-

strength option will be more than adequate in stacked

chip (Flash + CellularRAM) environments when there is

a dedicated memory bus. The reduced-drive-strength

option is included to minimize noise generated on the

data bus during READ operations. Normal output

impedance should be selected when using a discrete

CellularRAM device in a more heavily loaded data bus

environment. Cel lularRAM devices ar e tes ted using the

full drive strength setting. Partial drive is approxi-

mately one-quarter full drive strength. Outputs are

configured at full drive strength during testing.

Table 6: Sequence and Burst Length

STARTING

ADDRESS WRAP NO

WRAP

4-WORD

BURST

LENGTH 8-WORD

BURST LENGTH 16-WORD BURST LENGTH CONTINUOUS BURST

(DEC) BCR[3] BCR3 LINEAR LINEAR LINEAR LINEAR

0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-…

1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-4-5-6-7-…

2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-5-6-7-8-…

3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-6-7-8-9-…

4 0 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-7-8-9-10-…

5 0 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7-8-9-10-11-…

6 0 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-9-10-11-12-

7 0 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-10-11-12-13-…

... ... ... ... ... ... ...

14 0 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-17-18-19-20-..

15 0 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-20-21..

... ... ... ... ... ...

0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-…

1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-4-5-6-7-…

2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 2-3-4-5-6-7-8-…

3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 3-4-5-6-7-8-9-…

4 1 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 4-5-6-7-8-9-10-…

5 1 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20 5-6-7-8-9-10-11…

6 1 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21 6-7-8-9-10-11-12…

7 1 ... 7-8-9-10-11-12-13-

14 7-8-9-10-11-12-13-14-...-17-18-19-20-21-22 7-8-9-10-11-12-13…

... ... ... ... ... ...

14 1 ... 14-15-16-17-18-19-...-23-24-25-26-27-28-29 14-15-16-17-18-19-20-…

15 1 15-16-17-18-19-20-...-24-25-26-27-28-29-30 15-16-17-18-19-20-21-…

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Clock Configuration (BCR[6])

Default = Transactions Processed

on Rising Edge of Clock

The clock configuration bit indicates whether syn-

chronous operations are dependant upon the rising or

falling edge of the clock input. All of the timing dia-

grams in this data sheet show the bus interaction

aligned with the rising edge of the clock.

WAIT Configuration (BCR[8])

Default = WAIT Transitions One Clock

Before Data Valid/Invalid

The WAIT configuration bit is used to determine

when WAIT transitions between the asserted and the

de-asserted state with r espect to valid data pr esented on

the data bus. The memory controller will use the WAIT

signal to coordinate data transfer during synchronous

READ and WRITE operations. When BCR[8] = 0, data

will be valid or invalid on the clock edge immediately

after WAIT transitions to the de-asserted or asserted

state, respectively (Figure 14, below, and Figure 16 on

page 19). When A8 = 1, the WAIT signal transitions one

clock period prior to the data bus going valid or invalid

(Figures 15 below and 16 on pa ge18).

Figure 14: W AIT Configuration (BCR[8] = 0)

OTE:

Data valid/invalid immediat ely after W AIT transitions

(BCR[8] = 0). See Figure 15.

Figure 15: WAIT Configuration (BCR[8] = 1)

OTE:

Valid/invalid data delayed for one clock after WAIT

transitions (BCR[8] = 1). See Figure 16 on page 19.

WAIT Polarity (BCR[10])

Default = WAIT Active HIGH

The WAIT polarity bit indicates whether an asserted

WAIT output should be HIGH or LOW. This bit will

determine whether the WAIT signal requires a pull-up

or pull-down resistor to maintain the de-asserted

state.

Latency Counter (BCR[13:11])

Default = Three-Clock Latency

The latency counter bits determine how many

clocks occur between the beginning of a READ or

WRITE operation and the first data value transferred.

Only latency code two (three clocks) or latency code

three (four clocks) is allowed (see Table 7 on page 20

and Figure 17 on page 20).

WAIT

Q[15:0]

CLK

Data[0] Data[1]

Data immediately valid (or invalid

)

High-Z

WAIT

[15:0]

CLK

Data[0]

Data valid (or invalid) after one clock dela

High-Z

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

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Figure 16: WAIT Configuration During Burst Operation1

OTE:

1. Clocked on r ising edge.

WAIT

Q[15:0]

CLK

D[0] D[1]

BCR[8] = 0

DATA VALID IN CURRENT CYCL

BCR[8] = 1

DATA VALID IN NEXT CYCLE

DON’T CARE

D[2] D[3] D[4]

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

OTE:

1. Clock rates below 50 MHz are allowed as long as tCSP specifications are met.

Figure 17: Latency Counter

Operating Mode (BCR[15])

Default = Asynchronous Operation

The operating mode bit selects either synchronous

burst operation or the default asynchronous mode of

operation.

Refresh Configuration Register

The refresh configuration register (RCR) defines

how the CellularRAM device performs its transparent

self refresh. The RCR is loaded using either a synchro-

nous or an asynchronous WRITE operation when A[19]

is LOW and the configuration register enable (CRE)

input is HIGH (see Figures 12 and 13 on page15).

When CRE is LOW, a READ or WRITE operation will

access the memory array. The values placed on

addresses A[21:0] are latched into the RCR on the ris-

ing edge of ADV#, CE#, or WE#, whichever occurs first.

LB# and UB# are “Don’t Care.” Altering the refresh

parameters can dramatical ly r educe current consump-

tion during standby mode. Page mode control is also

embedded into the RCR. Table 8 on page 21 describes

the control bits used in the RCR. At power-up, the RCR

is set to 0070h.

Partial Array Refresh (RCR[2:0])

Default = Full Array Refresh

The PAR bits restrict refresh operation to a portion

of the total memory array. This feature allows the

device to reduce standby current by refreshing only

that part of the memor y array required by the host sys-

tem. The refresh options are full array, three-quarters

array, one-half array, one -quarter array, or none of th e

array. The mapping of these partitions can start at

either the beginning or the end of the addr es s map (see

Tables 9 and 10 on page 21).

Table 7: Latency Configuration

LATENCY CONFIGURATION CODE MAX INPUT CLK FREQUENCY (MHZ)

-701 -856

2 (3 clocks) 75 (13.3 ns) 441 (22.7 ns)

3 (4 clocks) – default 104 (9.62 ns) 66 (15.2 ns)

A[21:0]

ADV#

Q[15:0]

CLK

Code 2

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

Code 3 (Default)

Q[15:0]

DON’T CARE UNDEFINED

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

VALID

ADDRESS

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

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Table 8: Refresh Configuration Register Mapping

PAR

A4 A3 A2 A1 A0

Read Configuratio

Address Bus

45 1

RESERVED

Deep Power-Down

DPD Enable

DPD Disable (default)

RCR[4]

TCR

RCR[6] RCR[5]

Maximum Case Temp.

+85˚C (default)

+70˚C

+45˚C

+15˚C

All must be set to "0"

A[18:8]

18–8

21–20

Select

RESERVED

A[21:20] A19

Select RCR

Select BCR

RCR[19]

All must be set to "0"

RCR[1]

RCR[0]

Refresh Coverage

Full array (default)

Bottom 3/4 array

Bottom 1/2 array

Bottom 1/4 array

RCR[2]

None of array

Top 3/4 array

Top 1/2 array

Top 1/4 array

DPD

Must be set to "0"

PAGE

Page Mode Enable/Disable

Page Mode Disabled (default)

Page Mode Enable

RCR[7]

Table 9: 64Mb Address Patterns for PAR (A4 = 1)

RCR[2] RCR[1] RCR[0] ACTIVE SECTIO N ADDR ES S SP ACE SIZE DENSITY

0 0 0 Full die 000000h–3FFFFFh 4 Meg x 16 64Mb

0 0 1 Three-quarters of die 000000h–2FFFFFh 3 Meg x 16 48Mb

0 1 0 One-half of die 000000h–1FFFFFh 2 Meg x 16 32Mb

0 1 1 One-quarter of die 000000h–0FFFFFh 1 Meg x 16 16Mb

1 0 0 None of die 0 0 Meg x 16 0Mb

1 0 1 Three-quarters of die 100000h–3FFFFFh 3 Meg x 16 48Mb

1 1 0 One-half of die 200000h–3FFFFFh 2 Meg x 16 32Mb

1 1 1 One-quarter of die 300000h–3FFFFFh 1 Meg x 16 16Mb

Table 10: 32Mb Address Patterns for PAR (A4 = 1)

RCR[2] RCR[1] RCR[0] ACTIVE SECTION ADDRESS SPACE SIZE DENSITY

0 0 0 Full die 000000h–1FFFFFh 2 Meg x 16 32Mb

0 0 1 Three-quarters of die 000000h–17FFFFh 1.5 Meg x 16 24Mb

0 1 0 One-half of die 000000h–0FFFFFh 1 Meg x 16 16Mb

0 1 1 One-quarter of die 00000 0h–07FFFFh 512K x 16 8Mb

1 0 0 None of die 0 0 Meg x 16 0Mb

1 0 1 Three-quarters of die 080000h–1FFFFFh 1.5 Meg x 16 24Mb

1 1 0 One-half of die 100000h–1FFFFFh 1 Meg x 16 16Mb

1 1 1 One-quarter of die 180000h–1FFFFFh 512K x 16 8Mb

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

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Deep Power-Down (RCR[4])

Default = DPD Disabled

The deep power-down bit enables and disables all

refresh-related activity. This mode is used if the system

does not require the storage provided by the Cellular-

RAM device. Any stored data will become corrupted

when DPD is enabled. When refresh activity has been

re-enabled, the CellularRAM device will require 150µs

to perform an initialization procedure before normal

operations can resume.

Deep power-down is enabled when RCR[4] = 0, and

remains enabled until RCR[4] is set to “1.”

Temperature Compensated Refresh (RCR[6:5])

Default = +85°C Operation

The TCR bits allow for adequate refresh at four dif-

ferent temperature thresholds (+15°C, +45°C, +70°C,

and +85°C). The setting selected must be for a tem-

perature higher than the case temperature of the

CellularRAM device. If the case temperature is

+50°C, the system can minimize self refresh current

consumption by selecting the +70°C setting. The

+15°C and +45°C settings would result in inadequate

refreshing and cause data corruption.

Page Mode Operation (RCR[7])

Default = Disabled

The page mode operation bit determines whether

page mode is enabled for asynchronous READ opera-

tions. In the power-up default state, page mode is dis-

abled.

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Absolute Maximum Ratings*

Voltage to Any Ball Except VCC, VCCQ

Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . -0.50V to (4.0V or VccQ + 0.3V, whichever is less)

Voltage on VCC Supply Relative to VSS. . -0.2V to +2.45V

Voltage on VCCQ Supply Relative to VSS . -0.2V to +4.0V

Storage Temperature (plastic). . . . . . . . -55ºC to +150ºC

Operating Temperature (case)

Wire less. . . . . . . . . . . . . . . . . . . . . . . . . . -25ºC to +85ºC

Industrial . . . . . . . . . . . . . . . . . . . . . . . . -40ºC to +85ºC

Soldering Temperature and Time

10s (lead only) . . . . . . . . . . . . . . . . . . . . . . . . . . . +260ºC

*Stresses greater than those listed may cause per-

manent damage to the device. This is a stress rating

only, and functional operation of the device at these or

any other conditions above those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect reliability.

OTE:

1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the cur-

rent required to drive output capacitance expected in the actual system.

2. This device assumes a standby mode if the chip is disabled (CE# HIGH). It will also automatically go into a standby

mode whenever all input signal s are quiesc ent (not togglin g), regardless of the state of CE#. In order to achieve low

standby current, all inputs must be driven to either VCCQ or VSS.

3. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85°C.

Table 11: Electrical Characteristics and Operating Conditions

Wireless Temperature (-25ºC < TC < +85ºC )

Industrial Temperature (-40ºC < TC < +85ºC)

DESCRIPTION CONDITIONS SYMBOL

-70 (104 MHz) -85 (66 MHz)

UNITS NOTESMIN MAX MIN MAX

Supply Voltage VCC 1.70 1.95 1.70 1.95 V

I/O Supply Voltage VCCQ (1.8V) 1.70 2.25 1.70 2.25 V

Input High Voltage VIH 1.40 VCCQ +

0.2 1.40 VCCQ +

0.2 V

Input Low Voltage VIL -0.20 0.4 -0.20 0.4 V

Output High Voltage IOH = -0.2mA VOH 0.80

VCCQ0.80

VCCQV

Output Low Voltage IOL = +0.2mA VOL 0.20

VCCQ0.20

VCCQV

Input Leakage Current VIN = 0 to VCCQILI 11µA

Output Leakage Current OE# = VIH or

Chip Disabled ILO 11µA2

READ Operating Current VIN = VCCQ or 0V

Chip Enab led,

IOUT = 0

ICC1mA1, 2

Asynchronous Random READ 25 25

Asynchronous Page READ 15 15

Initial Access, Burst READ 35 35

Continuous Burst READ 11 11

WRITE Operating Current VIN = VCCQ or 0V

Chip Enabled ICC2 25 25 mA 1, 2

Standby Current (32Mb) VIN = VCCQ or 0V

Chip Disabled ISB 90 90 µA 2, 3

Standby Current (64Mb) VIN = VCCQ or 0V

Chip Disabled ISB 100 100 µA 2, 3

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

OTE:

ITCR (MAX) values measured with PAR set to FULL ARRAY.

OTE:

IPAR (MAX) values measured with TCR set to 85°C.

Table 12: Temperature Compensated Refresh Specifications and Conditions

DESCRIPTION CONDITIONS SYMBOL DENSITY MAX CASE

TEMPERATURES TYP MAX UNITS

Temperature

Compensated

Refresh Standby

Current

VIN = VCC or 0V

Chip Disabled ITCR 64Mb +85°C 100 µA

+70°C TBD µA

+45°C TBD µA

+15°C 50 µA

32Mb +85°C 90 µA

+70°C TBD µA

+45°C TBD µA

+15°C 50 µA

Table 13: Partial Array Refresh Specifications and Conditions

DESCRIPTION CONDITIONS SYMBOL DENSITY ARRAY

PARTITION TYP MAX UNITS

Partial Array

Refresh Standby

Current

VIN = VCC or 0V,

Chip Disabled IPAR 64Mb Full 100 µA

3/4 TBD µA

1/2 TBD µA

1/4 TBD µA

050µA

32Mb Full 90 µA

3/4 TBD µA

1/2 TBD µA

1/4 TBD µA

050µA

Table 14: Deep Power-Down Specifications

DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS

Deep Power-Down VIN = VCC or 0V; +25°C IZZ 10 µA

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

OTE:

1. These parameters are verified in device characterization and are not 100% tested.

Figure 18: AC Input/Output Reference Waveform

OTE:

AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input timing begins at VCCQ/2, and ou tput timing

ends at VCCQ/2. Input rise and fall times (10% to 90%) < 1.6ns.

Figure 19: Output Load Circuit

OTE:

All tests are performed with the outputs configured for

full drive strength (BCR[5] = 0).

Table 15: Capacitance

DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES

Input Capacitance TC = +25ºC; f = 1 MHz;

VIN = 0V CIN –6pF1

Input/Outp ut Capacitance (DQ ) CI/O–6pF1

Outpu

Test Points

nput

VCCQ

VSS

VCCQ/2VCCQ/2

DUT

VccQ

R230pF Test Poin

Table 16: Output Load Circuit

VCCQR1/R2

1.8V 2.7Ω

2.5V 3.7Ω

3.0V 4.5Ω

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

OTE:

1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).

2. See the Appendix at the end of this data sheet.

3. High-Z to Low-Z timings are tested with the circuit shown in Fig ure 19 on page 25. The Low-Z timings measure a

100mV transition away from the High-Z (VCCQ/2) leve l toward either VOH or VOL.

4. Low-Z to High-Z timings are tested with the circuit shown in Figure 19 on page 25. The High-Z timings measure a

100mV transition from either VOH or VOL toward VCCQ/2.

Table 17: Asynchronous READ Cycle Timing Requirements1

PARAMETER SYMBOL

-701, -706 -856

UNITS NOTESMIN MAX MIN MAX

Address Access Time tAA 70 85 ns

ADV# Access Time tAADV 70 85 ns

Page Access Time tAPA 20 25 ns

Address Hold from ADV# HIGH tAVH 55ns

Address Setup to ADV# HIGH tAVS 10 10 ns

LB#/UB# Access Time tBA 70 85 ns

LB#/UB# Disable to High-Z Output tBHZ 0808ns4

LB#/UB# Enable to Low-Z Output tBLZ 10 10 ns 3

CE# HIGH between Subsequent Mixed-Mode Operati ons tCBPH 55ns

Maximum CE# Pulse Width tCEM 10 10 µs 2

CE# LOW to WAIT Valid tCEW 17.517.5ns

Chip Select Access Time tCO 70 85 ns

CE# LOW to ADV# HIGH tCVS 10 10 ns

Chip Disable to High-Z Output tHZ 0808ns4

Chip Enable to Low-Z Output tLZ 10 10 ns 3

Output Enable to Valid Output tOE 20 20 ns

Output Hold from Output Disable tOH 55ns

Output Hold from Address Change tOHA 55ns

Output Disable to High-Z Output tOHZ 0808ns4

Output Enable to Low-Z Output tOLZ 55ns3

Page Cycle Time tPC 20 25 ns

READ Cycle Time tRC 70 85 ns

Address Setting Time tS10 10 µs 2

ADV# Pulse Width LOW tVP 10 10 ns

ADV# Pulse Width HIGH tVPH 10 10 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

OTE:

1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).

2. Low-Z to High-Z timings are tested with the circuit shown in Figure 19 on page 25. The High-Z timings measure a

100mV transition from either VOH or VOL toward VCCQ/2.

3. High-Z to Low-Z timings are tested with the circuit shown in Fig ure 19 on page 25. The Low-Z timings measure a

100mV transition away from the High-Z (VCCQ/2) leve l toward either VOH or VOL.

4. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifcations are met.

Table 18: Burst READ Cycle Timing Requirements1

PARAMETER SYMBOL

-701 -706, -856

UNITS NOTESMIN MAX MIN MAX

Burst to READ Access Time tABA 33 55 ns

CLK to Output Delay tACLK 6.5 10 ns

Address Setup to ADV# HIGH tAVS 10 10 ns

Burst OE# LOW to Output Delay tBOE 20 20 ns

CE# HIGH between Subsequen t Mixed-Mode Operations tCBPH 5 5 ns

CE# LOW to WAIT Valid tCEW 17.517.5ns

CLK Period tCLK 9.62 20 15 20 ns 4

CE# Setup Time to Active CLK Edge tCSP 4 20 4 20 ns

Hold Time from Active CLK Edge tHD 1 1 ns

Chip Disable to High-Z Output tHZ 0 8 0 8 ns 2

CLK Rise or Fall Time tKHKL 1.6 1.6 ns

CLK to WAIT Valid tKHTL 6.5 10 ns

CLK to High-Z Output tKHZ 3838ns

CLK to Low-Z Output tKLZ 2525ns

Output HOLD from CLK tKOH 2 2 ns

CLK HIGH or LOW Time tKP 3 3 ns

Output Disable to High-Z Output tOHZ 0 8 0 8 ns 2

Output Enable to Low-Z Output tOLZ 5 5 ns 3

Setup Time to Active CLK Edge tSP 3 3 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

OTE:

1. See the Appendix at the end of this data sheet.

2. Low-Z to High-Z timings are tested with the circuit shown in Figure 19 on page 25. The High-Z timings measure a

100mV transition from either VOH or VOL toward VCCQ/2.

3. High-Z to Low-Z timings are tested with the circuit shown in Fig ure 19 on page 25. The Low-Z timings measure a

100mV transition away from the High-Z (VCCQ/2) leve l toward either VOH or VOL.

Table 19: Asynchronous WRITE Cycle Timing Requirements

PARAMETER SYMBOL

-701, -706 -856

UNITS NOTESMIN MAX MIN MAX

Address Hold from ADV# Going HIGH tAVH 55ns

Address Setup to ADV# Going HIGH tAVS 10 10 ns

Address Valid to End of Write tAW 70 85 ns

LB#/UB# Select to End of Write tBW 70 85 ns

Maximum CE# Pulse Width tCEM 10 10 µs 1

CE# LOW to WAIT Valid tCEW 1 7.5 1 7.5 ns

Async Address-to-Burst Tr ansition Time tCKA 70 85 ns

CE# Low to ADV# HIGH tCVS 10 10 ns

Chip Enable to End of Write tCW 70 85 ns

Data Hold from Write Time tDH 00ns

Data to WRITE Time Overlap tDW 23 23 ns 1

Chip Enable to Low-Z Output tLZ 10 10 ns 3

End WRITE to Low-Z Output tOW 55ns 3

Address Setup Time tAS 00ns1

ADV# Pulse Widt h tVP 10 10 ns

ADV# Pulse Width HIGH tVPH 10 10 ns

ADV# Setup to End of WRITE tVS 70 85 ns

WRITE Cycle T i me tWC 70 85 ns

WRITE to High-Z Outp ut tWHZ 0808ns 2

WRITE Pulse Width tWP 46 55 ns 1

WRITE Pulse Widt h HI G H tWPH 10 10 ns

WRITE Recovery Time tWR 00ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

OTE:

1. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

Table 20: Burst WRITE Cycle Timing Requirements

PARAMETER SYMBOL

-701 -706, -856

UNITS NOTESMIN MAX MIN MAX

CE# HIGH between Subsequent Mixed-Mode Operations tCBPH 5 5 ns

CE# LOW to WAIT Valid tCEW 17.517.5ns

Clock Period tCLK 9.62 20 15 20 ns 1

CE# Setup to CLK Active Edge tCSP 4 20 4 20 ns

Hold Time from Active CLK Edge tHD 1 1 ns

CLK Rise or Fall Time tKHKL 1.6 1.6 ns

Clock to WAIT Valid tKHTL 6.5 10 ns

CLK HIGH or LOW Time tKP 33ns

Setup T ime to Activate CLK Edge tSP 3 3 ns

Table 21: Initialization Timing Requirements

PARAMETER SYMBOL

-701, -706 -856

UNITS NOTEMIN MAX MIN MAX

Initialization Period (required before normal operations) tPU 150 150 µs

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Burst CellularRAM

Timing Diagrams

Figure 20: Initialization Period

tPU

cc, VccQ = 1.70V Vcc (MIN)

Device ready fo

normal operatio

Table 22: Initialization Timing Parameters

PARAMETER SYMBOL

-701, -706 -856

UNITS NOTEMIN MAX MIN MAX

Initialization Period tPU 150 150 µs

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 21: Asynchronous READ

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

A[21:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

Q[15:0]

VALID ADDRESS

tCBPH

tAA

tHZ

tBA

High-Z High-Z

tRC

tCO

tOH

tBHZ

tOHZ

tOE

tCEW

VALID OUTPUT

High-Z

UNDEFINE

DON’T CARE

tBLZ

tLZ

tOLZ

Table 23: Asynchronous READ Timing Parameters

SYMBOL

-701, -706 -856

UNITS SYMBOL

-701, -706 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 85 ns

tHZ 0808ns

tBA 70 85 ns

tLZ 10 10 ns

tBHZ 0 8 0 8 ns tOE 20 20 ns

tBLZ 10 10 ns

tOH 5 5 ns

tCBPH 5 5 ns

tOHZ 0 8 0 8 ns

tCEW 1 7.5 1 7.5 ns tOLZ 5 5 ns

tCO 70 85 ns

tRC 70 85 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 22: Asynchronous READ Using ADV#

A[21:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

Q[15:0]

VALID ADDRESS

tVPH

tCBPH

tAADV

tAA

tVP

tHZ

tBA

High-Z High-Z

tCVS

tCO

tBLZ

tOH

tBHZ

tOHZ

tLZ

tOE

tOLZ

VALID OUTPUT

tAVH

tAVS

High-Z

UNDEFINED

DON’T CARE

tCEW

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

Table 24: Asynchronous READ Timing Parameters

SYMBOL

-701, -706 -856

UNITS SYMBOL

-701, -706 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 85 ns tCVS 10 10 ns

tAADV 70 85 ns

tHZ 0808ns

tAVH 5 5 ns

tLZ 10 10 ns

tAVS 10 10 ns

tOE 20 20 ns

tBA 70 85 ns

tOH 5 5 ns

tBHZ 0 8 0 8 ns tOHZ 0 8 0 8 ns

tBLZ 10 10 ns

tOLZ 5 5 ns

tCBPH 5 5 ns

tVP 10 10 ns

tCEW 1 7.5 1 7.5 ns tVPH 10 10 ns

tCO 70 85 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 23: Page Mode READ

A[3:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

Q[15:0]

VALID ADDRESS

tCBPH

tAA

tHZ

tBA

High-Z High-Z

tCO

tBLZ

tOH

tBHZ

tOHZ

tLZ

tOE

tOLZ

tCEW

High-Z

UNDEFINE

DON’T CARE

A[21:4] VALID ADDRESS

VALID

ADDRESS VALID

ADDRESS

tRC

Valid

Output Valid

Output

tAPA

tCBPH

tPC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

tOHA

Table 25: Asynchronous READ Timing Parameters (Page Mode Operation)

SYMBOL

-701, -706 -856

UNITS SYMBOL

-701, -706 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 85 ns

tLZ 10 10 ns

tAPA 20 25 ns tOE 20 20 ns

tBA 70 85 ns

tOH 5 5 ns

tBHZ 0 8 0 8 ns tOHA 5 5 ns

tBLZ 10 10 ns

tOHZ 0 8 0 8 ns

tCBPH 5 5 ns

tOLZ 5 5 ns

tCEW 1 7.5 1 7.5 ns tPC 20 25 ns

tCO 70 85 ns

tRC 70 85 ns

tHZ 0 8 0 8 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 24: Single-Access Burst READ Operation1

OTE:

1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

A[21:0]

VIH

VIL

ADV#

VIH

VIL

CE#

VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

Q[15:0]

VOH

VOL

CLK

VIH

VIL

VOH

VOL

CLK

ACLK

CEW

ABA

AVS

VALID

OUTPUT

VALID

ADDRESS

High-Z

KOH

OHZ

LB#/UB#

VIH

VIL

CSP

High-Z

OLZ

High-Z

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

KHTL

BOE

Table 26: Burst READ Timing Parameters

SYMBOL

-701 -706, -856

UNITS SYMBOL

-701 -706, -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tABA 33 55 ns tHZ 0 8 0 8 ns

tACLK 6.5 10 ns tKHTL 6.5 10 ns

tAVS 10 10 ns

tKOH 2 2 ns

tBOE 20 20 ns tKP 33ns

tCEW 17.517.5ns tOHZ 0 8 0 8 ns

tCLK 9.62 20 15 20 ns tOLZ 5 5 ns

tCSP 4 20 4 20 ns tSP 3 3 ns

tHD 1 1 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 25: 4-Word Burst READ Operation1

OTE:

1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

A[21:0]

ADV#

CE#

OE#

WE#

WAIT

Q[15:0]

CLK

tSP

tCLK

tHD

tABA

VALID

ADDRESS

High-Z

tKOH

tHZ

tHD

tSP

LB#/UB#

High-Z

tOLZ

High-Z

tCBPH

tCSP

tSP tHD

tOHZ

tAVS

tKP

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

tCEW

tACLK

tKHTL

VALID

OUTPUT

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

tBOE

Table 27: Burst READ Timing Parameters

SYMBOL

-701 -706, -856

UNITS SYMBOL

-701 -706, -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tABA 33 55 ns

tHD 1 1 ns

tACLK 6.5 10 ns tHZ 0 8 0 8 ns

tAVS 10 10 ns

tKHTL 6.5 10 ns

tBOE 20 20 ns tKOH 2 2 ns

tCBPH 5 5 ns

tKP 33ns

tCEW 1 7.5 1 7.5 ns tOHZ 0 8 0 8 ns

tCLK 9.62 20 15 20 ns tOLZ 5 5 ns

tCSP 4 20 4 20 ns tSP 3 3 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 26: 4-Word Burst READ Operation (with LB#/UB#)1

OTE:

1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as lo ng as tCSP specifications are met. BCR configured with a burst

length of four.

A[21:0]

ADV#

CE#

OE#

WE#

WAIT

Q[15:0]

CLK

tSP

tCLK

tHD

tABA

VALID

ADDRESS

High-Z

tKOH tKHZ tKHZ

tKLZ

tHZ

tHD

tSP

LB#/UB#

High-Z

tOLZ

High-Z

tCBPH

tCSP

tSP tHD

tOHZ

tAVS

tKP

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

tCEW

High-Z

tACLK

tKHTL

VALID

OUTPUT

VALID

OUTPUT VALID

OUTPUT

tBOE

Table 28: Burst READ Timing Parameters (with LB#/UB#)

SYMBOL

-701 -706, -856

UNITS SYMBOL

-701 -706, -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tABA 33 55 ns

tHZ 0 8 0 8 ns

tACLK 6.5 10 ns tKHTL 6.5 10 ns

tAVS 10 10 ns

tKHZ 3838ns

tBOE 20 20 ns tKLZ 2525ns

tCBPH 5 5 ns

tKOH 2 2 ns

tCEW 17.517.5ns tKP 33ns

tCLK 9.62 20 15 20 ns tOHZ 0 8 0 8 ns

tCSP 4 20 4 20 ns tOLZ 5 5 ns

tHD 11ns

tSP 3 3 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 27: READ Burst Suspend1

OTE:

1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

A[21:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

Q[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tSP tHD

High-Z

tOLZ

tACLK

LB#/UB# VIH

VIL

tCLK

tSP

tCSP

tSP tHD

tAVS

tKP

tSP tHD

tKOH

VALID

OUTPUT VALID

OUTPUT

UNDEFINED

DON’T CARE

VALID

ADDRESS

High-Z

tCBPH

tOHZ

VALID

OUTPUT VALID

OUTPUT

tBOE

OHZ

High-Z

VALID

ADDRESS

Table 29: Burst READ Timing Parameters

SYMBOL

-701 -706, -856

UNITS SYMBOL

-701 -706, -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tACLK 6.5 10 ns tHZ 0 8 0 8 ns

tAVS 10 10 ns

tKOH 22ns

tBOE 20 20 ns tKP 33ns

tCBPH 5 5 ns

tOHZ 0 8 0 8 ns

tCLK 9.62 20 15 20 ns tOLZ 5 5 ns

tCSP 4 20 4 20 ns tSP 3 3 ns

tHD 1 1 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 28: Continuous Burst READ Showing an Output Delay

with BCR[8] = 0(1) for End-of-Row Condition1

OTE:

1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

tACLK tKOH

A[21:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

Q[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tKHTL tKHTL

tCLK

tKP

tKHKL

LB#/UB# VIH

VIL

WAIT CONFIG (BCR8) = 1

WAIT CONFIG (BCR8) = 0

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

DON’T CARE

VALID

OUTPUT

Table 30: Burst READ Timing Parameters

SYMBOL

-701 -706, -856

UNITS SYMBOL

-701 -706, -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tACLK 6.5 10 ns tKHTL 6.5 10 ns

tCLK 9.62 20 15 20 ns tKOH 2 2 ns

tKHKL 1.6 1.6 ns tKP 3 3 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 29: CE#-Controlled Asynchronous WRITE

A[21:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

Q[15:0]

VALID ADDRESS

High-Z High-Z

tWC

tCEW

VALID INPUT

tAW

DON’T CARE

tWR

tCW

tDW

Q[15:0]

OUT

tWHZ

tBW

High-Z

tLZ

tDH

tAS

tCEM

tWP

tWPH

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

Table 31: Asynchronous WRITE Timing Parameters

SYMBOL

-701, -706 -856

UNITS SYMBOL

-701, -706 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tDW 23 23 ns

tAW 70 85 ns tLZ 10 10 ns

tBW 70 85 ns tWC 70 85 ns

tCEM 10 10 µs tWHZ 0808ns

tCEW 1 7.5 1 7.5 ns tWP 46 55 ns

tCW 70 85 ns tWPH 10 10 ns

tDH 00ns

tWR 00ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 30: LB#/UB#-Controlled Asynchronous WRITE

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

A[21:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

Q[15:0]

IN VIH

VIL

VALID ADDRESS

High-Z

tWC

tCEW

VALID INPUT

tAW

DON’T CAR

tWR

tCW

tDW

Q[15:0]

OUT VOH

VOL

tWHZ

tBW

tLZ

tDH

tAS

tCEM

tWP

tWPH

High-Z

Table 32: Asynchronous WRITE Timing Parameters

SYMBOL

-701, -706 -856

UNITS SYMBOL

-701, -706 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tDW 23 23 ns

tAW 70 85 ns

tLZ 10 10 ns

tBW 70 85 ns

tWC 70 85 ns

tCEM 10 10 µs tWHZ 08 08 ns

tCEW 1 7.5 1 7.5 ns tWP 46 55 ns

tCW 70 85 ns

tWPH 10 10 ns

tDH 0 0 ns

tWR 0 0 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figur e 31: WE#-Controlled Asynchronous WRITE

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

A[21:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

Q[15:0]

VIH

VIL

VALID ADDRESS

tWC

tCEW

VALID INPUT

tAW

DON’T CAR

tWR

tDW

Q[15:0]

OUT

VOH

VOL

tWHZ

tBW

tCW

tCEM

tLZ

tWP

tDH

tOW

tAS

tWPH

High-Z

Table 33: Asynchronous WRITE Timing Parameters

SYMBOL

-701, -706 -856

UNITS SYMBOL

-701, -706 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tLZ 10 10 ns

tAW 70 85 ns

tOW 55ns

tBW 70 85 ns

tWC 70 85 ns

tCEM 10 10 µs tWHZ 08 08 ns

tCEW 1 7.5 1 7.5 ns tWP 46 55 ns

tCW 70 85 ns

tWPH 10 10 ns

tDH 0 0 ns

tWR 0 0 ns

tDW 23 23 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 32: Asynchronous WRITE Using ADV#

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

A[21:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

Q[15:0]

IN VIH

VIL

VALID ADDRESS

High-Z High-Z

tCEW

VALID INPUT

tVS

DON’T CAR

tCW

tDW

Q[15:0]

OUT VOH

VOL

tWHZ

tBW

tLZ

tWP

tDH

tOW

tAS

tCEM

tWPH

tVPH

tAVH

tAVS

tVP

tAW

High-Z

Table 34: Asynchronous WRITE Timing Parameters

SYMBOL

-701, -706 -856

UNITS SYMBOL

-701, -706 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tDW 23 23 ns

tAVH 5 5 ns

tLZ 10 10 ns

tAVS 10 10 ns

tOW 55ns

tAW 70 85 ns

tVP 10 10 ns

tBW 70 85 ns

tVPH 10 10 ns

tCEM 10 10 µs tVS 70 85 ns

tCEW 1 7.5 1 7.5 ns tWHZ 08 08 ns

tCW 70 85 ns

tWP 46 55 ns

tDH 0 0 ns

tWPH 10 10 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 33: Burst WRITE Operation1

OTE:

1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

A[21:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

Q[15:0]

VOH

VOL

CLK VIH

VIL

VIH

VIL

tCLK

tSP

tCSP

D[3]D[2]D[1]D[0]

VALID

ADDRESS

tHD

tSP

tHD

tSP

High-Z High-Z

LB#/UB# VIH

VIL

tSP tHD

tHD

DON’T CAR

WRITE Burst Identified

(WE# = LOW)

tCBPH

tKHTL

tCEW

Table 35: Burst WRITE Timing Parameters

SYMBOL

-701 -706, -856

UNITS SYMBOL

-701 -706, -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tCBPH 5 5 ns

tHD 1 1 ns

tCEW 17.517.5ns tKHTL 6.5 10 ns

tCLK 9.62 20 15 20 ns tSP 3 3 ns

tCSP 4 20 4 20 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 34: Continuous Burst WRITE Showing an Output Delay

with BCR[8] = 0(1) for End-of-Row Condition1

OTE:

1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

A[21:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

Q[15:0]

VOH

VOL

CLK VIH

VIL

VIH

VIL

tKHTL tKHTL

tCLK tKP

tKHKL

tSP tHD

VALID

INPUT D[n] VALID

INPUT D[n+2]

END OF ROW

VALID

INPUT D[n+1] VALID

INPUT D[n+3]

DON’T CARE

VIH

VIL

LB#/UB#

Table 36: Burst WRITE Timing Parameters

SYMBOL

-701 -706, -856

UNITS SYMBOL

-701 -706, -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tCLK 9.62 20 15 20 ns tKHTL 6.5 10 ns

tHD 1 1 ns

tKP 3 3 ns

tKHKL 1.6 1.6 ns tSP 3 3 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 35: Burst WRITE Followed by Burst READ1

OTE:

1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. To allow self-refresh operations to occur between transactions, CE# must remain HIGH for at least 5ns (tCBPH) to

schedule the appropriate internal refresh operation.

3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

A[21:0]

VIH

VIL

ADV#

VIH

VIL

CE#

VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

Q[15:0]

IN/OUT

VOH

VOL

CLK

VIH

VIL

VIH

VIL

tCLK

tSP

tCSP

D[3]D[2]D[1]

D[0]

VALID

ADDRESS

tHD

tSP

tHD

tSP

tSP tHD

VALID

ADDRESS

tABA

tCSP tOHZ

tKOH

tACLK

VALID

OUTPUT

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

High-Z

VOH

VOL

LB#/UB#

VIH

VIL

tHD

tSP tHD

tHD

High-Z

UNDEFINE

DON’T CARE

tBOE

tCBPH1

High-Z

Table 37: WRITE Timing Parameters

SYMBOL

-701 -706, -856

UNITS SYMBOL

-701 -706, -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tCBPH 5 5 ns

tHD 1 1 ns

tCLK 9.62 20 15 20 ns tSP 3 3 ns

tCSP 4 20 4 20 ns

Table 38: READ Timing Parameters

SYMBOL

-701 -706, -856

UNITS SYMBOL

-701 -706, -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tABA 33 55 ns

tHD 11ns

tACLK 6.5 10 ns tKOH 2 2 ns

tBOE 20 20 ns tOHZ 0808ns

tCLK 9.62 20 15 20 ns tOHZ 0 8 0 8 ns

tCSP 420420ns tSP 33ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 36: Asynchronous WRITE Followed by Burst READ1

OTE:

1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. When transiti oning between asynchronous a nd burst operations , CE# must go HIGH. CE# must remain HIGH for at least 5ns

(tCBPH) to schedule the appropriate internal refresh operation.

3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

tCLK

tCBPH1

tSP tHD

VALID

ADDRESS

tOHZ

tKOH

tACLK

High-Z

VALID ADDRESS VALID ADDRESS

tAVS tAVH tAW tWR

tVPH

tVP tVS

tCKA

A[21:0] VIH

VIL

ADV# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

Q[15:0]

IN/OUT

VOH

VOL

CLK VIH

VIL

VIH

VIL

VOH

VOL

CE# VIH

VIL

LB#/UB# VIH

VIL

tCW

tWPH

tWP

tWC

tDH tDW

DATA DATA

High-Z

tCVS tHD

tSP

tCEW

tSP tHD

tCSP

tWC

tBW

tWHZ

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

DON’T CARE UNDEFINED

tABA

tBOE

Table 39: WRITE Timing Parameters

SYMBOL

-701, -706 -856

UNITS SYMBOL

-701, -706 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAVH 55ns

tVP 10 10 ns

tAVS 10 10 ns tVPH 10 10 ns

tAW 70 85 ns tVS 70 85 ns

tBW 70 85 ns tWC 70 85 ns

tCKA 70 85 ns tWHZ 08 08 ns

tCVS 10 10 ns

tWP 46 55 ns

tCW 70 85 ns tWPH 10 10 ns

tDH 0 0 ns

tWR 0 0 ns

tDW 20 23 ns

Table 40: READ Timing Parameters

SYMBOL

-701 -706, -856

UNITS SYMBOL

-701 -706, -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tABA 33 55 ns

tCSP 4 20 4 20 ns

tACLK 6.5 10 ns tHD 1 1 ns

tBOE 20 20 ns tKOH 2 2 ns

tCBPH 5 5 ns

tOHZ 0 8 0 8 ns

tCEW 17.517.5ns tSP 3 3 ns

tCLK 9.62 20 15 20 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 37: Asynchronous WRITE Followed By Burst READ—ADV# LOW1

OTE:

1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. When transiti oning between asynchronous a nd burst operations , CE# must go HIGH. CE# must remain HIGH for at least 5ns

(tCBPH) to schedule the appropriate internal refresh operation.

3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

tCLK

tSP tHD

VALID

ADDRESS

tABA

tCSP

tKOH

tACLK VALID

OUTPUT

High-Z

VALID ADDRESS VALID ADDRESS

tCKA

A[21:0] VIH

VIL

ADV# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

Q[15:0]

IN/OUT

VOH

VOL

CLK VIH

VIL

VIH

VIL VOH

VOL

CE# VIH

VIL

LB#/UB# VIH

VIL tCW

tWPH

tWP

tWC

tDH tDW

DATA DATA

High-Z

tHD

tSP

tSP tHD

tWC tWC

tBW

tWHZ

tAW tWR tSP

tKP

VALID

OUTPUT VALID

OUTPUT

UNDEFINE

DON’T CARE

tBOE

tOHZ

tCEW HIGH-Z

tCBPH1

Table 41: WRITE Timing Parameters

SYMBOL

-701, -706 -856

UNITS SYMBOL

-701, -706 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAW 70 85 ns tWC 70 85 ns

tBW 70 85 ns tWHZ 08 08 ns

tCKA 70 85 ns tWP 46 55 ns

tCW 70 85 ns tWPH 10 10 ns

tDH 00ns

tWR 0 0 ns

tDW 23 23 ns

Table 42: READ Timing Parameters

SYMBOL

-701 -706, -856

UNITS SYMBOL

-701 -706, -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tABA 33 55 ns tCSP 420420ns

tACLK 6.5 10 ns tHD 11ns

tBOE 20 20 ns tKOH 2 2 ns

tCBPH 5 5 ns

tKP 33ns

tCEW 17.517.5ns tOHZ 0 8 0 8 ns

tCLK 9.62 20 15 20 ns tSP 33ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 38: Asynchronous WRITE Followed by Asynchronous READ—ADV# LOW

OTE:

CE# must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation.

VALID ADDRESS VALID ADDRESS

A[21:0] VIH

VIL

ADV# VIH

VIL

OE#

WE#

WAIT

Q[15:0]

IN/OUT

VOH

VOL

VIH

VIL

VOH

VOL

CE#

LB#/UB# VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tCW

tWPH

tWP

tWC

tDH tDW

DATA

High-Z

VALID ADDRESS

tAA tHZ

tCBPH1

tCEM

VALID

OUTPUT

High-Z

tOE

tOLZ

tLZ

tBLZ

tOHZ

tBHZ

tAW tWR

tBW

tWHZ

DON’T CARE UNDEFINED

DATA

Table 43: WRITE Timing Parameters

SYMBOL

-701, -706 -856

UNITS SYMBOL

-701, -706 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAW 70 85 ns

tWC 70 85 ns

tBW 70 85 ns tWHZ 08 08 ns

tCW 70 85 ns

tWP 46 55 ns

tDH 0 0 ns

tWPH 10 10 ns

tDW 23 23 ns

tWR 0 0 ns

Table 44: READ Timing Parameters

SYMBOL

-701, -706 -856

UNITS SYMBOL

-701, -706 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 85 ns

tLZ 10 10 ns

tBHZ 0 8 0 8 ns tOE 20 20 ns

tBLZ 10 10 ns

tOHZ 0 8 0 8 ns

tCBPH 5 5 ns

tOLZ 5 5 ns

tCEM 10 10

µs tS 10 10

µs

tHZ 0 8 0 8 ns

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 39: Asynchronous WRITE Followed by Asynchronous READ

OTE:

CE# must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation.

VALID ADDRESS VALID ADDRESS

tAVS tAVH

tVPH tVP tVS

A[21:0] VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

ADV#

OE#

WE#

WAIT

Q[15:0]

IN/OUT

VOH

VOL

VIH

VIL

VOH

VOL

CE#

LB#/UB#

tCW

tWPH

tWP

tWC

tDH tDW

DATA DATA

High-Z

VALID ADDRESS

tAA tHZ

tCBPH1

tCEM

VALID

OUTPUT

High-Z

tOE

tCVS

tOLZ

tLZ

tBLZ

tOHZ

tBHZ

tAW tWR

tBW

tWHZ

UNDEFINED

DON’T CARE

Table 45: WRITE Timing Parameters

SYMBOL

-701, -706 -856

UNITS SYMBOL

-701, -706 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAVH 55ns

tVP 10 10 ns

tAVS 10 10 ns tVPH 10 10 ns

tAW 70 85 ns

tVS 70 85 ns

tBW 70 85 ns tWC 70 85 ns

tCVS 10 10 ns tWHZ 0808ns

tCW 70 85 ns

tWP 46 55 ns

tDH 00ns

tWPH 10 10 ns

tDW 23 23 ns

tWR 00ns

Table 46: READ Timing Parameters

SYMBOL

-701, -706 -856

UNITS SYMBOL

-701, -706 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 85 ns

tLZ 10 10 ns

tBHZ 0 8 0 8 ns tOE 20 20 ns

tBLZ 10 10 ns

tOHZ 0 8 0 8 ns

tCBPH 5 5 ns

tOLZ 5 5 ns

tCEM 10 10

µs tS 10 10

µs

tHZ 0 8 0 8 ns

8000 S. Federal Way, P.O. Box 6, Boise , ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, and the Micron and M Logos are trademarks and/or service marks of Micron Technology, Inc.

CellularRAM is a trademark of Micron Technology, Inc., inside the U.S. and a trademark of Infineon Technologies outside the U.S.

All other trademarks are the property of their respective owners.

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 40: 54-Ball FBGA

OTE:

1. All dimensions in millimeters; MAX/MIN, or typical, as noted.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

Data Sheet Designation: ADVANCE

This data sheet contains in itial des criptions of prod-

ucts still in development.

0.700 ±0.075

0.10 CCSOLDER BALL MATERIAL:

EUTECTIC 63% Sn, 37% Pb or

62% Sn, 36% Pb, 2% Ag

SOLDER BALL PAD: Ø 0.27mm

BALL A1 ID

ENCAPSULATION MATERIAL: EPOXY NOVOLA

SUBSTRATE: PLASTIC LAMINATE

0.75

TYP

8.00 ±0.10

BALL A1 ID

0.75

TYP

0.35 TYP54X Ø

1.00 MAX

EATING PLANE

BALL A6

SOLDER BALL DIAMETER

REFERS TO POST REFLOW

CONDITION. THE

PRE-REFLOW DIAMETER

IS Ø 0.33

BALL A1

6.00

3.00 ±0.05

1.875 ±0.050

3.00 ±0.05

6.00 ±0.10

4.00

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

APPENDIX A

How Extended Timings Impact

CellularRAMTM Operation

Introduction

This note describes CellularRAM timing require-

ments in systems that perform extended operations.

CellularRAM products use a DRAM technology that

periodically requires refresh to ensure against data cor-

ruption. CellularRAM devices include on-chip circuitry

that performs the required refresh in a manner that is

completely transparent in systems with normal bus

timings. The refresh circuitry imposes constraints on

timings in systems that take longer than 10µs to com-

plete an operation. WRITE operations are affected if

the device is configured for asynchronous operation.

Both READ and WRITE operations are affected if the

device is configured for burst-mode operation.

Asynchronous and Page-Mode Operation

CellularRAM products require that asynchronous

WRITE operations must be completed within 10µs.

After completing an operation, the device must either

enter standby (by transitioning CE# HIGH), or perform

a second operation using a new address. Figures 41

and 42 demonstrate these constraints as they apply

during an asynchronous (page-mode-disabled) opera-

tion. Either the CE# active period (tCEM in Figure41)

or the address valid period (tTM in Figure42) must be

less than 10µs during any operation to accommodate

orderly scheduling of refresh.

Figure 41: Extended Timing for tCEM

OTE:

Timing constraints when page mode is disabled.

Figure 42: Extended Timing for tTM

OTE:

1. Timing constraints when page mode is disabled.

When a CellularRAM device is configured for page-

mode operation, the address inputs are used to accel-

erate READ accesses and cannot be used by the on-

chip circuitry to schedule refresh. CE# must return

HIGH upon completion of all WRITE operations when

page mode is enabled (see Figure43 below). The total

time taken for a WRITE operation should not exceed

10µs to accommo dat e orderly scheduling of refresh.

Figure 43: Extended Timing for tCEM1

OTE:

1. Timing constraints when page mode is enabled.

Modified timings are only required during extended

WRITE operations (see Figure 44 below). An extended

WRITE operation requires that both the WRITE pulse

width (tWP) and the data valid period (tDW) be length-

ened to at least the minimum WRITE cycle time (tWC

[MIN]). These increased timings ensure that time is

available for both a refresh and successful completion of

the WRITE operation.

Figure 44: Extended Asynchronous

Write Operation

CE#

DDRESS

CEM

10µs

CE#

DDRESS

tTM 10µs

tCEM 10µs

Data Valid

DATA-IN

DDRESS

CE#

LB#/UB#

WE#

tCEM or tTM > 10µs

tWP tWC (MIN)

tDW tWC (MIN)

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Burst-Mode Operation

When configured for burst-mode operation, it is

necessary to allow the device to perform a refresh

within any 10µs window. One of two conditions will

enable the device to schedule a refresh within 10µs.

The first condition is when all burst operations com-

plete within 10µs . A burst comple te s when the CE# si g-

nal is registered HIGH on a positive (BCR[6] = 1) or a

negative (BCR[6] = 0) clock edge. The second condition

that allows a refresh is when a burst access crosses a

row boundary. The row-boundary crossing causes

WAIT to be asserte d while the next row is accessed and

enables the scheduling of refresh.

Summary

CellularRAM products are designed to ensure that

any possible asynchronous timings do not cause data

corruption due to lack of refresh. Slow bus timings will

only affect asynchronous WRITE operations (READs

are unaffected). The impact on asynchronous WRITE

operations is that some of the tim ing parameters (tWP

and tDW) are lengthened. Burst mode timings must

allow the device to perform a refresh within any 10µs

period. A burst operation must either complete (CE#

registered HIGH) or cross a row boundary within 10µs

to ensure successful refresh scheduling. These timing

requirements are likely to have little or no impact

when interfacing a CellularRAM device with a low-

speed memory bus.

4 MEG x 16, 2 MEG x 16

ASYNC/PAGE/BURST CellularRAM MEMORY

ADVANCE

09005aef80be2036/09005aef80be1fbd Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 47: Revision History

CHANGE DATE CHANGED

BY DESCRIPTION

7 07/10/03 ddb Input/Output leakage to 1µA.

Added tAS, removed tS.

6 06/23/03 ddb Incorporated Industrial Temperature data where applicable.

Rounded initial latency an d initial access to 39ns.

5 06/20/03 ddb Added -706 part information where applicable.

4 06/19/03 ddb Removed tSP and tHD from CE# in Burst diagrams.

3 06/18/03 ddb Changed standby power to 90µA and 100µA as marked; changed specified values

to “TBD.”

2 06/09/03 ddb Absolute Maximum Signal Input value changed.

1 06/06/03 ddb Initial release.