X28C010 1M 128K x 8 Bit 5 Volt, Byte Alterable E2PROM FEATURES DESCRIPTION * Access Time: 120ns * Simple Byte and Page Write --Single 5V Supply --No External High Voltages or VPP Control Circuits --Self-Timed * No Erase Before Write * No Complex Programming Algorithms * No Overerase Problem * Low Power CMOS: --Active: 50mA --Standby: 500A * Software Data Protection --Protects Data Against System Level Inadvertant Writes * High Speed Page Write Capability * Highly Reliable Direct WriteTM Cell --Endurance: 100,000 Write Cycles --Data Retention: 100 Years * Early End of Write Detection --DATA Polling --Toggle Bit Polling The Xicor X28C010 is a 128K x 8 E2PROM, fabricated with Xicor's proprietary, high performance, floating gate CMOS technology. Like all Xicor programmable nonvolatile memories the X28C010 is a 5V only device. The X28C010 features the JEDEC approved pinout for bytewide memories, compatible with industry standard EPROMs. The X28C010 supports a 256-byte page write operation, effectively providing a 19s/byte write cycle and enabling the entire memory to be typically written in less than 2.5 seconds. The X28C010 also features DATA Polling and Toggle Bit Polling, system software support schemes used to indicate the early completion of a write cycle. In addition, the X28C010 supports Software Data Protection option. Xicor E2PROMs are designed and tested for applications requiring extended endurance. Data retention is specified to be greater than 100 years. PIN CONFIGURATIONS 2 31 3 30 NC A12 A7 4 29 5 28 A14 A13 A6 A5 6 27 7 26 A4 A3 8 25 9 24 A2 A1 10 23 11 22 A0 I/O0 12 21 13 20 I/O1 I/O2 14 19 15 18 I/O5 I/O4 VSS 16 17 I/O3 X28C010 ????-1.0 2/12/99 ??/??/?? EP A8 A9 A11 OE A10 CE I/O6 I/O5 I/O0 I/O2 I/O 3 22 15 17 19 21 A1 13 A0 14 CE I/O4 I/O7 I/O1 VSS 24 20 23 16 18 A2 12 A3 11 A10 OE 25 26 A4 10 9 8 A6 7 X28C010 (BOTTOM VIEW) A7 A15 A12 6 A5 5 NC 2 VCC NC 36 34 A11 27 A9 28 A8 29 A 13 30 NC 32 A 14 31 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 4 3 2 WE NC A12 A15 A16 NC VCC WE NC NC VCC 30 32 31 54 3 2 29 1 6 28 7 27 26 8 X28C010 9 25 (TOP VIEW) 10 24 11 23 12 22 13 15 16 17 18 19 20 21 14 32 31 30 1 A14 A13 A8 A9 A11 OE A10 CE I/O7 A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 5 6 7 8 9 10 11 12 13 X28C010 (TOP VIEW) 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE I/O7 14 15 16 17 18 19 20 I/O4 I/O5 I/O6 A16 A15 VCC WE I/O1 I/O2 VSS I/O3 32 I/O1 I/O2 VSS I/O3 1 A 12 A 15 A 16 PGA NC EXTENDED LCC PLCC LCC I/O4 I/O5 I/O6 CERDIP FLAT PACK SOIC (R) TSOP 4 A 16 NC 3 NC 1 WE 35 NC 33 A11 A9 A8 A13 A14 NC NC NC WE VCC NC NC NC A16 A15 A12 A7 A6 A5 A4 I/O7 I/O6 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 X28C010 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 NC NC VSS NC NC I/O2 I/O1 I/O0 A0 A1 A2 A3 Characteristics subject to change without notice X28C010 PIN DESCRIPTIONS PIN NAMES Addresses (A0-A16) The Address inputs select an 8-bit memory location during a read or write operation. Symbol Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. A0-A16 Address Inputs I/O0-I/O7 Data Input/Output WE Write Enable CE Chip Enable OE Output Enable VCC +5V VSS Ground NC No Connect Data In/Data Out (I/O0-I/O7) Data is written to or read from the X28C010 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28C010. FUNCTIONAL DIAGRAM A8 -A16 X BUFFERS LATCHES AND DECODER A 0-A7 Y BUFFERS LATCHES AND DECODER 1M-BIT E 2PROM ARRAY I/O BUFFERS AND LATCHES I/O 0-I/O7 DATA INPUTS/OUTPUTS CE OE WE CONTROL LOGIC AND TIMING VCC V SS 2 Description X28C010 DEVICE OPERATION Write Operation Status Bits The X28C010 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Figure 1. Status Bit Assignment I/O Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C010 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. DP TB 5 4 3 2 1 0 RESERVED TOGGLE BIT DATA POLLING DATA Polling (I/O7) The X28C010 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28C010, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Note: If the X28C010 is in the protected state and an illegal write operation is attempted DATA Polling will not operate. Page Write Operation The page write feature of the X28C010 allows the entire memory to be written in 5 seconds. Page write allows two to two hundred fifty-six bytes of data to be consecutively written to the X28C010 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A8 through A16) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. Toggle Bit (I/O6) The X28C010 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle, I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to two hundred fifty six bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100s. 3 X28C010 DATA Polling I/O7 Figure 2. DATA Polling Bus Sequence WE LAST WRITE CE OE VIH V OH HIGH Z I/O7 VOL A 0-A 14 An An An X28C010 READY An An An An Figure 3. DATA Polling Software Flow DATA Polling can effectively halve the time for writing to the X28C010. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine. WRITE DATA NO WRITES COMPLETE? YES SAVE LAST DATA AND ADDRESS READ LAST ADDRESS IO7 COMPARE? NO YES X28C010 READY 4 X28C010 The Toggle Bit I/O6 Figure 4. Toggle Bit Bus Sequence WE LAST WRITE CE OE I/O6 VOH HIGH Z * VOL * X28C010 READY * Beginning and ending state of I/O6 will vary. Figure 5. Toggle Bit Software Flow The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28C010 memories that is frequently updated. Toggle Bit Polling can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit. LAST WRITE LOAD ACCUM FROM ADDR n COMPARE ACCUM WITH ADDR n COMPARE OK? NO YES READY 5 X28C010 HARDWARE DATA PROTECTION The X28C010 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. The X28C010 provides three hardware features that protect nonvolatile data from inadvertent writes. * Noise Protection--A WE pulse less than 10ns will not initiate a write cycle. * Default VCC Sense--All functions are inhibited when VCC is 3.5V. * Write inhibit--Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. Once the software protection is enabled, the X28C010 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. SOFTWARE DATA PROTECTION The X28C010 offers a software controlled data protection feature. The X28C010 is shipped from Xicor with the software data protection NOT ENABLED: that is the device will be in the standard operating mode. In this mode data should be protected during power-up/-down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable. SOFTWARE ALGORITHM Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figures 6 and 7 for the sequence. The three byte sequence opens the page write window enabling the host to write from one to two hundred fifty-six bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state. 6 X28C010 Software Data Protection Figure 6. Timing Sequence--Byte or Page Write VCC (VCC) 0V DATA ADDR AA 5555 55 2AAA A0 5555 WRITES OK CE t BLC MAX tWC WRITE PROTECTED BYTE OR PAGE WE Figure 7. Write Sequence for Software Data Protection Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the X28C010 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28C010 will be write protected during power-down and after any subsequent power-up. The state of A15 and A16 while executing the algorithm is don't care. WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA Note: WRITE DATA A0 TO ADDRESS 5555 WRITE DATA XX TO ANY ADDRESS OPTIONAL BYTE/PAGE LOAD OPERATION WRITE LAST BYTE TO LAST ADDRESS AFTER tWC RE-ENTERS DATA PROTECTED STATE 7 Once initiated, the sequence of write operations should not be interrupted. X28C010 Resetting Software Data Protection Figure 8. Reset Software Data Protection Timing Sequence V CC DATA ADDR AA 5555 55 2AAA 80 5555 AA 5555 55 2AAA 20 5555 t WC STANDARD OPERATING MODE CE WE Figure 9. Software Sequence to Deactivate Software Data Protection In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28C010 will be in standard operating mode. WRITE DATA AA TO ADDRESS 5555 Note: WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 80 TO ADDRESS 5555 WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 20 TO ADDRESS 5555 8 Once initiated, the sequence of write operations should not be interrupted. X28C010 the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1F high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. SYSTEM CONSIDERATIONS Because the X28C010 is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus. In addition, it is recommended that a 4.7F electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage drop caused by the inductive effects of the PC board traces. Because the X28C010 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on Active Supply Current vs. Ambient Temperature ICC (RD) by Temperature over Frequency 18 60 VCC = 5V 50 I CC RD (mA) 16 ICC WR (mA) 5.0 VCC 14 -55C +25C 40 +125C 30 12 20 10 -55 -10 +35 +80 10 +125 0 AMBIENT TEMPERATURE ( C) 0.3 VCC = 5V I SB (mA) 0.25 0.2 0.15 0.1 -10 +35 +80 6 9 FREQUENCY (MHz) Standby Supply Current vs. Ambient Temperature 0.05 -55 3 +125 AMBIENT TEMPERATURE ( C) 9 12 15 X28C010 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature under Bias X28C010............................................-10C to +85C X28C010I.........................................-65C to +135C X28C010M ......................................-65C to +135C Storage Temperature..............................-65C to +150C Voltage on any Pin with Respect to VSS .......................................... -1V to +7V D.C. Output Current ....................................................5mA Lead Temperature (Soldering, 10 seconds) ................................... 300C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMEND OPERATING CONDITIONS Temperature Min. Max. Supply Voltage Limits Commercial 0C +70C X28C010 5V 10% Industrial -40C +85C Military -55C +125C D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions ICC VCC Current (Active) (TTL Inputs) 50 mA CE = OE = VIL, WE = VIH, All I/O's = Open, Address Inputs = .4V/2.4V Levels @ f = 5MHz ISB1 VCC Current (Standby) (TTL Inputs) 3 mA CE = VIH, OE = VIL All I/O's = Open, Other Inputs = VIH ISB2 VCC Current (Standby) (CMOS Inputs) 500 A CE = VCC - 0.3V, OE = VIL All I/O's = Open, Other Inputs = VCC ILI Input Leakage Current 10 A VIN = VSS to VCC ILO Output Leakage Current 10 A VOUT = VSS to VCC, CE = VIH VlL(1) Input LOW Voltage -1 0.8 V VIH(1) Input HIGH Voltage 2 VCC + 1 V VOL Output LOW Voltage 0.4 V IOL = 2.1mA VOH Output HIGH Voltage V IOH = -400A 2.4 Notes: (1) VIL min. and VIH max. are for reference only and are not tested. 10 X28C010 POWER-UP TIMING Symbol Parameter Max. Units tPUR(2) Power-up to Read Operation 100 s tPUW(2) Power-up to Write Operation 5 ms CAPACITANCE TA = +25C, f = 1MHZ, VCC = 5V Symbol Parameter Max. Units Test Conditions CI/O(2) Input/Output Capacitance 10 pF VI/O = 0V CIN(2) Input Capacitance 10 pF VIN = 0V ENDURANCE AND DATA RETENTION Parameter Min. Endurance 10,000 Cycles Per Byte Endurance 100,000 Cycles Per Page Data Retention 100 Years A.C. CONDITIONS OF TEST Input Pulse Levels Units MODE SELECTION 0V to 3V Input Rise and Fall Times 10ns Input and Output Timing Levels 1.5V CE OE WE Mode I/O Power L L H Read DOUT Active L H L Write DIN Active H X X Standby and Write Inhibit High Z Standby X L X Write Inhibit -- -- X X H Write Inhibit -- -- EQUIVALENT A.C. LOAD CIRCUIT SYMBOL TABLE 5V WAVEFORM 1.92KW OUTPUT 1.37KW Max. 100pF Notes: (2) This parameter is periodically sampled and not 100% tested. 11 INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don't Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance X28C010 A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read Cycle Limits Symbol Parameter X28C010-12 X28C010-15 X28C010-20 X28C010-25 Min. Min. Min. Min. Max. Max. Max. Max. Units tRC Read Cycle Time tCE Chip Enable Access Time 120 150 200 250 ns tAA Address Access Time 120 150 200 250 ns tOE Output Enable Access Time 50 50 50 50 ns tLZ(3) CE LOW to Active Output 0 0 0 0 ns tOLZ(3) OE LOW to Active Output 0 0 0 0 ns tHZ(3) CE HIGH to High Z Output 50 50 50 50 ns tOHZ(3) OE HIGH to High Z Output 50 50 50 50 ns tOH Output Hold from Address Change 120 150 0 200 0 0 250 ns 0 ns Read Cycle tRC ADDRESS tCE CE tOE OE V IH WE t OLZ tOHZ tLZ DATA I/O t OH HIGH Z t HZ DATA VALID DATA VALID t AA Notes: (3) tLZ min.,tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven. 12 X28C010 Write Cycle Limits Symbol Parameter Min. Max. Units 10 ms tWC(4) Write Cycle Time tAS Address Setup Time 0 ns tAH Address Hold Time 50 ns tCS Write Setup Time 0 ns tCH Write Hold Time 0 ns tCW CE Pulse Width 100 ns tOES OE HIGH Setup Time 10 ns tOEH OE HIGH Hold Time 10 ns tWP WE Pulse Width 100 ns tWPH WE HIGH Recovery 100 ns tDV Data Valid tDS Data Setup 50 ns tDH Data Hold 0 ns tDW Delay to Next Write 10 s tBLC Byte Load Cycle 0.2 1 100 s s WE Controlled Write Cycle tWC ADDRESS tAS tAH tCS tCH CE OE t OES tOEH tWP WE tWPH tDV DATA IN DATA VALID tDS DATA OUT t DH HIGH Z Notes: (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to complete internal write operation. 13 X28C010 CE Controlled Write Cycle tWC ADDRESS tAS tAH tCW CE tWPH tOES OE tOEH tCS t CH WE tDV DATA VALID DATA IN tDS t DH HIGH Z DATA OUT Page Write Cycle OE (5) CE t WP tBLC WE t WPH ADDRESS * (6) I/O LAST BYTE BYTE 0 BYTE 1 BYTE 2 BYTE n *For each successive write within the page write operation, A8-A 16 should be the same or writes to an unknown address could occur. BYTE n+1 BYTE n+2 t WC Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. (6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. 14 X28C010 DATA Polling Timing Diagram(7) ADDRESS An An An CE WE tOEH tOES OE tDW DIN =X I/O 7 DOUT =X DOUT =X tWC Toggle Bit Timing Diagram CE WE tOES tOEH OE tDW I/O 6 HIGH Z * * tWC * I/O6 beginning and ending state will vary. Notes: (7) Polling operations are by definition read cycles and are therefore subject to read cycle timings. 15 X28C010 PACKAGING INFORMATION 32-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D 1.690 (42.95) MAX. 0.610 (15.49) 0.500 (12.70) PIN 1 0.005 (0.13) MIN. 0.100 (2.54) MAX. SEATING PLANE 0.232 (5.90) MAX. 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN. 0.200 (5.08) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) TYP. 0.100 (2.54) 0.065 (1.65) 0.033 (0.84) TYP. 0.055 (1.40) 0.023 (0.58) 0.014 (0.36) TYP. 0.018 (0.46) 0.620 (15.75) 0.590 (14.99) TYP. 0.614 (15.60) 0 15 0.015 (0.38) 0.008 (0.20) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FHD F09 16 X28C010 PACKAGING INFORMATION 32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E 0.300 (7.62) BSC 0.150 (3.81) BSC 0.015 (0.38) 0.003 (0.08) 0.020 (0.51) x 45 REF. 0.095 (2.41) 0.075 (1.91) PIN 1 0.022 (0.56) DIA. 0.006 (0.15) 0.200 (5.08) BSC 0.015 (0.38) MIN. 0.028 (0.71) 0.022 (0.56) (32) PLCS. 0.050 (1.27) BSC 0.055 (1.39) 0.045 (1.14) TYP. (4) PLCS. 0.040 (1.02) x 45 REF. TYP. (3) PLCS. 0.458 (11.63) 0.442 (11.22) 0.120 (3.05) 0.060 (1.52) 0.458 (11.63) -- 0.560 (14.22) 0.540 (13.71) 0.558 (14.17) -- 0.088 (2.24) 0.050 (1.27) 0.400 (10.16) BSC PIN 1 INDEX CORNER NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: 1% NLT 0.005 (0.127) 3926 FHD F14 17 X28C010 PACKAGING INFORMATION 32-LEAD CERAMIC FLAT PACK TYPE F 1.228 (31.19) 1.000 (25.40) PIN 1 INDEX 1 0.019 (0.48) 0.015 (0.38) 32 0.050 (1.27) BSC 0.830 (21.08) MAX. 0.045 (1.14) MAX. 0.005 (0.13) MIN. 0.488 0.430 (10.93) 0.007 (0.18) 0.004 (0.10) 0.120 (3.05) 0.090 (2.29) 0.370 (9.40) 0.270 (6.86) 0.347 (8.82) 0.330 (8.38) 0.045 (1.14) 0.026 (0.66) 0.030 (0.76) MIN NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FHD F20 18 X28C010 PACKAGING INFORMATION 32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J 0.030" TYPICAL 32 PLACES 0.050" TYPICAL 0.420 (10.67) 0.050" TYPICAL 0.510" TYPICAL 0.400" 0.050 (1.27) TYP. 0.300" REF 0.410" FOOTPRINT 0.045 (1.14) x 45 0.021 (0.53) 0.013 (0.33) TYP. 0.017 (0.43) 0.495 (12.57) 0.485 (12.32) TYP. 0.490 (12.45) 0.453 (11.51) 0.447 (11.35) TYP. 0.450 (11.43) 0.300 (7.62) REF. PIN 1 SEATING PLANE 0.004 LEAD CO - PLANARITY -- 0.015 (0.38) 0.095 (2.41) 0.060 (1.52) 0.140 (3.56) 0.100 (2.45) TYP. 0.136 (3.45) 0.048 (1.22) 0.042 (1.07) 0.595 (15.11) 0.585 (14.86) TYP. 0.590 (14.99) 0.553 (14.05) 0.547 (13.89) TYP. 0.550 (13.97) 0.400 (10.16)REF. 3 TYP. NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY 3926 FHD F13 19 X28C010 PACKAGING INFORMATION 36-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K 15 17 19 21 22 A 0.008 (0.20) 13 14 12 11 16 18 20 23 24 25 26 0.050 (1.27) A 10 9 27 28 8 7 29 30 NOTE: LEADS 5, 14, 23, & 32 TYP. 0.100 (2.54) ALL LEADS 6 TYP. 0.180 (.010) (4.57 .25) 4 CORNERS 5 2 36 34 32 4 3 1 35 33 31 TYP. 0.180 (.010) (4.57 .25) 4 CORNERS 0.120 (3.05) 0.100 (2.54) 0.072 (1.83) 0.062 (1.57) PIN 1 INDEX 0.770 (19.56) 0.750 (19.05) SQ 0.020 (0.51) 0.016 (0.41) A A 0.185 (4.70) 0.175 (4.45) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FHD F21 20 X28C010 PACKAGING INFORMATION 32-LEAD CERAMIC SMALL OUTLINE GULL WING PACKAGE TYPE R 0.060 NOM. SEE DETAIL "A" FOR LEAD INFORMATION 0.020 MIN. 0.165 TYP. 0.340 0.007 0.015 R TYP. 0.015 R TYP . 0.035 TYP . 0.035 MIN. DETAIL "A" 0.050" TYPICAL 0.0192 0.0138 0.050" TYPICAL 0.840 MAX. 0.750 0.005 0.050 0.560" TYPICAL FOOTPRINT 0.030" TYPICAL 32 PLACES 0.440 MAX. 0.560 NOM. NOTES: 1. ALL DIMENSIONS IN INCHES 2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES 3926 FHD F27 21 X28C010 PACKAGING INFORMATION 32-PAD STRETCHED CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE N 0.300 BSC 0.035 x 45 REF. DETAIL A 0.085 0.010 PIN 1 0.005/0.015 DETAIL A 0.025 0.003 0.006/0.022 0.400 BSC 0.050 0.005 0.050 BSC 0.020 (1.02) x 45 REF. TYP. (3) PLCS. 0.450 0.008 0.060/0.120 0.458 MAX. 0.700 0.010 0.708 MAX. PIN #1 INDEX CORNER NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: 1% NLT0.005 (0.127) 3926 FHD F35 22 X28C010 PACKAGING INFORMATION 40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T 0.493 (12.522) 0.045 (1.143) 0.483 (12.268) 0.035 (0.889) PIN #1 IDENT. O 0.040 (1.016) X 0.005 (0.127) DP. O 0.030 (0.762) 0.003 (0.076) DP. (0.038) 0.965 0.048 (1.219) 1 0.0197 (0.500) 0.396 (10.058) 0.392 (9.957) 0.007 (0.178) 15 TYP. A 0.0025 (0.065) SEATING PLANE 0.010 (0.254) 0.006 (0.152) 0.040 (1.016) SEATING PLANE 0.557 (14.148) 0.547 (13.894) DETAIL A 0.032 (0.813) TYP. 0.017 (0.432) 0.006 (0.152) TYP. 4 TYP. 0.020 (0.508) TYP. 14.80 0.05 (0.583 0.002) SOLDER PADS 0.30 0.05 (0.012 0.002) TYPICAL 40 PLACES 15 EQ. SPC.@ 0.50 0.04 0.0197 0.016 = 9.50 0.06 (0.374 0.0024) OVERALL TOL. NON-CUMULATIVE 0.17 (0.007) 0.03 (0.001) FOOTPRINT 0.50 0.04 (0.0197 0.0016) 1.30 0.05 (0.051 0.002) NOTE: 1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES). 23 0.017 (0.432) X28C010 ORDERING INFORMATION X28C010 X X -X Access Time -12 = 120ns -15 = 150ns -20 = 200ns -25 = 250ns Device Temperature Range Blank = Commercial = 0C to 70C I = Industrial = -40C to +85C M = Military = -55C to +125C MB = MIL-STD-883 Package D = 32-Lead Cerdip E = 32-Pad LCC F = 32-Lead Flat Pack J = 32-Lead PLCC K = 36-Lead Pin Grid Array R = 32-Lead Ceramic SOIC (Gull Wing) N = 32-Lead Extended LCC T = 40-Lead TSOP LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 24