Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply TTL/CMOS Comparator
ADCMP603
FEATURES FUNCTIONAL BLOCK DIAGRAM
V
P
NONINVERTING
INPUT
V
N
INVERTING
INPUT
S
DN
INPUT
Q OUTPUT
Q OUTPUT
V
CCI
V
CCO
LE/HYS INPUT
05915-001
ADCMP603
TTL
Fully specified rail to rail at V = 2.5 V to 5.5 V
CC
Input common-mode voltage from −0.2 V to V + 0.2 V
CC
Low glitch CMOS-/TTL-compatible output stage
Complementary outputs
3.5 ns propagation delay
12 mW at 3.3 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection > 50 dB
−40°C to +125°C operation
APPLICATIONS Figure 1.
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
GENERAL DESCRIPTION
The device passes 4.5 kV HBM ESD testing and the absolute
maximum ratings include current limits for all pins.
The ADCMP603 is a very fast comparator fabricated on
XFCB2, an Analog Devices, Inc. proprietary process. This
comparator is exceptionally versatile and easy to use. Features
include an input range from V The complementary TTL-/CMOS-compatible output stage is
designed to drive up to 5 pF with full timing specs and to
degrade in a graceful and linear fashion as additional
capacitance is added. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded.
Latch and programmable hysteresis features are also provided
with a unique single-pin control option.
− 0.5 V to V
EE CC + 0.2 V, low noise
complementary TTL-/CMOS-compatible output drivers, latch
inputs with adjustable hysteresis and a shutdown input.
The device offers 3.5 ns propagation delay with 10 mV
overdrive on 4 mA typical supply current.
A flexible power supply scheme allows the device to operate
with a single +2.5 V positive supply and a −0.5 V to +2.8 V
input signal range up to a +5.5 V positive supply with a −0.5 V
to +5.8 V input signal range. Split input/output supplies with no
sequencing restrictions support a wide input signal range while
still allowing independent output swing control and power
savings.
The ADCMP603 is available in a 12-lead LFCSP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
ADCMP603
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Timing Information ......................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Application Information................................................................ 10
Power/Ground Layout and Bypassing..................................... 10
TTL-/CMOS-Compatible Output Stage ................................. 10
Using/Disabling the Latch Feature........................................... 10
Optimizing Performance........................................................... 11
Comparator Propagation Delay Dispersion ........................... 11
Comparator Hysteresis .............................................................. 11
Crossover Bias Point .................................................................. 12
Minimum Input Slew Rate Requirement................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
10/06—Revision 0: Initial Version
ADCMP603
Rev. 0 | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCCI = VCCO = 2.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DC INPUT CHARACTERISTICS
Voltage Range VP, VNVCC = 2.5 V to 5.5 V −0.5 VCC + 0.2 V
Common-Mode Range VCC = 2.5 V to 5.5 V −0.2 VCC + 0.2 V
Differential Voltage VCC = 2.5 V to 5.5 V VCC + 0.8 V
Offset Voltage VOS −5.0 ±2 +5.0 mV
Bias Current IP, IN −5.0 ±2 +5.0 µA
Offset Current −2.0 2.0 µA
Capacitance CP, CN 1.0 pF
Resistance, Differential Mode −0.5 V to VCC + 0.2 V 200 700 kΩ
Resistance, Common Mode −0.2 V to VCC + 0.2 V 100 350 kΩ
Active Gain AV 85 dB
VCCI = 2.5 V, VCCO = 2.5 V,
VCM = −0.2 V to +2.7 V
50 dB
Common-Mode Rejection Ratio CMRR
VCCI = 5.5 V, VCCO = 5.5 V,
VCM = −0.2 V to +5.7 V
50 dB
Hysteresis RHYS = ∞ 0.1 mV
LATCH ENABLE PIN CHARACTERISTICS
VIH Hysteresis is shut off 2.0 VCC V
VIL Latch mode guaranteed −0.2 +0.4 +0.8 V
IIH V
IH = VCC −6 +6 µA
IOL V
IL = 0.4 V −0.1 mA
HYSTERESIS MODE AND TIMING
Hysteresis Mode Bias Voltage Current sink −1 A 1.145 1.25 1.35 V
Resistor Value Hysteresis = 120 mV 65 80 95 kΩ
Hysteresis Current Hysteresis = 120 mV −18 −14 −10 µA
Latch Setup Time tSVOD = 50 mV −2.0 ns
Latch Hold Time tHVOD = 50 mV 2.0 ns
Latch-to-Output Delay tPLOH, tPLOL VOD = 50 mV 30 ns
Latch Minimum Pulse Width tPL VOD = 50 mV 23 ns
SHUTDOWN PIN CHARACTERISTICS
VIH Comparator is operating 2.0 VCCO V
VIL Shutdown guaranteed −0.2 +0.4 +0.6 V
IIH V
IH = VCC −6 +6 µA
IOL V
IL = 0 V −80 µA
Sleep Time tSD IOUT < 0.5 mA 20 ns
Wake-Up Time tHVOD = 100 mV, output valid 50 ns
DC OUTPUT CHARACTERISTICS VCCO = 2.5 V to 5.5 V
Output Voltage High Level VOH IOH = 8 mA VCCO = 2.5 V VCC − 0.4 V
Output Voltage High Level −40°C VOH IOH = 6 mA VCCO = 2.5 V VCC − 0.4 V
Output Voltage Low Level VOL IOL = 8 mA, VCCO = 2.5 V 0.4 V
Output Voltage Low Level −40°C VOL IOL = 6 mA, VCCO = 2.5 V 0.4 V
ADCMP603
Rev. 0 | Page 4 of 16
Parameter Symbol Conditions Min Typ Max Unit
AC PERFORMANCE1
Rise Time /Fall time tR/tF10% to 90%, VCCO = 2.5 V 2.2 ns
10% to 90%, VCCO = 5.5 V 4.5 ns
Propagation Delay tPD VOD = 50 mV, VCCO = 2.5 V 3.5 ns
V
OD = 50 mV, VCCO = 5.5 V 4.8 ns
V
OD = 10 mV, VCCO = 2.5 V 5 ns
Propagation Delay Skew—Rising to
Falling Transition
tPINSKEW VCCO = 2.5 V to 5.5 V
VOD = 50 mV
500 ps
Propagation Delay Skew—Q to QB tDIFFSKEW VCCO =2.5 V to 5.5 V
VOD = 50 mV
300 ps
Overdrive Dispersion 10 mV < VOD < 125 mV 1.5 ns
Common-Mode Dispersion −2 V < VCM < VCCI + 2 V
VOD = 50 mV
200 ps
Minimum Pulse Width PWMIN VCCI = VCCO = 2.5 V
PWOUT = 90% of PWIN
3.3 ns
VCCI = VCCO = 5.5 V
PWOUT = 90% of PWIN
5.5 ns
POWER SUPPLY
Input Supply Voltage Range VCCI 2.5 5.5 V
Output Supply Voltage Range VCCO 2.5 5.5 V
Positive Supply Differential VCCI − VCCO Operating −3.0 +3.0 V
Positive Supply Differential VCCI − VCCO Nonoperating −5.5 +5.5 V
Input Section Supply Current IVCCI VCCI = 2.5 V to 5.5 V 1.1 1.8 mA
Output Section Supply Current IVCCO VCCI = 2.5 V to 5.5 V 2.3 3.5 mA
Power Dissipation PDVCC = 2.5 V 9 11 mW
P
DVCC = 5.5 V 21 30 mW
Power Supply Rejection Ratio PSRR VCCI = 2.5 V to 5.5 V −50 dB
Shutdown Mode Supply Current VCC =2.5 V 290 430 µA
1 VIN = 100 mV square input at 50 MHz, VCM = 0 V, CL = 5 pF, VCCI = VCCO = 2.5 V, unless otherwise noted.
ADCMP603
Rev. 0 | Page 5 of 16
TIMING INFORMATION
Figure 2 illustrates the ADCMP603 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
1.1V
50%
V
N
± V
OS
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
t
H
t
PDL
t
PLOH
t
F
V
IN
V
OD
t
S
t
PL
05915-023
50%
Q OUTPUT
t
PDH
t
PLOL
t
R
Figure 2. System Timing Diagram
Table 2. Timing Descriptions
Symbol Timing Description
tInput to output high delay Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
PDH
tInput to output low delay Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
PDL
tLatch enable to output high delay Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
PLOH
tLatch enable to output low delay Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
PLOL
tMinimum hold time Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
H
tMinimum latch enable pulse width Minimum time that the latch enable signal must be high to acquire an input signal change.
PL
tMinimum setup time Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.
S
tOutput rise time Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.
R
tOutput fall time Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.
F
VVoltage overdrive Difference between the input voltages V
OD A and V .
B
ADCMP603
Rev. 0 | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Supply Voltages
Input Supply Voltage (V to GND) −0.5 V to +6.0 V
CCI
−0.5 V to +6.0 V
Output Supply Voltage
(V to GND)
CCO
−6.0 V to +6.0 V
Positive Supply Differential
(V − V ) THERMAL RESISTANCE
CCI CCO
Input Voltages θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Input Voltage −0.5 V to V + 0.5 V
CCI
Differential Input Voltage ±(V + 0.5 V)
CCI
Table 4. Thermal Resistance
Maximum Input/Output Current ±50 mA
Shutdown Control Pin Package Type θ Unit
JA1
Applied Voltage (HYS to GND) −0.5 V to VCCO + 0.5 V ADCMP603 LFCSP 12-lead 62 °C/W
1 Measurement in still air.
Maximum Input/Output Current ±50 mA
ESD CAUTION
Latch/Hysteresis Control Pin
Applied Voltage (HYS to GND) −0.5 V to VCCO + 0.5 V
Maximum Input/Output Current ±50 mA
Output Current ±50 mA
Temperature
Operating Temperature, Ambient −40°C to +125°C
Operating Temperature, Junction 150°C
Storage Temperature Range −65°C to +150°C
ADCMP603
Rev. 0 | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1V
CCO
2V
CCI
3V
EE
9V
EE
8LE/HYS
7S
DN
4
V
P
5
V
EE
6
V
N
12 Q
11 V
EE
10 Q
TOP VIEW
(Not to Scale)
ADCMP603
05915-002
Figure 3. ADCMP603 Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 V Output Section Supply.
CCO
2 VCCI Input Section Supply.
3 VEE Negative Supply Voltage.
4 VPNoninverting Analog Input.
5 VEE Negative Supply Voltage.
6 VNInverting Analog Input.
7 SDN Shutdown. Drive this pin low to shut down the device.
8 LE/HYS Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch.
9 VEE Negative Supply Voltage.
10 QInverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog
voltage at the inverting input, VN, if the comparator is in compare mode. See the LE/HYS pin description (Pin 8)
for more information.
11 VEE Negative Supply Voltage.
12 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the
analog voltage at the inverting input, VN, if the comparator is in compare mode. See the LE pin description
(Pin 8) for more information.
V
Heat Sink
Paddle
The metallic back surface of the package is electrically connected to V
EE EE. It can be left floating because Pin 3, Pin 5,
Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board if
improved thermal and/or mechanical stability is desired. Exposed metal at package corners is connected to the
heat sink paddle.
ADCMP603
Rev. 0 | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = VCCO = 2.5 V, T = 25°C, unless otherwise noted.
A
4
1
2
3
0
–1
–2–5 0 5 10 15 20
05915-010
TYPICAL OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
OUTPUT VOLTAGE
–800
–101234 567
–600
–400
–200
0
200
400
600
800
05915-007
CURRENT (µA)
LE/HYSTERESIS PIN VOLTAGE (V)
V
CC
= 5.5V
V
CC
= 2.5V
Figure 4. LE/HYS Pin I/V Curve Figure 7. V vs. Load Current
OL
50 150 250 350 450 550 650
05915-004
HYSTERESIS (mV)
HYSTERESIS RESISTOR (kΩ)
1
10
100
1000
VCC = 5.5V
VCC = 2.5V
05915-006
CURRENT (µA)
SHUTDOWN PIN VOLTAGE (V)
–1 76543210
–150
150
–100
100
–50
50
0
200
V
CC
= 2.5V
V
CC
= 5.5V
Figure 5. S Pin I/V Curve Figure 8. Hysteresis vs. R
DN HYS
05915-005
I
B
(µA)
COMMON-MODE VOLTAGE (V)
–20
–15
15
–10
10
–5
5
0
20
–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
I
B
@ +125°C
I
B
@ +25°C
V
CC
= 2.5V
I
B
@ –40°C
0 –2 –4 –6 –8 –10 –12 –14 –16 –18
05915-003
HYSTERESIS (mV)
HYSTERESIS PIN CURRENT (µA)
0
50
100
150
200
250
300
350
HYSTERESIS @ +125°C
HYSTERESIS @ +25°C
HYSTERESIS @ –40°C
Figure 9. Hysteresis vs. Hysteresis Pin Current
Figure 6. Input Bias Current vs. Input Common Mode
ADCMP603
Rev. 0 | Page 9 of 16
8
7
6
5
4
2
3
05915-009
PROPAGATION DELAY (ns)
OVERDRIVE (mV)
0 10 20 30 40 50 60 70 80 90 100 110 120 140130
05915-024
500mV/DIV M2.00ns
Figure 10. Propagation Delay vs. Input Overdrive Figure 12. 50 MHz Output Voltage Waveform at VCCO = 2.5 V
–0.6 0 0.6 1.2 1.8 2.4 3.0
4.0
3.8
3.6
3.4
3.2
3.0
05915-008
DELAY (ns)
COMMON-MODE VOLTAGE (V)
PROP DELAY RISE ns
PROP DELAY FALL ns
V
CC
= 2.5V
05915-025
1.00V/DI
V
M2.00ns
Figure 13. 50 MHz Output Voltage Waveform at V
Figure 11. Propagation Delay vs. Input Common Mode CCO = 5.5 V
ADCMP603
Rev. 0 | Page 10 of 16
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING This delay is measured to the 50% point for the supply in use;
therefore, the fastest times are observed with the VCC supply at
2.5 V, and larger values are observed when driving loads that
switch at other levels.
The ADCMP603 comparator is a very high speed device. Despite
the low noise output stage, it is essential to use proper high speed
design techniques to achieve the specified performance. Because
comparators are uncompensated amplifiers, feedback in any phase
relationship is likely to cause oscillations or undesired hysteresis. Of
critical importance is the use of low impedance supply planes,
particularly the output supply plane (V
When duty cycle accuracy is critical, the logic being driven
should switch at 50% of VCC and load capacitance should be
minimized. When in doubt, it is best to power VCCO or the
entire device from the logic supply and rely on the input PSRR
and CMRR to reject noise.
CCO) and the ground plane
(GND). Individual supply planes are recommended as part of a
multilayer board. Providing the lowest inductance return path for
switching currents ensures the best possible performance in the
target application.
Overdrive and input slew rate dispersions are not significantly
affected by output loading and VCC variations.
The TTL-/CMOS-compatible output stage is shown in the
simplified schematic diagram (Figure 14). Because of its
inherent symmetry and generally good behavior, this output
stage is readily adaptable for driving various filters and other
unusual loads.
It is also important to adequately bypass the input and output
supplies. Multiple high quality 0.01 μF bypass capacitors should
be placed as close as possible to each of the VCCI and VCCO supply
pins and should be connected to the GND plane with redundant
vias. At least one of these should be placed to provide a physically
short return path for output currents flowing back from ground
to the V
OUTPUT
Q2
Q1
+
IN
–
IN
OUTPUT STAGE
V
LOGIC
GAIN STAGE
A2
A1
A
V
0
5915-012
CCO pin. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should also be strictly controlled to maximize
the effectiveness of the bypass at high frequencies.
If the input and output supplies have been connected separately
such that VCCI ≠ VCCO, care should be taken to bypass each of
these supplies separately to the GND plane. A bypass between
them is futile and defeats the purpose of having separate pins. It
is recommended that the GND plane separate the VCCI and VCCO
planes when the circuit board layout is designed to minimize
coupling between the two supplies and to take advantage of the
additional bypass capacitance from each respective supply to
the ground plane. This enhances the performance when split
input/output supplies are used. If the input and output supplies
are connected together for single-supply operation such that V
Figure 14. Simplified Schematic Diagram of
TTL-/CMOS-Compatible Output Stage
CCI =
VUSING/DISABLING THE LATCH FEATURE
CCO, coupling between the two supplies is unavoidable; however,
careful board placement can help keep output return currents
away from the inputs.
The latch input is designed for maximum versatility. It can
safely be left floating for fixed hysteresis or be tied to VCC to
remove the hysteresis, or it can be driven low by any standard
TTL/CMOS device as a high speed latch.
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
Specified propagation delay performance can be achieved only
by keeping the capacitive load at or below the specified minimums.
The low skew complementary outputs of the ADCMP603 are
designed to directly drive one Schottky TTL or three low power
Schottky TTL loads or the equivalent. For large fan outputs,
buses, or transmission lines, use an appropriate buffer to
maintain the excellent speed and stability of the comparator.
In addition, the pin can be operated as a hysteresis control pin
with a bias voltage of 1.25 V nominal and an input resistance of
approximately 7000 Ω, allowing the comparator hysteresis to be
easily controlled by either a resistor or an inexpensive CMOS DAC.
Hysteresis control and latch mode can be used together if an
open drain, an open collector, or a three-state driver is connected
parallel to the hysteresis control resistor or current source.
With the rated 5 pF load capacitance applied, more than half of
the total device propagation delay is output stage slew time,
even at 2.5 V V
Due to the programmable hysteresis feature, the logic threshold
of the latch pin is approximately 1.1 V regardless of VCC.
CC. Because of this, the total prop delay decreases
as VCCO decreases, and instability in the power supply may
appear as excess delay dispersion.
ADCMP603
Rev. 0 | Page 11 of 16
Q/Q OUTPUT
INPUT VOLTAGE
10V/ns
1V/ns
DISPERSION
V
N
± V
OS
05915-014
OPTIMIZING PERFORMANCE
As with any high speed comparator, proper design and layout
techniques are essential for obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and often cause oscillation. Large discontinuities along input
and output transmission lines can also limit the specified pulse-
width dispersion performance. The source impedance should
be minimized as much as is practicable. High source impedance,
in combination with the parasitic input capacitance of the
comparator, causes an undesirable degradation in bandwidth at
the input, thus degrading the overall response. Thermal noise
from large resistances can easily cause extra jitter with slowly
slewing input signals; higher impedances encourage undesired
coupling.
Figure 16. Propagation Delay—Slew Rate Dispersion
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a
noisy environment, or when the differential input amplitudes
are relatively small or slow moving. Figure 17 shows the transfer
function for a comparator with hysteresis. As the input voltage
approaches the threshold (0.0 V, in this example) from below
the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +V
COMPARATOR PROPAGATION
DELAY DISPERSION
The ADCMP603 comparator is designed to reduce propagation
delay dispersion over a wide input overdrive range of 5 mV to
V
H/2, and the
new switching threshold becomes −VH/2. The comparator remains
in the high state until the new threshold, −V
CCI – 1 V. Propagation delay dispersion is the variation in
propagation delay that results from a change in the degree of
overdrive or slew rate (that is, how far or how fast the input
signal exceeds the switching threshold).
H/2, is crossed from
below the threshold region in a negative direction. In this manner,
noise or feedback output signals centered on 0.0 V input cannot
cause the comparator to switch states unless it exceeds the region
bounded by ±VH/2.
Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications, such as data
communication, automatic test and measurement, and instru-
mentation. It is also important in event-driven applications, such
as pulse spectroscopy, nuclear instrumentation, and medical
imaging. Dispersion is defined as the variation in propagation
delay as the input overdrive conditions are changed (Figure 15
and Figure 16).
OUTPUT
INPUT
0
VOL
VOH
+VH
2
–VH
2
05915-015
ADCMP603 dispersion is typically < 2 ns as the overdrive varies
from 10 mV to 125 mV. This specification applies to both
positive and negative signals because the device has very closely
matched delays for both positive-going and negative-going
inputs.
Figure 17. Comparator Hysteresis Transfer Function
Q/Q OUTPUT
INPUT VOLTAGE
500mV OVERDRIVE
10mV OVERDRIVE
DISPERSION
V
N
± V
OS
05915-013
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. One limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance and induce
oscillation in some cases.
Figure 15. Propagation Delay—Overdrive Dispersion
ADCMP603
Rev. 0 | Page 12 of 16
05915-026
50 150 250 350 450 550 650
HYSTERESIS (mV)
HYSTERESIS RESISTOR (kΩ)
1
10
100
1000
V
CC
= 5.5V
V
CC
= 2.5V
The ADCMP603 comparator offers a programmable hysteresis
feature that can significantly improve accuracy and stability.
Connecting an external pull-down resistor or a current source
from the LE/HYS pin to GND varies the amount of hysteresis in
a predictable, stable manner. Leaving the LE/HYS pin
disconnected or driving it high removes the hysteresis. The
maximum hysteresis that can be applied using this pin is
approximately 160 mV. Figure 18 illustrates the amount of
hysteresis applied as a function of the external resistor value,
and Figure 9 illustrates hysteresis as a function of the current.
The hysteresis control pin appears as a 1.25 V bias voltage seen
through a series resistance of 7 kΩ ± 20% throughout the hysteresis
control range. The advantages of applying hysteresis in this manner
are improved accuracy, improved stability, reduced component
count, and maximum versatility. An external bypass capacitor is
not recommended on the HYS pin because it impairs the latch
function and often degrades the jitter performance of the device.
As described in the Using/Disabling the Latch Feature section,
hysteresis control need not compromise the latch function.
Figure 18. Hysteresis vs. R Control Resistor
HYS
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PC Board
design practice, as discussed in the Optimizing Performance
section, these comparators should be stable at any input slew
rate with no hysteresis. Broadband noise from the input stage is
observed in place of the violent chattering seen with most other
high speed comparators. With additional capacitive loading or
poor bypassing, more persistent oscillations are seen. This
oscillation is due to the high gain bandwidth of the comparator
in combination with feedback parasitics in the package and PC
board. In many applications, chattering is not harmful since the
first cycle of the oscillation occurs close to V
CROSSOVER BIAS POINT
In both op amps and comparators, rail-to-rail inputs of this type
have a dual front-end design. Certain devices are active near the
VCC rail and others are active near the VEE rail. At some predeter-
mined point in the common-mode range, a crossover occurs. At
this point, typically VCC/2, the direction of the bias current reverses
and the measured offset voltages and currents change. OS.
The ADCMP603 slightly elaborates on this scheme. Crossover
points can be found at approximately 0.8 V and 1.6 V.
ADCMP603
Rev. 0 | Page 13 of 16
TYPICAL APPLICATION CIRCUITS
ADCMP603
OUTPUT
+
–
5
V
0.1µF
10kΩ
10kΩ
INPUT
V
REF
05915-020
0.02µF
LE/HYS
ADCMP603
CMOS
OUTPUT
0.1µF
2.5V TO 5
V
0.1µF
2kΩ
2kΩ
INPUT
05915-017
Figure 22. Duty Cycle to Differential Voltage Converter
Figure 19. Self-Biased, 50% Slicer
ADCMP603
2.5V TO 5
V
10kΩ
LE/HYS
DIGITAL
INPUT
HYSTERESIS
CURRENT
74 AHC
1G07
0
5915-022
ADCMP603
CMOS
V
DD
2.5V TO 5V
100ΩLVDS
05915-018
CMOS
OUTPUT
Figure 23. Hysteresis Adjustment with Latch
Figure 20. LVDS-to-CMOS Receiver
CMOS
PWM
OUTPUT
ADCMP603
2.5
V
INPUT
1.25V
REF
INPUT
1.25V
±
50m
V
LE/HYS
ADCMP601
82pF
10kΩ
10kΩ
100kΩ
10kΩ
05915-021
LE/HYS
ADCMP603
5
V
150pF
10kΩ
150kΩ
10kΩ
150kΩ
CONTROL
VOLTAGE
0V TO 2.5V
05915-019
OUTPUT
Figure 24. Oscillator and Pulse-Width Modulator
Figure 21. Voltage-Controlled Oscillator
ADCMP603
2
Rev. 0 | Page 14 of 16
OUTLINE DIMENSIONS
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1
EXCEPT FOR EXPOSED PAD DIMENSION.
1
0.50
BSC
0.60 MAX PIN 1
INDICATOR
0.75
0.55
0.35
0.25 MIN
0.45
TOP
VIEW
12° MAX 0.80 MAX
0.65 TYP
PIN 1
INDICATOR
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
*1.45
1.30 SQ
1.15
12
4
10
6
7
9
3
2.75
BSC SQ
3.00
BSC SQ
2
5
8
11
COPLANARITY
0.08
EXPOSED PAD
(BOTTOM VIEW)
SEATING
PLANE
Figure 25. 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-12-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
ADCMP603BCPZ-WP −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-12-1 G0D
1
ADCMP603BCPZ-R2 −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-12-1 G0D
1
ADCMP603BCPZ-R7 −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-12-1 G0D
1
Z = Pb-free part.
1
ADCMP603
Rev. 0 | Page 15 of 16
NOTES
ADCMP603
2
Rev. 0 | Page 16 of 16
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05915-0-10/06(0)
