REV. B
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Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
ADG528A/ADG529A
CMOS Latched
4-/8-Channel Analog Multiplexers
FEATURES
44 V Supply Maximum Rating
VSS to VDD Analog Signal Range
Single-/Dual-Supply Specifications
Wide Supply Ranges (10.8 V to 16.5 V)
Microprocessor Compatible (100 ns WR Pulse)
Extended Plastic Temperature Range
(–40°C to +85°C)
Low Leakage (20 pA typ)
Low Power Dissipation (28 mW max)
Available in 18-Lead DIP/SOIC and 20-Lead PLCC Packages
Superior Alternative to:
DG528
DG529
FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The ADG528A and ADG529A are CMOS monolithic analog
multiplexers with eight channels and four dual channels, respec-
tively. On-chip latches facilitate microprocessor interfacing. The
ADG528A switches one of eight inputs to a common output,
depending on the state of three binary addresses and an enable
input. The ADG529A switches one of four differential inputs to
a common differential output, depending on the state of two
binary addresses and an enable input. Both devices have TTL
and 5 V CMOS logic-compatible digital inputs.
The ADG528A and ADG529A are designed on an enhanced
LC
2
MOS process, which gives an increased signal capability of
V
SS
to V
DD
and enables operation over a wide range of supply
voltages. The devices can comfortably operate anywhere in the
10.8 V to 16.5 V single- or dual-supply range. These multiplex-
ers also feature high switching and low R
ON
.
PRODUCT HIGHLIGHTS
1. Single-/dual-supply specifications with a wide tolerance.
The devices are specified in the 10.8 V to 16.5 V range for
both single- and dual-supplies.
2. Easily Interfaced
The ADG528A and ADG529A can be easily interfaced with
microprocessors. The WR signal latches the state of the
address control lines and the enable line. The RS signal
clears both the address and enable data in the latches result-
ing in no output (all switches off). RS can be tied to the
microprocessor reset pin.
3. Extended Signal Range
The enhanced LC
2
MOS processing results in a high breakdown
and an increased analog signal range of V
SS
to V
DD
.
4. Break-Before-Make Switching
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
5. Low Leakage
Leakage currents in the range of 20 pA make these multiplexers
suitable for high precision circuits.
REV. B–2–
ADG528A/ADG529A–SPECIFICATIONS
DUAL SUPPLY
ADG528A ADG528A ADG528A
ADG529A ADG529A ADG529A
K Version B Version T Version
–40°C to –40°C to –55°C to
Parameter +25°C+85°C+25°C+85°C+25°C+125°CUnits Comments
ANALOG SWITCH
Analog Signal Range V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V min
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V max
R
ON
280 280 280 Ω typ –10 V ≤ V
S
≤ +10 V, I
DS
= 1 mA;
Test Circuit 1
450 600 450 600 450 600 Ω max
300 400 300 400 Ω max V
DD
= 15 V (±10%), V
SS
= –15 V (±10%)
300 400 Ω max V
DD
= 15 V (±5%), V
SS
= –15 V (±5%)
R
ON
Drift 0.6 0.6 0.6 %/°C typ –10 V ≤ V
S
≤ +10 V, I
DS
= 1 mA
R
ON
Match 5 5 5 % typ –10 V ≤ V
S
≤ +10 V, I
DS
= 1 mA
I
S
(OFF), Off Input
Leakage 0.02 0.02 0.02 nA typ V1 = ±10 V, V2 = ⫿10 V; Test Circuit 2
150 150 150 nA max
I
D
(OFF), Off Input
Leakage 0.04 0.04 0.04 nA typ V1 = ±10 V, V2 = ⫿10 V; Test Circuit 3
ADG528A 1 100 1 100 1 100 nA max
ADG529A 1 50 1 50 1 50 nA max
I
D
(ON), On Channel
Leakage 0.04 0.04 0.04 nA typ V1 = ±10 V, V2 = ⫿10 V; Test Circuit 4
ADG528A 1 100 1 100 1 100 nA max
ADG529A 1 50 1 50 1 50 nA max
I
DIFF
, Differential Off
Output Leakage
(ADG529A only) 25 25 25 nA max V1 = ±10 V, V2 = ⫿10 V; Test Circuit 5
DIGITAL CONTROL
V
INH
, Input High Voltage 2.4 2.4 2.4 V min
V
INL
, Input Low Voltage 0.8 0.8 0.8 V max
I
INL
or I
INH
111µA max V
IN
= 0 to V
DD
C
IN
Digital Input
Capacitance 8 8 8 pF max
DYNAMIC CHARACTERISTICS
1
t
TRANSITION
200 200 200 ns typ V1 = ±10 V, V2 = ⫿10 V; Test Circuit 6
300 400 300 400 300 400 ns max
t
OPEN
50 50 50 ns typ Test Circuit 7
25 10 25 10 25 10 ns min
t
ON
(EN, WR)200 200 200 ns typ Test Circuits 8 and 9
300 400 300 400 300 400 ns max
t
OFF
(EN, RS)200 200 200 ns typ Test Circuits 8 and 10
300 400 300 400 300 400 ns max
t
W
Write Pulse Width 100 120 100 120 100 130 ns min See Figure 1
t
S
Address,
Enable Setup Time 100 100 100 ns min See Figure 1
t
H
, Address,
Enable Hold Time 10 10 10 ns min See Figure 1
t
RS
Reset Pulse Width 100 100 100 ns min See Figure 2
OFF Isolation 68 68 68 dB typ V
EN
= 0.8 V, R
L
= 1 kΩ, C
L
= 15 pF,
50 50 50 dB min V
S
= 7 V rms, f = 100 kHz
C
S
(OFF) 5 5 5 pF typ V
EN
= 0.8 V
C
D
(OFF)
ADG528A 22 22 22 pF typ V
EN
= 0.8 V
ADG529A 11 11 11 pF typ
Q
INJ
, Charge Injection 4 4 4 pC typ R
S
= 0 Ω, V
S
= 0 V; Test Circuit 11
(VDD = +10.8 V to +16.5 V, VSS = –10.8 V to –16.5 V, unless otherwise noted.)
REV. B
ADG528A/ADG529A
–3–
ADG528A ADG528A ADG528A
ADG529A ADG529A ADG529A
K Version B Version T Version
–40°C to –40°C to –55°C to
Parameter +25°C+85°C+25°C+85°C+25°C+125°CUnits Comments
POWER SUPPLY
I
DD
0.6 0.6 0.6 mA typ V
IN
= V
INL
or V
INH
1.5 1.5 1.5 mA max
I
SS
20 20 20 µA typ V
IN
= V
INL
or V
INH
0.2 0.2 0.2 mA max
Power Dissipation 10 10 10 mW typ
2.8 2.8 2.8 mW max
NOTE
1
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
SINGLE SUPPLY
ADG528A ADG528A ADG528A
ADG529A ADG529A ADG529A
K Version B Version T Version
–40°C to –40°C to –55°C to
Parameter +25°C+85°C+25°C+85°C+25°C+125°CUnits Comments
ANALOG SWITCH
Analog Signal Range GND GND GND GND GND GND V min
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V max
R
ON
500 500 500 Ω typ GND ≤ V
S
≤ +10 V, I
DS
= 0.5 mA;
Test Circuit 1
700 1000 700 1000 700 1000 Ω max
R
ON
Drift 0.6 0.6 0.6 %/°C typ GND ≤ V
S
≤ +10 V, I
DS
= 0.5 mA
R
ON
Match 5 5 5 % typ GND ≤ V
S
≤ +10 V, I
DS
= 0.5 mA
I
S
(OFF), Off Input
Leakage 0.02 0.02 0.02 nA typ V1 = +10 V/GND, V2 = GND/+10 V;
150150 1 50 nA max Test Circuit 2
I
D
(OFF), Off Input
Leakage 0.04 0.04 0.04 nA typ V1 = +10 V/GND, V2 = GND/+10 V;
ADG528A 1 100 1 100 1 100 nA max Test Circuit 3
ADG529A 1 50 1 50 1 50 nA max
I
D
(ON), On Channel
Leakage 0.04 0.04 0.04 nA typ V1 = +10 V/GND, V2 = GND/+10 V;
ADG528A 1 100 1 100 1 100 nA max Test Circuit 4
ADG529A 1 50 1 50 1 50 nA max
I
DIFF
, Differential Off
Output Leakage
(ADG529A only) 25 25 25 nA max V1 = +10 V/GND, V2 = GND/+10 V;
Test Circuit 5
DIGITAL CONTROL
V
INH
, Input High Voltage 2.4 2.4 2.4 V min
V
INL
, Input Low Voltage 0.8 0.8 0.8 V max
I
INL
or I
INH
111µA max V
IN
= 0 to V
DD
C
IN
Digital Input
Capacitance 8 8 8 pF max
DYNAMIC CHARACTERISTICS
1
t
TRANSITION
300 300 300 ns typ V1 = +10 V/GND, V2 = GND/+10 V;
Test Circuit 6
450 600 450 600 450 600 ns max
t
OPEN
50 50 50 ns typ Test Circuit 7
25 10 25 10 25 10 ns min
t
ON
(EN, WR)250 250 250 ns typ Test Circuits 8 and 9
450 600 450 600 450 600 ns max
t
OFF
(EN, RS)250 250 250 ns typ Test Circuits 8 and 10
450 600 450 600 450 600 ns max
t
W
Write Pulse Width 100 120 100 120 100 130 ns min See Figure 1
(VDD = +10.8 V to +16.5 V, VSS = GND = 0 V, unless otherwise noted.)
REV. B–4–
ADG528A/ADG529A
ADG528A ADG528A ADG528A
ADG529A ADG529A ADG529A
K Version B Version T Version
–40°C to –40°C to –55°C to
Parameter +25°C+85°C+25°C+85°C+25°C+125°CUnits Comments
DYNAMIC CHARACTERISTICS
1
(Cont’d)
t
S
Address,
Enable Setup Time 100 100 100 ns min See Figure 1
t
H
Address,
Enable Hold Time 10 10 10 ns min See Figure 1
t
RS
Reset Pulse Width 100 100 100 ns min See Figure 2
OFF Isolation 68 68 68 dB typ V
EN
= 0.8 V, R
L
= 1 kΩ, C
L
= 15 pF,
50 50 50 dB min V
S
= 3.5 V rms, f = 100 kHz
C
S
(OFF) 5 5 5 pF typ V
EN
= 0.8 V
C
D
(OFF)
ADG528A 22 22 22 pF typ V
EN
= 0.8 V
ADG529A 11 11 11 pF typ
Q
INJ
, Charge Injection 4 4 4 pC typ R
S
= 0 Ω, V
S
= 0 V; Test Circuit 11
POWER SUPPLY
I
DD
0.6 0.6 0.6 mA typ V
IN
= V
INL
or V
INH
1.5 1.5 1.5 mA max
Power Dissipation 11 10 10 mW typ
25 25 25 mW max
NOTE
1
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
REV. B
ADG528A/ADG529A
–5–
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
1
ADG528AKN –40°C to +85°CPDIP N-18
ADG528AKP –40°C to +85°CPLCC P-20A
ADG528AKP-REEL –40°C to +85°CPLCC P-20A
ADG528ABQ –40°C to +85°CCERDIP Q-18
ADG528ATQ –55°C to +125°CCERDIP Q-18
ADG528ABCHIPS DIE
ADG528ATCHIPS DIE
ADG529AKN –40°C to +85°CPDIP N-18
ADG529AKP –40°C to +85°CPLCC P-20A
ADG529AKRW –40°C to +85°CSOIC RW-18
ADG529AKRW-REEL –40°C to +85°CSOIC RW-18
ADG529AKRW-REEL7 –40°C to +85°CSOIC RW-18
ADG529ABQ –40°C to +85°CCERDIP Q-18
ADG529ATQ –55°C to +125°CCERDIP Q-18
ADG529ABCHIPS DIE
ADG529ATCHIPS DIE
NOTES
1
N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip; RW = SOIC.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C, unless otherwise noted)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V
Analog Inputs
2
Voltage at S, D . . . . . . . . . V
SS
– 2 V to V
DD
+ 2 V or 20 mA,
whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . 20 mA
Pulsed Current, S or D
1 ms duration, 10% Duty Cycle . . . . . . . . . . . . . . . 40 mA
Digital Inputs
1
Voltage at A, EN, WR, RS . . . . . . V
SS
– 4 V to V
DD
+ 4 V or
20 mA, whichever Occurs First
Power Dissipation (Any Package)
Up to +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
Commercial (K Version) . . . . . . . . . . . . . . . –40°C to +85°C
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Overvoltage at A, EN, WR, RS, S or D will be clamped by diodes. Current should
be limited to the maximum rating above.
PIN CONFIGURATIONS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG528A/ADG529A features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PLCCDIP/SOIC
REV. B–6–
ADG528A/ADG529A
TRUTH TABLES
A2 A1 A0 EN WR RS ON SWITCH PAIR
XXXX 1Retains Previous Switch Condition
XXXX X 0 NONE (Address and Enable
Latches Cleared)
XXX0 0 1 NONE
0001 0 11
0011 0 12
0101 0 13
0111 0 14
1001 0 15
1011 0 16
1101 0 17
1111 0 18
X = Don’t Care ADG528A
A1 A0 EN WR RS ON SWITCH PAIR
XXX 1Retains Previous Switch Condition
XXX X0NONE (Address and Enable Latches
Cleared)
XX0 01NONE
001 0 1 1
011 0 1 2
101 0 1 3
111 0 1 4
X = Don’t Care ADG529A
TIMING DIAGRAMS
Figure 1.
Figure 2.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; there-
fore, while WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of WR.
Figure 2 shows the Reset Pulse Width, t
RS
, and Reset Turn-off
Time, t
OFF
(RS).
Note: All digital input signals rise and fall times measured from
10% to 90% of 3 V. t
R
= t
F
= 20 ns.
REV. B
Typical Performance Characteristics–ADG528A/ADG529A
–7–
The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V.
TPC 1. R
ON
as a Function of V
D
(V
S
): Dual Supply
Voltage, T
A
= +25
°
C
TPC 2. Leakage Current as a Function of Temperature
(Note: Leakage Currents Reduce as the Supply
Voltages Reduce)
TPC 3. R
ON
as a Function of V
D
(V
S
): Single Supply
Voltage, T
A
= +25
°
C
TPC 4. Trigger Levels vs. Power Supply Voltage,
Dual or Single Supply, T
A
= +25
°
C
TPC 5. t
TRANSITION
vs. Supply Voltage: Dual and
Single Supplies, T
A
= +25
°
C
(Note: For V
DD
and |V
SS
| < 10 V; V1 = V
DD
/V
SS
, V2 =
V
SS
/V
DD
. See Test Circuit 6)
TPC 6. I
DD
vs. Supply Voltage: Dual or Single
Supply, T
A
= +25
°
C
REV. B–8–
ADG528A/ADG529A
Test Circuits
Test Circuit 1. R
ON
Test Circuit 2. I
S
(OFF)
Test Circuit 3. I
D
(OFF)
Test Circuit 4. I
D
(ON)
Test Circuit 5. I
DIFF
Test Circuit 6. Switching Time of Multiplexer, t
TRANSITION
Test Circuit 7. Break-Before-Make Delay, t
OPEN
REV. B
ADG528A/ADG529A
–9–
Test Circuit 8. Enable Delay, t
ON
(EN), t
OFF
(EN)
Test Circuit 9. Write Turn-On Time, t
ON
(
WR
)
Test Circuit 10. Reset Turn-Off Time, t
OFF
(
RS
)
Test Circuit 11. Charge Injection
REV. B–10–
ADG528A/ADG529A
TERMINOLOGY
R
ON
Ohmic resistance between terminals D and S
R
ON
Match Difference between the RON of any two channels
R
ON
Drift Change in RON versus temperature
I
S
(OFF) Source terminal leakage current when the switch
is off.
I
D
(OFF) Drain terminal leakage current when the switch is
off.
I
D
(ON) Leakage current that flows from the closed switch
into the body.
V
S
(V
D
)Analog voltage on terminal S or D
C
S
(OFF) Channel input capacitance for “OFF” condition
C
D
(OFF) Channel output capacitance for “OFF” condition
C
IN
Digital input capacitance
t
ON
(EN) Delay time between the 50% and 90% points of
the digital input and switch “ON” condition.
t
OFF
(EN) Delay time between the 50% and 10% points of
the digital input and switch “OFF” condition
t
TRANSITION
Delay time between the 50% and 90% points of
the digital inputs and switch “ON” condition
when switching from one address state to another.
t
OPEN
“OFF” time measured between 50% points of
both switches when switching from one address
state to another
V
INL
Maximum input voltage for Logic “0”
V
INH
Minimum input voltage for Logic “1”
I
INL
(I
INH
)Input current of the digital input
V
DD
Most positive voltage supply
V
SS
Most negative voltage supply
I
DD
Positive supply current
I
SS
Negative supply current
OUTLINE DIMENSIONS
18-Lead Plastic Dual In-Line Package [PDIP]
(N-18)
Dimensions shown in inches and (millimeters)
SEATING
PLANE
0.015 (0.38) MIN
0.180 (4.57)
MAX
0.022 (0.558)
0.014 (0.356)
0.150 (3.81)
0.110 (2.79) 0.100
(2.54)
BSC
0.060 (1.52)
0.045 (1.14)
18
19
10
0.885 (22.48)
0.845 (21.46) 0.295 (7.49)
0.275 (6.99)
0.015 (0.381)
0.008 (0.203)
0.325 (8.26)
0.300 (7.62)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AD
0.180 (4.57)
MAX
20-Lead Plastic Leaded Chip Carrier [PLCC]
(P-20A)
Dimensions shown in inches and (millimeters)
0.020 (0.50)
R
BOTTOM
VIEW
(PINS UP)
0.021 (0.53)
0.013 (0.33)
0.330 (8.38)
0.290 (7.37)
0.032 (0.81)
0.026 (0.66)
0.056 (1.42)
0.042 (1.07) 0.20 (0.51)
MIN
0.120 (3.04)
0.090 (2.29)
3
4
19
18
8
9
14
13
TOP VIEW
(PINS DOWN)
0.395 (10.02)
0.385 (9.78) SQ
0.356 (9.04)
0.350 (8.89) SQ
0.048 (1.21)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
R
0.050
(1.27)
BSC
0.180 (4.57)
0.165 (4.19)
0.040 (1.01)
0.025 (0.64) R
COMPLIANT TO JEDEC STANDARDS MO-047AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. B
ADG528A/ADG529A
–11–
OUTLINE DIMENSIONS
18-Lead Standard Small Outline Package [SOIC]
Wide Body
(RW-18)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AB
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
1.27
(0.0500)
BSC
18 10
9
1
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
11.75 (0.4626)
11.35 (0.4469)
8ⴗ
0ⴗ
0.75 (0.0295)
0.25 (0.0098) ⴛ 45ⴗ
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
18-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-18)
Dimensions shown in inches and (millimeters)
18
19
10
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005
(0.13)
MIN
0.098 (2.49)
MAX
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200
(5.08)
MAX
0.960 (24.38) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
15
0
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. B
C03337–0–10/04(B)
–12–
ADG528A/ADG529A
Revision History
Location Page
10/04—Data Sheet Changed from Rev. A to Rev. B
Deleted 20-Lead LCC package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SOIC added to DIP PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
