General Description
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
low-capacitance ±30kV ESD-protection diode arrays
are designed to protect sensitive electronics attached
to communication lines. Each channel consists of a pair
of diodes that steer ESD current pulses to VCC or GND.
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
protect against ESD pulses up to ±15kV Human Body
Model (HBM) and ±30kV Air-Gap Discharge, as speci-
fied in IEC 61000-4-2. These devices have a 6pF on-
capacitance per channel, making them ideal for use on
high-speed data I/O interfaces.
The MAX13204E is a quad-ESD structure designed for
Ethernet and FireWire®applications. The MAX13202E/
MAX13206E/MAX13208E are 2-channel, 6-channel,
and 8-channel devices. They are designed for cell-
phone connectors and SVGA video connections.
These devices are available in 6-, 8-, and 10-pin µDFN
packages and are specified over the -40°C to +125°C
automotive operating temperature range.
Applications
USB Ethernet
USB 2.0 Video
PDAs Cell Phones
FireWire
Features
♦High-Speed Data-Line ESD Protection
±15kV—Human Body Model
±30kV—IEC 61000-4-2, Air-Gap Discharge
♦Tiny µDFN Package
MAX13202E (1mm x 1.5mm)
MAX13204E (2mm x 2mm)
MAX13206E (2mm x 2mm)
MAX13208E (2mm x 2mm)
♦Low 6pF Input Capacitance
♦Low 1nA (max) Leakage Current
♦+0.9V to +16V Supply Voltage Range
MAX13202E/MAX13204E/MAX13206E/MAX13208E
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3855; Rev 1; 4/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Note: All devices are specified over the -40°C to +125°C auto-
motive operating temperature range.
+Denotes lead-free package
PART
PIN-
PKG
PROTECTED
I/O PORTS
TOP
MARK
PKG
CODE
MAX13202EALT+
6
µDFN
2BV
L611-1
MAX13204EALT+
6
µDFN
4
AAO
L622-1
MAX13206EALA+
8
µDFN
6AAL
L822-1
MAX13208EALB+
10
µDFN
8
AAD
L1022-1
Pin Configurations
FireWire is a registered trademark of Apple Computer, Inc.
MAX13202E
MAX13204E
MAX13206E
MAX13208E
PROTECTED
CIRCUIT
0.1µF
0.1µF
I/0_I/0
VCC
VCC
Typical Operating Circuit
123
654
MAX13202E
N.C.N.C.
I/O2
I/O1
GND
VCC
µDFN
(1mm x 1.5mm)
+
Pin Configurations continued at end of data sheet.
MAX13202E/MAX13204E/MAX13206E/MAX13208E
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = +5V ±5%, TA= TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: Limits over temperature are guaranteed by design, not production tested.
Note 2: Idealized clamp voltages (L1 = L2 = L3 = 0) (Figure 1); see the Applications Information section for more information.
Note 3: Guaranteed by design. Not production tested.
VCC to GND............................................................-0.3V to +18V
I/O_ to GND................................................-0.3V to (VCC + 0.3V)
Continuous Power Dissipation (TA= +70°C)
6-Pin, 1mm x 1.5mm µDFN (derate 2.1mW/°C
above +70°C)................................................................168mW
6-Pin, 2mm x 2mm µDFN (derate 4.5mW/°C
above +70°C)................................................................358mW
8-Pin, 2mm x 2mm µDFN (derate 4.8mW/°C
above +70°C)................................................................381mW
10-Pin, 2mm x 2mm µDFN (derate 5.0mW/°C
above +70°C)................................................................403mW
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature .....................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage VCC 0.9
16.0
V
Supply Current ICC 1100 nA
Diode Forward Voltage VFIF = 10mA
0.65 0.95
V
Positive transients
VCC + 25
TA = +25°C, ±15kV,
Human Body Model,
IF = 10A
Negative transients
-25
Positive transients
VCC + 80
TA = +25°C, ±14kV,
Contact Discharge
(IEC 61000-4-2), IF = 42A Negative transients
-80
Positive transients
VCC + 120
Channel Clamp Voltage
(Note 2) VC
TA = +25°C, ±30kV,
Air-Gap Discharge
(IEC 61000-4-2), IF = 90A Negative transients -120
V
TA = -40°C to +50°C -1 +1 nA
Channel Leakage Current
(Note 3) TA = -40°C to +125°C -1 +1 µA
Channel Input Capacitance
VCC = 5V, bias of VCC/2, f = 1MHz (Note 3) 6 7 pF
ESD PROTECTION
Human Body Model
±15
kV
MAX13204E/MAX13206E/MAX13208E
±14
IEC 61000-4-2
Contact Discharge MAX13202E
±12
kV
IEC 61000-4-2
Air-Gap Discharge
±30
kV
MAX13202E/MAX13204E/MAX13206E/MAX13208E
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
_______________________________________________________________________________________ 3
Typical Operating Characteristics
(VCC = +5V, TA = +25°C, unless otherwise noted.)
Pin Description
PIN
MAX13202E
MAX13204E
MAX13206E
MAX13208E
NAME
FUNCTION
1111V
CC Power-Supply Input. Bypass VCC to GND with a 0.1µF ceramic capacitor.
Place the capacitor as close as possible to the device.
2, 5 — — — N.C. No Connection. Not internally connected.
3, 4 2–5 2–7 2–9 I/O_ ESD-Protected Channel
66810 GND Ground
TEMPERATURE (°C)
SUPPLY CURRENT (nA)
SUPPLY CURRENT
vs. TEMPERATURE
100
10
1
0.1
0.01
0.001
-40 -25 -10 5 20 35 50 65 80 95 110 125
MAX13204E//6E/8E toc01
VCC = 12V
VCC = 5V VCC = 3.3V
1.1
1.0
0.9
0.8
0.7
30 9050 70 110 130 150
CLAMP VOLTAGE
vs. DC CURRENT
MAX13204E//6E/8E toc02
DC CURRENT (mA)
CLAMP VOLTAGE (V)
I/O TO VCC
I/O TO GND
4
7
6
5
8
9
10
11
12
13
14
021345
INPUT CAPACITANCE
vs. INPUT VOLTAGE
MAX13204E/6E/8E toc04
INPUT VOLTAGE (V)
INPUT CAPCITANCE (pF)
VCC = 3.3V
VCC = 5.0V
0
2
1
5
4
3
6
7
9
8
10
0231456789101211
MAX13204E/6E/8E toc05
INPUT VOLTAGE (V)
INPUT CAPACITANCE (pF)
VCC = 12V
INPUT CAPACITANCE
vs. INPUT VOLTAGE
TEMPERATURE (°C)
I/O LEAKAGE CURRENT (nA)
I/O LEAKAGE CURRENT
vs. TEMPERATURE
10
1
0.1
0.01
0.001
-40 -25 -10 5 20 35 50 65 80 95 110 125
MAX13204E//6E/8E toc03
VCC = 12V
VCC = 5V
VCC = 3.3V
Detailed Description
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
are diode arrays designed to protect sensitive electron-
ics against damage resulting from ESD conditions or
transient voltages. The low input capacitance makes
these devices ideal for high-speed data lines. The
MAX13202E/MAX13204E/MAX13206E/MAX13208E
protect two, four, six, and eight channels, respectively.
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
are designed to work in conjunction with a device’s
intrinsic ESD protection. The MAX13202E/MAX13204E/
MAX13206E/MAX13208E limit the excursion of the ESD
event to below ±25V peak voltage when subjected to the
Human Body Model waveform. When subjected to the
IEC 61000-4-2 waveform, the peak voltage is limited to
±80V (Contact Discharge) and ±120V (Air-Gap
Discharge). The device that is being protected by the
MAX13202E/MAX13204E/ MAX13206E/MAX13208E
must be able to withstand these peak voltages plus any
additional voltage generated by the parasitic board.
Applications Information
Design Considerations
Maximum protection against ESD damage results from
proper board layout (see the Layout Recommendations
section and Figure 2). A good layout reduces the para-
sitic series inductance on the ground line, supply line,
and protected signal lines.
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
ESD diodes clamp the voltage on the protected lines
during an ESD event and shunt the current to GND or
VCC. In an ideal circuit, the clamping voltage, VC, is
defined as the forward voltage drop, VF, of the protection
diode plus any supply voltage present on the cathode.
For positive ESD pulses:
VC= VCC + VF
For negative ESD pulses:
VC= -VF
In reality, the effect of the parasitic series inductance
on the lines must also be considered (Figure 1).
For positive ESD pulses:
For negative ESD pulses:
where IESD is the ESD current pulse.
VV Lx
dI
dt Lx
dI
dt
CFD ESD ESD
() ()
=− +
+
()
213
VV V Lx
dI
dt Lx
dI
dt
CCCFD ESD ESD
() ()
=+ +
+
()
112
MAX13202E/MAX13204E/MAX13206E/MAX13208E
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
4_______________________________________________________________________________________
L1
PROTECTED
LINE
L3
D2
GROUND RAIL
POSITIVE SUPPLY RAIL
I/O_
D1
L2
Figure 1. Parasitic Series Inductance
VCC
PROTECTED LINE
NEGATIVE ESD
CURRENT
PULSE
PATH TO
GROUND
PROTECTED
CIRCUIT
GND
D1
I/O_
VC
D2
L1
L3
L2
Figure 2. Layout Considerations
MAX13202E/MAX13204E/MAX13206E/MAX13208E
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
_______________________________________________________________________________________ 5
During an ESD event, the current pulse rises from zero
to peak value in nanoseconds (Figure 3). For example,
in a ±15kV IEC-61000-4-2 Air-Gap Discharge ESD
event, the pulse current rises to approximately 45A in
1ns (di/dt = 45 x 109). An inductance of only 10nH adds
an additional 450V to the clamp voltage. An inductance
of 10nH represents approximately 0.5in of board trace.
Regardless of the device’s specified diode clamp volt-
age, a poor layout with parasitic inductance significantly
increases the effective clamp voltage at the protected
signal line.
A low-ESR 0.1µF capacitor must be used between VCC
and GND. This bypass capacitor absorbs the charge
transferred by a +14kV (MAX13204E/MAX13206E/
MAX13208E) and ±12kV (MAX13202E) IEC61000-4-2
Contact Discharge ESD event.
Ideally, the supply rail (VCC) would absorb the charge
caused by a positive ESD strike without changing its
regulated value. In reality, all power supplies have an
effective output impedance on their positive rails. If a
power supply’s effective output impedance is 1Ω, then
by using V = I ×R, the clamping voltage of VCincreas-
es by the equation VC= IESD x ROUT. An ±8kV
IEC 61000-4-2 ESD event generates a current spike of
24A, so the clamping voltage increases by VC= 24A ×
1Ω, or VC= 24V. Again, a poor layout without proper
bypassing increases the clamping voltage. A ceramic
chip capacitor mounted as close to the MAX13202E/
MAX13204E/MAX13206E/MAX13208E VCC pin is the
best choice for this application. A bypass capacitor
should also be placed as close to the protected device
as possible.
±30kV ESD Protection
ESD protection can be tested in various ways. The
MAX13202E/MAX13204E/MAX13206E/MAX13208E are
characterized for protection to the following limits:
•±15kV using the Human Body Model
•±14kV (MAX13204E/MAX13206E/MAX13208E) and
±12kV (MAX13202E) using the Contact Discharge
method specified in IEC 61000-4-2
•±30kV using the IEC 61000-4-2 Air-Gap Discharge
method
ESD Test Conditions
ESD performance depends on a number of conditions.
Contact Maxim for a reliability report that documents
test setup, methodology, and results.
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1MΩ
RD
1.5kΩ
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 4. Human Body ESD Test Model
IP 100%
90%
36.8%
tRL TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
0
AMPERES
Figure 5. Human Body Model Current Waveform
tR = 0.7ns to 1ns 30ns
60ns
t
100%
90%
10%
I
PEAK
I
Figure 3. IEC 61000-4-2 ESD Generator Current Waveform
MAX13202E/MAX13204E/MAX13206E/MAX13208E
Human Body Model
Figure 4 shows the Human Body Model, and Figure 5
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the device through a
1.5kΩresistor.
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and
performance of finished equipment. The MAX13202E/
MAX13204E/MAX13206E/MAX13208E help users
design equipment that meets Level 4 of IEC 61000-4-2.
The main difference between tests done using the
Human Body Model and IEC 61000-4-2 is higher peak
current in IEC 61000-4-2. Because series resistance is
lower in the IEC 61000-4-2 ESD test model (Figure 6),
the ESD-withstand voltage measured to this standard is
generally lower than that measured using the Human
Body Model. Figure 3 shows the current waveform for
the ±8kV IEC 61000-4-2 Level 4 ESD Contact
Discharge test.
The Air-Gap Discharge test involves approaching the
device with a charged probe. The Contact Discharge
method connects the probe to the device before the
probe is energized.
Layout Recommendations
Proper circuit-board layout is critical to suppress ESD-
induced line transients. The MAX13202E/MAX13204E/
MAX13206E/MAX13208E clamp to ±120V; however, with
improper layout, the voltage spike at the device is much
higher. A lead inductance of 10nH with a 45A current
spike at a dv/dt of 1ns results in an ADDITIONAL 450V
spike on the protected line. It is essential that the layout
of the PC board follows these guidelines:
1) Minimize trace length between the connector or
input terminal, I/O_, and the protected signal line.
2) Use separate planes for power and ground to reduce
parasitic inductance and to reduce the impedance to
the power rails for shunted ESD current.
3) Ensure short ESD transient return paths to GND
and VCC.
4) Minimize conductive power and ground loops.
5) Do not place critical signals near the edge of the
PC board.
6) Bypass VCC to GND with a low-ESR ceramic capaci-
tor as close to VCC and ground terminals as possible.
7) Bypass the supply of the protected device to GND
with a low-ESR ceramic capacitor as close to the
supply pin as possible.
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
6_______________________________________________________________________________________
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
RC
50Ω to 100ΩRD
330Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 6. IEC 61000-4-2 ESD Test Model
Chip Information
PROCESS: BiCMOS
MAX13202E/MAX13204E/MAX13206E/MAX13208E
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
_______________________________________________________________________________________ 7
MAX13204E
VCC
GND
I/O1 I/O2 I/O3 I/O4I/O2
MAX13206E
MAX13208E
VCC
GND
I/O1 I/O2 I/O5 I/O6
I/O3 I/O4
GND
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
VCC
MAX13202E
VCC
GND
I/O1
Functional Diagrams
123
10 9 8
45
76
MAX13208E
I/O4
I/O3
I/O5
I/O6
I/O7
I/O8
I/O1
I/O2
GND
VCC
10 µDFN
(2mm x 2mm)
+
123
87
4
65
MAX13206E
I/O4
I/O3
I/O5
I/O6
I/O1
I/O2
GND
VCC
8 µDFN
(2mm x 2mm)
+
123
654
MAX13204E
I/O4I/O1
I/O3
I/O2
GND
VCC
6 µDFN
(2mm x 2mm)
+
Pin Configurations (continued)
MAX13202E/MAX13204E/MAX13206E/MAX13208E
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
8_______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
6L UDFN.EPS
-DRAWING NOT TO SCALE-
DOCUMENT CONTROL NO.APPROVAL
TITLE:
REV.
PACKAGE OUTLINE, 6L uDFN, 1.5x1.0x0.8mm
21-0147
2
2
D
2005 2006 2007 2008 2009 2010 2011 2012 2013 2014Calendar Year
Legend: Marked with bar Blank space - no bar required
06-11Payweek 12-17 18-23 24-29 30-35 36-41 42-47 48-51 52-05
TABLE 2 Translation Table for Payweek Binary Coding
TABLE 1 Translation Table for Calendar Year Code
Legend: Marked with bar Blank space - no bar required
MAX13202E/MAX13204E/MAX13206E/MAX13208E
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
©2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
6, 8, 10L UDFN.EPS
EVEN TERMINAL
L
C
ODD TERMINAL
L
C
L
e
L
A
e
E
D
PIN 1
INDEX AREA
b
e
A
b
N
SOLDER
MASK
COVERAGE
A A
1
PIN 1
0.10x45∞
LL1
(N/2 -1) x e)
XXXX
XXXX
XXXX
SAMPLE
MARKING
A1
A2
7
A
1
2
21-0164
PACKAGE OUTLINE,
6, 8, 10L uDFN, 2x2x0.80 mm
-DRAWING NOT TO SCALE-
COMMON DIMENSIONS
SYMBOL MIN. NOM.
A0.70 0.75
A1
D1.95 2.00
E1.95 2.00
L0.30 0.40
PKG. CODE N e b
PACKAGE VARIATIONS
L1
6L622-1 0.65 BSC 0.30±0.05
0.25±0.050.50 BSC8L822-1
0.20±0.030.40 BSC10L1022-1
2.05
0.80
MAX.
0.50
2.05
0.10 REF.
(N/2 -1) x e
1.60 REF.
1.50 REF.
1.30 REF.
A2
-
-DRAWING NOT TO SCALE-
A
2
2
21-0164
PACKAGE OUTLINE,
6, 8, 10L uDFN, 2x2x0.80 mm
0.15 0.20 0.25
0.020 0.025 0.035
