CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
PRELIMINARY
256/512/1K/4K/16K x36 Unidirectional
Synchronous FIFO w/ Bus Matching
Cypress Semiconductor Corporation • 3901 North First Street • Sa n Jose • CA 95134 • 40 8-943-2600
October 2
,
1998
Features
• High-speed, low-power , Unidirectional, first-in first-out
(FIFO) memories w/ bus m atching capabi lities
• 256x36 (CY7C43623)
• 512x36 (CY7C43633)
• 1Kx36 (CY7C43643)
• 4Kx36 (CY7C43663)
• 16Kx36 (CY7C43683)
• 0.35-micron CMOS for optimum speed/power
• High-speed 83-MHz operation (12 ns read/write cyc le
times)
• L ow po wer
—ICC= 100 mA
—ISB= 5 mA
• Fully asynchronous and simultaneous read and w rite
operation permitt ed
• Mailbox b ypass register for each FIFO
• P arallel and Seria l Programmab le Al most-Full and Al-
most-Empty flags
• Retransmit function
• Standard or FWFT mode user sel ectable
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Pin-compatible, feature enhanced, density upgrade to
IDT723623/33/43 fa mi ly
• Easily expandable in width and depth
Logic Block Diagram
Port-A
Control
Logic Port-B
Control
Logic
Mail 1
Register
Input
Register
Output
Register
Write
Pointer Read
Pointer
Status
Flag Logic
Programmable Flag
Offset Registers Timing
Mode
256/512/1K
4K/16K x36
Dual Ported
Memory
Mail 2
Register
FIFO,
Mail1
CLKA
CSA
W/RA
ENA
MBA
RT
MRS1
PRS
FF/IR
AF
SPM
FS0/SD
FS1/SEN
A0–35
MBF2
BE/FWFT
B0–35
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
EF/OR
AE
MBF1
Mail2
Reset
Logic
Bus Matching
36
36
MRS2
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
2
PRELIMINARY
CY7C43623
CY7C43633
CY7C43643
CY7C43663
CY7C43683
TQFP
Top View
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
FS0/SD
MRS2
FS1/SEN
GND
GND
MRS1
MBA
MBF2
NC
AF
VCC
PRS
FF/IR
CSA
ENB
W/RB
CSB
GND
NC
EF/OR
NC
AE
VCC
MBF1
MBB
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
B30
B26
B27
B28
B29
B31
GND
GND
B32
B33
B34
B35
VCC
VCC
CLKB
GND
SIZE
B16
B17
B18
B19
B20
B21
B22
B23
GND
BM
B24
B25
RT
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A2
B0
GND
A0
A1
VCC
SPM
A3
A4
A5
GND
A6
A7
A8
A9
B9
B8
B7
VCC
B6
GND
B5
B4
B3
B2
B1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
VCC
A29
GND
A30
A31
A32
A34
A35
GND
CLKA
ENA
W/RA
A12
A20
GND
A18
A19
A21
VCC
A22
GND
BE/FWFT
A23
A24
A25
A26
A27
A28
A33
72
71
70
69
68
67
66
65
B12
B10
B11
GND
B13
B14
B15
VCC
30
31
32
33
34
35
36
37
38
VCC
A10
A11
GND
A13
A14
A15
A16
A17
NC
Pin Configuration
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
3
PRELIMINARY
Functional Description
The CY7C436x3 is a monolithic, high-speed, low-power,
CMOS Unidirectional Synchronous (clocked) FIFO memory
which supports cloc k frequencies up to 83 MHz and has read
access times as fast as 9 ns. Two independent
256/512/1K/4K/16K x 36 dual-port SRAM FIFOs on board
each c hip buf f er d ata in opp osite direc tions . FIFO dat a o n P ort
B can be output in 36- bit, 18- bit, or 9-bit formats with a choice
of big- or little-endian configurations.
The CY7C436x3 is a synchronous (clocked) FIFO, meaning
each port employs a synchronous in ter face. All dat a transfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each por t are in-
dependent of one another and can be asynchronous or coin-
cident. The enables for each port are arranged to provide a
simple Unidirectional interface between microprocessors
and/or buses with synchronous control .
Commu nicati on betw een eac h port ma y b ypass th e FIFOs via
two mailbox registers. The mailbox registers’ width matches
the sel ected P ort B bu s width. Each mai lbox re gister has a f la g
(MBF1 and MBF2) to sign al when new mail has been stored.
Two kinds of reset are available on the CY7C436x3: Master
Reset and P arti al Reset . Master Rese t init ializ es t he read and
write point ers to the first location of the mem ory arr ay, config-
ures the FIFO for big- or little-endian byte arrangement and
selects serial flag programmi ng, paral lel flag programm ing, or
one of the three possible default flag offset settings, 8, 16, or
64. The FIFO also has a Master Reset pin, MRS1/MRS2.
Partial Reset also sets the read and write pointers to the first
location of the m emory. Unlike Master Reset, an y settings ex-
ist in g prior to P artia l Reset (i.e., pr ogrammi ng method a nd par-
tial flag default offsets) are retained. Partial Reset is useful
sinc e it permits f lushi ng of th e FIFO m emory witho ut chang in g
any configurat ion settings. The FIFO has its own i ndependent
P artial Reset pin, PRS.
The CY7C436x3 have two modes of operation: In the CY Stan-
dard Mode, the first word written to an empty FIFO is deposited
into t he m em ory array. A read oper ation is required to access
that word (along with all other words residing in memory). In
the First W ord Fall Through Mode
(FWFT), t he fi rst long-word
(36-bit wide) written to an empty FIFO appears automatically
on the outputs, no read operation required (nevertheless, ac-
cessing subsequent words does necessitate a form al read re-
quest). The state of the FWFT/STAN pin during FIFO opera-
tion det ermines t he m ode in use.
The FIFO has a com bined Empty/Output Ready f lag (EF/OR)
and a combi ned Full/Input Ready fl ag (FF/IR). The EF and FF
functions a re selected i n the CY Standard Mode. EF i ndicat es
whether the memory is full or not. The IR and OR funct ions are
selected in the First Word Fall Through Mode. IR indicates
whether or not the FIFO has available memory locations. OR
show s whether t he F IFO has dat a av ai labl e fo r readin g or not.
It marks the presence of valid data on the outputs.
The FIFO has a programm able Almost Empty flag (AE) and a
programmable Almost Full flag (AF). A E indicate when a se-
lected number of words written to FIFO memory achieve a
predetermi ned “almost empty state.” AF indicat es when a se-
lected number of words written to the memor y achieve a pre-
determined “ almost full state. ”
IR and AF are synchronized to the port clock that writes data
into its array. OR and AE are synchronized to the port clock
that r eads dat a from its arr a y. Progr ammab le of fse t f or AE and
AF are loaded in parallel using Por t A or in serial via the SD
input. Three default offset settings are also provided. The AE
threshold can be set at 8, 16, or 64 locations from the empty
boundary and AF thr esh old ca n b e se t at 8, 16, or 64 l ocat ions
from the full boundary. All these choices are made using the
FS0 and FS1 inputs during Master Reset.
Two or more devices may be used i n parallel to create wider
data paths. If any time, the FIFO is not actively performing a
function, the chip will automatically power down. During the
power-down state, supply current consumption (ICC) is at a
minimum . In iti ating any oper ati on ( by act iv at ing cont rol inputs )
will immediately take the device out of the power-down state.
The CY7C436x3 are characterized for operati on from 0°C to
70°C . Input ESD prot ection i s great er than 2001V, and latch- up
is prevented by the use of guard rings.
Selection G uid e
CY7C43623/33/43/63/83-12 CY7C43623/33/43/63/83-15
Maximum Frequency (MHz) 83 66.7
Maximum Access Time (ns) 910
Minimum Cycle Time (ns) 12 15
Minimum Data or Enable Set-Up (ns) 4 5
Minimum Data or Enable Hold (ns) 0 0
Maxim u m Flag Delay (ns) 8 8
Active Power Supply
Current (ICC1) ( mA ) Commercial 100 100
Industrial 100 100
CY7C43623 CY7C43633 CY7C43643 CY7C43663 CY7C43683
Density 256 x 36 512 x 36 1K x 36 4K x 36 16K x 36
Package 128 TQFP 128 TQFP 128 TQFP 128 TQF P 128 TQFP
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
4
PRELIMINARY
Pin Definitions
Signal Name Description I/O Function
A0–35 Po rt A Da ta I/O 36-bit Unidi rectio nal data port for side A.
AE Almost Empty
Flag (Por t B) O Programmable almo st- em pty fla g synchronized to CLKA. I t i s LO W wh en the num ber
of words i n the FI FO 2 is l ess than or equal to the value i n the al m ost-empty A offset
regist er, X.
AF Almost Full Flag O Programmable almost-full flag synchronized to CLKA. It is LOW when the num ber of
empty lo catio ns i n the FI FO is l ess than or equal to the v alue i n the a lmos t-fu ll A of fset
regist er, Y.
B0–35 Po rt B Da ta I/O 36-bit Unidi rectio nal data port for side B.
BE/FWFT Big Endian/First
Word F all
Through Select
I This i s a dual purpose pin. During Master Reset, a HIGH on BE will sel ect Big Endian
operat io n. In this case, depending on the bus size, the most signi ficant b yt e or word on
Port A is read from Port B first (A-to-B data flow) or written to Port B first (B-to-A data
flo w). A L OW on BE wil l s elect Litt le Endian oper ation. In this case , the lea st s ignificant
byte or word on Port A is r ead from Port B first (for A-to-B data flow) or wri tten to Port
B fir st (B-to -A da ta flo w). After M aster Reset, this pin se lects the t iming m ode. A HIG H
on FWFT selects CY Standard mode, a LOW selects First Word Fall Through m ode.
Once the t iming m ode has been se lected, the le vel on FWFT m ust be st atic thr oughout
device operation.
BM Bus Match
Select (Port B) I A HI GH on this pin enab les ei ther b yte or wor d bus widt h on Po rt B, depen ding on the
state of SIZE. A LOW selects long word operation. BM works with SIZE and BE to
select the bus s ize and endian arr angem ent for Port B. The level of BM m ust be stati c
throughout device operation.
CLKA Port A Clock I CLKA is a cont in uous clock that synchroni zes all data tr ansfer s through P ort A and can
be asynchronous or coincident to CLKB. FF /IR and AF are all synchronized to t he
LO W-t o-HIGH transition of CLKA.
CLKB Port B Clock I CLKB is a cont inuous cl ock that synchronizes al l data t ransf ers thro ugh P ort B a nd can
be asynchronous or coincident to CLKA. FB/IR, E F /OR, A F, and AE are all synchro-
nized t o the LOW -to-HI G H tr ansition of CLKB.
CSA Port A Chip
Select ICSA must be LOW to enable a LOW -t o HIGH transition of CLKA to read or write on
Port A. The A0–35 outputs are in the high-impedance state when CSA is HI GH.
CSB Port B Chip
Select ICSB must be LOW to enable a LOW -t o HIGH transition of CLKB to read or write on
Port B. The B0–35 out puts are in the high- impedance stat e when CSB is HI G H .
EF/OR Empty/Output
Ready Flag
(Por t B)
O This is a dual-function pin. In the CY Standard Mode, the EF function is selected. EF
indicates whether or not the FIFO memory is empty . In the FWFT mode, the OR function
is selected. OR indicates the presence of valid data on A0–35 outputs, avai lable for
reading . EF/OR is synchronized to t he LOW-to-HIGH transition of CLKB.
ENA Po rt A Enab le I ENA m ust be HI GH to ena ble a L O W -to- HIGH tra nsiti on of CLKA t o read or writ e data
on P ort A.
ENB Po rt B Enab le I ENB m ust be HI GH to ena ble a L O W -to- HIGH tra nsiti on of CLKB t o read or writ e data
on P ort B.
FF/IR Port B Full/Input
Ready Flag O This is a dual-function pin. In the CY Standard Mode, the FF function is selected. FF
indic ates whether or not the FIFO mem ory is full. In the FWFT mode , t he IR function
is selecte d. IR i ndicates whether or not there i s spa ce available for writi ng to the FIFO
memory. F F/IR is synchronized to the LO W-to-HIGH transition of CLKA.
FS1/SEN Flag Offset
Select 1/ Seri al
Enable
I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program-
ming. During M aster Re set, FS1/ SEN and FS0/SD, together with SPM , select t he flag
offset programming method. Three offset register programming methods are available:
automatically load one of three preset values ( 8, 16, or 64), parall el l oad from Port A,
and serial load. Whe n serial load is sele cted for flag offset register programming,
FS1/SEN is used as an enabl e synchronous to the LO W-to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA loa ds the bit present on FS0/SD into
the X and Y register s. The numb er of bit writ es requ ired to prog ram the offse t reg is ter s
is 32 for the CY7C43623, 36 for the CY7C43633, 40 for the CY7C43643, 48 for the
CY7C43663, and 56 for the CY7C43683. The first bit write stores the Y-register MSB
and the last bit writ e stores the X-regi ster LSB.
FS0/SD Flag Offset
Select 0/ Seri al
Data
I
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
5
PRELIMINARY
M BA Port A M a i lbox
Select I A HIGH level on M BA chooses a m ailbox regi ster for a Port A read or write oper ation.
M BB Port B M a i lbox
Select I A HIGH level on M BB chooses a m ailbox regi ster for a Port B read or write oper ation.
When the B 0–35 outp uts are active, a HIGH level on MBB selects dat a from the Mail 1
regist er for output and a LOW level selects FIF O output register data for output.
MBF1 Mail1 Register
Flag OMBF1 is set LOW by a LOW-to-HIGH transition of CLKA tha t writes dat a to the Mail1
regist er. Writes to t he Ma il 1 register are i nhibited while MBF1 is LOW. MBF1 is set
HIGH by a LOW-to-HI GH tr ansi tion of CLKB when a Port B r ead is select ed and MBB
is HIGH. MBF1 i s set HIGH fol lowing ei ther a Master or Partial Reset.
MBF2 Mail2 Register
Flag OMBF2 is set LOW by a LOW-to-HIGH transition of CLKB tha t writes dat a to the Mail2
regist er. Writes to t he Ma il 2 register are i nhibited while MBF2 is LOW. MBF2 is set
HIGH by a LOW-to-HI GH tr ansi tion of CLKA when a Port A r ead is select ed and MBA
is HIGH. MBF1 i s set HIGH fol lowing ei ther a Master or Partial Reset of FIFO2.
MRS1 Master Reset I A LOW on this pin ini tializes the FIFO read and wri te pointers to the first lo cation of
memory and sets the P ort B output register to all zeroes. A LOW pulse on MRS1 selects
the programming method (serial or parallel) and one of three programmable flag def ault
offset s. It also configure s Po rt B for bus size and endian arr angement. Four
LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur whil e MRS1 is LOW.
MRS2 Master Reset I A LOW on this pin initializes the Mail2 Register.
PRS P artial Reset I A LOW on this pin ini tializes the FIFO read and wri te pointers to the first lo cation of
memory and sets the Port B output regis ter to all zeroes. During Partial Reset, the
current ly select ed bus size, endian arran gem ent, program m ing method (serial or par-
allel), and progr am m able fl ag settings are al l retained .
RT Retransmit I A LOW strobe on this pin will ret ransmit data on FIFO from the location of the write
pointer at the last P arti al or Master res et.
SIZE Bus Size Sel ect I A HIG H on thi s pin when BM is HIGH selects byt e bus (9-bi t) size on Port B. A LOW
on this pin when BM is HIGH sele cts word (18-bit) b us size. SIZE works with BM and
BE to select the bus size and endian arrangement for Port B. The level of SIZE must
be static throughout device operation.
SPM Serial
Programming I A LO W on this pin selects serial programming o f partial fl ag offsets. A HIGH on thi s pin
selects paral lel program ming or def ault off sets ( 8, 16, or 64).
W/RA Port A
Write/Read
Select
I A HI GH selects a write operat ion and a LO W selects a r ead operation on Port A for a
LOW-to-HIGH trans it ion o f CLKA. The A 0–35 output s a re in the HI GH i mpedan ce sta te
when W/RA is H IGH.
W/RB Port B
Write/Read
Select
I A L OW se lects a write operation and a HIGH selects a read operation on Port B f or a
LO W -to- HIGH tr ansit ion of CL KB. T he B0–35 output s are i n the HIGH i mpeda nce state
when W/RB is LO W.
Pin Definitions (continued)
Signal Name Description I/O Function
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
6
PRELIMINARY
Maximum Ratings[1]
(Above which the usefu l l ife may be impa ired. For user guide-
li nes, not tes ted.)
Storage Temperature ... ....... ............ ............ .–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Supply Voltage to Ground Potent ial... ............–0.5V to +7.0V
DC Voltag e Applied to Outputs
in High Z State[2]......................................–0.5V to VCC+0.5V
DC Input Voltage[2]...................................–0.5V to VCC+0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage... .. ...... ....... .. ....... ............. ...>2001V
(per MIL- STD-883, Method 3015 )
La tc h -U p C u rre n t.. .. .......... .. ... ..... .. .. ..... ... .............. ... .>2 00 m A
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5.0V ± 0.5V
Industrial –40°C to +85°C 5. 0V ± 0.5V
Electrical Characte ristics Over the Operat ing Range
Parameter Description Test Conditions
CY7C43623/33/43/63/83
UnitMin. Max.
VOH Output HIGH Voltage VCC = 4. 5V.,
IOH = –4.0 m A 2.4 V
VOL Ou tput LOW Voltage VCC = 4. 5V.,
IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage 2.0 VCC V
VIL Input LOW Voltage –0.5 0.8 V
IIX Input Leakage Current VCC = Max. –10 +10 mA
IOZL
IOZH Output OFF, High Z
Current OE > VIH,
VSS < VO< VCC –10 +10 mA
ICC1[3] Active Power Supply
Current Com’l 100 mA
Ind 100 mA
ISB[4] Average Standby
Current Com’l 5mA
Ind 5mA
Capacitance[5]
Parameter Description Test Conditi ons Max. Unit
CIN Input Capacitance TA = 25 °C, f = 1 MHz,
VCC = 3.3V 4pF
COUT O utp u t Capac ita nc e 8pF
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output v oltage ratings may be exceeded provided the input and output current ratings are observed.
3. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0V or VCC.
4. All inputs = VCC – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
5. Tested initially and after any design or process changes that may affect these parameters.d
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
7
PRELIMINARY
AC Test Loads and Waveforms
Switching Charac teris t ics Ov er the Operating Range
Parameter Description
CY7C43623/33/43/63/83
–12 CY7C43623/33/43/63/83
–15
UnitMin. Max. Min. Max.
fSClock Frequency, CLKA or CLKB 83 67 MHz
tCLK Clock Cycl e Time , CLKA or CLKB 12 15 ns
tCLKH Pulse Duration, CLKA or CLKB HIGH 5 6 ns
tCLKL Pul se Duration, CLKA or CLKB LO W 5 6 ns
tDS Set-Up Time, A0–35 before CLKA↑ and B0–35 be -
fo re CLK B↑4 5 ns
tENS Set-Up Time, CSA, W/R A, ENA, and MBA be fo re
CLKA↑; CSB , W/RB, ENB, and MBB before
CLKB↑
4 5 ns
tRSTS Set-Up Time, MRS1/MRS2 or PRS LOW before
CLKA↑ or CLKB↑[6] 4 5 ns
tFSS Set-Up Tim e, FS0 and FS1 before MRS1/MRS2
HIGH 77.5 ns
tBES Set-Up Time, BE/FWFT befor e MRS1/MRS2
HIGH 77.5 ns
tSPMS Set-Up Time, SPM bef ore MRS1/MRS2 HIGH 77.5 ns
tSDS Set-Up Time, FS0/SD before CLKA↑4 5 ns
tSENS Set-Up Time, FS1/SEN before CLKA ↑4 5 ns
tFWS Set-Up Time, FWFT before CLKA↑0 0 ns
tDH Hold Time, A0–35 after CLKA↑ and B0–35 after
CLKB↑0 0 ns
tENH Hol d Time , CSA, W/R A , ENA, and MBA aft er
CLKA↑; CSB , W/ RB, ENB , and MBB aft er CLKB↑0 0 ns
tRSTH Hol d Time, MRS1/MRS2 or PRS LOW aft er
CLKA↑ or CLKB↑[6] 4 4 ns
tFSH Hol d Time, FS0 a nd FS1 after MRS1/MRS2 HIGH 2 2 ns
tBEH Hold Time , BE/ FW FT aft er MRS1/MRS2 HIGH 2 2 ns
tSPMH Hold Time, SPM after MRS1/MRS2 HIGH 2 2 ns
tSDH Hold Time, FS0/SD after CLKA↑0 0 ns
Note:
6. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3.0V
5V
OUTPUT
R2=680Ω
CL=30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤3ns ≤3ns
OUTPUT 1.910V
Equivalent to: THÉ VENIN EQUIVALENT
410 Ω
ALL INPUT PULSES
R1=1.1KΩ
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
8
PRELIMINARY
tSENH Hol d Time, FS1/SEN after CLKA↑0 0 ns
tSPH Hold Time , FS1/ SEN HIGH after MRS1/MRS2
HIGH 2 2 ns
tSKEW1[7] Skew Time between CLKA↑ and CLKB↑ for
EF/OR and FF/IR 67.5 ns
tSKEW2[7] Skew Time between CLKA↑ and CLKB↑ for AE
and AF 10 12 ns
tAAcc ess Time, CLKA↑ to A0–35 and CLKB↑ to
B0–35 19310 ns
tWFF Propagation Delay Time , CLKA↑ to FF/IR 1828ns
tREF Propagation Delay Time, CLKB↑ to EF/OR 1818ns
tPAE Propagation Delay Time, CLKB↑ to AE 1818ns
tPAF Propagation Delay Time, CLKA↑ to AF 1818ns
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or
MBF2 HIGH and CLKB↑ to MBF 2 LOW or M BF1
HIGH
09012 ns
tPMR Propagation Delay Time , CLKA↑ to B0–35[8] and
CLKB↑ to A0–35[9] 211 312 ns
tMDV Propagat ion Dela y Time , MBA to A0–35 Valid and
MBB to B0–35 Valid 210 311 ns
tRSF Pr opagati on Dela y Tim e, MRS1 or PRS1 LO W to
AEB LO W, AFA HIGH, and MBF1 HIGH and
MRS2 or PRS2 LOW to AEA LO W, AFB HIGH,
and MBF2 HIGH
112 115 ns
tEN Enable Time , CSA or W/RA LOW to A0–35 Active
and CSB LOW and W/RB HIGH to B0–35 Active 210 210 ns
tDIS Disable Time, CSA or W/RA HIGH to A0–35 at High
Impedance and CSB HIGH or W/RB LOW to B0–35
at High Im pedance
1718ns
Notes:
7. Skew time is not a timing constraint for proper device operation and is only inc luded to illustrate the timing r elationship between the CLKA cycl e and the CLKB
cycle.
8. Writing data to the Mail1 register when the B0–35 outputs are active and MBB is HIGH.
9. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.
Switching Charac teris t ics Ov er the Operating Range (cont inued)
Parameter Description
CY7C43623/33/43/63/83
–12 CY7C43623/33/43/63/83
–15
UnitMin. Max. Min. Max.
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
9
PRELIMINARY
Switching Wavefor ms
Note:
10. PRS1 must be HIGH during Master Reset.
Master Reset Loading X and Y wi th a Preset Value of Eight
CLKA
tRSF
tRSF
tRSF
tWFF
tFSS tFSH
tSPMS tSPMH
tBES tBEH
tRSTS
tRSTS
tFWS
CLKB
MRS1
MRS2
BE/FWFT
SPM
FS1, FS0
FF/IR
EF/OR
AE
AF
MBF1
[10]
tRSF
tRSF
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
10
PRELIMINARY
Notes:
11. MRS1/MRS2 must be HIGH during Partial Reset
12. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset regi ster on consec utive clock cycles.
13. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLK for FFB/IR to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and ri sing edge of CLKB is less than tSKEW1, then FF/IR may transition HIGH one cycle later than shown.
Switching Wavefor ms (continued)
Partial Reset (CY Standard and FWFT Modes)
tRSF
tRSF
tRSF
tRSTS tRSTH
CLKA
CLKB
PRS
FF/IR
EF/OR
AE
AF
MBF1
[11]
tWFF
tRSF
tRSF
Parallel Program ming of the Al m ost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Mo des)
tWFF
tFSS
tDS
tFSS tFSH
tFSH
tENS tENH
tDH
tSKEW1[13]
AF Offset (Y) First Word to FIFO
CLKA
MRS1
MRS2
SPM
FS1, FS0
FF/IR
ENA
A0−35
[12]
AE Offset (X)
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
11
PRELIMINARY
Notes:
14. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.
15. Programmable offsets are written serially to the SD input in the order AF offset (Y) then AE offset ( X).
16. Read From FIFO.
Switching Wavefor ms (continued)
Serial Programm ing of the Almost-Full Flag and Almost -Empty Flag
Offset Values (CY Standard and FWFT Mod es)
tFSS tSPH tSENS tSENH tSENH
tSENS
tSDH
tSDS tSDH
tSDS
tWFF
AF Offset (Y) MSB
tFSS tFSH
CLKA
MRS1
MRS2
SPM
FF/IR
FS1/SEN
[14]
FS0/SD[15]
AE Offset (X) LSB
OR
tCLKH tCLKL
tENS
tDIS
tENS tEN
tCLK
tDIS
tENH
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV
W1[16] W2[16]
W1[16] W2[16]
W3[16]
Previous Data
No Operation
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–35
(Standard
B0–35
(FW FT Mo de)
Port B Long-Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes)
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
12
PRELIMINARY
Notes:
17. Unused word B18–35 contains all zeroes for word-size reads.
18. Unused bytes B9–17, B18–26, and B27–35 contain all zeroes for byte-size reads.
Switching Wavefor ms (continued)
OR
tDIS
tENStENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
tA
tA
tA
tA
Pre vious Data
Read 1
Read 1
Read 2
Read 2
Read 3
Read 3
Read 4
Read 4
Read 5
No Operation
HIGH
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–8
(Standard
B0–8
(FWFT Mode)
P ort B Word Read Cycle Timing for FIFO (CY Standard and FW FT Mode s)[17]
OR
tDIS
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
Previous Data
Read 1
Read 1
Read 2
Read 2
Read 3
No Operation
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–17
(Standard
B0–17
(FWFT Mode)
Port B Byte Read Cycle Timing for FIFO (CY Standard and FWFT Modes)[18]
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
13
PRELIMINARY
Notes:
19. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively.
20. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load
of the first word to the output register may occur one CLKB cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENS
tCLK
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO Empty
LOW
HIGH
LOW
Old Data in FIFO Output Register W1
tENS tENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW1[20]
CLKA
CSA
W/RA
MBA
ENA
IR
A0–35
CLKB
OR
CSB
W/RB
MBB
ENB
B0–35
OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)[19]
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
14
PRELIMINARY
Notes:
21. If Port B size is word or byte, EF is set LOW by the last word or byte read from FIFO, respectively.
22. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO Empty
LOW
HIGH
LOW
W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW[22]
CLKA
CSA
W/RA
MBA
ENA
FF
A0–35
CLKB
EF
CSB
W/RB
MBB
ENB
B0–35
EF Flag Timi ng and First Data Read F all Through when FIFO is Empty (CY Standard Mode)[21]
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
15
PRELIMINARY
Notes:
23. If Port B size is word or byte, tSKEW1 is referenced to the rising CLK B edge that reads the last word or byte write of the long word, respectively.
24. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
HIGH
FIFO Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[24]
tDH
tDS
tENH
tENS
Previous W ord in FIFO Output Register Next Word From FIFO
To FIFO
CLKB
CSB
W/RB
MBB
ENB
OR
B0–35
CLKA
IR
CSA
W/RA
MBA
ENA
A0–35
IR Flag Ti m ing and First Ava ilable Wri te when FIF O is Full (FWFT Mode )[23]
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
16
PRELIMINARY
Notes:
25. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively
26. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to trans ition HIGH in the nex t CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
HIGH
FIFO Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[26]
tDH
tDS
tENH
tENS
Previou s Word in FIFO Output Register Next Word From FIFO
CLKB
CSB
W/RB
MBB
ENB
OR
B0–35
CLKA
IR
CSA
W/RA
MBA
ENA
A0−35
FF Flag Timing and First Available Write when FIFO is Full (CY Standard Mode)[25]
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
17
PRELIMINARY
Notes:
27. FIFO Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been
read from the FIFO.
28. D = Maximum FIFO Depth = 256 for the CY7C43623, 512 for the CY7C43633, 1K for the CY7C43643, 4K for the 43663, and 16K for the CY7C43683.
29. If Port B size is word or byte, tSKEW2 is referenced to the rising CLK B edge that writes the last word or byte of the long word, respectively.
30. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown.
31. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been
read from the FIFO.
32. If Port B size is word or byte, AE is set LOW by the last word or byte read from FIFO, respectively.
33. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
Switching Wavefor ms (continued)
Timing for AF when FIFO is Almost Full (CY Standard and FWFT Modes)
tPAF
tENH
tENS
tPAF
tENS tENH
[D–(Y1+1)] Words in FIFO (D–Y1)Words in FIFO
tSKEW2[30]
CLKA
ENA
AF
CLKB
ENB
[27, 28, 29]
tPAE
tPAE
tENH
tENS
tSKEW2[33]
tENS tENH
X1 Word in FIFO (X1+1) Words in FIFO
CLKA
ENA
CLKB
AE
ENB
Timing for AE when FIFO is Almost Empty (CY Standar d and FWFT Modes)[31, 32]
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
18
PRELIMINARY
Note:
34. If P ort B is configured for word size , data can be written to the Mail1 register using A0–17 (A18–35 are don’t care inputs). In this first case B0–17 will have valid
data (B18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0–8 (A9–35 are don’t care inputs). In
this second case, B0–8 will have valid data (B9–35 will be indeterminate).
Switching Wavefor ms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO Output Register W1 (Remains valid in Mail1 Register after read)
CLKA
CSA
W/RA
MBA
ENA
A0–35
CLKB
MBF1
CSB
W/RB
MBB
ENB
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes) [34]
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
19
PRELIMINARY
Notes:
35. If P ort B is configured for word size , data can be written to the Mail2 register using B0–17 (B18–35 are don’t care inputs). In this first case A0–17 will have valid
data (A18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0–8 (B9–35 are don’t care inputs). In
this second case, A0–8 will have valid data (A9–35 will be indeterminate).
36. Clocks are free running in this case.
37. The flags may change state during Retransmit as a res ult of the offset of the read and write pointers, but flags will be valid at tRTR.
38. For the synchronous PAE and PAF flags (S MODE), a n appropriate clo ck c ycle is necess ary after tRTR to upda te the se flags.
Switching Wavefor ms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO2 Output Register W1 (Remains valid in Mail2 Register after read)
CLKB
CSB
W/RB
MBB
ENB
B0–35
CLKA
MBF2
CSA
W/RA
MBA
ENA
A0−35
Timing for Mail2 Register and MBF2 Flag (CY Standar d and FWFT Modes)[35]
FIFO Retransmit Timing
ENB
RT1
tPRT tRTR
EF/FF
[ 36, 37 , 38]
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
20
PRELIMINARY
Signal Description
Master Reset (MRS1, MRS2)
The FIFO mem ory of the CY7C436x3 undergoes a complete
reset by taking its associated Master Reset (MRS1, MRS2)
input LOW for at least four Port A clock (CLKA) and four Por t
B clock (CLKB) LOW-to-HIGH transitions. The Master Reset
input can switch asynchronously to the cl ocks. A Mast er Reset
initializes the internal read and write pointers and forces the
Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready
flag (EF/OR) LOW, the Almost Empty flag (AE) LOW, and the
Almost Full flag (AF) HIGH. A Master Reset also forces the
Mailbox flag (MBF1, MBF2) of the parallel mailbox register
HIGH. After a Master Reset, the FIFO’s Full/Input Ready flag
is set HIGH after two clock cycles to begin normal operation.
A Master Reset must be performed on the FIFO after power
up, before data i s wri tten to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latches the value of the Big Endian (BE) input or
determining the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Fl ag select (FS0, FS1) and Se-
rial Programming Mode (SPM) inputs for cho osing the Al m ost
Full and Almost Empty offset programming method (see Al-
most Empty and Almost Full flag offset programming below).
Partial Reset (PRS)
Each of t he two FIFO memories o f t he CY7C436x3 undergoes
a limited reset by taking its associated Partial Reset (PRS)
input LOW for at least four Port A clock (CLKA) and four Por t
B clock (CLKB) LOW-to-HIGH transitions. The Partial Reset
input s can switch asynchr onous ly to the cloc k s. A P artial Rest
initializes the internal read and write pointers and forces the
Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready
flag (EF/OR) LOW, the Almost Empty flag (AE ) LOW, and the
Almost Full flag (AF) HIGH. A Partial Reset also forces the
Mailbox flag (MBF1, MBF2) of the parallel mailbox register
HIGH. After a Part ial Reset, the FIFO’s Full/Input Ready flag
is set HIGH aft er two clock cycles to begi n norma l oper ation.
Whatever flag offsets, programming method (parallel or seri-
al), and timing mode (FWFT or IDT Standard mode) are cur-
rently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be in-
convenient.
Big Endian/First Word Fall Through (BE/FW FT)
This is a dual pu rpose pin. At the time of Mas ter Res et, the BE
select function is active, permitting a choice of big or little en-
dian byte arrangement for data written to or read from Port B.
This select ion determi nes the order by which bytes (or wor ds)
of data are trans f err ed thr ough this port. F or the followi ng illus-
trations, assume that a byte (or word) bus size has been se-
lected for Port B. (Note that when Port B is configured for a
long wor d siz e, t he Big Endi an func tion has n o appli cati on and
the
A HIGH on the BE/FWFT input when the Master Reset (MRS1,
MRS2) inputs go from LOW to HIGH will select a Big Endian
arrangement. When data is moving in the direction from Por t
A to Por t B, the most significant byte (word) of the long word
written to Port A will be read from P ort B first; the least signif-
icant b y te (wor d) of t he long wor d written t o P ort A will be read
from P ort B las t. When data is mo ving in the dir ection from P ort
B to Por t A, the byte (word) written to Port B first will be read
from Port A as the most significant byte (word) of the long
word; the byte (word) written to Port B last will be read from
Port A as the l east signi fi cant byte (word) of the l ong word.
A LOW on the BE /FWFT in put whe n t he M aster Reset (MRS1 ,
MRS2) input s go from LO W to HIGH will select a Lit tl e Endian
arrangement. When data is moving in the direction from Port
A to Por t B, the least significant byte (word) of the long word
written to Port A wil l be rea d from Port B first; the most si gnif-
icant byte ( word) of the l ong word wri tten to P o rt A wi ll be r ead
from P ort B last. When data is moving in the di rection from P ort
B to Por t A, the byte (word) written to Port B first will be read
from port A as the least significant byte (word) of the long word;
the byte (word) written to Port B last will be read from Por t A
as the most si gnifican t byte (wor d) of the long word.
After Master Reset, the FWFT sel ect f unction is activ e, permit-
ting a choice between two possible timing modes: CY Stan-
dard Mode or First Word Fall Thro ugh (FWFT) Mode. On ce the
Master Reset (MRS1, MRS2) input is HIGH, a HIGH on the
BE/FWFT input during the next LOW-to-HIGH transition of
CLKA will select CY Standard Mode. This mode uses the Emp-
ty Flag function (EF) to indicate whether or not there are any
words present i n the FIFO memo ry. It uses the Full Flag func-
tion ( FF) to indicate whether or not the FIFO mem ory has any
free space f or writing. In CY Standard mode, ev ery word read
from the FIFO, including the first, must be requested using a
for mal read operation.
Once t he Master Res e t (MRS1 , MRS2) input is HIGH, a LOW
on the BE/ FWFT input duri ng the ne xt LO W- to -HIGH tran sition
of CLKA will select FWFT Mode. This mode uses the Output
Ready function (OR) to indicate whether or not there is valid
data at the data outputs (B 0–35). It also uses the Input Ready
function (IR) to indicate whether or not the FIFO memory has
any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes direct ly to data outp uts, no r ead
request necessary. Subsequent words must be accessed by
performing a f ormal r ead operati on.
Following Master Reset, the level applied to the BE/FWFT in -
put to choose the desired timing mode must remain static
throughout the FIFO ope ration.
Programming the Almost Empty and Almost Full Flags
Four registers in the CY7C436x3 are used to hold the offset
values for the Al mo st Empty and Almost Full flags. The Port A
Almost Empty f lag (AE) offse t regi ster i s label ed X. The Port B
Almost Full flag (AF) offset register is labeled Y. The index of
each regi ster name cor respond s wi th prese t va lue s during the
reset of a FIFO , progr am m ed in paral lel using the FI FO ’s Port
A data inputs, or programmed in serial using the Serial Data
(SD) input (see
Table 1
).
To l oad a FIFO’s Almost Empt y flag and Almost Ful l fl ag offse t
registers with one of the three preset values listed in
Ta bl e 1
,
the Serial Program Mode (SPM) and at least one of the
flag-select inputs must be HIGH during the LOW-to-HIGH tran-
sition of its Master Reset input (MRS1, MR S2). Fo r ex amp le,
to loa d the pr eset v a lue of 64 int o X and Y, SPM, FS0 and FS1
must be HIGH when the FIFO reset (MRS1, MRS2) returns
HIGH. When using one of the preset values for t he fl ag offset s,
the FIFO can be reset simultaneously or at different ti me s.
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
21
PRELIMINARY
To program the X and Y registers from Port A, perf orm a Mas-
ter Reset on both FIFOs simultaneously with SPM HIGH and
FS0 and FS1 LOW during the LOW-to-HIGH transition of
MRS1/MRS2. A fter th is re se t is c omple te, the first fo ur w r ites
to the FIFO do not store data i n RAM but load the offset regis-
ters in the order Y and X. The Port A data inputs used by the
off set registers are ( A7–0), (A8–0), ( A9–0), (A11–0), or (A13–0),for
the CY7C436x3, respectively. The highest numbered input is
used as the most significant bit of the binary number in each
case. Vali d programming values for th e registers range from 1
to 252 for the CY7C43623; 1 to 508 for the CY7C43633; 1 to
1012 for the CY7C43643; 1 to 4092 for the CY7C43663; 1 to
16380 for the CY7C43683. After all the offset registers are
programmed from Port A, the Port B Full/Input Ready (FF/IR)
is set HIGH and both FIFOs begin normal ope ration.
To program the X and Y registers serially, initiate a Master
Reset wit h SPM LO W, FS0/SD LO W and FS1/ SEN HIGH dur-
ing the LOW-to-HIGH transition of MRS1/MRS2. After this re-
set is complete , the X a nd Y register values a re loaded bit-wis e
through the FS0/SD input on each LO W-to-HIGH transiti on of
CLKA that the FS1/SEN input is LOW. Thirty-two, thirty-six,
for ty, forty-eight, or fifty-six bit writes are needed to complete
the programming for the CY7C436x3, respectively. The four
registers are written in the order Y then finally X. The first-bit
write stores the most significant bit of the Y register and the
last-bit write stores the least significant bit of the X register.
Each register value can be programmed from 1 to 252
(CY7C43623), 1 to 508 (CY7C43633), 1 to 1020
(CY7C43643), 1 to 4092 (CY7C43663), or 1 to 16380
(CY7C43683).
When the opt ion t o p rogr am t he off set r egist ers seriall y is cho-
sen, the Port A Full/Input Ready (FF/IR) flag remains LOW
until all register bits are written. FF/IR is set HIGH by the
LOW-to-HIGH transition of CLKA after the last bit is loaded to
allow normal FIFO operation. The Port B Full/Input ready
(FF/ IR) flag also remains LO W throughout th e serial program-
ming process, until all register bits are wri tten.
SPM, FS0/SD, and FS1/SEN function the same way in both
CY Standard and FWFT modes.
FIFO Write/Read Operat ion
The state of the Por t A data (A 0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the High-impedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active outputs
when bot h CS A and W/RA are LO W.
Data is loaded into the FIFO from the A0–35 inputs on a
LO W-to-HIG H tr ansiti on of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW, and FF/IR is HIGH. (see
Table 2
). FIFO writes on Port A are independent of any con-
current Port B operation.
The Port B c ontrol signals are i dentical to those of Port A with
the exception that the Port B W rite/Read select (W/RB) is the
inverse of the Por t A Write/Read select (W/RA). The state of
the Por t B data ( B0–35) lines is controlled by the Por t B Chip
Selec t (CSB) and Port B Wri te/Read selec t (W/RB). The B0–35
lines are in the high-impedance state when either CSB is
HIGH or W/RB is LOW. The B0–35 lines are active outputs
when CSB is L OW and W/RB is HIGH.
Data is read from the FIFO to the B0–35 outputs by a
LO W-to-HIG H tr ansiti on of CLKB when CSB is LOW, W/RB is
HIGH, ENB is HIGH, MBB is LOW, and EF/OR is HIG H (see
Table 3
). FI FO reads and wri tes on Port B are independent of
any concurrent Port A operation.
The set-up and hold t ime constraints t o the port clocks for the
port Chip Se lects and Write/Read select s are only f or enabl ing
write and read operations and are not related to high-imped-
ance cont rol of t he data outp uts. If a port e nable is LOW during
a clock cycle, the port’s Chip Select and Write/Read select
ma y change s tat es during the set-up and hold ti me window of
the cycle.
When operating the FIFO in FWFT Mode and the Output
Ready flag i s LO W, the next word wri tten is automatically sent
to the FIFO’s output register by the LOW-to-HIGH t ransition o f
the port clock that sets the Output Ready flag HIGH, data re-
sidi ng in t he F IFO’s memory arra y i s cl oc ked t o t he out put reg -
ister only when a read i s selec ted usi ng t he port’ s Ch ip Sel ect ,
Write/Rea d select, Enab le, and Mailbox select.
When ope rati ng the FIF O in CY St andard M ode, r egardle ss of
whether t he Emp ty Fl ag is LO W or HIGH, data residing in the
FIFO’s memory array is clocked to the output register only
when a read is selected using the port’s Chip Select,
Write/Rea d select, Enab le, and Mailbox select.
Synchronized FIFO Fla gs
Each FIFO is synchronized to its port clock through at least
two flip- flop stages . This is done to impr ove fla g-signal reliabi l-
ity by reducing the probability of the metastable events when
CLKA and CLKB operate asynchronously to one another.
EF/OR and AE are synchronized to CLKA. FF/IR and AF are
synchronized to CLKB.
Table 4
sho ws th e relat ionshi p of each
port f lag to the FIFO.
Empty/Output Ready Fla gs (EF/OR)
These are dual-purpos e fl ags. In the FWFT Mode , the Output
Ready (OR) f unc tion is s ele cted. When the Output- Ready flag
is HIGH, new data i s present i n the FIFO ou tput regi ster . When
the Output Ready flag is LOW, the previous data word is
present in the FIFO output regi ster and att em pted FIFO reads
are ignored.
In the CY Standard Mode, the Empty Flag (EF) function is
selected. When the Empty Flag is HIGH, data is available in
the FIFO’s RAM memory for reading to the output register.
When Empty Flag is LOW, the previous data word is present
in the FIFO output register and attempted FIFO reads are ig-
nored.
The Empty/Out put Ready fla g of a FI FO is sy nchroniz ed to the
port clock that reads data from its array. For both the FWFT
and CY Standard modes, the FI FO read pointer is i ncrement-
ed each time a new word i s clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write p ointer an d read pointer co mp arator t hat indi cates when
the FIFO SRAM status is empty, empty+1, or empty+2.
In FWFT Mode, from t he time a wor d is written to a FIFO , it can
be shifted to the FIFO output register in a minimum of three
cycles of the Output Ready flag synchronizing clock. There-
fore, an Output Ready flag is LOW if a word in memory is the
next data to be sent to the FIFO output register and three cy-
cles ha ve not e lapsed sinc e th e time the wor d was writt en. The
Output Ready flag of the FIFO remains LOW until the third
LO W-to-HIGH transition of the synchroni zing clock occurs, si -
multa neously forcing th e Outpu t Ready fl ag HIGH and shi fti ng
the word to the FIFO output register.
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
22
PRELIMINARY
In th e CY Standard Mode, f rom the time a word is written to a
FIFO, the Empty Flag will indicate the presence of data avail-
able for re ading in a minimum of two cycles of the Emp ty Flag
synchronizing clock. Therefore, an Empty Flag is LOW if a
w ord in memory is the ne xt data t o be sent to the FI FO output
register and two cycles have not elapsed since the time the
word was written. The Em pty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
cloc k occurs , forcing t he Empty Fl ag HIGH ; onl y then can data
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizing clo ck beg ins the first synchronization cycle of a
write if the clock transition occurs at time tSKEW1 or greater
after the write. Otherwi se, the subsequent clock cycle can be
the fi rst synchronizat ion cycle.
Full/Input Ready Flags (FF/IR)
This is a dual-pur pose flag. In FWFT Mode, the Input Ready
(IR) function is selected. In CY Standard Mode, t he Full Flag
(FF) function is selected. For both timing modes, when the
Full /Inpu t Ready fl ag is HI GH, a memory l ocatio n is free i n th e
SRAM to receive new data. No memory locations are free
when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
The Full /Input Read y fl ag of a FI FO is sy nchroniz ed to the port
cloc k that writes dat a to its arra y. For both FWFT and CY Stan-
dard modes, each time a word is written to a FIFO, its write
pointer is incremented. The state machine that controls a
Full /Inpu t Ready f l ag monit ors a wri te poi nter an d re ad point er
comp arator th at i ndicates when t he FIFO SRAM status is f ull ,
full–1, or full–2. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a mini-
mum of two cycles of the Full/Input Ready flag synchronizing
clock. Therefore, an Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock
have elapsed since the next memory wri te location has been
read. The second LOW-to-HIGH transition on the Full/Input
Read y fl ag synchronizing cl ock after the read set s the Full/In-
put Ready flag HIGH.
A LO W -to -HIGH tr ansiti on on a Full /Input Ready flag s ynchr o-
nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at tim e tSKEW1 or greater after t he
read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
Almost Empty Flags (AE)
The Almost Empty flag of a FIFO is synchronized to the por t
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a write pointer and
read pointer comparator that indicates when the FIFO SRAM
status is almost empty, almost empty+1, or almost empty+2.
The Almost Empty state is defined by the contents of register
X f or AE. Thes e regi sters are loaded with pr eset values d uring
a FIFO reset, programmed from Por t A, or programmed ser i-
ally (see Almost Empty flag and Almost Full flag offset pro-
gramming above). An Almost Empty flag is LOW when its FIFO
contains X or less wor ds and is HI GH when it s FIFO contains
(X+1) or more words. A data word present in the FIFO output
register has been read from memory.
Two LOW-to-HIGH transitions of the Almost Empty flag syn-
chronizing clock are required after a FIFO write for its Almost
Empty flag to r eflect the new level of fill. Theref ore, the Al m ost
Full flag of a FIFO containing (X+1) or more words remains
LO W i f two cycles of its synchronizing cloc k ha ve not elapsed
since the write that filled the memory to the (X+1) level. An
Almost Empty flag is set HIGH by the second LOW-to-HIGH
transition of its synchronizing clock after the FIFO write that
fills memory to t he (X+1) l evel . A LOW- to- HIGH trans it io n of an
Almost Empty flag synchronizing clock begins the first syn-
chronization cycle if it occurs at time tSKEW2 or greater after
the write that fills the FIFO to (X+1) words. Otherwise, the sub-
sequent synchronizing clock cycle may be the first synchroni-
zation cycle.
Almost Full Flags (AFA, A F B)
The Almost Full flag of a FIFO is sync hronized to the port clock
that writ es da ta to i ts ar ra y. The s tate mac hine t hat contr ols an
Almost Full fla g mon itors a write po inter a nd read po inter c om-
parator that indicates when the FIFO SRAM status is almost
full, almost full–1, or almost full–2. The Almost Full state is
defined by the contents of register Y for AF. These registers
are loaded with preset values during a FIFO reset, pro-
grammed from Port A, or programmed serially (see Almost
Empty f lag and Al most Full fl ag offset programming above) . An
Almost Full fl ag is LOW when the number of words in its F IFO
is greater than or equal to (256–Y), (512–Y), (1024–Y),
(4096–Y), or (16384–Y) for the CY7C436x3 respectively. An
Almost F ull f lag i s HIGH when t he number of wo rds in its F IFO
is less than or equal to [256–(Y+1)], [512–(Y+1)],
[1024–(Y+1)], [4096–(Y+1)], or [16384–(Y+1)], for the
CY7C436x3 respectively. Note that a data word pr esent in the
FIFO output register has been read from memory.
Two LOW-to-HIGH transiti ons of the Almost Full fl ag synchro-
nizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [256/512/1024/4096/16384–(Y+1)]
or less words remains LOW if two cycles of its synchronizing
clock have not elapsed since the read that reduced the number
of words in memory to [ 256/512/1024/4096/16384–(Y+1)]. An
Almost Ful l flag is set HIGH by the second LOW- to-HIGH tran -
siti on of its s ynch ronizing cl ock aft er th e FIFO r ead t hat r educ -
es the number of words in memory to
[256/512/1024/4096/16384–(Y+1)]. A LOW-to-HIGH transition
of an Almost Ful l flag synchronizing cl ock begins the first syn-
chronization cycle if it occurs at time tSKEW2 or greater after
the read that reduces the number of words in memory to
[256/512/1024/4096/16384–(Y+1)]. Otherwise, the subse-
quent synchronizing clock cycle may be the first synchroniza-
tion cycle.
Mailbox Regist ers
Each FIFO has a 36-bit bypass registe r to pass command and
control informat ion between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable width of bot h the Mail1 and Mail 2 regis-
ters matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes A0−35 data to the
Mail1 Reg ister when a P ort A write is se lecte d b y CSA, W/RA,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register em-
ploys data lines A0−A35. If the selected Port A bus size is 18
bits , then the usabl e width of the Mail1 Registe r employs data
lines A0−A17. (In this case, A18−A35 are don’t care inputs.) If
the sel ected Port A bus size is 9 bits, then the usable width of
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
23
PRELIMINARY
the Mail1 Register employs data lines B0−B8. (In this case,
A9−A35 are don’t care inputs.)
A LOW-to-HIGH transition on CLKB writes B0−35 data to the
Mail2 r egister when a P ort B write is select ed by CSB, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register em-
plo ys data li nes B0–35. If the se lec ted Port B b us size is 18 bits,
then the usable width of the Mail2 register employs data lines
B0–17. ( In th is case , B 18–35 are don’ t car e input s.) If t he selec t-
ed Po rt B bus size is 9 bits, then the usable width of the Mai l2
Regis ter emplo ys data lin es B0−8. (In this case, B9−35 are don’t
care i nputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LO W. At tempted writes t o a mail regi ster ar e
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the por t
Ma ilbox Sele c t in pu t is HIG H .
The Mail1 Register flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Port B read is se-
lected by CSB, W/RB, and ENB with MBB HIGH. For a 36-bit
bus size, 36 bits of mail box data are placed on B0–35. For an
18-bi t b us size , 18 bits of mai lb ox data are plac ed on B0–17. (In
this case, B18–35 are indeterminate.) For a 9-b it bus si ze, 9 bi ts
of mailbox data are placed on B0–8. (In this case, B9–35 are
indeterminate.)
The Mail2 Register flag (MBF2) is set HIGH by a
LOW-to-HIGH transition on CLKA when a Port A read is se-
lect ed by CSA, W/RA, and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A0–35. For an 1 8-b it bu s size , 18 bits of mailbo x data are placed
on A0–17. (In t his c ase , A18–35 are indeter minate.) For a 9- bit
bus size, 9 bits of mailbox data are placed on A0–8. (In this
case, A9–35 are indeterminate.)
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the m ailbox data.
Bus Sizi ng
The Port B bus ca n be configured in a 36-bit l ong word, 18-bit
word, or 9-bit byte for mat for data read from FIFO. The levels
applied to the Port B Bus Size Select (SIZE) and the Bus
Match Se lect (BM) determine th e Port B b us size . These lev els
shoul d be static through out FIF O operat ion. Both bus siz e se-
lections are implemented at the completion of Master Reset,
by the time the Full/Input Re ady fl ag is set HIGH.
Two differ ent methods for sequencing data transfer are avai l-
able for Port B when the bus size selection is either byte-or
word-siz e. They ar e ref erred to a s Big Endian (most sign ificant
byte first) and Little Endian (least significant byte first). The
level applied to the Big Endian Select (BE) input during the
LOW-to-HIGH transition of MRS1/MRS2 selects the endian
method th at wil l be act ive duri ng FIFO oper atio n. BE is a d on’t
care input when the bus size selected for Port B is long word.
The endian method is implement ed at the completio n of Mas-
ter Reset , by the time the Full/Input r eady flag is set HIGH.
Only 36-bit long word data is written to or read from the two
FIFO me mories on t he CY7C 436x3. Bu s-mat ching operat ions
are don e after data is r ead from t he FIF O. Thes e bus -matching
operations are not av ailable when transferring data via mailbox
registers. Furthermore, both the word- and byte-size bus se-
lections limit the width of the dat a bus that can be use d for mail
regis ter oper a tions . In this c ase, onl y those b y te lan es belong -
ing to the selected word- or byte-size bus can carry mailbox
data. The remaining data outputs will be indeterminate. The
remaining data inputs will be don’t care inputs. For example,
when a word-size bus is selected, then mailbox data can be
transmitted only between A0–17 and B0–17. When a byte-size
bus is select ed, t hen mail bo x data can be transm it ted only be-
tween A 0–8 and B0–8.
Bus-Matching FIFO Reads
Data is read from the FIFO RAM in 36-bit long word incre-
ments. If a long word bus size is implem ented, the ent ire long
word immediately shifts to the FIFO output register. If byte or
word size is implemented on Port B, only the first one or two
byte s appea r on the sel ected porti on of th e FIFO output regis -
ter, with the rest of the long word stored in auxiliar y registers.
In this case, subsequent FIFO reads ou tput the re st o f the long
word to the FIFO output register.
When reading data from the FIFO in the byte or word format,
the unused B0–35 outputs are indeter minate.
Retransmit (RT)
The retransmit feature is beneficial when transferr ing packets
of data. It enables the receipt of data to be acknowledged by
the recei ver and ret ransmitted if necessary.
The retransmit feature is intended for use when a number of
writes equal to or less than the depth of the FIFO have oc-
curred and at l east one word has be en read si nce the l ast rese t
cycle. A LOW pulse on RT resets the internal read pointer to
the firs t physi cal location of t he FIF O. CLKA an d CLKB ma y be
free running but must be disabled during and tRTR after the
retransmit pulse. With ever y valid read cycle after retransmit,
pre vi ously accessed dat a is r ead a nd the r ead point er is incre -
mented un ti l i t is equal to t he writ e po inter. Fla gs a re go v erned
by the re lati ve lo cation s of the read and write poi nters and are
updated during a retransmit cycle. Data written to the FIFO
after acti vat ion o f R T are t r ansmit ted al so . The full depth of the
FIFO can be repeatedly transmitted.
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
24
PRELIMINARY
A
A35–27 B
A26–18 C
A17–9 D
A8–0
A
B35–27 B
B26–18 C
B17–9 D
B8–0
B35–27 A
B17–9 B
B8–0
C
B17–9 D
B8–0
C
B17–9 D
B8–0
A
B17–9 B
B8–0
A
B8–0
B
B8–0
C
B8–0
D
B8–0
B35–27
B35–27
B35–27
B35–27
B35–27
B35–27
B35–27
B26–18
B26–18
B26–18
B26–18
B26–18
B26–18
B26–18
B26–18
B17–9
B17–9
B17–9
B17–9
(a) LO NG WORD SIZE
(b) WORD SIZE – BIG ENDIAN
(c) WORD SIZE – LITTLE ENDIAN
(d) BYTE SI ZE – BIG ENDIAN
BE BM SIZE
XLX
BE BM SIZE
HHL
BE BM SIZE
LHL
BE BM SIZE
HHH
Writ e to FI FO
Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
3rd: Read from
FIFO
4th: Read from
FIFO
BYTE ORDER ON
PORT A:
D
B8–0
C
B8–0
B
B8–0
A
B8–0
B35–27
B35–27
B35–27
B35–27
B26–18
B26–18
B26–18
B26–18
B17–9
B17–9
B17–9
B17–9
( e) BYT E SIZE – L ITT L E EN DIAN
BE BM SIZE
LHH
1st: Read from
FIFO
2nd: Read from
FIFO
3rd: Read from
FIFO
4th: Read from
FIFO
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
25
PRELIMINARY
..
Table 1. Flag Programming
SPM FS1/SEN FS0/SD MRS1/MRS2 X and Y Registers[39]
H H H ↑64
H H L ↑16
H L H ↑8
H L L ↑P arall el pr ogram ming via Port A
L H L ↑Serial programming via SD
L H H ↑Reserved
L L H ↑Reserved
L L L ↑Reserved
Table 2. Po rt A Enable Function
CSA W/RA ENA MBA CLKA A0–35 Outp uts Port Function
H X X X X In high-impedance state None
L H L X X In high-impedance state None
LHHL↑In high-impedance state FIFO write
LHHH↑In high-i m pedance state Mail1 write
L L L L X Active, Mail2 register None
LLHL↑Activ e, Mail2 register None
L L L H X Ac tive, Mail2 register None
LLHH↑Active, Mail2 register Mail2 read (set MBF2 HIGH)
Table 3. P ort B Enabl e Function
CSB W/RB ENB MBB CLKB B0–35 Outputs P ort Function
H X X X X In high-impedance state N one
L L L X X In high-impedance stat e Non e
LLHL↑In high- impedance stat e None
LLHH↑In high-impedance state Mail2 write
L H L L X Act ive, FIFO output regi ster None
LHHL↑Acti ve, FIFO output register FIFO read
L H L H X Acti ve, Mail1 register None
LHHH↑Act ive, M ail1 register Mail1 read ( set MBF1 HIGH)
Note:
39. X register holds the offset for AE; Y register holds the offset for AF.
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
26
PRELIMINARY
Table 4. FIFO Flag Operati on (CY Standard and FWFT Modes)
Number of W ords in FIFO Memory[40,41,42,43] Synchr onized to
CLKA Synchronized to
CLKB
CY7C43623 CY7C43633 CY7C43643 CY7C43663 CY7C 43683 EF/OR AE AF FF/IR
0 0 0 0 0 L L H H
1 TO X1 1 TO X1 1 TO X1 1 TO X1 1 TO X1 H L H H
(X1+1) to
[256–(Y1+1)] (X1 + 1) to
[512–(Y1+1)] ( X 1+1) to
[1024–(Y1+1)] (X1+1) to
[4096–(Y1+1)] (X1+1) to
[16384–(Y1+1)] H H H H
(256–Y1) to
255 ( 512–Y1) to
511 (1024–Y1) to
1023 (4096–Y1) to
4095 (16384–Y1) to
16383 H H L H
256 512 1024 4096 16384 H H L L
Table 5. Data Size for FIFO Long-Word Reads
Size Mode [44] Data Written to FIFO2 Data Read From FIFO2
BM SIZE BE A35–27 A26–18 A17–9 A8–0 B26–18 B26–18 B17–9 B8–0
LXXABCDABCD
Table 6. Data Size for W or d Reads
Size Mode[44] Data Written to FIFO Read No. Data Read From FIFO
BM SIZE BE A35–27 A26–18 A17–9 A8–0 B17–9 B8–0
HLHABCD1AB
2CD
HLLABCD1CD
2AB
Table 7. Data Size for Byte Reads from FIFO
Size Mode[44] Data Written to FIFO Read No. Data Read From
FIFO
BM SIZE BE A35–27 A26–18 A17–9 A8–0 B8–0
HHHABCD1 A
2B
3C
4D
HHLABCD1 D
2C
3B
4A
Notes:
40. X1 is the almost-empty offset for FIFO used by AE. Y is the almost-full offset for FIFO used by AF. Both X1 and Y1 are selected during a FIFO reset or port
A programming.
41. When a w ord loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
42. Data i n the output register does not count as a “word in FIFO memory”. Since in FWFT mode, the first word written to an empty FIFO goes unrequested to
the output register (no read operation necessary), it is not included in the FIFO memory count.
43. The OR and IR func tions are active during FWFT mode; the EF and FFA functions are active in CY Standard mode.
44. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
27
PRELIMINARY
256 x36 Unidirectional Synchronous FIFO w/ bus-matching
Speed
(ns) O rd e ring C o de Package
Name Package
Type Operating
Range
12 CY7C43623–12AC A128 128-Lead Thin Quad Fl at Package Commercial
12 CY7C43623–12AI A128 128-Lead Thin Quad Flat Package Industrial
15 CY7C43623–15A C A128 128- Lead Thin Quad Flat Package Commercial
512 x36 Unidirectional Synchronous FIFO w/ bus-matching
Speed
( ns ) Ordering C o de Package
Name Package
Type Operating
Range
12 CY7C43633–12AC A128 128-Lead Thi n Q uad Flat Package Comme rci al
12 CY7C43633–12AI A128 128-Lead Thin Quad Fl at Package Industrial
15 CY7C43633–15AC A128 128-Lead Thi n Q uad Flat Package Comme rci al
1K x36 Unidirectional S ynchronous FIFO w/ bus-matching
Speed
( ns ) Ordering C o de Package
Name Package
Type Operating
Range
12 CY7C43643–12AC A128 128-Lead Thi n Q uad Flat Package Comme rci al
12 CY7C43643–12AI A128 128-Lead Thin Quad Fl at Package Industrial
15 CY7C43643–15AC A128 128-Lead Thi n Q uad Flat Package Comme rci al
4K x36 Unidirectional S ynchronous FIFO w/ bus-matching
Speed
( ns ) Ordering C o de Package
Name Package
Type Operating
Range
12 CY7C43663–12AC A128 128-Lead Thi n Q uad Flat Package Comme rci al
12 CY7C43663–12AI A128 128-Lead Thin Quad Fl at Package Industrial
16K x36 Uni dire ctiona l Synchronous FIFO w/ bus-matchi ng
Speed
( ns ) Ordering C o de Package
Name Package
Type Operating
Range
12 CY7C43683–12AC A128 128-Lead Thi n Q uad Flat Package Comme rci al
12 CY7C43683–12AI A128 128-Lead Thin Quad Fl at Package Industrial
15 CY7C43683–15AC A128 128-Lead Thi n Q uad Flat Package Comme rci al
Document #: 38–00699–A
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
PRELIMINARY
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circu itry embodied i n a Cypress Sem ic onductor product. Nor does it conv ey or imply any license under patent or oth er rights . Cypress Semiconductor does not authoriz e
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Di ag ra m
128-Pin Thi n Plastic Quad Flatpack (14 x 20 x 1. 4 mm) A128
51-85101
