ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 1 -
GENERAL DESCRIPTION
The AK4395 is a high performance stereo DAC for the 192kHz sampling mode of DVD-Audio including a
24bit digital filter. The digital filter has high stopband attenuation with 110dB or more that reduces wide
band aliasing noise. The AK4395 introduces the advanced multi-bit system for ∆Σ modulator. This new
architecture achieves the wider dynamic range, while keeping much the same superior distortion
characteristics as conventional Single-Bit way. The analog outputs are filtered in the analog domain by
switched-capacitor filter (SCF) with high tolerance to clock jitter. The AK4395 also includes digital
volume, so the device is suitable for multi-channel audio system.
FEATURES
• 128x Oversampling
• Sampling Rate up to 192kHz
• High Performance 24Bit 8x Digital Filter (Slow Roll-off Option)
Ripple: ±0.0002dB, Attenuation: 110dB
• High Tolerance to Clock Jitter
• Low Distortion Differential Output
• Digital de-emphasis for 32, 44.1 & 48kHz sampling
• Channel Independent Digital Volume with Soft-transition
• Soft Mute
• THD+N: -100dB
• DR, S/N: 120dB
• I/F format: MSB justified, 16/20/24bit LSB justified, I2S
• Master Clock: Normal Speed: 256fs, 384fs, 512fs or 768fs
Double Speed: 128fs, 192fs, 256fs or 384fs
Quad Speed: 128fs or 192fs
• Power Supply: 5V±5%
• TTL Level Digital I/F
• Small Package: 28pin VSOP
• Pin Compatible with AK4393/4
DEM1
LRCK
BICK
SDAT
A
Audio Data
Interface
DEM0DVDD
CSN
AVDD
AOUTR+
8x
Interpolator SCF
∆Σ
Modulator
AOUTR-
SCF
De-emphasis
DATT, Soft Mute
Control Register Clock Divider
De-emphasis
Control
PDN
CCLK CDTI P/S MCLK VREFH VREFL
AOUTL+
AOUTL-
V
COM
BVSS
AVSSDVSS
DIF2DIF1DIF0
SMUTE
CAD0
DZFL
DZFR
De-emphasis
DATT, Soft Mute
8x
Interpolator ∆Σ
Modulator
CAD1
Advanced Multi-Bit 192kHz 24-Bit ∆Σ DAC
AK4395
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 2 -
Ordering Guide
AK4395VF -10 ~ +70 °C 28pin VSOP (0.65mm pitch)
AKD4395 Evaluation Board
Pin Layout
6
5
4
3
2
1
DVSS
DVDD
PDN
MCLK
BICK
SDATA
LRCK 7
SMUTE/CSN 8
ACKS/DZFR
CKS1/CAD1
CKS0/DZFL
P/S
VCOM
AOUTL+
AOUTL-
AOUTR+
Top
View
10
9
DFS0/CAD0
DEM0/CCLK
DEM1/CDTI 11
DIF0 12
AOUTR-
AVSS
AVDD
VREFH
23
24
25
26
27
28
22
21
19
20
18
17
13
14
16
15
DIF1
DIF2
VREFL
BVSS
Compatibility with AK4393/4
AK4395 AK4394 AK4393
fs (max) 216kHz 216kHz 108kHz
DVDD 4.75~5.25V 4.75~5.25V 3~5.25V
Digital Filter Stopband Attenuation 110dB 75dB 75dB
Digital Volume 256 levels, 0.5dB N/A N/A
µP I/F Address Pin CAD0/CAD1 N/A N/A
De-emphasis filter 32k,44.1k,48k 32k,44.1k,48k,96k 32k,44.1k,48k,96k
Optional Filter Slow Roll-off Slow Roll-off N/A
Zero Detection Pin DZFL/DZFR DZFL/DZFR N/A
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 3 -
PIN/FUNCTION
No. Pin Name I/O Function
1 DVSS - Digital Ground Pin
2 DVDD - Digital Power Supply Pin, 5.0V
3 MCLK I Master Clock Input Pin
4
PDN I Power-Down Mode Pin
When at “L”, the AK4395 is in power-down mode and is held in reset.
The AK4395 should always be reset upon power-up.
5BICK I Audio Serial Data Clock Pin
The clock of 64fs or more than is recommended to be input on this pin.
6SDATA I Audio Serial Data Input Pin
2’s complement MSB-first data is input on this pin.
7 LRCK I L/R Clock Pin
SMUTE I Soft Mute Pin in parallel mode
When this pin goes “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
8
CSN I Chip Select Pin in serial mode
DFS0 I Sampling Speed Mode Select Pin in parallel mode (Internal pull-down pin)
“L”: Normal Speed, “H”: Double Speed
9
CAD0 I Chip Address 0 Pin in serial mode (Internal pull-down pin)
DEM0 I De-emphasis Enable Pin in parallel mode
10 CCLK I Control Data Clock Pin in serial mode
DEM1 I De-emphasis Enable Pin in parallel mode
11 CDTI I Control Data Input Pin in serial mode
12 DIF0 I Digital Input Format Pin
13 DIF1 I Digital Input Format Pin
14 DIF2 I Digital Input Format Pin
15 BVSS - Substrate Ground Pin, 0V
16 VREFL I Low Level Voltage Reference Input Pin
17 VREFH I High Level Voltage Reference Input Pin
18 AVDD - Analog Power Supply Pin, 5.0V
19 AVSS - Analog Ground Pin, 0V
20 AOUTR- O Rch Negative analog output Pin
21 AOUTR+ O Rch Positive analog output Pin
22 AOUTL- O Lch Negative analog output Pin
23 AOUTL+ O Lch Positive analog output Pin
24 VCOM O Common Voltage Output Pin, 2.6V
25 P/S I Parallel/Serial Select Pin (Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
CKS0 I Master Clock Select Pin in parallel mode
26 DZFL O Lch Zero Input Detect Pin in serial mode
CKS1 I Master Clock Select Pin in parallel mode (Internal pull-down pin)27
CAD1 I Chip Address 1 Pin in serial mode (Internal pull-down pin)
ACKS I Master Clock Auto Setting Mode Pin in parallel mode
28 DZFR O Rch Zero Input Detect Pin in serial mode
Note: All input pins except internal pull-up/down pins should not be left floating.
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 4 -
ABSOLUTE MAXIMUM RATINGS
(AVSS, BVSS, DVSS = 0V; Note 1)
Parameter Symbol min max Units
Power Supplies: Analog
Digital
| BVSS-DVSS | (Note 2)
AVDD
DVDD
∆ GND
-0.3
-0.3
-
6.0
6.0
0.3
V
V
V
Input Current , Any pin Except Supplies IIN - ±10 mA
Input Voltage VIND -0.3 DVDD+0.3 V
Ambient Operating Temperature Ta -10 70 °C
Storage Temperature Tstg -65 150 °C
Notes: 1. All voltages with respect to ground.
2. AVSS, BVSS and DVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, BVSS, DVSS=0V; Note 1)
Parameter Symbol min typ max Units
Power Supplies:
(Note 3)
Analog
Digital
AVDD
DVDD
4.75
4.75
5.0
5.0
5.25
5.25
V
V
Voltage Reference
(Note 4)
“H” voltage reference
“L” voltage reference
VREFH-VREFL
VREFH
VREFL
∆ VREF
AVDD-0.5
AVSS
3.0
-
-
-
AVDD
-
AVDD
V
V
V
Notes: 3. The power up sequence between AVDD and DVDD is not critical.
4. Analog output voltage scales with the voltage of (VREFH-VREFL).
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = ±2.4Vpp×(VREFH-VREFL)/5.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 5 -
ANALOG CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 5V; AVSS, BVSS, DVSS = 0V, VREFH = AVDD, VREFL = AVSS;
fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement Bandwidth = 20Hz~20kHz;
RL ≥ 600Ω; External circuit: Figure 12; unless otherwise specified)
Parameter min typ max Units
Resolution 24 Bits
Dynamic Characteristics (Note 5)
fs=44.1kHz
BW=20kHz
0dBFS
-60dBFS
-100
-53
-90
-
dB
dB
fs=96kHz
BW=40kHz
0dBFS
-60dBFS
-97
-51
-87
-
dB
dB
THD+N
fs=192kHz
BW=40kHz
0dBFS
-60dBFS
-97
-51
-
-
dB
dB
Dynamic Range (-60dBFS with A-weighted) (Note 6)
(Note 7)
112
-
117
120
dB
dB
S/N (A-weighted) (Note 8)
(Note 7)
112
-
117
120
dB
dB
Interchannel Isolation (1kHz) 100 120 dB
DC Accuracy
Interchannel Gain Mismatch 0.15 0.3 dB
Gain Drift (Note 9) 20 - ppm/°C
Output Voltage (Note 10) ±2.25 ±2.4 ±2.55 Vpp
Load Resistance (Note 11) 600 Ω
Output Current 3.5 mA
Power Supplies
Power Supply Current
Normal Operation (PDN = “H”)
AVDD
DVDD(fs=44.1kHz)
DVDD(fs=96kHz)
DVDD(fs=192kHz)
AVDD + DVDD
60
7
10
17
-
-
-
-
110
mA
mA
mA
mA
mA
Power-Down Mode (PDN = “L”)
AVDD + DVDD (Note 12) 10 100 µA
Power Supply Rejection (Note 13) 50 dB
Notes: 5. At 44.1kHz, measured by Audio Precision, System Two. Averaging mode.
At 96kHz and 192kHz, measured by ROHDE & SCHWARZ, UPD. Averaging mode.
Refer to the evaluation board manual.
6. 101dB at 16bit data and 116dB at 20bit data.
7. By Figure13. External LPF Circuit Example 2.
8. S/N does not depend on input bit length.
9. The voltage on (VREFH-VREFL) is held +5V externally.
10. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFH-VREFL).
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = ±2.4Vpp×(VREFH-VREFL)/5.
11. For AC-load. 1kΩ for DC-load.
12. In the power-down mode. P/S = DVDD, and all other digital input pins including clock pins (MCLK, BICK and
LRCK) are held DVSS.
13. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFH pin is held +5V.
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 6 -
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; Normal Speed Mode; DEM = OFF; SLOW = “0”)
Parameter Symbol min typ max Units
Digital Filter
Passband ±0.01dB (Note 14)
-6.0dB
PB 0
- 22.05
20.0
-
kHz
kHz
Stopband (Note 14) SB 24.1 kHz
Passband Ripple PR ± 0.0002 dB
Stopband Attenuation SA 110 dB
Group Delay (Note 15) GD - 43.5 - 1/fs
Digital Filter + SCF
Frequency Response 0 ∼ 20.0kHz - ± 0.1 - dB
Note: 14. The passband and stopband frequencies scale with fs.
For example, PB = 0.4535×fs (@±0.01dB), SB = 0.546×fs.
15. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of
both channels to input register to the output of analog signal.
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 96kHz; Double Speed Mode; DEM = OFF; SLOW = “0”)
Parameter Symbol min typ max Units
Digital Filter
Passband ±0.01dB (Note 14)
-6.0dB
PB 0
- 48.0
43.5
-
kHz
kHz
Stopband (Note 14) SB 52.5 kHz
Passband Ripple PR ± 0.0002 dB
Stopband Attenuation SA 110 dB
Group Delay (Note 15) GD - 43.5 - 1/fs
Digital Filter + SCF
Frequency Response 0 ∼ 40.0kHz - ± 0.2 - dB
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 192kHz; Quad Speed Mode; DEM = OFF; SLOW = “0”)
Parameter symbol min typ max Units
Digital Filter
Passband ±0.01dB (Note 14)
-6.0dB
PB 0
- 96.0
87.0
-
kHz
kHz
Stopband (Note 14) SB 105 kHz
Passband Ripple PR ± 0.0002 dB
Stopband Attenuation SA 110 dB
Group Delay (Note 15) GD - 43.5 - 1/fs
Digital Filter + SCF
Frequency Response 0 ∼ 80.0kHz - +0/-0.5 - dB
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 7 -
SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; Normal Speed Mode; DEM = OFF; SLOW = “1”)
Parameter Symbol min typ max Units
Digital Filter
Passband ±0.04dB (Note 16)
-3.0dB
PB 0
- 18.2
8.1
-
kHz
kHz
Stopband (Note 16) SB 39.2 kHz
Passband Ripple PR ± 0.005 dB
Stopband Attenuation SA 72 dB
Group Delay (Note 15) GD - 43.5 - 1/fs
Digital Filter + SCF
Frequency Response 0 ∼ 20.0kHz - +0/-5 - dB
Note: 16. The passband and stopband frequencies scale with fs.
For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.
SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 96kHz; Double Speed Mode; DEM0 = OFF; SLOW = “1”)
Parameter Symbol min typ max Units
Digital Filter
Passband ±0.04dB (Note 16)
-3.0dB
PB 0
- 39.6
17.7
-
kHz
kHz
Stopband (Note 16) SB 85.3 kHz
Passband Ripple PR ± 0.005 dB
Stopband Attenuation SA 72 dB
Group Delay (Note 15) GD - 43.5 - 1/fs
Digital Filter + SCF
Frequency Response 0 ∼ 40.0kHz - +0/-4 - dB
SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 192kHz; Quad Speed Mode; DEM = OFF; SLOW = “1”)
Parameter Symbol min typ max Units
Digital Filter
Passband ±0.04dB (Note 16)
-3.0dB
PB 0
- 79.1
35.5
-
kHz
kHz
Stopband (Note 16) SB 171 kHz
Passband Ripple PR ± 0.005 dB
Stopband Attenuation SA 72 dB
Group Delay (Note 15) GD - 43.5 - 1/fs
Digital Filter + SCF
Frequency Response 0 ∼ 80.0kHz - +0/-5 - dB
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 8 -
DC CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
2.2
-
-
-
-
0.8
V
V
High-Level Output Voltage (Iout = -100µA)
Low-Level Output Voltage (Iout = 100µA)
VOH
VOL
DVDD-0.5
-
-
-
-
0.5
V
V
Input Leakage Current (Note 17) Iin - - ± 10 µA
Note: 17. DFS0/CAD0, CKS1/CAD1 and P/S pins have internal pull-down or pull-up devices, nominally 100kΩ.
SWITCHING CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V; CL = 20pF)
Parameter Symbol min typ max Units
Master Clock Timing
Frequency
Duty Cycle
fCLK
dCLK
7.7
40
41.472
60
MHz
%
LRCK Frequency (Note 18)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
30
60
120
45
54
108
216
55
kHz
kHz
kHz
%
Serial Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (Note 19)
LRCK Edge to BICK “↑” (Note 19)
SDATA Hold Time
SDATA Setup Time
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fs
1/64fs
1/64fs
30
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
50
50
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
Reset Timing
PDN Pulse Width (Note 20) tPD 150 ns
Notes: 18. When the normal/double/quad speed modes are switched, AK4395 should be reset by PDN pin or RSTN bit.
19. BICK rising edge must not occur at the same time as LRCK edge.
20. The AK4395 can be reset by bringing PDN “L” to “H”.
When the states of CKS2-0 or DFS1-0 change, the AK4395 should be reset by PDN pin or RSTN bit.
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 9 -
Timing Diagram
1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK VIL
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Clock Timing
tLRB
LRCK
VIH
BICK VIL
tSDS
VIH
SDATA VIL
tSDH
VIH
VIL
tBLR
Audio Interface Timing
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 10 -
tCSS
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
C1 C0 R/W A4
tCCKL tCCKH
tCDS tCDH
WRITE Command Input Timing
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
D3 D2 D1 D0
tCSW
tCSH
WRITE Data Input Timing
tPD
VIL
PDN
Power-down Timing
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 11 -
OPERATION OVERVIEW
System Clock
The external clocks, which are required to operate the AK4395, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =
“0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). CKS0/1/2 set the frequency of MCLK at each sampling
speed (Table 2). In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 6),
and the internal master clock becomes the appropriate frequency, it is not necessary to set DFS0/1 and CKS0/1/2. In
parallel mode, CKS2 and DFS1 are fixed to “0”.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4395 is in normal operation
mode (PD = “H”). If these clocks are not provided, the AK4395 may draw excess current because the device utilizes
dynamic refreshed logic internally. If the external clocks are not present, the AK4395 should be in the power-down mode
(PDN = “L”) or in the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4395 is in power-down mode
until MCLK and LRCK are input.
DFS1 DFS0 Sampling Rate (fs)
0 0 Normal Speed Mode 30kHz~54kHz Default
0 1 Double Speed Mode 60kHz~108kHz
1 0 Quad Speed Mode 120kHz~216kHz
Table 1. Sampling Speed (Manual Setting Mode)
Mode CKS2 CKS1 CKS0 Normal Double Quad
0 0 0 0 256fs 128fs N/A Default
1 0 0 1 256fs 256fs N/A
2 0 1 0 384fs 192fs N/A
3 0 1 1 384fs 384fs N/A
4 1 0 0 512fs 256fs 128fs
5 1 0 1 512fs N/A N/A
6 1 1 0 768fs 384fs 192fs
7 1 1 1 768fs N/A N/A
Table 2. System Clocks (Manual Setting Mode)
Note: The master clock at quad speed supports only 128fs or 192fs.
LRCK MCLK BICK
fs 256fs 384fs 512fs 768fs 64fs
32.0kHz 8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 2.0480MHz
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 2.8224MHz
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 3.0720MHz
Table 3. System clock example (Normal Speed Mode @Manual Setting Mode)
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 12 -
LRCK MCLK BICK
fs 128fs 192fs 256fs 384fs 64fs
88.2kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz
96.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz
Table 4. System clock example (Double Speed Mode @Manual Setting Mode)
LRCK MCLK BICK
fs 128fs 192fs 64fs
176.4kHz 22.5792MHz 33.8688MHz 11.2896MHz
192.0kHz 24.5760MHz 36.8640MHz 12.2880MHz
Table 5. System clock example (Quad Speed Mode @Manual Setting Mode)
MCLK Sampling Speed
512fs 768fs Normal
256fs 384fs Double
128fs 192fs Quad
Table 6. Sampling Speed (Auto Setting Mode)
LRCK MCLK (MHz)
fs 128fs 192fs 256fs 384fs 512fs 768fs Sampling Speed
32.0kHz - - - - 16.3840 24.5760
44.1kHz - - - - 22.5792 33.8688
48.0kHz - - - - 24.5760 36.8640
Normal
88.2kHz - - 22.5792 33.8688 - -
96.0kHz - - 24.5760 36.8640 - - Double
176.4kHz 22.5792 33.8688 - - - -
192.0kHz 24.5760 36.8640 - - - - Quad
Table 7. System clock example (Auto Setting Mode)
Audio Serial Interface Format
Data is shifted in via the SDATA pin using BICK and LRCK inputs. Five data formats are supported and selected by the
DIF0-2 as shown in Table 8. In all formats the serial data is MSB-first, 2's compliment format and is latched on the rising
edge of BICK. Mode 2 can be used for 20 and 16 MSB justified formats by zeroing the unused LSBs.
Mode DIF2 DIF1 DIF0 Mode BICK Figure
0 0 0 0 0: 16bit LSB Justified ≥32fs Figure 1
1 0 0 1 1: 20bit LSB Justified ≥40fs Figure 2
2 0 1 0 2: 24bit MSB Justified ≥48fs Figure 3
3 0 1 1 3: I2S Compatible ≥48fs Figure 4
4 1 0 0 4: 24bit LSB Justified ≥48fs Figure 2
Table 8. Audio Data Formats
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 13 -
SDATA
BICK
LRCK
SDATA 15 14 6 5 4
BICK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
3210 1514
(
32fs
)
(
64fs
)
014
115 16 17 31 0 1 14 15 16 17 31 0 1
15 14 0 15 14 0
Mode 0 Don’t care Don’t care
15:MSB, 0:LSB
Mode 0 15 14 6 5 4 3 2 1 0
Lch Data Rch Data
Figure 1. Mode 0 Timing
SDATA
LRCK
BICK
(
64fs
)
091 10 11 12 31 0 1 9 10 11 12 31 0 1
19 0 19 0
Mode 1 Don’t care Don’t care
19:MSB, 0:LSB
SDATA
Mode 4
23:MSB, 0:LSB
20 19 0 20 19 0
Don’t care Don’t care
22 21 22 21
Lch Data Rch Data
8
23 23
8
Figure 2. Mode 1,4 Timing
LRCK
BICK
(
64fs
)
SDATA
0221 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 1 0 Don’t care23
Lch Data Rch Data
23 30 2222423 30
22 1 0 Don’t care
23 2223
Figure 3. Mode 2 Timing
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 14 -
LRCK
BICK
(
64fs
)
SDATA
031 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 10Don’t care
23
Lch Data Rch Data
23 25 322423 25
22 1 0Don’t care23 23
Figure 4. Mode 3 Timing
De-emphasis filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled with
DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always off.
DEM1 DEM0 Mode
0 0 44.1kHz Default
01OFF
1 0 48kHz
1 1 32kHz
Table 9. De-emphasis filter control (Normal Speed Mode)
Output Volume
The AK4395 includes channel independent digital output volumes (ATT) with 256 levels at 0.5dB steps including MUTE.
These volumes are in front of the DAC and can attenuate the input data from 0dB to –127dB and mute. When changing
levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions.
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
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Zero detection
The AK4395 has channel-independent zeros detect function. When the input data at each channel is continuously zeros for
8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input data
of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF pins of both
channels go to “L” at 4~5/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both channels go to “H”
only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect function can be
disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the polarity of DZF pin.
Soft mute operation
Soft mute operation is performed at digital domain. When SMUTE goes to “H”, the output signal is attenuated by -∞
during 1024 LRCK cycles. When SMUTE is returned to “L”, the mute is cancelled and the output attenuation gradually
changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the
operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SMUTE
Attenuation
DZF
1024/fs
0dB
-∞
AOUT
1024/fs
8192/fs
GD GD
(1)
(2)
(3)
(4)
Notes:
(1) The output signal is attenuated by -∞ during 1024 LRCK cycles (1024/fs).
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes
to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 5. Soft mute and zero detection
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 16 -
System Reset
The AK4395 should be reset once by bringing PDN = “L” upon power-up. The AK4395 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4395 is in the power-down
mode until MCLK and LRCK are input.
Power-Down
The AK4395 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z). Figure
6 shows an example of the system timing at the power-down and power-up.
Normal Operation
Internal
State
PDN
Power-down Normal Operation
GD GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, LRCK, BICK
(1) (3)
(6)
DZFL/DZFR
External
MUTE (5)
(3) (1)
Mute ON
(2)
(4)
Don’t care
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN = “L”).
Figure 6. Power-down/up sequence example
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 17 -
Reset Function
When RSTN = ”0”, the AK4395’s digital section is powered down but the internal register values are not initialized. The
analog outputs go to VCOM voltage and DZF pins of both channels go to “H”. Figure 7 shows the example of reset by
RSTN bit.
Internal
State
RSTN bit
Digital Block Power-down Normal Operation
GD GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK,LRCK,BICK
(1) (3)
DZFL/DZFR
(3) (1)
(2)
Normal Operation
2/fs(5)
Internal
RSTN bit
2~3/fs (6)3~4/fs (6)
Don’t care
(4)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage.
(3) Click noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0” data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN “1”.
Figure 7. Reset sequence example
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 18 -
Mode Control Interface
Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4395. For DIF0/1/2, the
setting of pin and register are “ORed” internally. So, even serial control mode, these functions can be also controlled by pin
setting.
The serial control interface is enabled by the P/S pin = “L”. In this mode, pin setting must be all “L”. Internal registers may
be written by 3-wire µP interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2bits,
CAD0/1), Read/Write (1bit; fixed to “1”), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). The
AK4395 latches the data on the rising edge of CCLK, so data should be clocked in on the falling edge. The writing of data
becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz (max). The CSN and CCLK must be fixed to “H” when the
register does not be accessed.
Function Parallel mode Serial mode
Auto Setting Mode O O
Manual Setting Mode O (Partially) O
De-emphasis O O
SMUTE O O
Zero Detection X O
Slow roll-off response X O
Digital Attenuator X O
Table 10. Function List (O: Available, X: Not available)
PDN = “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4395 should be reset by
PDN = “L”. In serial mode, the internal timing circuit is reset by RSTN bit, but the registers are not initialized.
CDTI
CCLK
C1
012345678 9 10 11 12 13 14 15
D4D5
D6
D7A1A2A3A4R/WC0 A0 D0D1D2D3
CSN
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 8. Control I/F Timing
*When the AK4395 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control register
is inhibited.
*For setting the registers, the following sequence is recommended.
Control 1 register
(1) Writing RSTN = “0” and other bits (D7-D1) to the register at the same time.
(2) Writing RSTN = “1” to the register. The other bits are no change.
Control 2 register
This writing sequence has no limitation like control 1 register.
When setting DEM0/1 and SMUTE, RSTN is not needed.
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
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Register Map
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 ACKS CKS2 CKS1 CKS0 DIF2 DIF1 DIF0 RSTN
01H Control 2 DZFE DZFM SLOW DFS1 DFS0 DEM1 DEM0 SMUTE
02H Output Gain GA1 GA0 0 0 0 DZFB 0 0
03H AOUTL ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H AOUTR ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
Notes:
For address from 05H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default values.
DIF0-2 bits are ORed with pins respectively.
Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 ACKS CKS2 CKS1 CKS0 DIF2 DIF1 DIF0 RSTN
default 10000001
RSTN: Internal timing reset
0: Reset. All registers are not initialized.
1: Normal Operation
When the states of CKS2-0 or DFS1-0 change, the AK4395 should be reset by PDN pin or RSTN bit.
DIF2-0: Audio data interface modes (see Table 8)
Initial: “000”, Mode 0
Register bits are ORed with DIF2-0 pins if P/S = “L”.
CKS2-0: Master Clock Frequency Select (see Table 2)
Initial: “000”, Mode 0
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of CKS2-0
and DFS1-0 are ignored. When this bit is “0”, CKS2-0 and DFS1-0 set the master clock frequency.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Control 2 DZFE DZFM SLOW DFS1 DFS0 DEM1 DEM0 SMUTE
default 00000010
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis response (see Table 9)
Initial: “01”, OFF
DFS1-0: Sampling Speed Control
00: Normal Speed Mode
01: Double Speed Mode
10: Quad Speed Mode
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
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SLOW: Slow Roll-off Filter Enable
0: Sharp Roll-off Filter
1: Slow Roll-off Filter
DZFE: Data Zero Detect Enable
0: Disable
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of all channels are
always “L”.
DZFM: Data Zero Detect Mode
0: Channel Separated Mode
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of all channels go to “H” only when the input data at all
channels are continuously zeros for 8192 LRCK cycles.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Output Gain GA1 GA0 0 0 0 DZFB 0 0
default 11000000
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
GA1-0: Output Gain Control
00: -1.16dB
01: -2.18dB
10: +1.34dB
11: 0dB
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H AOUTL ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H AOUTR ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
default 11111111
ATT7-0: Attenuation Level
256 levels, 0.5dB step
Data Attenuation
FFH 0dB
FEH -0.5dB
FDH -1.0dB
: :
: :
02H -126.5dB
01H -127.0dB
00H MUTE (-∞)
The transition between set values is soft transition of 7425 levels. It takes 7424/fs (168ms@fs=44.1kHz) from
FFH (0dB) to 00H (MUTE). If PDN pin goes to “L”, the ATTs are initialized to FFH. The ATTs are FFH when
RSTN = “0”. When RSTN return to “1”, the ATTs fade to their current value. This digital attenuator is
independent of soft mute function.
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 21 -
SYSTEM DESIGN
Figure 9 and 10 show the system connection diagram. The output filter circuits are shown in Figure 12 and Figure 13. An
evaluation board (AKD4395) is available which demonstrates the optimum layout, power supply arrangements and
measurement results.
DVSS
1
DVDD
2
MCLK
3
PDN
4
BICK
5
SDATA6
LRCK
7
CSN
8
CAD09
CCLK10
CDTI
11
DIF0
12
DZFR 28
CAD1 27
DZFL 26
P/S 25
VCOM 24
AOUTL+ 23
AOUTL- 22
AOUTR+ 21
AOUTR- 20
AVSS 19
AVDD 18
VREFH 17
Master Clock
Micro-
controller
0.1u10u
+
10u
0.1u +
10u
+Supply 5V
AK4395
0.1u
Digital
Supply 5V
13
14
16
15
DIF1
DIF2
VREFL
BVSS
fs
24bit Audio Data
Reset & Power down
64fs
10u
0.1u +
Lch
LPF
Rch
LPF Rch Out
Lch Out
Analog GroundDigital Ground
Lch
Mute
Rch
Mute
Analog
Figure 9. Typical Connection Diagram (Serial Mode, Chip Address = “00”)
Notes:
- LRCK = fs, BICK = 64fs.
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of
regulator etc.
- AVSS, BVSS and DVSS must be connected to the same analog ground plane.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins except pull-down/pull-up pins should not be left floating.
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
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DVSS
1
DVDD
2
MCLK
3
PDN
4
BICK
5
SDATA6
LRCK
7
SMUTE
8
DFS09
DEM010
DEM1
11
DIF0
12
ACKS 28
CKS1 27
CKS0 26
P/S 25
VCOM 24
AOUTL+ 23
AOUTL- 22
AOUTR+ 21
AOUTR- 20
AVSS 19
AVDD 18
VREFH 17
Master Clock
Mode
setting
0.1u10u
+
10u
0.1u +
10u
+Supply 5V
AK4395
0.1u
Digital
Supply 5V
13
14
16
15
DIF1
DIF2
VREFL
BVSS
fs
24bit Audio Data
Reset & Power down
64fs
10u
0.1u +
Lch
LPF
Rch
LPF Rch Out
Lch Out
Analog
Analog GroundDigital Ground
Master
Clock
Select
Figure 10. Typical Connection Diagram (Parallel mode)
Notes:
- LRCK = fs, BICK = 64fs.
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator
etc.
- AVSS, BVSS and DVSS must be connected to the same analog ground plane.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins except pull-down/pull-up pins should not be left floating.
Analog GroundDigital Ground
System
Controller
DVSS
1
DVDD
2
MCLK
3
PDN
4
BICK
5
SDATA6
LRCK
7
SMUTE
8
CAD09
DEM010
DEM1
11
DIF0
12
DZFR 28
CAD1 27
DZFL 26
P/S 25
VCOM 24
AOUTL+ 23
AOUTL- 22
AOUTR+ 21
AOUTR- 20
AVSS 19
AVDD 18
VREFH
AK4395
17
13
14
16
15
DIF1
DIF2
VREFL
BVSS
Figure 11. Ground Layout
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 23 -
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively.
AVDD is supplied from analog supply in system and DVDD is supplied from digital supply in system. If AVDD and
DVDD are supplied separately, the power up sequence is not critical. AVSS, BVSS and DVSS must be connected
to analog ground plane. System analog ground and digital ground should be connected together near to where the
supplies are brought onto the printed circuit board. Decoupling capacitors for high frequency should be placed as near as
possible.
2. Voltage Reference
The differential Voltage between VREFH and VREFL set the analog output range. VREFH pin is normally connected to
AVDD and VREFL pin is normally connected to AVSS. VREFH and VREFL should be connected with a 0.1µF ceramic
capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor
attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All
signals, especially clocks, should be kept away from the VREFH, VREFL and VCOM pins in order to avoid unwanted
coupling into the AK4395.
3. Analog Outputs
The analog outputs are full differential outputs and 2.4Vpp (typ@VREF=5V) centered around VCOM. The differential
outputs are summed externally, VAOUT = (AOUT+) - (AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the
output range is 4.8Vpp (typ@VREF=5V). The bias voltage of the external summing circuit is supplied externally. The
input data format is 2's complement. The output voltage (VAOUT) is a positive full scale for 7FFFFFH (@24bit) and a
negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H(@24bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband.
Figure 12 shows an example of external LPF circuit summing the differential outputs by an op-amp.
Figure 13 shows an example of differential outputs and LPF circuit example by three op-amps.
1k 1k
1k
1k 1k
1k 1n
+Vop
1n
-Vop
AOUT-
AOUT+
2.2n
Analog
Out
AK4395
Figure 12. External LPF Circuit Example 1
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 24 -
300
47u 300
AOUTL-
620
6.8n
330
200
6.8n
6
4
3
2
7
10u
0.1u
0.1u
10u
10u
NJM5534D
300
47u
300
AOUTL+
620
6.8n
330
200
6.8n
6
4
3
2
7
10u
0.1u
0.1u
10u
NJM5534D
32
1
100
100
0.1u +
NJM5534D
0.1u 10u
100
4
3
2
2.2n
620
620
470
7
+
+
++
-
+
-
+
+
+
-
+
+
2.2n
Lch
-15
+15
6
470
Figure 13. External LPF Circuit Example 2
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 25 -
PACKAGE
0.1±0.1
Detail A
Seating Plane
NOTE: Dimension "*" does not include mold flash.
0.10
0.15-0.05
0.22±0.1 0.65
*9.8±0.2 1.25±0.2
A
114
15
28
28
p
in VSOP
(
Unit: mm
)
*5.6
±0.2
7.6±0.2
0.5±0.2
+0.1
0.675
Material & Lead finish
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder plate
ASAHI KASEI [AK4395]
MS0040-E-01 2001/4
- 26 -
MARKING
AKM
AK4395VF
XXXBYYYYC
XXXXBYYYYC data code identifier
XXXB: Lot number (X : Digit number, B : Alpha character )
YYYYC: Assembly date (Y : Digit number C : Alpha character)
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or
other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.