166 4522B Programmable BCD Counter @ Rte TH WYP POY t Qt 16 VDD 2UT H Op, 2 15a, eas x PRESET ENABLE 14Dp3 ia Ba 13 CASCADE INHIBIT 4: FEEDBACK Dp; 54 120" CLOCK 6. 11 DP2 Q, ?. 10 CLEAR Vss 90, BA FY TRE @ 2-75 , Vdd [typ [max [Bir 1 RIA % & 7 SVT WoT Wt ns (277 | & * foe To + Ay MERERBCDY YY - AYP 1oV [50] 100 {ns [ar | HEWZ UT, TURK, BAUD FYE y ORME. 7 ey KADILE OTAY IPT ATG NT as | Se i tf iV 50| 100| ns [eee [osm |e = vetp tye oe te i5V{ 40] 80| ns | mm | Uppasz2ac ele + POSTINI Y, Yr eta PEATE S Tan v 173501 1100 T ns | Bay | Hbiaszze w (CLK. In > gy LOW 225] 450 [ns | a RHR [ Inpute Output Resutting 15V{ 160] 3201 ns | aT | mNa5208 ele Preset | Cascade} Function V1 350 | 1100 ns |= Clock Reset inhibit Enable | Feedback oO + PHL Vv 25 50 3 x x tom | x | ow | | ow [atteneneue rover (CLK, INH > TasvTten aeons [MOT [RTE e [Le synchronous reso x 4 x x 4 H_|{ Asynchronaus reset {PL V | 260} 520] ns }NS | CD4522B e x t x H x 1_| Asynchronous preset (Pn -> Q ) x 126 my ns RCA 1 inhibitec ns eI EL tft | otetaeniness nome: PL Vv ( 260] 520 [ns | S1G|HeraszP | | @ L L L L | No change** (inactive edge) | * Output "0" is low when reset goes high (Pn -> Q ) 1ov | 120{ 240] ns | SSS | ScL45228 H ec |Z L t L_ | No change" (inactive edge) | only if PE ana CF are low. 15V_| 100} 200/ ns Sf L L t L L | Decrement"? ** Qutput 0 ia high when reset is low, VDD | min | typ | Sir 4 ct Ne t L t | Decrement only if CF is nigh and count is 0000. VIL 2.0) Miz X= Dont Gare rep ov 3.0] 5.0 | Mi 16V] fol 6.6 | Miz