LY62W25616
Rev. 1.4 256K X 16 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
®
REVISION HISTORY
Revision Description Issue Date
Rev. 1.0 Initial Issue Mar.21.2008
Rev. 1.1 Revised FEATURES & ORDERING INFORMATION
Lead free and green package available to Green package av ailable
Added packing type in ORDERING INFORMATION
Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS
Revised PACKAGE OUTLINE DIMENSION in page 10
Revised VIH to 0.7*Vcc
Revised VDR to 1.5V
Ma
y
.7.2010
Rev. 1.2 Revised ORDERING INFORMATION in page 11
A
ug.25.2010
Rev. 1.3
A
dded SL Grade
Deleted E Grade
Revised ISB1/IDR
A
ug.9.2011
Rev. 1.4 Revised “Standby Power Supply Current” in page 3 April.30.2012
Revised “Data Retention Current” in page 8
LY62W25616
Rev. 1.4 256K X 16 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1
®
FEATURES
Fast access time : 55/70ns
Low power consumption:
Operating current : 30/20mA (TYP.)
Standby current : 4μA (TYP.) LL-version
3μA (TYP.) SL-version
Single 2.7V ~ 5.5V power supply
All outputs TTL compatible
Fully static operation
Tri-state output
Data byte control : LB# (DQ0 ~ DQ7)
UB# (DQ8 ~ DQ15)
Data retention voltage : 1.5V (MIN.)
Green package av ailable
Package : 44-pin 400 mil TSOP-II
48-ball 6mm x 8mm TFBGA
GENERAL DESCRIPTION
The LY62W25616 is a 4,194,304-bit low power
CMOS static random access memory organized as
262,144 words by 16 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
The LY62W25616 is well designed for low power
application, and particularly well suited for battery
back-up nonvolatile memory application.
The LY62W25616 operates from a single power
supply of 2.7V ~ 5.5V and all inputs and outputs are
fully TTL compatible
PRODUCT FAMILY
Product
Family Operating
Temperature Vcc Range Speed Power Dissipation
Standby(ISB1,TYP.) Operating(Icc,TYP.)
LY62W25616 0 ~ 70℃ 2.7 ~ 5.5V 55/70ns 4µA(LL)/3µA(SL) 30/20mA
LY62W25616(I) -40 ~ 85℃ 2.7 ~ 5.5V 55/70ns 4µA(LL)/3µA(SL) 30/20mA
FUNCTIONAL BLOCK DIAGRAM
CONTROL
CIRCUIT
CE#
WE#
OE#
DECODER 256Kx16
MEMORY ARRAY
COLUMN I/O
A0-A17
Vcc
Vss
DQ8-DQ15
Upper Byte
DQ0-DQ7
Lower Byte I/O DATA
CIRCUIT
LB#
UB#
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A17 Address Inputs
DQ0 – DQ15 Data Inputs/Outputs
CE# Chip Enable Input
WE# Write Enable Input
OE# Output Enable Input
LB# Lower Byte Control
UB# Upper Byte Control
VCC Power Supply
VSS Ground
LY62W25616
Rev. 1.4 256K X 16 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
2
®
PIN CONFIGURATION
TFBGA(Top View)
ABSOLUTE MAXIMUN RATINGS*
PARAMETER SYMBOL RATING UNIT
Voltage on VCC relative to VSS VT1 -0.5 to 6.5 V
Voltage on any other pin relative to VSS VT2 -0.5 to VCC+0.5 V
Operating Temperature TA 0 to 70(C grade) ℃
-40 to 85(I grade)
Storage Temperature TSTG -65 to 150 ℃
Power Dissipation PD 1 W
DC Output Current IOUT 50 mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
LY62W25616
Rev. 1.4 256K X 16 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
3
®
TRUTH TABLE
MODE CE# OE# WE# LB# UB# I/O OPERATION SUPPLY CURRENT
DQ0-DQ7 DQ8-DQ15
Standby H
X X
X X
X X
H X
H High – Z
High – Z High – Z
High – Z ISB1
Output Disable L
L H
H H
H L
X X
L High
–
Z
High – Z High
–
Z
High – Z ICC,ICC1
Read L
L
L
L
L
L
H
H
H
L
H
L
H
L
L
DOUT
High – Z
DOUT
High
–
Z
DOUT
DOUT ICC,ICC1
Write L
L
L
X
X
X
L
L
L
L
H
L
H
L
L
DIN
High – Z
DIN
High
–
Z
DIN
DIN ICC,ICC1
Note: H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITION MIN. TYP.
*
4
MAX. UNIT
Supply Voltage VCC 2.7 3.0 5.5 V
Input High Voltage VIH
*1
0.7*VCC - VCC+0.3 V
Input Low Voltage VIL
*2
- 0.2 - 0.6 V
Input Leakage Current ILI V
CC ≧ VIN ≧ VSS - 1 - 1
µA
Output Leakage
Current ILO VCC ≧ VOUT ≧VSS,
Output Disabled - 1 - 1 µA
Output High Voltage VOH I
OH = -1m
A
2.4 2.7 - V
Output Low Voltage VOL I
OL = 2m
A
- - 0.4 V
Average Operating
Power supply Current
ICC Cycle time = Min.
CE# = VIL , II/O = 0mA
Other pins at VIL or VIH
- 55 - 30 60 mA
- 70 - 20 50 mA
ICC1 Cycle time = 1µs
CE# = 0.2V , II/O = 0mA
Other pins at 0.2V or VCC - 0.2V - 4 10 mA
Standby Power
Supply Current ISB1 CE# V≧CC - 0.2V
Others at 0.2V or
VCC - 0.2V
LL/LLI - 4 50
µA
SL
*
5
SLI*5 25℃- 3 10
µA
40℃- 3 10
µA
SL/SLI - 3 25
µA
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical values are measured at VCC = VCC(TYP.) and TA = 25℃
5. This parameter is measured at VCC = 3.0V
LY62W25616
Rev. 1.4 256K X 16 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
®
CAPACITANCE (TA = 25 , f℃ = 1.0MHz)
PARAMETER SYMBOL MIN. MA
X
UNIT
Input Capacitance CIN -6 pF
Input/Output Capacitance CI/O -8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0.2V to VCC -0.2V
Input Rise and Fall Times 3ns
Input and Output Timing Reference Levels 1.5V
Output Load CL= 30pF + 1TTL, IOH
/
IOL = -1mA/2m
A
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER SYM. LY62W25616-55 LY62W25616-70
UNIT
MIN. MAX. MIN. MAX.
Read Cycle Time tRC 55 - 70 - ns
A
ddress Access Time tAA - 55 - 70 ns
Chip Enable Access Time tACE - 55 - 70 ns
Output Enable Access Time tOE - 30 - 35 ns
Chip Enable to Output in Low-Z tCLZ* 10 - 10 - ns
Output Enable to Output in Low-Z tOLZ* 5 - 5 - ns
Chip Disable to Output in High-Z tCHZ* - 20 - 25 ns
Output Disable to Output in High-Z tOHZ* - 20 - 25 ns
Output Hold from Address Change tOH 10 - 10 - ns
LB#, UB#
A
ccess Ti me tBA - 55 - 70 ns
LB#, UB# to High-Z Output tBHZ* - 25 - 30 ns
LB#, UB# to Low-Z Output tBLZ* 10 - 10 - ns
(2) WRITE CYCLE
PARAMETER SYM. LY62W25616-55 LY62W25616-70 UNIT
MIN. MAX. MIN. MAX.
Write Cycle Time
t
WC 55 - 70 - ns
A
ddress Valid to End of Write tAW 50 - 60 - ns
Chip Enable to End of Write tCW 50 - 60 - ns
A
ddress Set-up Time tAS 0-0- ns
Write Pulse Width
t
WP 45 - 55 - ns
Write Recovery Time
t
WR 0-0- ns
Data to Write Time Overlap tDW 25 - 30 - ns
Data Hold from End of Write Time tDH 0-0- ns
Output Active from End of Write tOW* 5-5- ns
Write to Output in High-Z
t
WHZ* - 20 - 25 ns
LB#, UB# Valid to End of Write tBW 45 - 60 - ns
*These parameters are guaranteed by device characterization, but not production tested.
LY62W25616
Rev. 1.4 256K X 16 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
5
®
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
Dout Data Valid
tOHtAA
Address
tRC
Previous Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
Dout Data Valid High-ZHigh-Z
tCLZ
tOLZ
tCHZ
tOHZ
tOH
OE#
tOE
LB#,UB#
tBHZ
tACE
CE#
tAA
Address
tRC
tBA
tBLZ
Notes :
1.WE#is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low.
3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter.
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.
LY62W25616
Rev. 1.4 256K X 16 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
6
®
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
Dout
Din Data Valid
tDW tDH
(4) High-Z
tWHZ
WE#
tWP
tCW
tWRtAS
(4)
TOW
LB#,UB#
CE#
tAW
Address
tWC
tBW
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
Dout
Din Data Valid
tDW tDH
(4) High-Z
tWHZ
WE#
LB#,UB#
tCW
CE#
Address
tWRtAS
tAW
tWC
tWP
tBW
LY62W25616
Rev. 1.4 256K X 16 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7
®
WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6)
Dout
Din Data Valid
tDW tDH
(4) High-Z
tWHZ
WE#
LB#,UB#
tCW
CE#
Address
tWR
tAS
tAW
tWC
tWP
tBW
Notes :
1.WE#,CE#, LB#, UB# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance
state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
LY62W25616
Rev. 1.4 256K X 16 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
®
DATA RETENTION CHARACTERISTICS
PARAMETER SYMBO
L
TEST CONDITION MIN. TYP. MAX. UNIT
VCC for Data Retention VDR CE# V≧CC - 0.2V 1.5 - 5.5 V
Data Retention Current IDR VCC = 1.5V
CE# V≧CC - 0.2V
Others at 0.2V or VCC-0.2V
LL/LLI - 2 30
µA
SL
SLI 25℃- 2 8
µA
40℃- 2 8
µA
SL/SLI - 2 23
µA
Chip Disable to Data
Retention T i me tCDR See Data Retention
Waveforms (below) 0 - - ns
Recovery Time tR t
RC*- - ns
tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1 ) (CE# controlled)
Vcc
CE#
VDR ≧1.5V
CE# V≧cc-0.2V
Vcc(min.)
VIH
tRtCDR
VIH
Vcc(min.)
Low Vcc Data Retention Waveform (2 ) (LB#, UB# controlled)
Vcc
LB#,UB#
VDR ≧1.5V
LB#,UB# V≧cc-0.2V
Vcc(min.)
VIH
tRtCDR
VIH
Vcc(min.)
LY62W25616
Rev. 1.4 256K X 16 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9
®
PACKAGE OUTLINE DIMENSION
44-pin 400mil TSOP-Ⅱ Package Outline Dimension
SYMBOLS DIMENSIONS IN MILLMETERS DIMENSIONS IN MILS
MIN. NOM. MAX. MIN. NOM. MAX.
A - - 1.20 - - 47.2
A1 0.05 0.10 0.15 2.0 3.9 5.9
A2 0.95 1.00 1.05 37.4 39.4 41.3
b 0.30 - 0.45 11.8 - 17.7
c 0.12 - 0.21 4.7 - 8.3
D 18.212 18.415 18.618 717 725 733
E 11.506 11.760 12.014 453 463 473
E1 9.957 10.160 10.363 392 400 408
e - 0.800 - - 31.5 -
L 0.40 0.50 0.60 15.7 19.7 23.6
ZD - 0.805 - - 31.7 -
y - - 0.076 - - 3
Θ 0
o 3
o 6
o 0
o 3
o 6
o
LY62W25616
Rev. 1.4 256K X 16 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10
®
48-ball 6mm × 8mm TFBGA Package Outline Dimension
LY62W25616
Rev. 1.4 256K X 16 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
11
®
ORDERING INFORMATION
LY62W25616
Rev. 1.4 256K X 16 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
12
®
THIS PAGE IS LEFT BLANK INTENTIONALLY.
