LTC3625/LTC3625-1 1A High Efficiency 2-Cell Supercapacitor Charger with Automatic Cell Balancing Features n n n n n n n n n Description High Efficiency Step-Up/Step-Down Charging of Two Series Supercapacitors Automatic Cell Balancing Prevents Capacitor Overvoltage During Charging Programmable Charging Current Up to 500mA (Single Inductor), 1A (Dual Inductor) VIN = 2.7V to 5.5V Selectable 2.4V/2.65V Regulation per Cell (LTC3625) Selectable 2V/2.25V Regulation per Cell (LTC3625-1) Low No-Load Quiescent Current: 23A IVOUT, IVIN < 1A in Shutdown Low Profile 12-lead 3mm x 4mm DFN Package Applications n n n n The LTC(R)3625/LTC3625-1 are programmable supercapacitor chargers designed to charge two supercapacitors in series to a fixed output voltage (4.8V/5.3V or 4V/4.5V selectable) from a 2.7V to 5.5V input supply. Automatic cell balancing prevents overvoltage damage to either supercapacitor while maximizing charge rate. No balancing resistors are required. High efficiency, high charging current, low quiescent current and low minimum external parts count (one inductor, one bypass capacitor at VIN and one programming resistor) make the LTC3625/LTC3625-1 ideally suited for small form factor backup or high peak power systems. Charging current/maximum input current level is programmed with an external resistor. When the input supply is removed and/or the EN pin is low, the LTC3625/LTC3625-1 automatically enter a low current state, drawing less than 1A from the supercapacitors. Servers, RAID Systems, Mass Storage, High Current Backup Supplies Solid State Hard Drives Wireless Power Meters High Peak Power Boosted Supplies L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. The LTC3625/LTC3625-1 are available in a compact 12lead 3mm x 4mm x 0.75mm DFN package. Typical Application 1A SCAP Charger VIN 10F LTC3625 SW2 SW1 PROG 6 VOUT 3.3H 3.3H VMID PGOOD PFO CTOP = 50F CBOT = 100F RPROG = 61.9k CTL = 0 VSEL = 0 5 CTOP 0.1F CBOT 0.1F 61.9k PFI EN CTL VSEL VOUT 4.8V VOLTAGE (V) VIN 2.7V TO 5.5V Charging Two 2:1 Mismatched Supercapacitors 4 VOUT 3 VMID 2 1 3625 TA01a 0 0 20 40 60 80 100 120 140 160 180 200 TIME (SECONDS) 3625 TA01b 3625f LTC3625/LTC3625-1 Absolute Maximum Ratings (Note 1) Pin Configuration VIN, VOUT (Transient) t < 1ms, Duty Cycle < 1%........................................... -0.3V to 7V VIN, VOUT, VMID, PGOOD, CTL, PROG, PFI, PFO.................................... -0.3V to 6V EN, VSEL. .......................................... -0.3V to VIN + 0.3V VOUT Short-Circuit Duration.............................. Indefinite IPGOOD, IPFO............................................................50mA IPROG. .......................................................................1mA IVIN, ISW1, ISW2, IVOUT (Note 2)....................................3A Operating Junction Temperature Range (Notes 3, 4)............................................. -40C to 125C Storage Temperature Range................... -65C to 125C TOP VIEW SW1 1 12 SW2 VIN 2 11 VOUT CTL 3 VSEL 4 9 PGOOD EN 5 8 PFO PROG 6 7 PFI 13 GND 10 VMID DE PACKAGE 12-LEAD (4mm s 3mm) PLASTIC DFN TJMAX = 125C, JA = 43C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3625EDE#PBF LTC3625EDE#TRPBF 3625 -40C to 125C 12-Lead (4mm x 3mm) Plastic DFN LTC3625EDE-1#PBF LTC3625EDE-1#TRPBF 36251 -40C to 125C 12-Lead (4mm x 3mm) Plastic DFN LTC3625IDE#PBF LTC3625IDE#TRPBF 3625 -40C to 125C 12-Lead (4mm x 3mm) Plastic DFN LTC3625IDE-1#PBF LTC3625IDE-1#TRPBF 36251 -40C to 125C 12-Lead (4mm x 3mm) Plastic DFN Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C. VIN = 3.6V, RPROG = 143k, unless otherwise specified. SYMBOL PARAMETER VIN Input Voltage Range VIN(UVLO) Input Undervoltage Lockout (VIN Rising) CONDITIONS MIN VSEL = VIN (LTC3625) VSEL = 0V (LTC3625) VSEL = 0V or VIN (LTC3625-1) l VIN(UVLO) l 2.8 l 2.53 l 2.53 Charger Termination Voltage VSEL = VIN (LTC3625) VSEL = 0V (LTC3625) VSEL = VIN (LTC3625-1) VSEL = 0V (LTC3625-1) l l l l Recharge Hysteresis Below VOUT(SLEEP) Input UVLO Hysteresis VOUT(SLEEP) VTOP , VBOT 2.9 2.63 2.63 MAX CTL = 0V CTL = VIN 5.2 4.7 4.4 3.9 5.3 4.8 4.5 4.0 V 3.0 2.73 2.73 V V V mV 5.4 4.9 4.6 4.1 135 l l l l UNITS 5.5 100 Maximum Voltage Across Either of VSEL = VIN, VOUT = 5.3V (LTC3625) the Supercapacitors After Charging VSEL = 0V, VOUT = 4.8V (LTC3625) VSEL = VIN, VOUT = 4.5V (LTC3625-1) VSEL = 0V, VOUT = 4V (LTC3625-1) Maximum Supercapacitor Offset After Charging TYP V V V V mV 2.7 2.45 2.3 2.05 2.75 2.5 2.35 2.1 V V V V 100 50 180 120 mV mV 3625f LTC3625/LTC3625-1 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C. VIN = 3.6V, RPROG = 143k, unless otherwise specified. SYMBOL PARAMETER CONDITIONS TYP MAX UNITS IVIN Input Operating Current, ISW1 = ISW2 = 0A, No Switching CTL = VIN, VMID = 1.5V, VOUT = 2.5V (Boost Only) CTL = VIN, VMID = 1.5V, VOUT = 3.5V (Buck Only) CTL = 0, VMID = 1.5V, VOUT = 2.5V (Buck and Boost) 135 275 365 200 400 530 A A A Input Sleep Current VIN = 5.5V, VOUT = 5.4V VIN = 3.6V, VOUT = 5.4V 23 8 35 15 A A Input SD Current VOUT = 0V 0 1 A IVOUT MIN VOUT SD Current VOUT = 5.4V 0 1 A VOUT Sleep Current VOUT = 5.4V, VIN = 3.6V, EN = VIN VOUT = 5.4V, VIN = 5.5V, EN = VIN 17 1 25 2.5 A A VOUT = 3.5V, VMID = 1.5V 1.2 1.23 V VPROG PROG Servo Voltage hPROG Ratio of Measured IPROG Current to IBUCK Programmed Current IBUCK Programmed Buck Charge Current RPROG = 143k (Note 5) RPROG = 71.5k (Note 5) 0.88 1.76 0.99 1.98 1.10 2.20 A A IMAX Maximum Programmed Charge Current RPROG = 0 (Fault Condition) (Note 5) 1.98 2.65 3.31 A VMID(GOOD) VMID Voltage Where the Boost Regulator is Enabled 1.35 V VMID(GOOD) Hysteresis 150 mV VMID V VTRICKLE VOUT Voltage Above Which Boost Regulator Will Exit Trickle Charge Mode and Enter Normal Charge Mode l 1.17 118,000 VOUT Rising VTRICKLE Falling Hysteresis 50 mV IPEAK(BUCK) Buck Charge Current Peak 1.1 * IBUCK A IVALLEY(BUCK) Buck Charge Current Valley 0.9 * IBUCK A IPEAK(BOOST) Boost Charge Current Peak VOUT = 3V, VMID = 2V (Note 5) VOUT = 1V, VMID = 2V (Note 5) 1.59 2.12 200 2.65 A mA IVALLEY(BOOST) Boost Charge Current Valley VOUT = 3V, VMID = 2V VOUT = 1V, VMID = 2V 1.41 1.88 0 2.35 A mA Maximum Boost Valley Time VOUT = 1V, VMID = 2V 6.5 s RPMOS PMOS On-Resistance 120 m RNMOS NMOS On-Resistance 100 m ILEAK SW Pin Leakage Current for SW1, SW2 VPFI IPFI EN = 0V PFI Falling Threshold 1 l 1.17 1.2 PFI Hysteresis 15 Pin Leakage Current for PFI Pin 0 1.23 A V mV 30 nA 0.4 V 1 A Logic (EN, CTL, VSEL, PGOOD, PFO) VIL Input Low Logic Voltage EN, CTL, VSEL Pins l l VIH Input High Logic Voltage EN, CTL, VSEL Pins IIL, IIH Input Low, High Current for CTL CTL RPD EN Pin Pull-Down Resistance VSEL Pin Pull-Down Resistance EN = VIN VOL Output Low Logic Voltage PGOOD, PFO Pins; Sinking 5mA IOH Logic High Leakage Current PGOOD, PFO Pins; Pin Voltage = 5V PGOOD Rising Threshold VOUT as a Percentage of Final Target PGOOD Hysteresis VOUT as a Percentage of Final Target 1.2 l 90 V 4.5 M 4.5 M 70 200 mV 1 A 92.5 95 % 3 % 3625f LTC3625/LTC3625-1 Electrical Characteristics Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3625/LTC3625-1 internal switches are guaranteed to survive up to 3A of peak current. Internal current limits will restrict peak current to lower levels. Note 3: The LTC3625/LTC3625-1 are tested under pulsed load conditions such that TJ TA. The LTC3625E/LTC3625E-1 are guaranteed to meet specifications from 0C to 85C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3625I/LTC3625I-1 are guaranteed over the -40C to 125C operating junction temperature range. The junction temperature (TJ in C) is calculated from the ambient temperature (TA in C) and power dissipation (PD in Watts) according to the formula: TJ = TA + (PD * JA) where JA (in C/W) is the package thermal impedance. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability or permanently damage the device. Note 5: Measurements are tested with CTL = 0V. Typical Performance Characteristics TA = 25C, L1 = 3.3H, L2 = 3.3H, CIN = 10F, CTOP = CBOT , LTC3625 unless otherwise specified. 2.0 1.5 Input and Output Sleep Currents vs Temperature 25 VIN = 3.6V VIN = 3.6V VSEL = 3.6V LTC3625 IVOUT VOUT = 5.3V 20 0.5 SLEEP THRESHOLD 0 WAKE THRESHOLD -0.5 CURRENT (A) 1.0 OFFSET (%) 25 15 10 Sleep Current vs VIN VOUT = 4.8V VSEL = 0V 20 CURRENT (A) Charge Termination Error vs Temperature LTC3625-1 IVOUT VOUT = 4.5V IVOUT 15 10 IVIN IVIN -1.0 5 5 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 0 -1.5 -2.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 3625 G13 1200 VIN = 3.6V RPROG = 143k 1.195 2500 5.5 5.1 IPROG CLAMPED VIN = 3.6V VMID = 2V CTL = 0V 2000 1050 1000 1500 950 IVALLEY 1000 1.190 900 1.185 850 1.180 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 800 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 3625 G02 4.7 Buck Output Current vs RPROG 1100 CURRENT (mA) VPROG (V) 1.210 3000 IPEAK 1150 1.200 3.9 4.3 VIN (V) 3625 G01 Buck Current Limits vs Temperature 1.205 3.5 IBUCK (mA) 1.215 3.1 3625 G14 PROG Voltage and PFI Falling Threshold vs Temperature 1.220 2.7 500 VIN = 3.6V RPROG = 143k 3625 G03 0 0 50 100 150 200 250 300 350 400 450 500 RPROG (k) 3625 G04 3625f LTC3625/LTC3625-1 Typical Performance Characteristics TA = 25C, L1 = 3.3H, L2 = 3.3H, CIN = 10F, CTOP = CBOT , LTC3625 unless otherwise specified. Buck Input Power vs RPROG VIN = 5.5V VMID = 2.65V CTL = 0V VSEL = VIN 5 4 3 85 80 75 70 65 60 1 0 55 VIN = 3.6V VMID = 2V CTL = 0V 50 200 50 100 150 200 250 300 350 400 450 500 RPROG (k) 0 700 Buck Efficiency vs VMID 1700 1200 IBUCK (mA) RPROG = 143k 2 RPROG = 286k 0.2 0.6 1.0 1.4 1.8 VMID (V) 2.2 VIN = 5.5V VSEL = VIN CTL = 0 2.6 3625 G07 Buck Output Current vs VMID Boost Input Current vs VTOP 2500 2250 RPROG = 71.5k 2000 NORMAL OPERATION 2000 1750 RPROG = 71.5k RPROG = 143k 70 1250 RPROG = 286k RPROG = 143k 1000 60 750 500 250 0.2 0.6 1.0 1.4 1.8 VMID (V) 2.2 0 2.6 Boost Efficiency vs VTOP 0.2 0.6 1.0 1.4 1.8 VMID (V) 0 0.5 1.0 1.5 PMOS RDS(ON) () 2.0 2.5 VTOP (V) 3625 G11 1.0 1.5 2.0 2.5 Charge Time vs RPROG 400 0.25 0.20 PMOS VIN = 3.6V VSEL = 3.6V VOUT INITIAL = 0V CTOP = CBOT = 10F 0.10 0.05 0.15 NMOS 0.10 VIN = 2.7V VIN = 5.5V 0 0.05 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 3625 G12 300 NMOS RDS(ON) () VIN = 3.6V VMID = 2.5V VTOP = VOUT - VMID CTL = 0 0.5 0 3625 G10 350 VOUT TRICKLE CHARGE OPERATION VIN = 3.6V VMID = 2.5V VTOP = VOUT - VMID CTL = 0 VTOP (V) RFET vs Temperature 0.15 30 20 -1.5 -1.0 -0.5 0 -1.5 -1.0 -0.5 2.6 2.2 NORMAL OPERATION 40 VOUT TRICKLE CHARGE OPERATION 500 VIN = 5.5V VSEL = VIN CTL = 0 0.20 70 50 1000 3625 G09 90 80 1500 RPROG = 286k 3625 G08 60 IBOOST (mA) 1500 50 EFFICIENCY (%) 3 0 2200 2500 80 40 RPROG = 71.5k 3625 G06 IBUCK (mA) EFFICIENCY (%) 90 4 1 3625 G05 100 VIN = 5.5V VSEL = VIN CTL = 0 5 90 2 Buck Input Power vs VMID 6 95 EFFICIENCY (%) INPUT POWER (W) 6 Buck Efficiency vs IBUCK INPUT POWER (W) IPROG CLAMPED 7 100 TIME (SECONDS) 8 250 SINGLE INDUCTOR APPLICATION 200 150 100 IPROG CLAMPED 50 0 0 DUAL INDUCTOR APPLICATION 50 100 150 200 250 300 350 400 450 500 RPROG (k) 3625 G15 3625f LTC3625/LTC3625-1 Typical Performance Characteristics TA = 25C, L1 = 3.3H, L2 = 3.3H, CIN = 10F, CTOP = CBOT , LTC3625 unless otherwise specified. VMID SINGLE INDUCTOR APPLICATION 0 6 VOUT 4 VMID 2 0 DUAL INDUCTOR APPLICATION 0 20 40 60 80 100 120 TIME (SECONDS) 140 Charge Profile with CTOP > CBOT VOUT VIN = 3.6V, VSEL = 3.6V RPROG = 143k 4 C TOP = 10F, CBOT = 50F VMID 2 SINGLE INDUCTOR APPLICATION 0 6 VOUT 4 VMID 2 0 DUAL INDUCTOR APPLICATION 0 50 100 150 200 250 TIME (SECONDS) 3625 G16 SINGLE INDUCTOR VOLTAGE (V) 2 VOUT 6 DUAL INDUCTOR VOLTAGE (V) VIN = 3.6V, VSEL = 3.6V RPROG = 143k CTOP = CBOT = 10F 4 Charge Profile with CBOT > CTOP SINGLE INDUCTOR VOLTAGE (V) 6 DUAL INDUCTOR VOLTAGE (V) DUAL INDUCTOR VOLTAGE (V) SINGLE INDUCTOR VOLTAGE (V) Charge Profile Into Matched SuperCaps 6 VIN = 3.6V, VSEL = 3.6V RPROG = 143k 4 C TOP = 50F, CBOT = 10F 2 VOUT VMID SINGLE INDUCTOR APPLICATION 0 6 VOUT 4 VMID 2 0 DUAL INDUCTOR APPLICATION 0 50 100 150 200 250 300 350 TIME (SECONDS) 3625 G17 3625 G18 Pin Functions SW1 (Pin 1): Switch Pin for the Buck Regulator. External inductor connects between SW1 pin and VMID. VIN (Pin 2): Input Voltage Pin. Bypass to GND with a 10F or larger ceramic capacitor. CTL (Pin 3): Logic Input. CTL sets the charge mode of the LTC3625/LTC3625-1. A logic high at CTL programs the part to operate with a single inductor; a logic low programs the part to operate with two inductors. In the 2-inductor application the capacitor stack will charge approximately twice as quickly. CTL is a high impedance input and must be tied to either VIN or GND. Do not float. VSEL (Pin 4): Logic Input. VSEL selects the output voltage of the LTC3625/LTC3625-1. A logic low at VSEL sets the per-cell maximum voltage to 2.45V/2.05V (VOUT = 4.8V/4.0V); a logic high sets the per-cell maximum voltage to 2.70V/2.30V (VOUT = 5.3V/4.5V). When the part is enabled, VSEL has a 4.5M internal pull-down resistor; if EN is low, then VSEL is a high impedance input pin. EN (Pin 5): Logic Input. Enables the LTC3625/LTC3625-1. Active high. Has a 4.5M internal pull-down resistor. PROG (Pin 6): Charge Current Program Pin. Connecting a resistor from PROG to ground programs the buck output current. This pin servos to 1.2V. PFI (Pin 7): Input to the Power Fail Comparator. This pin connects to an external resistor divider between VIN and GND. If this functionality is not desired, PFI should be tied to VIN. PFO (Pin 8): Open-Drain Output of the Power-Fail Comparator. The part pulls this pin low if VIN is less than a value programmed by an external divider. This pin is active low in shutdown mode. If this functionality is not desired PFO should be left unconnected. PGOOD (Pin 9): Logic Output. This is an open-drain output which indicates that VOUT has settled to its final value. Upon start-up, this pin remains low until the output voltage, VOUT , is within 92.5% (typical) of its final value. Once VOUT is valid, PGOOD becomes high impedance. If VOUT falls to 89.5% (typical) of its correct regulation level, PGOOD is pulled low. PGOOD may be pulled up through an external resistor to an appropriate reference level. This pin is active low in shutdown mode. 3625f LTC3625/LTC3625-1 Pin Functions VMID (Pin 10): Midpoint of Two Series Supercapacitors. The pin voltage is monitored and used, along with VOUT , to enable or shut down the buck and boost converters during charging to achieve voltage balancing of the top and bottom supercapacitors. SW2 (Pin 12): Switch Pin for the Boost Regulator. External inductor connects between the SW2 pin and VMID. If CTL is logic high, then SW2 must be connected to SW1. GND (Exposed Pad Pin 13): Ground. The exposed pad must be connected to a continuous ground plane on the printed circuit board directly under the LTC3625/ LTC36251 for electrical contact and to achieve rated thermal performance. VOUT (Pin 11): Output Voltage Pin. Connect VOUT to the positive terminal of the top supercapacitor. The pin voltage is monitored and used, along with VMID, to enable or shut down the buck and boost converters during charging to achieve voltage balancing of the top and bottom supercapacitors. Block Diagram 7 8 PFI PFO + - 1.20V BOOST REGULATOR PGOOD + 9 - 4 10 VSEL VMID VOUT 2A AVG INPUT CURRENT SYNCHRONOUS BOOST CURRENT REGULATOR SD_BOOST 4.44V/4.90V (LTC3625) 3.7V/4.16V (LTC3625-1) THRESHOLD DETECTOR VIN VOUT SW2 VMAXER VIN 3 CTL OVERTEMPERATURE SHUTDOWN 6 REF/R PROGRAMMED AVG OUTPUT CURRENT SYNCHRONOUS BUCK CURRENT REGULATOR EN MASTER LOGIC PROG VMID_GOOD SD_BUCK 1.2V 12 C BUCK REGULATOR 5 11 D A SW1 2 1 B + - - + GND 13 3625 BD 3625f LTC3625/LTC3625-1 Operation The LTC3625/LTC3625-1 are dual cell supercapacitor chargers. Their unique topology charges two series connected capacitors to a fixed output voltage with programmable charging current without overvoltaging either of the cells -- even if they are severely mismatched. No balancing resistors are required. The LTC3625/LTC3625-1 include an internal buck converter between VIN and VMID to regulate the voltage on CBOT (across the bottom capacitor) as well as an internal boost converter between VMID and VOUT to regulate the voltage on CTOP (across the top capacitor). The output current of the buck converter is user-programmed via the PROG pin and the input current of the boost converter is set at 2A (typical). Table 1 indicates the various functions of the LTC3625/ LTC3625-1 that can be digitally controlled. Table 1. Digital Input Functions PIN VALUE CTL* 0 Part runs in 2-inductor application 1 Part runs in 1-inductor application 0 4.8V/4.0V sleep threshold 1 5.3V/4.5V sleep threshold 0 Part shuts down, VOUT becomes high impedance 1 Part enables and regulates the output VSEL EN FUNCTION *CTL pin must be hard tied to either VIN or GND. VIN Undervoltage Lockout (UVLO) An internal undervoltage lockout circuit monitors VIN and keeps the LTC3625/LTC3625-1 disabled until VIN rises above 2.90V/2.63V (typical) if VSEL is high or 2.63V/2.63V (typical) if VSEL is low. Hysteresis on the UVLO turns off the LTC3625/LTC3625-1 if VIN drops by approximately 100mV below the UVLO rising threshold. When in UVLO, only current needed to detect a valid input will be drawn from VIN and VOUT . Buck Converter The buck converter regulates a user-programmed average output current given by: IBUCK = hPROG * 1.2V RPROG where hPROG = 118,000 (typical). The buck converter regulates the current hysteretically by switching on the buck PMOS until a peak current limit is reached and then turning on the buck NMOS until a valley current limit is reached. In the single inductor application the boost NMOS is used in conjunction with the buck NMOS to increase efficiency at high currents. The forward current limit is set to 1.1 * IBUCK (typical) and the valley current limit is set to 0.9 * IBUCK (typical). Because of this method of regulation, overcurrent limit and reverse-current limit protection is automatically provided. The LTC3625/ LTC3625-1 will continue to regulate its programmed current even into a grounded output. In fault conditions where the PROG pin is shorted to ground, or RPROG is conductive enough to program IBUCK to operate outside of specification, the current out of the PROG pin will be clamped to 22.5A (typical) and IBUCK will be set to 2.65A (typical). If input current limit is not a concern, the PROG pin may be grounded to minimize charge times. Boost Converter The boost converter regulates a fixed average input current of 2A (typical). The current is regulated hysteretically by switching on the boost NMOS until the peak current limit of 2.12A (typical) is reached, and turning on the boost PMOS until the valley current limit of 1.88A (typical) is reached. In the single inductor application the buck NMOS is used in conjunction with the boost NMOS to increase efficiency. Because of this method of regulation, overcurrent limit and reverse-current limit protection is automatically provided. In normal operation VOUT will increase with VMID so VOUT should never be below VMID. In the case where there is a reverse voltage on CTOP due to a faulty precondition or a large load on the output, the boost converter will operate in trickle charge mode. In this mode the boost PMOS gate will remain high and instead allow the SW2 node to increase until SW2 VMAX + 1V to allow a higher reverse voltage across the inductor, and the current is ramped down to 0mA. This will result in a less efficient charge delivery through the PMOS. To keep dissipation low, IPEAK is limited to 200mA (typical). In this mode the discharge phase is terminated if it lasts longer than 6.5s (typical). The boost converter is disabled if VMID falls below the VMID(GOOD) hysteresis threshold of 1.2V (typical). 3625f LTC3625/LTC3625-1 Operation Single Inductor Operation With the CTL pin tied to VIN the LTC3625/LTC3625-1 will operate in single inductor mode. In this mode the same inductor serves in the power path for both the buck and the boost converters. Thus, the buck converter and boost converter will never run simultaneously. Under certain conditions with a single inductor, a small amount of current can flow from the supercapacitors to VIN when the boost charger is active. A 25mA load is required on VIN to prevent the VIN supply from being pumped to a higher voltage while the boost is active. This minimum load is not needed in the two inductor application and it is also not needed when the charger is disabled. A typical charge cycle for a fully discharged capacitor stack will proceed as follows: the inductor current reaches 0mA. This optimizes charge delivery to the output capacitors. Charge time is dependant on the programmed buck output current as well as the value of the supercapacitors being charged. For estimating charge profiles in the single inductor application, see the Typical Performance Characteristics graph Charge Time vs RPROG. The effective average VOUT referred charge current can be approximated as: ICHARGE 0.5 * IBUCK * BOOST * 2A IBUCK + 2A where BOOST is the boost converter efficiency, which is typically about 85% (see the Typical Performance Characteristics graph Boost Efficiency vs VTOP). 1. The buck converter will turn on and regulate its output current ramping hysteretically between 1.1 * IBUCK and 0.9 * IBUCK until the VMID(GOOD) threshold is met (1.35V typical). Seen another way, this is the maximum steady-state load the part can support without losing VOUT regulation. 2. Once the VMID(GOOD) threshold is reached, the boost converter will turn on and regulate its input current ramping hysteretically between 2.12A and 1.88A until VMID falls below the VMID(GOOD) hysteresis threshold (1.2V typical). With the CTL pin tied to GND, the LTC3625/LTC3625-1 will operate in dual inductor mode. In this mode two inductors will serve as the power path for the buck and the boost converters. This will allow both the buck and the boost converter to run simultaneously. As a result, the total charge time will be greatly reduced at the cost of an additional board component. 3. Phases 1 and 2 will alternate until VOUT is approximately 2.4V. When VTOP (equal to VOUT - VMID) is approximately 50mV > VMID, the boost regulator will turn off and the buck regulator will turn on. Likewise, when VMID is approximately 50mV > VTOP , the boost regulator will turn on and the buck regulator will turn off. 4. Phase 3 will continue until VOUT has reached its programmed output voltage. Once this happens, the part will enter sleep mode and only minimal power will be consumed (see the Electrical Characteristics table). 5. If the supercapacitors' self discharge or an external load cause the output to drop by more than 135mV (typical), then the LTC3625/LTC3625-1 will exit sleep mode and begin charging the appropriate supercapacitor. In all cases whenever either of the converters is shut down, it will switch to its appropriate discharge phase (NMOS on for the buck and PMOS on for the boost) until Dual Inductor Operation A typical charge cycle for a fully discharged capacitor stack will proceed as follows: 1. The buck converter will turn on and regulate its output current ramping hysteretically between 1.1 * IBUCK and 0.9 * IBUCK until the VMID(GOOD) threshold is met (1.35V typical). 2. Once the VMID(GOOD) threshold is reached, the boost converter will turn on and regulate its input current ramping hysteretically between 2.12A and 1.88A. The buck converter will continue to run at the same time. In some cases (IBUCK ~ <1A) the boost converter's input current will exceed the current delivered to CBOT ; even though the buck converter is running, charge will be removed and VMID may decrease. Thus, if VMID falls below the VMID(GOOD) hysteresis threshold, the boost 3625f LTC3625/LTC3625-1 Operation converter will turn off. Once VMID has again risen above the VMID(GOOD) threshold, the boost converter will be re-enabled. In the case where VOUT < VMID, the boost converter will operate in trickle charge mode until VOUT exceeds VMID (see Boost Converter). 3. During phase 2, if CBOT exceeds its individual maximum threshold voltage (2.45V/2.05V typical if VSEL is low or 2.7V/2.3V typical if VSEL is high) or if VTOP exceeds VBOT by more than 50mV (typical), then the appropriate converter will turn off until the capacitor has fallen below its hysteresis threshold (2.40V/2V typical if VSEL is low and 2.65V/2.25V typical if VSEL is high for the buck converter or VTOP < VMID - 50mV typical for the boost converter). 4. Once VOUT has reached its programmed output voltage, the part will enter sleep mode, and only minimal power will be consumed (see the Electrical Characteristics table). 5. If the supercapacitors' self discharge or an external load cause the output to drop by more than 135mV (typical), then the LTC3625/LTC3625-1 will exit sleep mode and begin recharging the supercapacitor stack. In all cases, whenever either of the converters is shut down, it will switch to its appropriate discharge phase (NMOS on for the buck and PMOS on for the boost) until the inductor current reaches 0mA. This optimizes charge delivery to the output capacitors. Charge time is dependent on the programmed buck output current as well as the value of supercapacitors being charged. For estimating charge profiles in the dual inductor application, see the Typical Performance Characteristics graph Charge Time vs RPROG. The effective average VOUT referred charge current, while both converters are continuously active, can be approximated as: V ICHARGE 0.5 * IBUCK - 1A * 1- 2 * BOOST * MID VOUT And, while both supercapacitors are in balance and VMID is above the VMID(GOOD) threshold as: ICHARGE 0.5 * IBUCK * BOOST 10 where BOOST is the boost converter efficiency which is typically around 85% (see the Typical Performance Characteristics graph Boost Efficiency vs VTOP). Seen another way this is the maximum steady-state load the part can support without losing VOUT regulation. PGOOD PIN The PGOOD pin is an open-drain output used to indicate that VOUT has approached its final regulation value. PGOOD remains active low until VOUT reaches 92.5% of its regulation value at which point it will become high impedance. If VOUT falls below 89.5% of its regulation voltage after PGOOD has been asserted, PGOOD will once again pull active low. PGOOD is an open-drain output and requires a pull-up resistor to the input voltage of the monitoring microprocessor or another appropriate power source. PGOOD is pulled active low in shutdown or input UVLO. Power-Fail Input Comparator The PFI/PFO pins provide an input failure notification to the user. The PFI pin is a high impedance input pin that should be tied to a resistive divider from VIN. PFO is an open-drain output and requires a pull-up resistor to the input voltage of the monitoring microprocessor or another appropriate power source. When PFI is above 1.2V, PFO is high impedance and will be pulled up through the external resistor. If PFI drops below 1.2V, PFO will be pulled low indicating a power failure. This allows the user to program any desired input power failure indication threshold. There is 15mV of hysteresis on the PFI pin. If this functionality is not desired the PFI pin should be tied to VIN. PFO is pulled active low in shutdown or input UVLO Shutdown Operation When the EN pin is pulled low the LTC3625/LTC3625-1 are put into shutdown. In this case, all of the active circuitry is powered down and there will be less than 1A of leakage current from both VIN and VOUT . This allows the input to be present or absent as well as the capacitor stacks to be fully charged or discharged in shutdown without leakage between VIN, VOUT and GND. 3625f LTC3625/LTC3625-1 Applications Information Programming Charge Current/Maximum Input Current VIN Capacitor Selection The CBOT charge current is programmed with a single resistor connecting the PROG pin to ground. The program resistor and buck output current are calculated using the following equation: The style and value of capacitors used with the LTC3625/ LTC3625-1 determine input voltage ripple. Because the LTC3625/LTC3625-1 use a step-down switching power supply from VIN to VMID, its input current waveform contains high frequency components. It is strongly recommended that a low equivalent series resistance (ESR) multilayer ceramic capacitor be used to bypass VIN. RPROG = hPROG * 1.2V IBUCK where hPROG = 118,000 (typical). Excluding quiescent current, IBUCK is always greater than the average buck input current. An RPROG resistor value of less than 53.6k will cause the LTC3625/LTC3625-1 to enter overcurrent protection mode and proceed to charge at 2.65A (typical). Tantalum and aluminum capacitors are not recommended because of their high ESR. The value of the capacitor on VIN directly controls the amount of input ripple for a given IBUCK. Increasing the size of this capacitor will reduce the input ripple. The effective buck input current can be calculated as: Multilayer ceramic chip capacitors typically have exceptional ESR performance. MLCCs combined with a tight board layout and an unbroken ground plane will yield very good performance and low EMI emissions. There are several types of ceramic capacitors available, each having considerably different characteristics. For example, X7R ceramic capacitors have the best voltage and temperature stability. X5R ceramic capacitors have higher packing density but poorer performance over their rated voltage and temperature ranges. Y5V ceramic capacitors have the highest packing density, but must be used with caution because of their extreme non-linear characteristic of capacitance verse voltage. IVIN = IBUCK VMID * BUCK VIN where eBUCK is the buck converter efficiency (see the Typical Performance Characteristics graph Buck Efficiency vs VMID). Output Voltage Programming The LTC3625/LTC3625-1 have a VSEL input pin that allows the user to set the output threshold voltage to either 4.8V/4.0V or 5.3V/4.5V by forcing a low or high at the VSEL pin respectively. In the single inductor application the chip will balance the supercapacitors to within 50mV (typical) of each other, resulting in a possible 25mV of over/undercharge per cell. In the dual inductor application the chip will balance the supercapacitors to within 100mV (typical) of each other, resulting in a possible 50mV of over/undercharge per cell. Thermal Management If the junction temperature increases above approximately 150C, the thermal shutdown circuitry automatically deactivates the output. To reduce the maximum junction temperature, a good thermal connection to the PC board is recommended. Connecting the exposed pad (Pin 13) of the DFN package to a ground plane under the device on two layers of the PC board, will reduce the thermal resistance of the package and PC board considerably. The actual in-circuit capacitance of a ceramic capacitor should be measured with a small AC signal as is expected in-circuit. Many vendors specify the capacitance versus voltage with a 1VRMS AC test signal and as a result, overstate the capacitance that the capacitor will present in the application. Using similar operating conditions as the application, the user must measure or request from the vendor the actual capacitance to determine if the selected capacitor meets the minimum capacitance that the application requires. Inductor Selection Many different sizes and shapes of inductors are available from numerous manufacturers. Choosing the right inductor from such a large selection of devices can be overwhelming, but following a few basic guidelines will make the selection process much simpler. 3625f 11 LTC3625/LTC3625-1 Applications Information The buck and boost converters are designed to work with inductors over a wide range of inductances. Choosing a higher valued inductor will decrease operating frequencies, while a lower valued inductor will increase frequency but also increase peak current overshoot/undershoot. For most applications a 3.3H inductor is recommended. To maximize efficiency, choose an inductor with a low DC resistance. Choose an inductor with a DC current rating at least as large as the maximum IPEAK the application will see according to the specifications table to ensure that the inductor does not saturate during normal operation. If the single inductor application is used, make sure to size the inductor for the higher of buck or boost peak currents. Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or Permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. Inductors that are very thin or have a very small volume typically have much higher core and DCR losses, and will not give the best efficiency. The choice of which style inductor to use often depends more on the price versus size, performance and any radiated EMI requirements than on what the LTC3625/LTC3625-1 family requires to operate. Table 2 shows several inductors that work well with the LTC3625/LTC3625-1 regulators. These inductors offer a good compromise in current rating, DCR and physical size. Consult each manufacturer for detailed information on their entire selection of inductors. Supercapacitor Selection The LTC3625/LTC3625-1 are designed to charge supercapacitors of values greater than 0.1F per cell. In general, lower capacitance cells have higher ESRs, therefore lower charge currents should be used to help reduce sleep modulation towards the end of a charge cycle. In general, the ESR of a supercapacitor cell should not exceed: ESR 100mV IBUCK where 100mV is the sleep threshold hysteresis. Higher capacitance cells typically have lower ESRs and can therefore be charged with higher currents. Typically, the LTC3625/LTC3625-1 are designed to charge supercapacitors with values up to 100F, but higher capacitance cells could be used at the expense of greater charge time. Table 3 shows several supercapacitors that work well with the LTC3625/LTC3625-1. Printed Circuit Board Layout Considerations In order to be able to deliver maximum current under all conditions, it is critical that the exposed pad on the backside of the LTC3625/LTC3625-1 package be soldered to the PC Table 2. Inductor Manufacturers MANUFACTURER PART NUMBER INDUCTANCE (H) CURRENT (A) DCR (m) DR73-3R3-R 3.3 3.0 20 7x7 MSS7341-332NL 3.3 3.2 20 7x7 Vishay IHLM2525CZER3R3M11 3.3 6.5 26 6.5 x 6.9 Sumida CDRH6D28P-3RON 3.0 3.0 24 7x7 B1077AS-3RON 3.0 3.3 30 7.6 x 7.6 Coiltronics Coilcraft TOKO SIZE (mm) Table 3. Supercapacitor Manufacturers MANUFACTURER PART NUMBER VALUE (F) OPERATING VOLTAGE (V) MAXIMUM ESR (m) SIZE (mm) Cooper Bussmann B1860-2R5107-R 100 2.5 20 18 x 60 Illinois Capacitor 107DCN2R7M 100 2.7 10 22 x 45 NESS Capacitor ESHSR-0100C0002R7 100 2.7 9 22 x 45 TPLS-100//22 X 45F 100 2.7 9 22 x 45 BCAP120P250 120 2.5 2.5 26 x 51 Tecate Maxwell 3625f 12 LTC3625/LTC3625-1 Applications Information board ground. Failure to make thermal contact between the exposed pad on the backside of the package and the copper board will result in higher thermal resistances. resistance can be kelvined out by a dedicated voltage sense trace from the VMID pin to a point halfway between the bottom plate of CTOP and the top plate of CBOT . In the case of CTOP , however, it is even more critical to keep any resistance in the connection to a minimum. Excessive series resistance may cause the part to duty cycle in and out of sleep or prematurely shut down the boost, due to the voltage seen at the part being equal to VOUT + IOUT * ESR. Likewise the CBOT supercapacitor should be provided with a low impedance contact to the ground plane with an unbroken, low impedance, path back to the backside of the LTC3625/LTC3625-1 package. Furthermore, due to its potentially high frequency switching circuitry, it is imperative that the input capacitor, inductors, and output bypass capacitors be as close to the LTC3625/LTC3625-1 as possible, and that there be an unbroken ground plane under the IC and all of its external high frequency components. High frequency currents, such as the VIN and VOUT currents on the LTC3625/LTC3625-1, tend to find their way along the ground plane in a myriad of paths ranging from directly back to a mirror path beneath the incident path on the top of the board. If there are slits or cuts in the ground plane due to other traces on that layer, the current will be forced to go around the slits. If high frequency currents are not allowed to flow back through their natural least-area path, excessive voltage will build up and radiated emissions will occur. There should be a group of vias under the grounded backside of the package leading directly down to an internal ground plane. To minimize parasitic inductance, the ground plane should be on the highest possible layer of the PC board. When laying out the printed circuit, the following checklist should be used to ensure proper operation of the LTC3625/LTC3625-1. 1. Are the bypass capacitors at VIN and VOUT as close as possible to the LTC3625/LTC3625-1? These capacitors provide the AC current to the internal power MOSFETs and their drivers. Minimizing inductance from these capacitors to the LTC3625/LTC3625-1 is a top priority. 2. Are the CBOT bypass capacitor and the power inductor(s) closely connected? The (-) terminal of the CBOT bypass capacitor returns current to the GND plane, and then back to CIN. Any board resistance between inductor(s) and the positive terminal of CBOT will add to the capacitors internal ESR. Likewise, any resistance between the VOUT pin and the positive terminal of CTOP will add to its internal ESR. Any added resistance to the capacitors will reduce the effective charging efficiency. In the case of CBOT this 3. Keep sensitive components away from the SW pins. 4. Keep the current carrying traces from VOUT to CTOP and the inductors to CBOT to a minimum. Typical Applications 450mA Charge Current 1-Inductor Application VIN* 2.7V TO 5.5V C1 10F VIN VIN R1 287k R2 100k VOUT VIN LTC3625-1 L1 3.3H VOUT 4.0V/4.5V C2 0.1F SW1 SW2 EN CTL VSEL PGOOD PFO PFI PROG VMID GND C3 0.1F 3625 TA03 R3 71.5k *25mA MINIMUM LOAD REQUIRED ON VIN 3625f 13 LTC3625/LTC3625-1 Typical Applications Solar Powered SCAP Charger with MPPT D1 CMSH3-40 R4 10k R1 26.7k + C4 390F 16V VOUT SW1 EN C1 10F LTC3625 PFI GND C5 10nF C3 1F GND R3 143k 4 - 5 V+ LT1784CS5 - 3 + V 2 D2 1.2V C2 1F L2 3.3H SW2 PROG R5 174k R2 10.0k L1 3.3H VMID VSEL C6 100pF D3 SOLAR PANEL 6.0V OPEN CIRCUIT 4.4V MPP VIN CTL 1 3625 TA04 5V Power Ride-Through Q2 Si4421DY 5V C5 22F Q1 Si4421DY VOUT VIN C1 10F R1 287k R2 100k CTL EN SW1 LTC3625 SW2 PFI VMID VSEL GND GND PROG PFO VIN1 VOUT1 VIN2 FB1 LTM4616 GND ITHM1 VOUT2 FB2 L1 3.3H C2 100F C3 100F LTC4412 VIN SENSE GND GATE CTL STAT ITHM2 GND R5 4.78k R6 10k C6 100F C7 100F 1.8V C8 100F 3625 TA05 R4 470k R3 143k 3625f 14 LTC3625/LTC3625-1 Typical Applications 12V Power Ride-Through IDEAL DIODE LTC4355 FDS3672 12V LT1737 FLYBACK 4 * 10 * 2 * GND DC-A CTL EN 7 11 * LT1737 VIN VOUT LTC3625 SW1 L2 3.3H VMID VSEL C2 100F PROG R1 143k DC-C GND GND GND UV DETECTOR *EXPOSED PAD TO BE CONNECTED TO A THERMAL PAD ISOLATED FROM THE SYSTEM GROUND 8 12 FDS3672 C1 100F SW2 GND DC-B L1 3.3H 1.8V VOUT LTM4601A M1 IRF7424 * 6 DC/DC VIN * VIN CTL EN VOUT LTC3625 L3 3.3H C3 100F SW1 L4 3.3H SW2 GND C4 100F VMID VSEL PROG R2 143k VIN CTL EN VOUT LTC3625 L5 3.3H C5 100F SW1 L6 3.3H SW2 GND VMID VSEL C6 100F PROG R3 143k Package Description DE Package 12-Lead Plastic DFN (4mm x 3mm) (Reference LTC DWG # 05-08-1695) 4.00 p0.10 (2 SIDES) 0.70 p0.05 3.60 p0.05 2.20 p0.05 0.25 p 0.05 PIN 1 TOP MARK (NOTE 6) PACKAGE OUTLINE 0.50 BSC R = 0.115 TYP 0.200 REF 3.30 p0.10 3.00 p0.10 (2 SIDES) 1.70 p 0.10 0.75 p0.05 6 0.25 p 0.05 NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 1 PIN 1 NOTCH R = 0.20 OR 0.35 s 45o CHAMFER (UE12/DE12) DFN 0806 REV D 0.50 BSC 2.50 REF 2.50 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.40 p 0.10 12 R = 0.05 TYP 3.30 p0.05 1.70 p 0.05 7 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 3625f 15 LTC3625/LTC3625-1 Typical Application Minimum External Component Application (500mA Charge Current) VIN* 2.7V TO 5.5V C1 10F NC NC VIN VOUT SW1 LTC3625 L1 3.3H VOUT 4.8V/5.3V C2 0.1F SW2 PFI CTL EN VSEL PGOOD PFO PROG GND VMID C3 0.1F 3625 TA02 *25mA MINIMUM LOAD REQUIRED ON VIN Related Parts PART NUMBER DESCRIPTION COMMENTS LTC3203/LTC3203B/ LTC3203B-1/LTC3203-1 500mA Low Noise High Efficiency Dual Mode Step-Up Charge Pumps VIN: 2.7V to 5.5V, 3mm x 3mm 10-Lead DFN Package LTC3204/LTC3204B-3.3/ LTC3204-5 Low Noise Regulating Charge Pumps Up to 150mA Output Current (LTC3204-5), Up to 50mA Output Current (LTC3204-3.3) LTC3221/LTC3221-3.3/ LTC3221-5 Micropower Regulated Charge Pump Up to 60mA Output Current LTC3225/LTC3225-1 150mA Supercapacitor Charger Programmable Supercapacitor Charger Designed to Charge Two Supercapacitors in Series to a Fixed Output Voltage (4.8V/5.3V Selectable) from a 2.8V/3V to 5.5V Input Supply. Automatic Cell Balancing Prevents Overvoltage Damage to Either Supercapacitor. No Balancing Resistors are Required. LTC3240-3.3/LTC3240-2.5 Step-Up/Step-Down Regulated Charge Pumps Up to 150mA Output Current LT 3420/LT3420-1 1.4A/1A Photoflash Capacitor Charger with Automatic Top-Off Charges 220F to 320V in 3.7 Seconds from 5V, VIN: 2.2V to 16V, ISD < 1A, 10-Lead MS Package LT3468/LT3468-1/ LT3468-2 1.4A/1A/0.7A, Photoflash Capacitor Charger VIN: 2.5V to 16V, Charge Time = 4.6 Seconds for the LT3468 (0V to 320V, 100F, VIN = 3.6V), ISD < 1A, ThinSOTTM Package LTC3484-0/LTC3484-1/ LTC3484-2 1.4A/0.7A/1A, Photoflash Capacitor Charger VIN: 1.8V to 16V, Charge Time = 4.6 Seconds for the LT3484-0 (0V to 320V, 100F, VIN = 3.6V), ISD < 1A, 2mm x 3mm 6-Lead DFN Package LT3485-0/LT3485-1/ LT3485-2/LT3485-3 1.4A/0.7A/1A/2A Photoflash Capacitor Charger with Output Voltage Monitor and Integrated IGBT VIN: 1.8V to 10V, Charge Time = 3.7 Seconds for the LT3485-0 (0V to 320V, 100F, VIN = 3.6V), ISD < 1A, 3mm x 3mm 10-Lead DFN Driver LT3750 Capacitor Charger Controller Charges Any Size Capacitor, 10-Lead MS Package LT3751 Capacitor Controller with Regulation Charges Any Size Capacitor, 4mm x 5mm QFN-20 Package LTC4425 Supercapacitor Charger with Current-Limited Ideal Diode CC/CV Linear Charger for 2-Cell Supercapacitor Stack from a Li-Ion/ Polymer Battery, USB Port or a 2.7V to 5.5V Current-Limited Supply, 3mm x 3mm DFN-12 and MSOP-12E Packages (R) 3625f 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LT 0710 * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2010