LTC3625/LTC3625-1
1
3625f
Typical applicaTion
FeaTures DescripTion
1A High Efficiency 2-Cell
Supercapacitor Charger
with Automatic Cell
Balancing
The LTC
®
3625/LTC3625-1 are programmable supercapaci-
tor chargers designed to charge two supercapacitors in
series to a fixed output voltage (4.8V/5.3V or 4V/4.5V
selectable) from a 2.7V to 5.5V input supply. Automatic
cell balancing prevents overvoltage damage to either
supercapacitor while maximizing charge rate. No balancing
resistors are required.
High efficiency, high charging current, low quiescent cur-
rent and low minimum external parts count (one inductor,
one bypass capacitor at VIN and one programming resistor)
make the LTC3625/LTC3625-1 ideally suited for small form
factor backup or high peak power systems.
Charging current/maximum input current level is pro-
grammed with an external resistor. When the input supply is
removed and/or the EN pin is low, the LTC3625/LTC3625-1
automatically enter a low current state, drawing less than
1µA from the supercapacitors.
The LTC3625/LTC3625-1 are available in a compact
12-lead 3mm × 4mm × 0.75mm DFN package.
1A SCAP Charger
applicaTions
n High Efficiency Step-Up/Step-Down Charging of Two
Series Supercapacitors
n Automatic Cell Balancing Prevents Capacitor
Overvoltage During Charging
n Programmable Charging Current Up to 500mA
(Single Inductor), 1A (Dual Inductor)
n VIN = 2.7V to 5.5V
n Selectable 2.4V/2.65V Regulation per Cell (LTC3625)
n Selectable 2V/2.25V Regulation per Cell (LTC3625-1)
n Low No-Load Quiescent Current: 23µA
n IVOUT
, IVIN < 1µA in Shutdown
n
Low Profile 12-lead 3mm × 4mm DFN Package
n Servers, RAID Systems, Mass Storage, High Current
Backup Supplies
n Solid State Hard Drives
n Wireless Power Meters
n High Peak Power Boosted Supplies
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
Charging Two 2:1 Mismatched Supercapacitors
TIME (SECONDS)
0
VOLTAGE (V)
2
4
6
1
3
5
40 80 120 160
3625 TA01b
200200 60 100 140 180
VOUT
VMID
CTOP = 50F
CBOT = 100F
RPROG = 61.9k
CTL = 0
VSEL = 0
VOUT
SW1
SW2
VMID
PGOOD
PFO
LTC3625
3.3µH CTOP ≥ 0.1F
CBOT ≥ 0.1F
VOUT
4.8V
3625 TA01a
10µF
VIN
2.7V TO 5.5V
VIN
PROG
61.9k
PFI
EN
CTL
VSEL
3.3µH
LTC3625/LTC3625-1
2
3625f
pin conFiguraTionabsoluTe MaxiMuM raTings
VIN, VOUT (Transient) t < 1ms,
Duty Cycle < 1% .......................................... –0.3V to 7V
VIN, VOUT, VMID, PGOOD,
CTL, PROG, PFI, PFO ................................... –0.3V to 6V
EN, VSEL ........................................... –0.3V to VIN + 0.3V
VOUT Short-Circuit Duration ............................. Indefinite
IPGOOD, IPFO ............................................................50mA
IPROG ........................................................................1mA
IVIN, ISW1, ISW2, IVOUT (Note 2) ...................................3A
Operating Junction Temperature Range
(Notes 3, 4) ............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
(Note 1)
12
11
10
9
8
7
1
2
3
4
5
6
SW2
VOUT
VMID
PGOOD
PFO
PFI
SW1
VIN
CTL
VSEL
EN
PROG
TOP VIEW
13
GND
DE PACKAGE
12-LEAD (4mm s 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3625EDE#PBF LTC3625EDE#TRPBF 3625 12-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LTC3625EDE-1#PBF LTC3625EDE-1#TRPBF 36251 12-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LTC3625IDE#PBF LTC3625IDE#TRPBF 3625 12-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LTC3625IDE-1#PBF LTC3625IDE-1#TRPBF 36251 12-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, RPROG = 143k, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Voltage Range lVIN(UVLO) 5.5 V
VIN(UVLO) Input Undervoltage Lockout
(VIN Rising)
VSEL = VIN (LTC3625)
VSEL = 0V (LTC3625)
VSEL = 0V or VIN (LTC3625-1)
l
l
l
2.8
2.53
2.53
2.9
2.63
2.63
3.0
2.73
2.73
V
V
V
Input UVLO Hysteresis 100 mV
VOUT(SLEEP) Charger Termination Voltage VSEL = VIN (LTC3625)
VSEL = 0V (LTC3625)
VSEL = VIN (LTC3625-1)
VSEL = 0V (LTC3625-1)
l
l
l
l
5.2
4.7
4.4
3.9
5.3
4.8
4.5
4.0
5.4
4.9
4.6
4.1
V
V
V
V
Recharge Hysteresis Below VOUT(SLEEP) 135 mV
VTOP
, VBOT Maximum Voltage Across Either of
the Supercapacitors After Charging
VSEL = VIN, VOUT = 5.3V (LTC3625)
VSEL = 0V, VOUT = 4.8V (LTC3625)
VSEL = VIN, VOUT = 4.5V (LTC3625-1)
VSEL = 0V, VOUT = 4V (LTC3625-1)
l
l
l
l
2.7
2.45
2.3
2.05
2.75
2.5
2.35
2.1
V
V
V
V
Maximum Supercapacitor Offset
After Charging
CTL = 0V
CTL = VIN
100
50
180
120
mV
mV
LTC3625/LTC3625-1
3
3625f
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, RPROG = 143k, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IVIN Input Operating Current,
ISW1 = ISW2 = 0µA, No Switching
CTL = VIN, VMID = 1.5V, VOUT = 2.5V (Boost Only)
CTL = VIN, VMID = 1.5V, VOUT = 3.5V (Buck Only)
CTL = 0, VMID = 1.5V, VOUT = 2.5V (Buck and Boost)
135
275
365
200
400
530
µA
µA
µA
Input Sleep Current VIN = 5.5V, VOUT = 5.4V
VIN = 3.6V, VOUT = 5.4V
23
8
35
15
µA
µA
Input SD Current VOUT = 0V 0 1 µA
IVOUT VOUT SD Current VOUT = 5.4V 0 1 µA
VOUT Sleep Current VOUT = 5.4V, VIN = 3.6V, EN = VIN
VOUT = 5.4V, VIN = 5.5V, EN = VIN
17
1
25
2.5
µA
µA
VPROG PROG Servo Voltage VOUT = 3.5V, VMID = 1.5V l1.17 1.2 1.23 V
hPROG Ratio of Measured IPROG Current to
IBUCK Programmed Current
118,000
IBUCK Programmed Buck Charge Current RPROG = 143k (Note 5)
RPROG = 71.5k (Note 5)
0.88
1.76
0.99
1.98
1.10
2.20
A
A
IMAX Maximum Programmed Charge
Current
RPROG = 0Ω (Fault Condition) (Note 5) 1.98 2.65 3.31 A
VMID(GOOD) VMID Voltage Where the Boost
Regulator is Enabled
1.35 V
VMID(GOOD) Hysteresis 150 mV
VTRICKLE VOUT Voltage Above Which Boost
Regulator Will Exit Trickle Charge
Mode and Enter Normal Charge
Mode
VOUT Rising VMID V
VTRICKLE Falling Hysteresis 50 mV
IPEAK(BUCK) Buck Charge Current Peak 1.1 • IBUCK A
IVALLEY(BUCK) Buck Charge Current Valley 0.9 • IBUCK A
IPEAK(BOOST) Boost Charge Current Peak VOUT = 3V, VMID = 2V (Note 5)
VOUT = 1V, VMID = 2V (Note 5)
1.59 2.12
200
2.65 A
mA
IVALLEY(BOOST) Boost Charge Current Valley VOUT = 3V, VMID = 2V
VOUT = 1V, VMID = 2V
1.41 1.88
0
2.35 A
mA
Maximum Boost Valley Time VOUT = 1V, VMID = 2V 6.5 µs
RPMOS PMOS On-Resistance 120 mΩ
RNMOS NMOS On-Resistance 100 mΩ
ILEAK SW Pin Leakage Current for SW1,
SW2
EN = 0V 1 µA
VPFI PFI Falling Threshold l1.17 1.2 1.23 V
PFI Hysteresis 15 mV
IPFI Pin Leakage Current for PFI Pin 0 30 nA
Logic (EN, CTL, VSEL, PGOOD, PFO)
VIL Input Low Logic Voltage EN, CTL, VSEL Pins l0.4 V
VIH Input High Logic Voltage EN, CTL, VSEL Pins l1.2 V
IIL, IIH Input Low, High Current for CTL CTL 1 µA
RPD EN Pin Pull-Down Resistance 4.5 MΩ
VSEL Pin Pull-Down Resistance EN = VIN 4.5 MΩ
VOL Output Low Logic Voltage PGOOD, PFO Pins; Sinking 5mA l70 200 mV
IOH Logic High Leakage Current PGOOD, PFO Pins; Pin Voltage = 5V 1 µA
PGOOD Rising Threshold VOUT as a Percentage of Final Target 90 92.5 95 %
PGOOD Hysteresis ∆VOUT as a Percentage of Final Target 3 %
LTC3625/LTC3625-1
4
3625f
Typical perForMance characTerisTics
Buck Output Current vs RPROG
Sleep Current vs VIN
PROG Voltage and PFI Falling
Threshold vs Temperature
Buck Current Limits
vs Temperature
TA = 25°C, L1 = 3.3µH, L2 = 3.3µH, CIN = 10µF, CTOP = CBOT
, LTC3625 unless otherwise specified.
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3625/LTC3625-1 internal switches are guaranteed to
survive up to 3A of peak current. Internal current limits will restrict peak
current to lower levels.
Note 3: The LTC3625/LTC3625-1 are tested under pulsed load conditions
such that TJ ≈ TA. The LTC3625E/LTC3625E-1 are guaranteed to meet
specifications from 0°C to 85°C junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3625I/LTC3625I-1 are guaranteed over the –40°C to 125°C
operating junction temperature range.
The junction temperature (TJ in °C) is calculated from the ambient
temperature (TA in °C) and power dissipation (PD in Watts) according to
the formula:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance.
Note 4: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability or permanently damage the
device.
Note 5: Measurements are tested with CTL = 0V.
VIN (V)
2.7 3.1
0
CURRENT (µA)
10
25
IVOUT
IVIN
3.5 4.3 4.7
3625 G01
5
20
15
3.9 5.1 5.5
VOUT = 4.8V
VSEL = 0V
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
VPROG (V)
1.205
1.210
1.215
3625 G02
1.195
1.180
1.220
1.200
1.190
1.185
VIN = 3.6V
RPROG = 143k
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
CURRENT (mA)
1050
1100
1150
1200
3625 G03
950
800
1000
900
850
IPEAK
IVALLEY
VIN = 3.6V
RPROG = 143k
RPROG (kΩ)
0
IBUCK (mA)
1000
2000
3000
500
1500
2500
100 200 300 400
3625 G04
500500 150 250 350 450
VIN = 3.6V
VMID = 2V
CTL = 0V
IPROG
CLAMPED
Charge Termination Error
vs Temperature
TEMPERATURE (°C)
–40
OFFSET (%)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
95
3625 G13
5 35 65 12580–10–25 20 50 110
VIN = 3.6V
SLEEP THRESHOLD
WAKE THRESHOLD
Input and Output Sleep Currents
vs Temperature
TEMPERATURE (°C)
–40
CURRENT (µA)
25
20
15
10
5
0
95
3625 G14
5 35 65 125
IVIN
80–10–25 20 50 110
VIN = 3.6V
VSEL = 3.6V
LTC3625-1 IVOUT
VOUT = 4.5V
LTC3625 IVOUT
VOUT = 5.3V
LTC3625/LTC3625-1
5
3625f
Buck Input Power vs RPROG Buck Efficiency vs IBUCK
RPROG (kΩ)
0
INPUT POWER (W)
8
7
6
5
4
3
2
1
0
400
3625 G05
100 200 300 50035050 150 250 450
VIN = 5.5V
VMID = 2.65V
CTL = 0V
VSEL = VIN
IPROG
CLAMPED
IBUCK (mA)
200
EFFICIENCY (%)
80
90
100
2200
3625 G06
70
60
75
85
95
65
55
50 700 1200 1700
VIN = 3.6V
VMID = 2V
CTL = 0V
Typical perForMance characTerisTics
TA = 25°C, L1 = 3.3µH, L2 = 3.3µH, CIN = 10µF, CTOP = CBOT
, LTC3625 unless otherwise specified.
Buck Input Power vs VMID
Buck Efficiency vs VMID Buck Output Current vs VMID
VMID (V)
0.2
0
IBUCK (mA)
500
1000
1500
0.6 1.0 1.4 1.8
3625 G09
2.2
2000
2500
250
750
1250
1750
2250
2.6
VIN = 5.5V
VSEL = VIN
CTL = 0
RPROG = 71.5k
RPROG = 143k
RPROG = 286k
Boost Input Current vs VTOP
VTOP (V)
–1.5
IBOOST (mA)
1500
2000
2500
0 1.0 2.5
3625 G10
1000
500
0
–1.0 –0.5 0.5 1.5 2.0
VIN = 3.6V
VMID = 2.5V
VTOP = VOUT – VMID
CTL = 0
NORMAL OPERATION
VOUT
TRICKLE
CHARGE
OPERATION
RFET vs TemperatureBoost Efficiency vs VTOP
VTOP (V)
–1.5
EFFICIENCY (%)
60
70
80
1.5
3625 G11
50
40
–0.5 0.5
–1.0 2.0
0 1.0 2.5
30
20
90
VIN = 3.6V
VMID = 2.5V
VTOP = VOUT – VMID
CTL = 0
NORMAL OPERATION
VOUT TRICKLE
CHARGE OPERATION
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
PMOS RDS(ON) (Ω)
NMOS RDS(ON) (Ω)
0.15
3625 G12
0
0.20
0.10
0.05
0.20
0.05
0.25
0.15
0.10
VIN = 2.7V
VIN = 5.5V
PMOS
NMOS
Charge Time vs RPROG
RPROG (kΩ)
0
TIME (SECONDS)
400
350
300
250
200
150
100
50
0
400
3625 G15
100 200 300 50035050 150 250 450
SINGLE
INDUCTOR
APPLICATION
DUAL
INDUCTOR
APPLICATION
VIN = 3.6V
VSEL = 3.6V
VOUT INITIAL = 0V
CTOP = CBOT = 10F
IPROG
CLAMPED
LTC3625/LTC3625-1
6
3625f
Typical perForMance characTerisTics
TA = 25°C, L1 = 3.3µH, L2 = 3.3µH, CIN = 10µF, CTOP = CBOT
, LTC3625 unless otherwise specified.
SW1 (Pin 1): Switch Pin for the Buck Regulator. External
inductor connects between SW1 pin and VMID.
VIN (Pin 2): Input Voltage Pin. Bypass to GND with a 10µF
or larger ceramic capacitor.
CTL (Pin 3): Logic Input. CTL sets the charge mode of the
LTC3625/LTC3625-1. A logic high at CTL programs the part
to operate with a single inductor; a logic low programs
the part to operate with two inductors. In the 2-inductor
application the capacitor stack will charge approximately
twice as quickly. CTL is a high impedance input and must
be tied to either VIN or GND. Do not float.
VSEL (Pin 4): Logic Input. VSEL selects the output volt-
age of the LTC3625/LTC3625-1. A logic low at VSEL sets
the per-cell maximum voltage to 2.45V/2.05V (VOUT =
4.8V/4.0V); a logic high sets the per-cell maximum volt-
age to 2.70V/2.30V (VOUT = 5.3V/4.5V). When the part is
enabled, VSEL has a 4.5MΩ internal pull-down resistor; if
EN is low, then VSEL is a high impedance input pin.
EN (Pin 5): Logic Input. Enables the LTC3625/LTC3625-1.
Active high. Has a 4.5MΩ internal pull-down resistor.
Charge Profile Into Matched
SuperCaps Charge Profile with CBOT > CTOP Charge Profile with CTOP > CBOT
pin FuncTions
PROG (Pin 6): Charge Current Program Pin. Connecting a
resistor from PROG to ground programs the buck output
current. This pin servos to 1.2V.
PFI (Pin 7): Input to the Power Fail Comparator. This pin
connects to an external resistor divider between VIN and
GND. If this functionality is not desired, PFI should be
tied to VIN.
PFO (Pin 8): Open-Drain Output of the Power-Fail Compara-
tor. The part pulls this pin low if VIN is less than a value
programmed by an external divider. This pin is active low
in shutdown mode. If this functionality is not desired PFO
should be left unconnected.
PGOOD (Pin 9): Logic Output. This is an open-drain
output which indicates that VOUT has settled to its final
value. Upon start-up, this pin remains low until the output
voltage, VOUT
, is within 92.5% (typical) of its final value.
Once VOUT is valid, PGOOD becomes high impedance. If
VOUT falls to 89.5% (typical) of its correct regulation level,
PGOOD is pulled low. PGOOD may be pulled up through
an external resistor to an appropriate reference level. This
pin is active low in shutdown mode.
TIME (SECONDS)
0
SINGLE INDUCTOR
VOLTAGE (V)
DUAL INDUCTOR
VOLTAGE (V)
0
2
4
120
3625 G16
6
4
20 40 60 80 100 140
2
0
6
VOUT
VMID
VMID
VIN = 3.6V, VSEL = 3.6V
RPROG = 143k
CTOP = CBOT = 10F
VOUT
SINGLE INDUCTOR APPLICATION
DUAL INDUCTOR APPLICATION
TIME (SECONDS)
0
SINGLE INDUCTOR
VOLTAGE (V)
DUAL INDUCTOR
VOLTAGE (V)
0
2
4
200
3625 G17
6
4
50 100 150 250
2
0
6VOUT
VMID
VMID
VIN = 3.6V, VSEL = 3.6V
RPROG = 143k
CTOP = 10F, CBOT = 50F
VOUT
SINGLE INDUCTOR APPLICATION
DUAL INDUCTOR APPLICATION
TIME (SECONDS)
0
SINGLE INDUCTOR
VOLTAGE (V)
DUAL INDUCTOR
VOLTAGE (V)
0
2
4
300
3625 G18
6
4
50 100 150 200 250 350
2
0
6
VOUT
VMID
VMID
VOUT
SINGLE INDUCTOR APPLICATION
DUAL INDUCTOR APPLICATION
VIN = 3.6V, VSEL = 3.6V
RPROG = 143k
CTOP = 50F, CBOT = 10F
LTC3625/LTC3625-1
7
3625f
pin FuncTions
VMID (Pin 10): Midpoint of Two Series Supercapacitors.
The pin voltage is monitored and used, along with VOUT
,
to enable or shut down the buck and boost converters
during charging to achieve voltage balancing of the top
and bottom supercapacitors.
VOUT (Pin 11): Output Voltage Pin. Connect VOUT to the
positive terminal of the top supercapacitor. The pin volt-
age is monitored and used, along with VMID, to enable or
shut down the buck and boost converters during charg-
ing to achieve voltage balancing of the top and bottom
supercapacitors.
SW2 (Pin 12): Switch Pin for the Boost Regulator. External
inductor connects between the SW2 pin and VMID. If CTL
is logic high, then SW2 must be connected to SW1.
GND (Exposed Pad Pin 13): Ground. The exposed pad
must be connected to a continuous ground plane on
the printed circuit board directly under the LTC3625/
L
TC3625-1 for electrical contact and to achieve rated
thermal performance.
block DiagraM
8
–
+
PFO
7PFI
1.20V
4.44V/4.90V (LTC3625)
3.7V/4.16V (LTC3625-1)
9
–
+
PGOOD
4
VSEL
10
VMID
THRESHOLD
DETECTOR
5EN
3CTL VMID_GOOD
SD_BUCK
6
13
2
PROG
MASTER
LOGIC
OVERTEMPERATURE
SHUTDOWN 1.2V
–
+
–
+
GND
SW1
VIN
B
3625 BD
A
D
SD_BOOST
REF/R PROGRAMMED
AVG OUTPUT CURRENT
SYNCHRONOUS
BUCK CURRENT
REGULATOR
BUCK REGULATOR
BOOST REGULATOR
1
11
SW2
VOUT
C
2A AVG
INPUT CURRENT
SYNCHRONOUS
BOOST CURRENT
REGULATOR
12
VMAXER
VIN
VOUT
LTC3625/LTC3625-1
8
3625f
operaTion
The LTC3625/LTC3625-1 are dual cell supercapacitor char-
gers. Their unique topology charges two series connected
capacitors to a fixed output voltage with programmable
charging current without overvoltaging either of the cells
— even if they are severely mismatched. No balancing
resistors are required. The LTC3625/LTC3625-1 include an
internal buck converter between VIN and VMID to regulate
the voltage on CBOT (across the bottom capacitor) as well
as an internal boost converter between VMID and VOUT to
regulate the voltage on CTOP (across the top capacitor). The
output current of the buck converter is user-programmed
via the PROG pin and the input current of the boost con-
verter is set at 2A (typical).
Table 1 indicates the various functions of the LTC3625/
LTC3625-1 that can be digitally controlled.
Table 1. Digital Input Functions
PIN VALUE FUNCTION
CTL* 0 Part runs in 2-inductor application
1 Part runs in 1-inductor application
VSEL 0 4.8V/4.0V sleep threshold
1 5.3V/4.5V sleep threshold
EN 0 Part shuts down, VOUT becomes high
impedance
1 Part enables and regulates the output
*CTL pin must be hard tied to either VIN or GND.
VIN Undervoltage Lockout (UVLO)
An internal undervoltage lockout circuit monitors VIN and
keeps the LTC3625/LTC3625-1 disabled until VIN rises
above 2.90V/2.63V (typical) if VSEL is high or 2.63V/2.63V
(typical) if VSEL is low. Hysteresis on the UVLO turns off
the LTC3625/LTC3625-1 if VIN drops by approximately
100mV below the UVLO rising threshold. When in UVLO,
only current needed to detect a valid input will be drawn
from VIN and VOUT
.
Buck Converter
The buck converter regulates a user-programmed average
output current given by:
I h V
R
BUCK PROG
PROG
=•.1 2
where hPROG = 118,000 (typical).
The buck converter regulates the current hysteretically by
switching on the buck PMOS until a peak current limit is
reached and then turning on the buck NMOS until a valley
current limit is reached. In the single inductor application
the boost NMOS is used in conjunction with the buck
NMOS to increase efficiency at high currents. The forward
current limit is set to 1.1 • IBUCK (typical) and the valley
current limit is set to 0.9 • IBUCK (typical). Because of this
method of regulation, overcurrent limit and reverse-current
limit protection is automatically provided. The LTC3625/
LTC3625-1 will continue to regulate its programmed cur-
rent even into a grounded output.
In fault conditions where the PROG pin is shorted to ground,
or RPROG is conductive enough to program IBUCK to operate
outside of specification, the current out of the PROG pin
will be clamped to 22.5µA (typical) and IBUCK will be set to
2.65A (typical). If input current limit is not a concern, the
PROG pin may be grounded to minimize charge times.
Boost Converter
The boost converter regulates a fixed average input current
of 2A (typical). The current is regulated hysteretically by
switching on the boost NMOS until the peak current limit of
2.12A (typical) is reached, and turning on the boost PMOS
until the valley current limit of 1.88A (typical) is reached.
In the single inductor application the buck NMOS is used
in conjunction with the boost NMOS to increase efficiency.
Because of this method of regulation, overcurrent limit and
reverse-current limit protection is automatically provided.
In normal operation VOUT will increase with VMID so VOUT
should never be below VMID. In the case where there is a
reverse voltage on CTOP due to a faulty precondition or a
large load on the output, the boost converter will operate
in trickle charge mode. In this mode the boost PMOS
gate will remain high and instead allow the SW2 node to
increase until SW2 ≈ VMAX + 1V to allow a higher reverse
voltage across the inductor, and the current is ramped down
to 0mA. This will result in a less efficient charge delivery
through the PMOS. To keep dissipation low, IPEAK is limited
to 200mA (typical). In this mode the discharge phase is
terminated if it lasts longer than 6.5µs (typical).
The boost converter is disabled if VMID falls below the
VMID(GOOD) hysteresis threshold of 1.2V (typical).
LTC3625/LTC3625-1
9
3625f
operaTion
Single Inductor Operation
With the CTL pin tied to VIN the LTC3625/LTC3625-1 will
operate in single inductor mode. In this mode the same
inductor serves in the power path for both the buck and
the boost converters. Thus, the buck converter and boost
converter will never run simultaneously.
Under certain conditions with a single inductor, a small
amount of current can flow from the supercapacitors to VIN
when the boost charger is active. A 25mA load is required
on VIN to prevent the VIN supply from being pumped to
a higher voltage while the boost is active. This minimum
load is not needed in the two inductor application and it
is also not needed when the charger is disabled.
A typical charge cycle for a fully discharged capacitor stack
will proceed as follows:
1. The buck converter will turn on and regulate its output
current ramping hysteretically between 1.1 • IBUCK and
0.9 • IBUCK until the VMID(GOOD) threshold is met (1.35V
typical).
2. Once the VMID(GOOD) threshold is reached, the boost
converter will turn on and regulate its input current
ramping hysteretically between 2.12A and 1.88A until
VMID falls below the VMID(GOOD) hysteresis threshold
(1.2V typical).
3. Phases 1 and 2 will alternate until VOUT is approximately
2.4V. When VTOP (equal to VOUT – VMID) is approximately
50mV > VMID, the boost regulator will turn off and the
buck regulator will turn on. Likewise, when VMID is
approximately 50mV > VTOP
, the boost regulator will
turn on and the buck regulator will turn off.
4. Phase 3 will continue until VOUT has reached its pro-
grammed output voltage. Once this happens, the part
will enter sleep mode and only minimal power will be
consumed (see the Electrical Characteristics table).
5. If the supercapacitors’ self discharge or an external load
cause the output to drop by more than 135mV (typical),
then the LTC3625/LTC3625-1 will exit sleep mode and
begin charging the appropriate supercapacitor.
In all cases whenever either of the converters is shut
down, it will switch to its appropriate discharge phase
(NMOS on for the buck and PMOS on for the boost) until
the inductor current reaches 0mA. This optimizes charge
delivery to the output capacitors.
Charge time is dependant on the programmed buck output
current as well as the value of the supercapacitors being
charged. For estimating charge profiles in the single induc-
tor application, see the Typical Performance Characteristics
graph Charge Time vs RPROG.
The effective average VOUT referred charge current can
be approximated as:
I I A
I A
CHARGE BUCK BOOST
BUCK
≅+
0 5 2
2
. • • •ε
where εBOOST is the boost converter efficiency, which is
typically about 85% (see the Typical Performance Char-
acteristics graph Boost Efficiency vs VTOP).
Seen another way, this is the maximum steady-state load
the part can support without losing VOUT regulation.
Dual Inductor Operation
With the CTL pin tied to GND, the LTC3625/LTC3625-1
will operate in dual inductor mode. In this mode two
inductors will serve as the power path for the buck and
the boost converters. This will allow both the buck and
the boost converter to run simultaneously. As a result, the
total charge time will be greatly reduced at the cost of an
additional board component.
A typical charge cycle for a fully discharged capacitor stack
will proceed as follows:
1. The buck converter will turn on and regulate its output
current ramping hysteretically between 1.1 • IBUCK
and 0.9 • IBUCK until the VMID(GOOD) threshold is met
(1.35V typical).
2. Once the VMID(GOOD) threshold is reached, the boost
converter will turn on and regulate its input current
ramping hysteretically between 2.12A and 1.88A. The
buck converter will continue to run at the same time. In
some cases (IBUCK ~ <1A) the boost converter’s input
current will exceed the current delivered to CBOT
; even
though the buck converter is running, charge will be
removed and VMID may decrease. Thus, if VMID falls
below the VMID(GOOD) hysteresis threshold, the boost
LTC3625/LTC3625-1
10
3625f
operaTion
converter will turn off. Once VMID has again risen above
the VMID(GOOD) threshold, the boost converter will be
re-enabled. In the case where VOUT < VMID, the boost
converter will operate in trickle charge mode until VOUT
exceeds VMID (see Boost Converter).
3. During phase 2, if CBOT exceeds its individual maximum
threshold voltage (2.45V/2.05V typical if VSEL is low
or 2.7V/2.3V typical if VSEL is high) or if VTOP exceeds
VBOT by more than 50mV (typical), then the appropri-
ate converter will turn off until the capacitor has fallen
below its hysteresis threshold (2.40V/2V typical if VSEL
is low and 2.65V/2.25V typical if VSEL is high for the
buck converter or VTOP < VMID – 50mV typical for the
boost converter).
4. Once VOUT has reached its programmed output voltage,
the part will enter sleep mode, and only minimal power
will be consumed (see the Electrical Characteristics
table).
5. If the supercapacitors’ self discharge or an external load
cause the output to drop by more than 135mV (typical),
then the LTC3625/LTC3625-1 will exit sleep mode and
begin recharging the supercapacitor stack.
In all cases, whenever either of the converters is shut
down, it will switch to its appropriate discharge phase
(NMOS on for the buck and PMOS on for the boost) until
the inductor current reaches 0mA. This optimizes charge
delivery to the output capacitors.
Charge time is dependent on the programmed buck out-
put current as well as the value of supercapacitors being
charged. For estimating charge profiles in the dual inductor
application, see the Typical Performance Characteristics
graph Charge Time vs RPROG.
The effective average VOUT referred charge current, while
both converters are continuously active, can be approxi-
mated as:
I I A V
V
CHARGE BUCK BOOST
MID
OUT
≅
0 5 1 1 2. • – • – • •ε
And, while both supercapacitors are in balance and VMID
is above the VMID(GOOD) threshold as:
ICHARGE ≅ 0.5 • IBUCK • εBOOST
where εBOOST is the boost converter efficiency which is
typically around 85% (see the Typical Performance Char-
acteristics graph Boost Efficiency vs VTOP).
Seen another way this is the maximum steady-state load
the part can support without losing VOUT regulation.
PGOOD PIN
The PGOOD pin is an open-drain output used to indicate
that VOUT has approached its final regulation value. PGOOD
remains active low until VOUT reaches 92.5% of its regula-
tion value at which point it will become high impedance.
If VOUT falls below 89.5% of its regulation voltage after
PGOOD has been asserted, PGOOD will once again pull
active low. PGOOD is an open-drain output and requires
a pull-up resistor to the input voltage of the monitoring
microprocessor or another appropriate power source.
PGOOD is pulled active low in shutdown or input UVLO.
Power-Fail Input Comparator
The PFI/PFO pins provide an input failure notification to
the user. The PFI pin is a high impedance input pin that
should be tied to a resistive divider from VIN. PFO is an
open-drain output and requires a pull-up resistor to the
input voltage of the monitoring microprocessor or another
appropriate power source. When PFI is above 1.2V, PFO is
high impedance and will be pulled up through the external
resistor. If PFI drops below 1.2V, PFO will be pulled low
indicating a power failure. This allows the user to program
any desired input power failure indication threshold. There
is 15mV of hysteresis on the PFI pin. If this functionality
is not desired the PFI pin should be tied to VIN. PFO is
pulled active low in shutdown or input UVLO
Shutdown Operation
When the EN pin is pulled low the LTC3625/LTC3625-1 are
put into shutdown. In this case, all of the active circuitry is
powered down and there will be less than 1µA of leakage
current from both VIN and VOUT
. This allows the input to
be present or absent as well as the capacitor stacks to be
fully charged or discharged in shutdown without leakage
between VIN, VOUT and GND.
LTC3625/LTC3625-1
11
3625f
applicaTions inForMaTion
Programming Charge Current/Maximum Input Current
The CBOT charge current is programmed with a single
resistor connecting the PROG pin to ground. The program
resistor and buck output current are calculated using the
following equation:
R h V
I
PROG PROG
BUCK
=•.1 2
where hPROG = 118,000 (typical). Excluding quiescent cur-
rent, IBUCK is always greater than the average buck input
current. An RPROG resistor value of less than 53.6k will
cause the LTC3625/LTC3625-1 to enter overcurrent protec-
tion mode and proceed to charge at 2.65A (typical).
The effective buck input current can be calculated as:
IIV
V
VIN
BUCK
BUCK
MID
IN
=ε•
where εBUCK is the buck converter efficiency (see the
Typical Performance Characteristics graph Buck Efficiency
vs VMID).
Output Voltage Programming
The LTC3625/LTC3625-1 have a VSEL input pin that
allows the user to set the output threshold voltage to
either 4.8V/4.0V or 5.3V/4.5V by forcing a low or high at
the VSEL pin respectively. In the single inductor application
the chip will balance the supercapacitors to within 50mV
(typical) of each other, resulting in a possible 25mV of
over/undercharge per cell. In the dual inductor application
the chip will balance the supercapacitors to within 100mV
(typical) of each other, resulting in a possible 50mV of
over/undercharge per cell.
Thermal Management
If the junction temperature increases above approximately
150°C, the thermal shutdown circuitry automatically de-
activates the output. To reduce the maximum junction
temperature, a good thermal connection to the PC board
is recommended. Connecting the exposed pad (Pin 13) of
the DFN package to a ground plane under the device on two
layers of the PC board, will reduce the thermal resistance
of the package and PC board considerably.
VIN Capacitor Selection
The style and value of capacitors used with the LTC3625/
LTC3625-1 determine input voltage ripple. Because the
LTC3625/LTC3625-1 use a step-down switching power sup-
ply from VIN to VMID, its input current waveform contains
high frequency components. It is strongly recommended
that a low equivalent series resistance (ESR) multilayer
ceramic capacitor be used to bypass VIN.
Tantalum and aluminum capacitors are not recommended
because of their high ESR. The value of the capacitor on
VIN directly controls the amount of input ripple for a given
IBUCK. Increasing the size of this capacitor will reduce the
input ripple.
Multilayer ceramic chip capacitors typically have excep-
tional ESR performance. MLCCs combined with a tight
board layout and an unbroken ground plane will yield
very good performance and low EMI emissions. There are
several types of ceramic capacitors available, each having
considerably different characteristics. For example, X7R
ceramic capacitors have the best voltage and temperature
stability. X5R ceramic capacitors have higher packing
density but poorer performance over their rated voltage
and temperature ranges. Y5V ceramic capacitors have
the highest packing density, but must be used with cau-
tion because of their extreme non-linear characteristic of
capacitance verse voltage.
The actual in-circuit capacitance of a ceramic capacitor
should be measured with a small AC signal as is expected
in-circuit. Many vendors specify the capacitance versus
voltage with a 1VRMS AC test signal and as a result,
overstate the capacitance that the capacitor will present
in the application. Using similar operating conditions as
the application, the user must measure or request from
the vendor the actual capacitance to determine if the
selected capacitor meets the minimum capacitance that
the application requires.
Inductor Selection
Many different sizes and shapes of inductors are avail-
able from numerous manufacturers. Choosing the right
inductor from such a large selection of devices can be
overwhelming, but following a few basic guidelines will
make the selection process much simpler.
LTC3625/LTC3625-1
12
3625f
applicaTions inForMaTion
The buck and boost converters are designed to work with
inductors over a wide range of inductances. Choosing a
higher valued inductor will decrease operating frequen-
cies, while a lower valued inductor will increase frequency
but also increase peak current overshoot/undershoot. For
most applications a 3.3µH inductor is recommended. To
maximize efficiency, choose an inductor with a low DC
resistance. Choose an inductor with a DC current rating
at least as large as the maximum IPEAK the application will
see according to the specifications table to ensure that the
inductor does not saturate during normal operation. If the
single inductor application is used, make sure to size the
inductor for the higher of buck or boost peak currents.
Different core materials and shapes will change the size/cur-
rent and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or Permalloy materials
are small and do not radiate much energy, but generally
cost more than powdered iron core inductors with similar
electrical characteristics. Inductors that are very thin or
have a very small volume typically have much higher core
and DCR losses, and will not give the best efficiency. The
choice of which style inductor to use often depends more
on the price versus size, performance and any radiated
EMI requirements than on what the LTC3625/LTC3625-1
family requires to operate.
Table 2 shows several inductors that work well with the
LTC3625/LTC3625-1 regulators. These inductors offer a
good compromise in current rating, DCR and physical
size. Consult each manufacturer for detailed information
on their entire selection of inductors.
Supercapacitor Selection
The LTC3625/LTC3625-1 are designed to charge super-
capacitors of values greater than 0.1F per cell. In general,
lower capacitance cells have higher ESRs, therefore lower
charge currents should be used to help reduce sleep
modulation towards the end of a charge cycle. In general,
the ESR of a supercapacitor cell should not exceed:
ESR mV
IBUCK
≤100
where 100mV is the sleep threshold hysteresis. Higher
capacitance cells typically have lower ESRs and can
therefore be charged with higher currents. Typically, the
LTC3625/LTC3625-1 are designed to charge supercapaci-
tors with values up to 100F, but higher capacitance cells
could be used at the expense of greater charge time.
Table 3 shows several supercapacitors that work well with
the LTC3625/LTC3625-1.
Printed Circuit Board Layout Considerations
In order to be able to deliver maximum current under all
conditions, it is critical that the exposed pad on the backside
of the LTC3625/LTC3625-1 package be soldered to the PC
Table 2. Inductor Manufacturers
MANUFACTURER PART NUMBER INDUCTANCE (µH) CURRENT (A) DCR (mΩ) SIZE (mm)
Coiltronics DR73-3R3-R 3.3 3.0 20 7 × 7
Coilcraft MSS7341-332NL 3.3 3.2 20 7 × 7
Vishay IHLM2525CZER3R3M11 3.3 6.5 26 6.5 × 6.9
Sumida CDRH6D28P-3RON 3.0 3.0 24 7 × 7
TOKO B1077AS-3RON 3.0 3.3 30 7.6 × 7.6
Table 3. Supercapacitor Manufacturers
MANUFACTURER PART NUMBER VALUE (F) OPERATING VOLTAGE (V) MAXIMUM ESR (mΩ) SIZE (mm)
Cooper Bussmann B1860-2R5107-R 100 2.5 20 18 × 60
Illinois Capacitor 107DCN2R7M 100 2.7 10 22 × 45
NESS Capacitor ESHSR-0100C0002R7 100 2.7 9 22 × 45
Tecate TPLS-100//22 X 45F 100 2.7 9 22 × 45
Maxwell BCAP120P250 120 2.5 2.5 26 × 51
LTC3625/LTC3625-1
13
3625f
applicaTions inForMaTion
board ground. Failure to make thermal contact between
the exposed pad on the backside of the package and the
copper board will result in higher thermal resistances.
Furthermore, due to its potentially high frequency switch-
ing circuitry, it is imperative that the input capacitor,
inductors, and output bypass capacitors be as close to
the LTC3625/LTC3625-1 as possible, and that there be an
unbroken ground plane under the IC and all of its external
high frequency components. High frequency currents, such
as the VIN and VOUT currents on the LTC3625/LTC3625-1,
tend to find their way along the ground plane in a myriad of
paths ranging from directly back to a mirror path beneath
the incident path on the top of the board. If there are slits or
cuts in the ground plane due to other traces on that layer,
the current will be forced to go around the slits. If high
frequency currents are not allowed to flow back through
their natural least-area path, excessive voltage will build
up and radiated emissions will occur. There should be a
group of vias under the grounded backside of the pack-
age leading directly down to an internal ground plane. To
minimize parasitic inductance, the ground plane should
be on the highest possible layer of the PC board.
Any board resistance between inductor(s) and the posi-
tive terminal of CBOT will add to the capacitors internal
ESR. Likewise, any resistance between the VOUT pin
and the positive terminal of CTOP will add to its internal
ESR. Any added resistance to the capacitors will reduce
the effective charging efficiency. In the case of CBOT this
resistance can be kelvined out by a dedicated voltage
sense trace from the VMID pin to a point halfway between
the bottom plate of CTOP and the top plate of CBOT
. In the
case of CTOP
, however, it is even more critical to keep any
resistance in the connection to a minimum. Excessive
series resistance may cause the part to duty cycle in and
out of sleep or prematurely shut down the boost, due to
the voltage seen at the part being equal to VOUT + IOUT •
ESR. Likewise the CBOT supercapacitor should be provided
with a low impedance contact to the ground plane with
an unbroken, low impedance, path back to the backside
of the LTC3625/LTC3625-1 package.
When laying out the printed circuit, the following check-
list should be used to ensure proper operation of the
LTC3625/LTC3625-1.
1. Are the bypass capacitors at VIN and VOUT as close as
possible to the LTC3625/LTC3625-1? These capacitors
provide the AC current to the internal power MOSFETs
and their drivers. Minimizing inductance from these
capacitors to the LTC3625/LTC3625-1 is a top priority.
2. Are the CBOT bypass capacitor and the power inductor(s)
closely connected? The (–) terminal of the CBOT bypass
capacitor returns current to the GND plane, and then
back to CIN.
3. Keep sensitive components away from the SW pins.
4. Keep the current carrying traces from VOUT to CTOP and
the inductors to CBOT to a minimum.
Typical applicaTions
450mA Charge Current 1-Inductor Application
VOUT
VMID
SW2
SW1
R3
71.5k
LTC3625-1
PROG GND
*25mA MINIMUM LOAD REQUIRED ON VIN
C2 ≥ 0.1F
C3 ≥ 0.1F
VOUT
4.0V/4.5V
3625 TA03
C1
10µF
R1
287k
R2
100k
VIN*
2.7V TO 5.5V VIN
VIN
VIN EN
CTL
VSEL
PGOOD
PFO
PFI
L1 3.3µH
LTC3625/LTC3625-1
14
3625f
Typical applicaTions
Solar Powered SCAP Charger with MPPT
VOUT
SW1
SW2
VMID
GND
CTL
EN
PFI
VSEL
GND
R3
143k
LTC3625
PROG
L2 3.3µH
C2
1F
C3
1F
3625 TA04
C1
10µF
VIN L1 3.3µH
–
+
LT1784CS5
V+
V–
1
R5
174k
R2
10.0k
C4
390µF
16V
D3
SOLAR PANEL
6.0V OPEN CIRCUIT
4.4V MPP
D2
1.2V
C5
10nF
R1
26.7k
R4
10k
D1
CMSH3-40
C6
100pF
2
5
3
4
+
VOUT
SW1
SW2
VMID
GND
PFO
CTL
5V
EN
PFI
VSEL
GND
R3
143k
LTC3625
PROG
L1
3.3µH C2
100F
Q1
Si4421DY
Q2
Si4421DY
C3
100F
C1
10µF
VIN
R2
100k
R1
287k
VIN
GND
CTL
SENSE
GATE
STAT
LTC4412
VIN1
VIN2
VOUT1
FB1
ITHM1
FB2
ITHM2
GND
GND
VOUT2
LTM4616
R4
470k
R5
4.78k
R6
10k
3625 TA05
C7
100µF
C6
100µF
1.8V
C8
100µF
C5
22µF
5V Power Ride-Through
LTC3625/LTC3625-1
15
3625f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
package DescripTion
DE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695)
4.00 p0.10
(2 SIDES)
3.00 p0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.40 p 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 p 0.10
0.75 p0.05
R = 0.115
TYP
R = 0.05
TYP
2.50 REF
16
127
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
CHAMFER
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(UE12/DE12) DFN 0806 REV D
3.30 p0.10
0.25 p 0.05
0.50 BSC
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 p0.05
0.70 p0.05
3.60 p0.05
PACKAGE
OUTLINE
1.70 p 0.05
3.30 p0.05
0.50 BSC
0.25 p 0.05
Typical applicaTions
•
VOUT
SW1
SW2
CTL
EN
GND
VSEL
VMID
LTC3625
PROG
L2 3.3µH
C1
100F
*M1
IRF7424
UV
DETECTOR
*EXPOSED PAD TO
BE CONNECTED TO A
THERMAL PAD ISOLATED
FROM THE SYSTEM GROUND
FDS3672
VIN
DC-A
64
LT1737 FLYBACK
2
GND
12V
•
10
L1 3.3µH
L4 3.3µH
L3 3.3µH
L6 3.3µH
L5 3.3µH
C2
100F
R1
143k
VOUT
CTL
EN
GND
VSEL
LTC3625
PROG
C3
100F
VIN
C4
100F
R2
143k
VOUT
CTL
EN
GND
VSEL
LTC3625
PROG
C5
100F
VIN
C6
100F
R3
143k
FDS3672
LTC4355
IDEAL DIODE
DC/DC
LTM4601A
VIN VOUT
GND GND
1.8V
GND
DC-B
7
•
11
DC-C
8
•
12
LT1737
*
SW1
SW2
VMID
SW1
SW2
VMID
12V Power Ride-Through
LTC3625/LTC3625-1
16
3625f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2010
LT 0710 • PRINTED IN USA
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LTC3203/LTC3203B/
LTC3203B-1/LTC3203-1
500mA Low Noise High Efficiency Dual Mode
Step-Up Charge Pumps
VIN: 2.7V to 5.5V, 3mm × 3mm 10-Lead DFN Package
LTC3204/LTC3204B-3.3/
LTC3204-5
Low Noise Regulating Charge Pumps Up to 150mA Output Current (LTC3204-5), Up to 50mA Output Current
(LTC3204-3.3)
LTC3221/LTC3221-3.3/
LTC3221-5
Micropower Regulated Charge Pump Up to 60mA Output Current
LTC3225/LTC3225-1 150mA Supercapacitor Charger Programmable Supercapacitor Charger Designed to Charge Two
Supercapacitors in Series to a Fixed Output Voltage (4.8V/5.3V Selectable)
from a 2.8V/3V to 5.5V Input Supply. Automatic Cell Balancing Prevents
Overvoltage Damage to Either Supercapacitor. No Balancing Resistors are
Required.
LTC3240-3.3/LTC3240-2.5 Step-Up/Step-Down Regulated Charge Pumps Up to 150mA Output Current
LT
®
3420/LT3420-1 1.4A/1A Photoflash Capacitor Charger with
Automatic Top-Off
Charges 220µF to 320V in 3.7 Seconds from 5V, VIN: 2.2V to 16V,
ISD < 1µA, 10-Lead MS Package
LT3468/LT3468-1/
LT3468-2
1.4A/1A/0.7A, Photoflash Capacitor Charger VIN: 2.5V to 16V, Charge Time = 4.6 Seconds for the LT3468 (0V to 320V,
100µF, VIN = 3.6V), ISD < 1µA, ThinSOT
TM
Package
LTC3484-0/LTC3484-1/
LTC3484-2
1.4A/0.7A/1A, Photoflash Capacitor Charger VIN: 1.8V to 16V, Charge Time = 4.6 Seconds for the LT3484-0 (0V to 320V,
100µF, VIN = 3.6V), ISD < 1µA, 2mm × 3mm 6-Lead DFN Package
LT3485-0/LT3485-1/
LT3485-2/LT3485-3
1.4A/0.7A/1A/2A Photoflash Capacitor Charger
with Output Voltage Monitor and Integrated
IGBT
VIN: 1.8V to 10V, Charge Time = 3.7 Seconds for the LT3485-0 (0V to 320V,
100µF, VIN = 3.6V), ISD < 1µA, 3mm × 3mm 10-Lead DFN Driver
LT3750 Capacitor Charger Controller Charges Any Size Capacitor, 10-Lead MS Package
LT3751 Capacitor Controller with Regulation Charges Any Size Capacitor, 4mm × 5mm QFN-20 Package
LTC4425 Supercapacitor Charger with Current-Limited
Ideal Diode
CC/CV Linear Charger for 2-Cell Supercapacitor Stack from a Li-Ion/
Polymer Battery, USB Port or a 2.7V to 5.5V Current-Limited Supply,
3mm × 3mm DFN-12 and MSOP-12E Packages
Minimum External Component Application (500mA Charge Current)
VOUT
SW1
SW2
VMID
LTC3625
PROG GND
L1
3.3µH C2 ≥ 0.1F
VOUT
4.8V/5.3V
C3 ≥ 0.1F
*25mA MINIMUM LOAD REQUIRED ON VIN
3625 TA02
C1
10µF
NC
NC
VIN*
2.7V TO 5.5V VIN
PFI
CTL
EN
VSEL
PGOOD
PFO