1518 data 3 delay devices, inc. 5-TAP SMD DELAY LINE TD/TR = 3 (SERIES 1518) FEATURES * * * * * PACKAGES IN N/C 5 taps of equal delay increment Delays to 200ns Low profile Epoxy encapsulated Meets or exceeds MIL-D-23859C T2 N/C T4 T5 GND 1 14 2 3 13 12 4 5 11 10 6 7 9 8 N/C T1 N/C N/C The 1518-series device is a fixed, single-input, fiveoutput, passive delay line. The signal input (IN) is reproduced at the outputs (T1-T5) in equal increments. The delay from IN to T5 (TD) and the characteristic impedance of the line (Z) are determined by the dash number. The rise time (TR) of the line is 30% of TD, and the 3dB bandwidth is given by 1.05 / TD. The device is available in a 14-pin SMD with two pinout options. 1518 - xxx - zzz p DELAY TIME Expressed in nanoseconds (ns) First two digits are significant figures Last digit specifies # of zeros to follow IMPEDANCE Expressed in nanoseconds (ns) First two digits are significant figures Last digit specifies # of zeros to follow Part numbers are constructed according to the scheme shown at right. For example, 1518-101-500A is a 100ns, 50 delay line with pinout code A. Similarly, 1518-151501 a is 150ns, 500 delay line with standard pinout. SERIES SPECIFICATIONS Dielectric breakdown: Distortion @ output: Operating temperature: Storage temperature: Temperature coefficient: 50 Vdc 10% max. -55C to +125C -55C to +125C 100 PPM/C IN T5 GND GND Functional Diagram .505 8 .290 1 TI (ns) 1.0 2.0 3.0 4.0 5.0 6.0 8.0 10.0 12.0 15.0 16.0 20.0 22.0 25.0 30.0 36.0 50.0 TR (ns) 3.0 4.0 5.0 6.0 7.0 10.0 13.0 15.0 20.0 25.0 26.0 30.0 32.0 40.0 50.0 60.0 70.0 Z=50 N/A 3 3 3 3 3 3 3 3 3 4 4 4 4 N/A N/A N/A CODE STD A .100 IN 1 1 Package Dimensions Doc #97030 2/7/97 ATTENUATION (%) TYPICAL Z=100 Z=200 Z=300 Z=500 5 N/A N/A N/A 5 5 N/A N/A 5 5 N/A N/A 5 5 5 N/A 5 5 5 7 5 5 5 7 5 5 5 7 5 5 7 7 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 8 10 10 7 8 10 10 8 10 12 12 PINOUT CODES .425 7 .300 TD (ns) 5 10 15 20 25 30 40 50 60 75 80 100 110 125 150 180 200 Notes: TI represents nominal tap-to-tap delay increment Tolerance on TD = 5% or 2ns, whichever is greater Tolerance on TI = 5% or 1ns, whichever is greater "N/A" indicates that delay is not available at this Z .050 .185 14 PINOUT CODE See Table Omit for STD pinout DELAY SPECIFICATIONS T1 T2 T3 T4 .018 Note: Standard pinout shown Alt. pinout available N/C PART NUMBER CONSTRUCTION FUNCTIONAL DESCRIPTION * * * * * IN Signal Input T1-T5 Tap Outputs GND Ground N/C T3 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 T1 13 12 T2 3 4 T3 11 10 T4 5 6 T5 6 7 GND 7 8,14 1997 Data Delay Devices 1 1518 PASSIVE DELAY LINE TEST SPECIFICATIONS TEST CONDITIONS INPUT: Ambient Temperature: Input Pulse: OUTPUT: Rload: Cload: Threshold: 25oC 3oC High = 3.0V typical Low = 0.0V typical Source Impedance: 50 Max. Rise/Fall Time: 3.0 ns Max. (measured at 10% and 90% levels) Pulse Width (TD <= 75ns): PWIN = 100ns Period (TD <= 75ns): PERIN = 1000ns Pulse Width (TD > 75ns): PWIN = 2 x TD Period (TD > 75ns): PERIN = 10 x TD 10M 10pf 50% (Rising & Falling) NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. PERIN PWIN TRISE INPUT SIGNAL TFALL VIH 90% 50% 10% 90% 50% 10% TRISE VIL TFALL TRISE OUTPUT SIGNAL 90% 50% 10% TFALL VOH 90% 50% 10% VOL Timing Diagram For Testing OUT PULSE GENERATOR RIN IN DEVICE UNDER TEST (DUT) TRIG 50 RIN = ROUT = ZLINE IN T1 T2 T3 T4 T5 TRIG OSCILLOSCOPE ROUT Test Setup Doc #97030 2/7/97 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2