K6F2016S4E-EF85 - Samsung - Datasheet.Live

CMOS SRAMK6F2016S4E Family

- 1 - Revision 1.0

September 2001

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Document Title

128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM

Revision History

Revision No.

0.0

1.0

Remark

Preliminary

Final

History

Initial Draft

Finalize

- Changed 48-TBGA vertical dimension

E1(Typical) 0.55mm to 0.58mm

E2(Typical) 0.35mm to 0.32mm

Draft Date

April 17, 2001

September 27, 2001

CMOS SRAMK6F2016S4E Family

- 2 - Revision 1.0

September 2001

PRODUCT FAMILY

1. The parameter is measured with 30pF test load.

2. Typical value are measured at VCC=2.5V, TA=25°C and not 100% tested.

Product Family Operating Temperature Vcc Range Speed Power Dissipation PKG Type

Standby

(ISB1, Typ.) Operating

(ICC1, Max)

K6F2016S4E-F Industrial(-40~85°C) 2.3~2.7V 701)/85ns 0.5µA2) 2mA 48-TBGA-6.00x7.00

128K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM

GENERAL DESCRIPTION

The K6F2016S4E families are fabricated by SAMSUNG′s

advanced full CMOS process technology. The families support

industrial temperature range and 48 ball Chip Scale Package

for user flexibility of system design. The families also support

low data retention voltage for battery back-up operation with

low data retention current.

FEATURES

• Process Technology: Full CMOS

• Organization: 128K x16 bit

• Power Supply Voltage: 2.3~2.7V

• Low Data Retention Voltage: 1.5V(Min)

• Three State Outputs

• Package Type: 48-TBGA-6.00x7.00

FUNCTIONAL BLOCK DIAGRAM

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Precharge circuit.

Memory array

1024 rows

128 × 16 columns

I/O Circuit

Column select

Clk gen.

Row

select

I/O1~I/O8Data

cont

Data

cont

Data

cont

I/O9~I/O16

Vcc

Vss

Row

Addresses

Control Logic

Column Addresses

PIN DESCRIPTION

Name Function Name Function

CS1, CS2Chip Select Inputs Vcc Power

OE Output Enable Input Vss Ground

WE Write Enable Input UB Upper Byte(I/O9~16)

A0~A16 Address Inputs LB Lower Byte(I/O1~8)

I/O1~I/O16 Data Inputs/Outputs DNU Do Not Use

48-TBGA: Top View(Ball Down)

LB OE A0 A1 A2 DNU

I/O9 UB A3 A4 CS1I/O1

I/O10 I/O11 A5 A6 I/O2 I/O3

Vss I/O12 DNU A7 I/O4 Vcc

Vcc I/O13 A16 I/O5 Vss

I/O15 I/O14 A14 A15 I/O6 I/O7

I/O16 DNU A12 A13 WE I/O8

DNU A8 A9 A10 A11 DNU

1 23456

DNU

CMOS SRAMK6F2016S4E Family

- 3 - Revision 1.0

September 2001

ABSOLUTE MAXIMUM RATINGS1)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions longer than 1seconds may affect reliability.

Item Symbol Ratings Unit

Voltage on any pin relative to Vss VIN,VOUT -0.2 to VCC+0.3V V

Voltage on Vcc supply relative to Vss VCC -0.2 to 3.0V V

Power Dissipation PD1.0 W

Storage temperature TSTG -65 to 150 °C

Operating Temperature TA-40 to 85 °C

FUNCTIONAL DESCRIPTION

1. X means don′t care. (Must be low or high state)

CS OE WE LB UB I/O1~8 I/O9~16 Mode Power

HX1) X1) X1) X1) High-Z High-Z Deselected Standby

X1) X1) X1) H H High-Z High-Z Deselected Standby

LH H LX1) High-Z High-Z Output Disabled Active

LH H X1) LHigh-Z High-Z Output Disabled Active

L L HLHDout High-Z Lower Byte Read Active

L L H H LHigh-Z Dout Upper Byte Read Active

L L HL L Dout Dout Word Read Active

LX1) L L HDin High-Z Lower Byte Write Active

LX1) LHLHigh-Z Din Upper Byte Write Active

LX1) L L L Din Din Word Write Active

PRODUCT LIST

Industrial Temperature Products(-40~85°C)

Part Name Function

K6F2016S4E-EF70

K6F2016S4E-EF85 48-TBGA, 70ns, 2.5V

48-TBGA, 85ns, 2.5V

CMOS SRAMK6F2016S4E Family

- 4 - Revision 1.0

September 2001

DC AND OPERATING CHARACTERISTICS

1. Typical values are measured at VCC=2.5V, TA=25°C and not 100% tested.

Item Symbol Test Conditions Min Typ1) Max Unit

Input leakage current ILI VIN=Vss to Vcc -1 -1µA

Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 -1µA

Average operating current

ICC1 Cycle time=1µs, 100%duty, IIO=0mA, CS≤0.2V,

LB≤0.2V or/and UB≤0.2V, VIN≤0.2V or VIN≥VCC-0.2V - - 2mA

ICC2 Cycle time=Min, IIO=0mA, 100% duty, CS=VIL,

LB=VIL or/and UB=VIL, VIN=VIL or VIH 85ns - - 15 mA

70ns - - 17 mA

Output low voltage VOL IOL=0.5mA - - 0.4 V

Output high voltage VOH IOH=-0.5mA 2.0 - - V

Standby Current (CMOS) ISB1 Other input =0~Vcc

1) CS≥Vcc-0.2V(CS controlled) or

2) LB=UB≥Vcc-0.2V, CS≤0.2V(LB/UB controlled) -0.5 5µA

RECOMMENDED DC OPERATING CONDITIONS1)

Note:

1. TA=-40 to 85°C, otherwise specified

2. Overshoot: Vcc + 1.0V in case of pulse width ≤20ns.

3. Undershoot: -1.0V in case of pulse width ≤ 20ns.

4. Overshoot and undershoot are sampled, not 100% tested.

Item Symbol Min Typ Max Unit

Supply voltage Vcc 2.3 2.5 2.7 V

Ground Vss 000V

Input high voltage VIH 2.0 -Vcc+0.22) V

Input low voltage VIL -0.23) -0.6 V

CAPACITANCE1) (f=1MHz, TA=25°C)

1. Capacitance is sampled, not 100% tested

Item Symbol Test Condition Min Max Unit

Input capacitance CIN VIN=0V -8pF

Input/Output capacitance CIO VIO=0V -10 pF

CMOS SRAMK6F2016S4E Family

- 5 - Revision 1.0

September 2001

AC CHARACTERISTICS(Vcc=2.3~2.7V, Industrial product:TA=-40 to 85°C)

Parameter List Symbol Speed Bins Units

70ns 85ns

Min Max Min Max

Read

Read Cycle Time tRC 70 -85 -ns

Address Access Time tAA -70 -85 ns

Chip Select to Output tCO -70 -85 ns

Output Enable to Valid Output tOE -35 -40 ns

UB, LB Access Time tBA -70 -85 ns

Chip Select to Low-Z Output tLZ 10 -10 -ns

UB, LB Enable to Low-Z Output tBLZ 10 -10 -ns

Output Enable to Low-Z Output tOLZ 5-5-ns

Chip Disable to High-Z Output tHZ 025 025 ns

UB, LB Disable to High-Z Output tBHZ 025 025 ns

Output Disable to High-Z Output tOHZ 025 025 ns

Output Hold from Address Change tOH 10 -10 -ns

Write

Write Cycle Time tWC 70 -85 -ns

Chip Select to End of Write tCW 60 -70 -ns

Address Set-up Time tAS 0-0-ns

Address Valid to End of Write tAW 60 -70 -ns

UB, LB Valid to End of Write tBW 60 -70 -ns

Write Pulse Width tWP 50 -60 -ns

Write Recovery Time tWR 0-0-ns

Write to Output High-Z tWHZ 020 025 ns

Data to Write Time Overlap tDW 30 -35 -ns

Data Hold from Write Time tDH 0-0-ns

End Write to Output Low-Z tOW 5-5-ns

DATA RETENTION CHARACTERISTICS

1. 1) CS≥Vcc-0.2V(CS controlled) or

2) LB=UB≥Vcc-0.2V, CS≤0.2V(LB/UB controlled)

2. Typical values are measured at TA=25°C and not 100% tested.

Item Symbol Test Condition Min Typ2) Max Unit

Vcc for data retention VDR CS≥Vcc-0.2V1) 1.5 -2.7 V

Data retention current IDR Vcc= 1.5V, CS≥Vcc-0.2V1) -0.5 2µA

Data retention set-up time tSDR See data retention waveform 0- - ns

Recovery time tRDR tRC - -

AC OPERATING CONDITIONS

TEST CONDITIONS(Test Load and Test Input/Output Reference)

Input pulse level: 0.4 to 2.2V

Input rising and falling time: 5ns

Input and output reference voltage: 1.1V

Output load(See right): CL= 100pF+1TTL

CL= 30pF+1TTL CL1)

1. Including scope and jig capacitance

R22)

R12)

VTM3)

2. R1=3070Ω, R2=3150Ω

3. VTM =2.3V

CMOS SRAMK6F2016S4E Family

- 6 - Revision 1.0

September 2001

Address

Data Out Previous Data Valid Data Valid

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Data Valid

High-Z

tRC

Address

UB, LB

Data out

tAA

tRC

tOH

tAA

tCO

tBA

tOE

tOLZ

tBLZ

tLZ tOHZ

tBHZ

tHZ

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

CMOS SRAMK6F2016S4E Family

- 7 - Revision 1.0

September 2001

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

Address

Data Valid

UB, LB

Data in

Data out High-Z High-Z

tWC

tCW(2)

tAW tBW

tWP(1)

tDH

tDW

tWR(4)

tAS(3)

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

Data Undefined

UB, LB

Data in

Data out

tWC

tCW(2) tWR(4)

tAWtBW

tWP(1)

tAS(3) tDHtDW

tWHZ tOW

High-Z High-Z

Data Valid

CMOS SRAMK6F2016S4E Family

- 8 - Revision 1.0

September 2001

Address

Data Valid

UB, LB

Data in

Data out High-Z High-Z

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-

tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

tWC

tCW(2)

tBW

tWP(1)

tDH

tDW

tWR(4)

tAW

DATA RETENTION WAVE FORM

CS or LB/UB controlled

VCC

2.3V

2.0V

VDR

CS or LB/UB

GND

Data Retention Mode

CS≥VCC-0.2V or LB=UB≥Vcc-0.2V

tSDR tRDR

tAS(3)

CMOS SRAMK6F2016S4E Family

- 9 - Revision 1.0

September 2001

C1/2

PACKAGE DIMENSION

6 5 4 3 2 1

B/2

Bottom ViewTop View

Side View

0.58/Typ.

0.32/Typ.

Detail A

Min Typ Max

A-0.75 -

B5.90 6.00 6.10

B1 -3.75 -

C6.90 7.00 7.10

C1 -5.25 -

D0.40 0.45 0.50

E0.80 0.90 1.00

E1 -0.58 -

E2 0.27 0.32 0.37

Y- - 0.08

#A1

Notes.

1. Bump counts: 48(8 row x 6 column)

2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)

3. All tolerence are ±0.050 unless

otherwise specified.

4. Typ: Typical

5. Y is coplanarity: 0.08(Max)

Unit: millimeters

48 TAPE BALL GRID ARRAY(0.75mm ball pitch)